Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device enabling improvement in reliability, and a method of manufacturing the silicon carbide semiconductor device.SOLUTION: A bottom surface of a trench 6 is a Si surface or C surface and a side surface of the trench 6 is an m surface. A gate electrode 8 is provided inside the trench 6 via a gate insulating film 7. The gate insulating film 7 is a high temperature oxide (HTO) film of 50 nm or larger in thickness t1. Annealing after HTO deposition in a mixed gas atmosphere of nitrogen monoxide, nitrogen and oxygen at a temperature of 1,250 to 1,300°C inclusive makes a film density of the gate insulating film 7 fall within a range between 2.21 and 2.38 g / cm3. The total oxygen flow rate in the mixed gas atmosphere of the annealing after the HTO deposition is 5% or less. The gate insulating film 7 has a two-layered structure of a low-density film 7a of relatively low film density within a range t11 of 3 nm from an SiC / SiO2 interface 20, and a high-density film 7b of relatively high film density within a range of 3 nm or more away from the SiC / SiO2 interface 20.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Conventionally, in a trench gate type SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate composed of a three-layer structure of gate - oxide film - semiconductor) using silicon carbide (SiC) as a semiconductor material, a silicon oxide (SiO2) film deposited by high temperature oxidation (H igh Temperature Oxide process (HTO process) (hereinafter referred to as an HTO film) is often used. The reasons are as follows.

[0003] In a SiC-MOSFET, the film quality of the gate insulating film affects the device characteristics and reliability. The SiO2 film formed by thermal oxidation (hereinafter referred to as a thermal oxide film) is superior as a SiO2 film to the HTO film. However, in order to thermally oxidize a semiconductor substrate made of SiC, excess carbon (C) due to this thermal oxidation reaction is generated at the bonding interface between the semiconductor substrate and the gate insulating film (hereinafter referred to as the SiC / SiO2 interface). This excess carbon has an adverse effect on the interface characteristics of the SiC / SiO2 interface (such as an increase in defects in SiO2 and interface energy levels), and causes deterioration of the device characteristics.

[0004] In order to suppress the generation of excess carbon, instead of thermal oxidation, the gate insulating film is often formed by deposition. Also, it is desirable that the gate insulating film has a good film quality with a high film density and high denseness, and high insulating performance. In the case of a trench gate structure, it is desirable that a gate insulating film is formed with a sufficient thickness also on the bottom surface of the trench. From these points, an HTO film formed with a relatively uniform thickness in the plane of the inner wall of the trench and having a relatively good film quality is used as the gate insulating film of the trench gate structure High-temperature acidification (SiO2 film deposited by).

[0005] As a method for forming a gate insulating film, oxygen is obliquely ion-implanted through an oxide film mask that becomes a screen oxide film to form an oxygen ion implantation layer in the surface region of the side wall of the trench, and after removing the oxide film mask, a method of forming an HTO film that becomes a gate insulating film has been proposed (for example, see Patent Document 1 below). In Patent Document 1 below, excess carbon generated at the initial stage of HTO film deposition and excess carbon in the gate insulating film react with oxygen in the oxygen ion implantation layer to become carbon dioxide and desorb, so the generation of excess carbon is suppressed compared to the case of forming a gate insulating film by thermal oxidation.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Normally, during the operation of a trench gate type MOSFET, since the electric field concentrates near the bottom surface of the trench, it is desirable that the thickness of the gate insulating film is thicker at the bottom surface portion than at the portion on the side wall of the trench. However, generally, High-temperature acidification the thickness of the HTO film deposited along the inner wall of the trench tends to be slightly thinner at the bottom surface portion than at the portion on the side wall of the trench. In addition, the HTO film has lower density and inferior insulation performance compared to a thermal oxide film. For this reason, the reliability of the MOSFET may decrease, and the life (service life) of the MOSFET may be shortened.

[0008] An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can improve reliability in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0009] In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device having an insulated gate composed of a three-layer structure of a gate-oxide film-semiconductor, and has the following characteristics. A semiconductor substrate made of silicon carbide constitutes the semiconductor. A trench having a predetermined depth extending in a direction perpendicular to the first main surface of the semiconductor substrate is provided from the first main surface of the semiconductor substrate. A gate insulating film constituting the oxide film is provided along the inner wall of the trench. The gate insulating film is in contact with the semiconductor substrate at the inner wall of the trench.

[0010] A gate electrode constituting the gate is provided on the gate insulating film inside the trench. It is a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during turn-on. The first main surface of the semiconductor substrate is an Si surface or a C surface. The side wall of the trench is an m surface. The gate insulating film is a silicon oxide film having a thickness of 50 nm or more deposited by high-temperature oxidation. The film density of the gate insulating film is within the range of 2.21 g / cm 3 or more and 2.38 g / cm 3 or less, and is higher at the bottom surface portion of the trench than at the portion on the side wall of the trench.

[0011] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the film density of the gate insulating film is 2.27 g / cm or more in the plane of the side wall of the trench. 3 It is characterized by the above.

[0012] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the gate insulating film is a low-density film in a range within 3 nm from the interface between the semiconductor substrate and the gate insulating film, which is in contact with the semiconductor substrate at the inner wall of the trench, and a portion in a range more than 3 nm away from the interface between the semiconductor substrate and the gate insulating film, and is a two-layer structure of a high-density film having a higher film density than the low-density film, which is in contact with the low-density film and the gate electrode.

[0013] In addition, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the nitrogen concentration at the interface between the semiconductor substrate and the gate insulating film is 5×10 20 atoms / cm 3 or more.

[0014] In addition, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the average nitrogen concentration in the thickness direction of the gate insulating film from the interface between the semiconductor substrate and the gate insulating film to the contact surface with the gate electrode is 5×10 19 atoms / cm 3 or less.

[0015] In addition, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the thickness of the gate insulating film is thinner on the bottom surface portion than on the side wall portion of the trench.

[0016] In addition, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to this invention is a method for manufacturing a silicon carbide semiconductor device including an insulated gate having a three-layer structure of a gate - oxide film - semiconductor, and has the following features. A first step of forming a trench having a predetermined depth extending in a direction orthogonal to the first main surface of a semiconductor substrate made of silicon carbide, which constitutes the semiconductor, from the first main surface of the semiconductor substrate is performed. A second step of forming a gate insulating film that constitutes the oxide film along the inner wall of the trench on the inner wall of the trench is performed. A third step of annealing the gate insulating film by heat treatment is performed.

[0017] After the third step, a gate electrode that forms the gate is formed on the gate insulating film inside the trench, thereby performing a fourth step of forming a trench gate structure in which a channel is formed in a portion along the sidewall of the trench of the semiconductor substrate during turn-on. The first main surface of the semiconductor substrate is an Si surface or a C surface. The sidewall of the trench is an m surface. In the second step, as the gate insulating film, a silicon oxide film with a thickness of 50 nm or more is deposited by high-temperature oxidation. In the third step, the heat treatment is performed at a temperature of 1250 °C or higher and 1300 °C or lower in an atmosphere of a mixed gas of nitric oxide, nitrogen, and oxygen. below The heat treatment is performed at Yes, the film density of the gate insulating film is set within a range of 2.21 g / cm 3 or more and 2.38 g / cm 3 or less in the in-plane direction of the inner wall of the trench, and made higher at the bottom surface of the trench than at the portion on the side wall of the trench 。

[0018] Also, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, in the third step, the total oxygen flow rate in the mixed gas atmosphere is 5% or less.

[0019] According to the above-described invention, since the film density (compactness) of the gate insulating film can be increased, the film quality of the gate insulating film is improved, and the insulating performance of the gate insulating film can be enhanced. As a result, leakage current characteristics and dielectric breakdown withstand voltage can be improved. Further, since the film quality of the gate insulating film is improved, the thickness of the gate insulating film can be reduced and the voltage applied to the gate electrode can be lowered, so that the time-dependent dielectric breakdown withstand voltage can be enhanced.

[0020] Also, according to the above-described invention, electrical characteristics (such as channel mobility) almost equivalent to those obtained when annealing is performed after HTO deposition under conventional conditions (a mixed gas atmosphere of only nitric oxide and nitrogen) can be achieved. Further, compared with the case where annealing is performed after HTO deposition under conventional conditions, the gate threshold voltage can be lowered, and the variation in the gate threshold voltage can be suppressed and stabilized.

Advantages of the Invention

[0021] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, an effect of improving reliability can be achieved.

Brief Description of Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0023] With reference to the accompanying drawings, preferred embodiments of the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the layers and regions denoted by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index.

[0024] (Embodiment) The structure of the silicon carbide semiconductor device according to the embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 2 is an enlarged view schematically showing an enlarged view of the vicinity of the trench in FIG. 1. The silicon carbide semiconductor device 10 according to the embodiment shown in FIG. 1 is a vertical MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material. The semiconductor substrate 30 is an epitaxial substrate formed by sequentially laminating an n + -type starting substrate 31 on the front surface, and n - -type drift region 2 and p-type base region 3, and epitaxial layers 32 and 33 serving as the epitaxial layers.

[0025] The semiconductor substrate 30 has the main surface on the p-type epitaxial layer 33 side as the front surface (first main surface), and the main surface on the n + -type starting substrate 31 side as the back surface. The crystal structure of the semiconductor substrate 30 is, for example, a four-layer periodic hexagonal crystal structure (4H-SiC) of silicon carbide. The front surface of the semiconductor substrate 30 is a (0001) surface, a so-called Si (silicon) surface, or a (000-1) surface, a so-called C (carbon) surface. The n + -type starting substrate 31 is an n + -type drain region 1. The n - -type drift region 2 is an n -The n-type epitaxial layer 32 + is the part on the side of the n-type starting substrate 31, and the n + type starting substrate 31 is adjacent. The p-type base region 3 is provided between the front surface of the semiconductor substrate 30 and the n - type drift region 2.

[0026] The trench gate structure is composed of a p-type base region 3, an n + type source region 4, a p ++ type contact region 5, a trench 6, a gate insulating film 7, and a gate electrode 8. Between the p-type base region 3 and the n - type drift region 2, at a position deeper than the bottom surface of the trench 6 on the side of the n + type drain region 1, an n-type current diffusion region 23 and a p + type regions 21, 22 are selectively provided respectively. The n-type current diffusion region 23 and the p + type regions 21, 22 are diffusion regions formed inside the n - type epitaxial layer 32 by ion implantation. The part of the n - type epitaxial layer 32 excluding the n-type current diffusion region 23 and the p + type regions 21, 22 is the n - type drift region 2.

[0027] The n-type current diffusion region 23 is a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the spreading resistance of carriers. The n-type current diffusion region 23 contacts the p-type base region 3 and the n - type drift region 2 in the depth direction between adjacent trenches 6, reaches up to the trench 6 in the direction parallel to the front surface of the semiconductor substrate 30, and contacts the gate insulating film 7. The n-type current diffusion region 23 may not be provided. In this case, instead of the n-type current diffusion region 23, the n - type drift region 2 reaches from the n + type drain region 1 side to the p-type base region 3, reaches up to the trench 6 in the direction parallel to the front surface of the semiconductor substrate 30, and contacts the gate insulating film 7.

[0028] p+ The p-type regions 21 and 22 are fixed to the potential of the source electrode 11 described later, and deplete when the MOSFET (silicon carbide semiconductor device 10) is off (or deplete the n-type current diffusion region 23, or both), and have a function of relaxing the electric field applied to the gate insulating film 7 on the bottom surface of the trench 6. + The p-type region 21 is provided apart from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction. + The p-type region 21 is partially connected to the p-type region 22 (not shown) or is connected to another p-type region, and is electrically connected to the source electrode 11. + The p-type region 21 may be in contact with the gate insulating film 7 at the bottom surface of the trench 6 or may be separated from the bottom surface of the trench 6. + The p-type region 21 preferably also faces the bottom corner portion of the trench 6 in the depth direction.

[0029] p + When the p-type region 21 faces the bottom corner portion of the trench 6 in the depth direction, the electric field applied to the gate insulating film 7 at the bottom corner portion of the trench 6 is relaxed when the MOSFET is off, so that the electric field relaxation effect near the bottom surface of the trench 6 is enhanced. The bottom corner portion of the trench 6 is the connecting portion between the side wall and the bottom surface of the trench 6. In FIG. 2, the rounded state of the bottom corner portion (corner portion) of the trench 6 is not shown, and the connecting portion between the side wall and the bottom surface of the trench 6 is made clear. The p-type region 22 shown in FIG. 1 is provided between adjacent trenches 6, separated from the trenches 6 and the p-type regions 21. + The p-type region 22 is provided between adjacent trenches 6, separated from the trenches 6 and the p-type regions 21. + The p-type region 22 is in contact with the p-type base region 3 on the surface on the n-type source region 4 side and is electrically connected to the source electrode 11 through the p-type base region 3. + The trench 6 penetrates the p-type epitaxial layer 33 in the depth direction from the front surface of the semiconductor substrate 30 and reaches the n-type current diffusion region 23 (or the n-type drift region 2 if the n-type current diffusion region 23 is not provided). The trench 6 is formed in the p-type epitaxial layer 33. + The trench 6 penetrates the p-type epitaxial layer 33 in the depth direction from the front surface of the semiconductor substrate 30 and reaches the n-type current diffusion region 23 (or the n-type drift region 2 if the n-type current diffusion region 23 is not provided). + The trench 6 penetrates the p-type epitaxial layer 33 in the depth direction from the front surface of the semiconductor substrate 30 and reaches the n-type current diffusion region 23 (or the n-type drift region 2 if the n-type current diffusion region 23 is not provided).

[0030] The trench 6 penetrates the p-type epitaxial layer 33 in the depth direction from the front surface of the semiconductor substrate 30 and reaches the n-type current diffusion region 23 (or the n-type drift region 2 if the n-type current diffusion region 23 is not provided). - The trench 6 penetrates the p-type epitaxial layer 33 in the depth direction from the front surface of the semiconductor substrate 30 and reaches the n-type current diffusion region 23 (or the n-type drift region 2 if the n-type current diffusion region 23 is not provided). +It may terminate inside the p-type region 21. The trench 6 extends in a stripe shape, for example, in a direction parallel to the front surface of the semiconductor substrate 30 (the depth direction in FIG. 1). Between adjacent trenches 6, an n + -type source region 4 and a p ++ -type contact region 5 are selectively provided, respectively. The n + -type source region 4 and the p ++ -type contact region 5 are diffusion regions formed inside the p-type epitaxial layer 33 by ion implantation.

[0031] The n + -type source region 4 and the p ++ -type contact region 5 are exposed on the front surface of the semiconductor substrate 30. Exposing on the front surface of the semiconductor substrate 30 means contacting the source electrode 11 described later on the front surface of the semiconductor substrate 30. The n + -type source region 4 is provided closer to the trench 6 than the p ++ -type contact region 5 and contacts the gate insulating film 7 at the side wall of the trench 6. The p ++ -type contact region 5 may not be provided. In this case, instead of the p ++ -type contact region 5, the p-type base region 3 reaches the front surface of the semiconductor substrate 30 and is exposed. The portion of the p-type epitaxial layer 33 excluding the n + -type source region 4 and the p ++ -type contact region 5 is the p-type base region 3.

[0032] The bottom surface of the trench 6 shows the same crystal plane as the semiconductor substrate 30. The side walls of the trench 6 are {1-100} planes, so-called m planes. Inside the trench 6, a gate insulating film 7 is provided along the inner wall of the trench 6. The gate insulating film 7 is at the inner wall of the trench 6 and contacts the n + -type source region 4, the p-type base region 3, and the n-type current diffusion region 23 (when the n-type current diffusion region 23 is not provided, n -It is in contact with the type drift region 2). As will be described later, when the MOSFET is on, among the bonding interfaces (SiC / SiO2 interfaces) 20 between the semiconductor substrate 30 and the gate insulating film 7, a channel (n-type inversion layer) is formed in a portion 3a of the p-type base region 3 along the side wall (i.e., the m-plane) of the trench 6.

[0033] The gate insulating film 7 is generally such height formed by high-temperature oxidation (HTO process ) deposited silicon oxide (SiO2) film (hereinafter referred to as HTO film). The film density of the HTO film varies depending on the crystal plane on the SiC surface where the HTO film is deposited, and it has been confirmed by the intensive research of the present inventor that it is higher on the Si plane and the C plane than on the m-plane. Also, the thickness of the HTO film tends to be thinner at the bottom of the trench 6 than at the side wall of the trench 6. Since the film density of the HTO film increases as the thickness increases (see FIG. 4 described later), when trying to improve the insulation performance as the gate insulating film 7, a certain thickness of the HTO film is required. The thickness of the gate insulating film of a general trench gate type SiC-MOSFET is, for example, about 60 nm to 80 nm.

[0034] As described above, the bottom surface of the trench 6 is the Si plane or the C plane, and the side wall of the trench 6 is the m-plane. Therefore, the film density of the gate insulating film 7 is higher on the bottom surface (Si plane or C plane) of the trench 6 than on the portion on the side wall (m-plane) of the trench 6. Therefore, generally High-temperature acidification By being deposited, even if the thickness t1 of the gate insulating film 7 is slightly thinner on the bottom surface portion than on the side wall portion of the trench 6, the film quality of the gate insulating film 7 on the bottom surface of the trench 6 is good. For this reason, by setting the bottom surface of the trench 6 as the Si plane or the C plane and using the HTO film as the gate insulating film 7, the electric field relaxation effect near the bottom surface of the trench 6 can be increased, and various characteristics such as realizing a predetermined breakdown voltage can be ensured.

[0035] In addition, the gate insulating film 7 has a higher film density and better film quality than when annealing is performed under predetermined conditions (hereinafter referred to as post-HTO deposition annealing: step S5 in FIG. 3) after the deposition of the gate insulating film 7, compared to the case of performing post-HTO deposition annealing under conventional conditions (post-HTO deposition annealing conditions of a conventional example described later: see FIG. 6). FIG. 6 shows only the film density of the HTO film (corresponding to the gate insulating film 7) on the m plane. Although not shown, the film density of the HTO film on the Si plane and the C plane is higher than that of the HTO film on the m plane. The film density of the gate insulating film 7 on the m plane has a value closer to the film density of the gate insulating film 7 on the Si plane and the C plane than before the post-HTO deposition annealing by annealing under the predetermined conditions described later.

[0036] Specifically, the overall film density of the gate insulating film 7 is, for example, 2.24 g / cm, which is the film density of the HTO film on the m plane before post-HTO deposition annealing, in the measurement by the XRR (X-Ray Reflectivity) method. 3 or more. More specifically, the film density of the gate insulating film 7 is, in the measurement by the XRR method, including the measurement error (±0.03 g / cm 3 ), for example, 2.21 g / cm or more within the range of 2.38 g / cm or less in the plane of the inner wall of the trench 6, and preferably higher than the film density (=2.26 g / cm 3 ) of the HTO film obtained by post-HTO deposition annealing under conventional conditions, for example, 2.27 g / cm or more in the plane of the side wall (m plane) of the trench 6 (see FIG. 6). 3 3 ) (see FIG. 6). 3

[0037] ​​Also, by increasing the film density of the gate insulating film 7 by annealing after HTO deposition under predetermined conditions to be described later, the thickness t1 of the gate insulating film 7 can be made relatively thinner, for example, to about 50 nm on the bottom surface of the trench 6 where it becomes slightly thinner. The thinner the thickness t1 of the gate insulating film 7, the lower the voltage applied to the gate electrode 8 (gate voltage) can be. Therefore, from the viewpoints of reliability and lifespan, it is preferable that the thickness t1 of the gate insulating film 7 is as thin as possible. In the present embodiment, the thickness t1 of the gate insulating film 7 can be, for example, about 50 nm or more and about 80 nm or less, which is the same as the thickness of the gate insulating film of a general trench gate type SiC-MOSFET.

[0038] Also, by performing annealing after HTO deposition under the predetermined conditions to be described later, the nitrogen concentration (nitrogen atom concentration) of nitrogen (N) atoms accumulated (piled up) at the SiC / SiO2 interface 20 is maintained at approximately the same level as when annealing is performed after HTO deposition under conventional conditions, and the nitrogen concentration (nitrogen atom concentration) in the gate insulating film 7 can be reduced compared to when annealing is performed after HTO deposition under conventional conditions (see FIG. 8). Specifically, the nitrogen concentration at the SiC / SiO2 interface 20 is, for example, 5×10 20 atoms / cm 3 or more. The average nitrogen concentration in the thickness direction of the gate insulating film 7 from the SiC / SiO2 interface 20 to the contact surface with the gate electrode 8 is, for example, 5×10 19 atoms / cm 3 or less.

[0039] Further, the gate insulating film 7 has a two-layer structure in which a low-density film 7a with a relatively low film density and a high-density film 7b with a relatively high film density are deposited in this order (see FIG. 2). In FIG. 2, the interface between the low-density film 7a and the high-density film 7b is indicated by a broken line. The low-density film 7a is a portion within a range t11 of 3 nm or less from the SiC / SiO2 interface 20 that contacts the semiconductor substrate 30 at the inner wall of the trench 6 among the gate insulating film 7. The low-density film 7a is a portion at the initial stage of deposition of the HTO film that becomes the gate insulating film 7, has a lower film density and inferior film quality than the high-density film 7b (see FIG. 5). The high-density film 7b is a portion in a range separated from the SiC / SiO2 interface 20 by 3 nm or more. The high-density film 7b is a portion of the gate insulating film 7 excluding the low-density film 7a, and contacts the low-density film 7a and the gate electrode 8.

[0040] Inside the trench 6, a gate electrode 8 is provided on the gate insulating film 7 so as to fill the trench 6. Although FIG. 1 shows only one unit cell (the constituent unit of the element) of the MOSFET, a plurality of unit cells having the same trench gate structure are arranged adjacent to each other on the semiconductor substrate 30. The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 8. In the contact hole of the interlayer insulating film 9, an n + -type source region 4 and a p ++ -type contact region 5 are exposed. The p ++ -type contact region 5 may not be provided. In this case, instead of the p ++ -type contact region 5, the p-type base region 3 reaches the front surface of the semiconductor substrate 30 and is exposed in the contact hole of the interlayer insulating film 9.

[0041] The source electrode 11 makes an ohmic contact with the n + -type source region 4 and the p ++ -type contact region 5 in the contact hole of the interlayer insulating film 9, and is electrically connected to the n + -type source region 4, the p ++ -type contact region 5, and the p-type base region 3. The p ++When the type - contact region 5 is not provided, the source electrode 11 makes an ohmic contact with the p - type base region 3 at the contact hole of the interlayer insulating film 9. On the entire back surface (the back surface of the n + - type starting substrate 31) of the semiconductor substrate 30, a drain electrode 12 is provided. The drain electrode 12 is in contact with the n + - type drain region 1 (the n + - type starting substrate 31) and is electrically connected to the n + - type drain region 1.

[0042] The operation of the silicon carbide semiconductor device 10 according to the embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 while a positive voltage (forward voltage) is applied to the drain electrode 12 with respect to the source electrode 11, a channel (n - type inversion layer) is formed in a portion along the side wall (m - plane) of the trench 6 in the p - type base region 3. Thereby, current flows from the n + - type drain region 1 through the channel toward the n + - type source region 4, and the MOSFET is turned on. Since the film density of the gate insulating film 7 is increased by the post - annealing of HTO deposition under predetermined conditions described later, even when the gate insulating film 7 is formed on the m - plane, the electrical characteristics and reliability of the MOSFET (silicon carbide semiconductor device 10) can be ensured.

[0043] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 8 while a forward voltage is applied between the source and the drain, the pn junctions (main junctions) between the p + - type regions 21, 22 and the p - type base region 3, and the n - type current diffusion region 23 and the n - - type drift region 2 are reverse - biased, so that current does not flow and the MOSFET maintains the off state. Also, as the depletion layer spreads from the pn junction to the p + - type regions 21, 22, the electric field applied to the gate insulating film 7 on the bottom surface of the trench 6 is relaxed. Further, since the bottom surface of the trench 6 is the Si - plane or the C - plane, the film quality of the gate insulating film 7 is good at the bottom surface of the trench 6, so that the electric - field relaxation effect is high near the bottom surface of the trench 6.

[0044] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 3 is a flowchart showing an outline of the method for manufacturing the semiconductor device according to the embodiment. First, for example, an n + -type starting substrate (starting wafer) 31 using 4H-SiC as a semiconductor material is prepared. The front surface of the n + -type starting substrate 31 is an Si surface or a C surface. After the RCA cleaning of the n + -type starting substrate 31, an n + -type epitaxial layer 32 to be the n - -type drift region 2 is epitaxially grown (deposited) on the front surface of the n - -type starting substrate 31 (step S1: part 1). The impurity concentration of the n - -type epitaxial layer 32 is, for example, about 1×10 16 / cm 3 .

[0045] RCA cleaning is a wet cleaning that performs SC-1 cleaning and SC-2 cleaning. In SC-1 cleaning, a semiconductor wafer is immersed and cleaned in a mixed aqueous solution of ammonium hydroxide (NH4OH), hydrogen chloride (HCl), and hydrogen peroxide (H2O2). In SC-1 cleaning, organic substances and particles on the surface of the semiconductor wafer (the contact surface with the mixed aqueous solution) are removed. SC-2 cleaning is performed after SC-1 cleaning. In SC-2 cleaning, a semiconductor wafer is immersed and cleaned in a mixed aqueous solution of hydrogen chloride (HCl) and hydrogen peroxide (H2O2). In SC-2 cleaning, metal ion contaminants on the surface of the semiconductor wafer are removed. A rinsing process with pure water (highly purified water: H2O) is performed between SC-1 cleaning and SC-2 cleaning.

[0046] Next, by photolithography and ion implantation of p-type impurities, p - -type regions 21 and the lower portions of the p + -type regions 22 (the portions on the n + -type drain region 1 side) are selectively formed so as to be alternately arranged at intervals on the surface region of the n + -type epitaxial layer 32. Also, by photolithography and ion implantation of n-type impurities, n- On the surface region of the p-type epitaxial layer 32, the lower part of the n-type current diffusion region 23 is formed between the adjacent p-type regions 21 and p-type regions 22. + type region 21 and p + type region 22. The part of the n-type epitaxial layer 32 on the side of the n-type starting substrate 31, which is closer to the n-type starting substrate 31 than the p-type regions 21, 22 and the n-type current diffusion region 23, becomes the n-type drift region 2. - type epitaxial layer 32, between the p + type regions 21, 22 and the n-type current diffusion region 23, forms the lower part of the n-type current diffusion region 23. + type starting substrate 31 side becomes the n - type drift region 2.

[0047] Next, further epitaxial growth is performed to thicken the n-type epitaxial layer 32 to a predetermined thickness. Next, by photolithography and ion implantation of p-type impurities, on the thickened part of the n-type epitaxial layer 32, the upper part of the p-type region 22 (the part on the side of the n-type source region 4) is selectively formed. Also, by photolithography and ion implantation of n-type impurities, on the thickened part of the n-type epitaxial layer 32, the upper part of the n-type current diffusion region 23 is formed. - type epitaxial layer 32 is thickened to a predetermined thickness. Next, by photolithography and ion implantation of p-type impurities, on the thickened part of the n-type epitaxial layer 32, the upper part of the p-type region 22 (the part on the side of the n-type source region 4) is selectively formed. Also, by photolithography and ion implantation of n-type impurities, on the thickened part of the n-type epitaxial layer 32, the upper part of the n-type current diffusion region 23 is formed. - type epitaxial layer 32, the upper part of the p + type region 22 (the part on the side of the n + type source region 4) is selectively formed. Also, by photolithography and ion implantation of n-type impurities, on the thickened part of the n-type epitaxial layer 32, the upper part of the n-type current diffusion region 23 is formed. - type epitaxial layer 32, the upper part of the n-type current diffusion region 23 is formed. The upper part of the p + type region 22 and the upper part of the n-type current diffusion region 23 are formed at positions facing the lower part of the p + type region 22 and the lower part of the n-type current diffusion region 23 in the depth direction, respectively, and are connected to the lower part of the p + type region 22 and the lower part of the n-type current diffusion region 23, respectively.

[0048] Next, on the n - type epitaxial layer 32, a p-type epitaxial layer 33 that becomes the p-type base region 3 is epitaxially grown (deposited) (Step S1: Part 2). Through the steps so far, a semiconductor substrate (semiconductor wafer) 30 with the epitaxial layers 32 and 33 laminated in order on the front surface of the n + type starting substrate 31 is fabricated (manufactured). Next, photolithography and ion implantation are repeatedly performed under different conditions, and on the surface region of the p-type epitaxial layer 33, the n + type source region 4 and p ++Selectively form the type contact regions 5 respectively (step S2). Of the p-type epitaxial layer 33, the portion on the n + type source region 4 and the p ++ type contact region 5 closer to the n - type epitaxial layer 32 side becomes the p-type base region 3.

[0049] Next, for all the diffusion regions (p + type regions 21, 22, n-type current diffusion region 23, n + type source region 4 and p ++ type contact region 5) formed by ion implantation, perform a heat treatment for impurity activation. The heat treatment for impurity activation may be performed each time a diffusion region is formed by ion implantation. Next, by photolithography and etching, a trench 6 is formed that penetrates the n + type source region 4 and the p-type base region 3 from the front surface of the semiconductor substrate 30 (the surface of the p-type epitaxial layer 33) in the depth direction and reaches the n-type current diffusion region 23 (step S3: first step). The bottom surface of the trench 6 exposes the same crystal plane (Si plane or C plane) as the front surface of the semiconductor substrate 30, and the side walls of the trench 6 are m planes.

[0050] Next, after RCA cleaning, High-temperature acidification deposit a SiO2 film (HTO film) to be the gate insulating film 7 with a predetermined thickness t1 (step S4: second step). In the process of step S4, the thickness of the HTO film deposited as the gate insulating film 7 is the thickest at the portion on the front surface of the semiconductor substrate 30 and becomes thinner as it approaches the bottom surface of the trench 6 along the inner wall of the trench 6. Also, the portion within a range t11 of 3 nm or less from the SiC / SiO2 interface 20 at the initial stage of the deposition of the gate insulating film 7 becomes a low-density film 7a with a relatively low film density. The gate insulating film 7 becomes a high-density film 7b with a relatively high film density at the portion more than 3 nm away from the SiC / SiO2 interface 20 on which it is deposited on the low-density film 7a.

[0051] Next, a heat treatment (Post HTO Annealing) is performed at a temperature of, for example, 1250°C or higher and 1300°C or lower in a mixed gas atmosphere of nitrogen monoxide (NO), nitrogen (N2), and oxygen (O2) (Step S5: Third step). By performing the Post HTO Annealing in Step S5 under the above conditions, compared with the case of performing the Post HTO Annealing in a conventional condition (a mixed gas atmosphere of nitrogen monoxide and nitrogen only), the densification of the gate insulating film 7 progresses, and the film density of the gate insulating film 7 can be increased overall to be within the predetermined range described above. In addition, the film density of the gate insulating film 7 on the m-plane with a relatively low film density can be made close to the film density of the gate insulating film 7 on other crystal planes.

[0052] In the Post HTO Annealing in Step S5, the total oxygen (O2) flow rate in the mixed gas atmosphere of nitrogen monoxide, nitrogen, and oxygen (the total flow rate of oxygen molecules generated by oxygen atoms in nitrogen monoxide and oxygen molecules in oxygen gas introduced into the furnace) is preferably, for example, about 5% or less. By setting the total oxygen flow rate in the mixed gas atmosphere of nitrogen monoxide, nitrogen, and oxygen to about 5% or less, the oxygen partial pressure of the mixed gas atmosphere is made as low as possible, so that oxygen atoms reach the SiC / SiO2 interface 20 and the densification of the gate insulating film 7 progresses overall, and the re-oxidation of SiC (epitaxial layers 32, 33 forming the inner wall surface of the trench 6) at the SiC / SiO2 interface 20 can be suppressed.

[0053] Also, by the Post HTO Annealing in Step S5, the nitrogen concentration (nitrogen atom concentration) of nitrogen atoms accumulated at the SiC / SiO2 interface 20 is maintained at approximately the same level as in the case of performing the Post HTO Annealing under conventional conditions, and the nitrogen concentration (nitrogen atom concentration) in the gate insulating film 7 can be reduced compared with the case of performing the Post HTO Annealing under conventional conditions. By maintaining the nitrogen concentration at the SiC / SiO2 interface 20, the channel mobility can be increased to approximately the same level as in the Post HTO Annealing under conventional conditions. By reducing the nitrogen concentration in the gate insulating film 7 compared with the Post HTO Annealing under conventional conditions, the gate threshold voltage can be lowered, and the gate threshold voltage fluctuation can be suppressed and stabilized.

[0054] The higher the temperature of the annealing after HTO deposition in step S5, the higher the film density of the gate insulating film 7. However, when the temperature of the annealing after HTO deposition in step S5 exceeds 1300°C, the post-oxidation of SiC at the SiC / SiO2 interface 20 progresses too much. Also, the nitrogen concentration at the SiC / SiO2 interface 20 deviates from the appropriate value whether the temperature of the annealing after HTO deposition in step S5 is too high or too low, and becomes the appropriate value at about 1300°C. If the temperature of the annealing after HTO deposition in step S5 is about 1250°C or higher and 1300°C or lower, the film density of the gate insulating film 7 becomes relatively high, the post-oxidation of SiC at the SiC / SiO2 interface 20 is suppressed, and the nitrogen concentration at the SiC / SiO2 interface 20 can be brought close to the appropriate value.

[0055] Specifically, for example, annealing after HTO deposition is performed at a temperature of 1250°C or higher in a mixed gas atmosphere with nitric oxide, nitrogen, and oxygen at ratios of 6%, 92%, and 2% respectively. More specifically, for example, nitric oxide gas, nitrogen gas, and oxygen gas are introduced into a vacuum-exhausted furnace at flow rates of 0.3 slm, 4.6 slm, and 0.1 slm respectively and the temperature is raised. A semiconductor substrate 30 is introduced into the furnace that has been heated to a temperature of about 700°C. Then, 5 slm of nitrogen gas is further introduced into the furnace to make the total oxygen flow rate of the mixed gas atmosphere of nitric oxide, nitrogen, and oxygen 5% or less, and the temperature of the furnace is raised to about 1300°C, and annealing after HTO deposition is performed for about 30 minutes.

[0056] Next, a polysilicon (poly-Si) layer is deposited on the front surface of the semiconductor substrate 30 so as to fill the inside of the trench 6. Then, the polysilicon layer is etched back, for example, to leave only inside the trench 6 to form the gate electrode 8 (step S6: the fourth step). Next, an interlayer insulating film 9 covering the gate electrode 8 is formed on the front surface of the semiconductor substrate 30. Next, surface electrodes serving as the source electrode 11 and the drain electrode 12 are formed on the front surface and the back surface of the semiconductor substrate 30, respectively, by a general method (step S7). Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, whereby the silicon carbide semiconductor device 10 shown in FIGS. 1 and 2 is completed.

[0057] As described above, according to the embodiment, High-temperature acidification By depositing a SiO2 film (HTO film) that becomes a gate insulating film, SiC (the epitaxial layer forming the inner wall surface of the trench) is less likely to be oxidized on the inner wall surface of the trench, as compared with the case of forming a SiO2 film (thermal oxide film) that becomes a gate insulating film by thermal oxidation. Excess carbon due to the thermal oxidation reaction of SiC is less likely to occur. For this reason, adverse effects on the interface characteristics of the SiC / SiO2 interface (such as defects in the gate insulating film and an increase in interface levels) can be suppressed, and element characteristic degradation can be suppressed.

[0058] Also, according to the embodiment, High-temperature acidification After deposition of the gate insulating film by, for example, annealing is performed at a temperature of about 1250° C. or higher and 1300° C. or lower in a mixed gas atmosphere of nitric oxide, nitrogen, and oxygen. Thereby, as compared with the case of performing annealing after HTO deposition under conventional conditions (a mixed gas atmosphere of only nitric oxide and nitrogen) mainly for improving channel mobility, the film density of the gate insulating film can be increased, so that the film quality of the gate insulating film is improved and the insulating performance of the gate insulating film can be increased. Thereby, leakage current can be reduced. In addition, the breakdown voltage tolerance of the gate insulating film can be improved.

[0059] Further, according to the embodiment, by improving the film quality of the gate insulating film, the thickness of the gate insulating film can be reduced. Therefore, the thickness of the gate insulating film can be reduced to lower the voltage applied to the gate electrode, and the endurance breakdown voltage of the gate insulating film can be improved. As a result, the life of the device can be extended and the reliability can be improved. Also, according to the embodiment, by setting the total oxygen flow rate in the mixed gas atmosphere of annealing after HTO deposition to 5% or less, the post-oxidation of SiC at the SiC / SiO2 interface is suppressed, so that the adverse effect of excess carbon on the interface characteristics of the SiC / SiO2 interface is further suppressed.

[0060] Also, according to the embodiment, by performing annealing after HTO deposition under the above-described predetermined conditions, the nitrogen concentration at the SiC / SiO2 interface is maintained at approximately the same level as when annealing after HTO deposition under conventional conditions, and the nitrogen concentration in the gate insulating film can be reduced as compared with the case of performing annealing after HTO deposition under conventional conditions. Therefore, electrical characteristics (such as channel mobility) approximately the same as those in the case of performing annealing after HTO deposition under conventional conditions can be obtained, and the gate threshold voltage can be lowered as compared with the case of performing annealing after HTO deposition under conventional conditions, and the variation in the gate threshold voltage can be suppressed and stabilized.

[0061] (Experimental Example) The film density of the HTO film ( High-temperature acidification SiO2 film deposited thereby) was verified. FIG. 4 is a chart showing the relationship between the thickness and the film density of the HTO film in the experimental example. FIG. 5 is a chart showing the relationship between the distance from the SiC / SiO2 interface and the film density of the HTO film in the experimental example. FIGS. 4 and 5 show the measured values (measurement error ±0.03 g / cm 3 ) of the film density of the HTO film not subjected to annealing after HTO deposition in step S5 (see FIG. 3) described above by the XRR method.

[0062] As an experimental example, a general High-temperature acidificationA plurality of flat samples on which a SiO2 film (HTO film) was deposited were prepared. Specifically, as experimental examples, three samples with different crystal planes (Si plane, C plane, and m plane) on the main surface of the epitaxial substrate (the SiC surface on which the HTO film was deposited) were prepared in pairs by varying the thickness of the HTO film (26 nm, 53 nm) (six in total).

[0063] More specifically, each sample in the experimental example was prepared on the main surface of a starting substrate made of SiC with the Si plane, C plane, and m plane as the main surfaces (hereinafter referred to as the Si plane substrate, C plane substrate, and m plane substrate), respectively, with a concentration of 1×10 16 / cm 3 of n - -type epitaxial layer epitaxially grown to a thickness of 5 μm using an epitaxial substrate. The Si plane substrate, C plane substrate, and m plane substrate were subjected to RCA cleaning before epitaxially growing the n - -type epitaxial layer.

[0064] The surface of the n - -type epitaxial layer of the samples prepared using the Si plane substrate and C plane substrate (i.e., the Si plane and C plane) corresponds to the bottom surface of the trench 6 of the silicon carbide semiconductor device 10 according to the above-described embodiment. The surface of the n - -type epitaxial layer of the sample prepared using the m plane substrate (i.e., the m plane) corresponds to the side wall of the trench 6 of the silicon carbide semiconductor device 10 according to the above-described embodiment.

[0065] For each of these epitaxial substrates prepared using the Si plane substrate, C plane substrate, and m plane substrate, after RCA cleaning, a HTO film with a predetermined thickness (26 nm or 53 nm) ( - SiO2 film by High-temperature acidification ) was deposited on the surface of the n

[0066] -type epitaxial layer (i.e., the Si plane, C plane, and m plane) using chemical vapor deposition (CVD) to prepare each sample in the experimental example. -The results of measuring the film density in the range more than 3 nm away from the interface between the type epitaxial layer and the HTO film (SiC / SiO2 interface) are shown in FIG. 4. From the results shown in FIG. 4, it was confirmed that the film density of the HTO film varies depending on the crystal plane on which it is deposited, and is lower on the m-plane than on the Si-plane and C-plane. Also, it was confirmed that the film density of the HTO film increases as the thickness increases.

[0067] Therefore, since the film quality of the gate insulating film 7 varies depending on on which crystal plane of SiC the gate electrode 8 is formed, it is advisable to increase the film density of the gate insulating film 7 as much as possible to improve the film quality of the gate insulating film 7. For example, in a trench gate structure, since an electric field concentrates near the bottom surface of the trench 6, it is advisable to use the Si-plane or C-plane as the bottom surface of the trench 6 to increase the film density of the gate insulating film 7 on the bottom surface of the trench 6.

[0068] Also, when the bottom surface of the trench 6 is the Si-plane or C-plane, the side wall of the trench 6 becomes the m-plane, so it is particularly necessary to increase the film density of the gate insulating film 7. Since the film density of the gate insulating film 7 can be increased by the annealing after HTO deposition in step S5 described above, this embodiment is suitable for a trench gate structure. Also, by increasing the film density of the gate insulating film 7 to improve the film quality of the gate insulating film 7, it is also possible to thin the gate insulating film 7.

[0069] FIG. 5 shows the results of measuring the film density of the HTO film in the portion within 3 nm from the SiC / SiO2 interface and the portion more than 3 nm away from the SiC / SiO2 interface for a sample with the HTO film thickness of 53 nm in the experimental example. From the results shown in FIG. 5, it was confirmed that the film density of the HTO film is lower in the portion within 3 nm from the SiC / SiO2 interface than in the portion more than 3 nm away from the SiC / SiO2 interface.

[0070] (Example) The annealing conditions after HTO deposition in step S5 of the manufacturing method of the silicon carbide semiconductor device 10 according to the above-described embodiment (see FIG. 3) were verified. FIG. 6 is a chart showing the relationship between the film density of the HTO film and the annealing conditions after HTO deposition. FIG. 7 is a characteristic diagram showing the secondary ion intensity distribution of oxygen in the HTO film of the example. FIG. 8 is a characteristic diagram showing the nitrogen concentration distribution at the SiC / SiO2 interface and in the HTO film of the example.

[0071] Among the samples of the above-described experimental examples, a plurality of samples in which an HTO film was deposited on the m-plane with a thickness of 53 nm (the sample in the bottom row of FIG. 5) were prepared, and annealing after HTO deposition was performed under different conditions (hereinafter referred to as examples, conventional examples, and comparative examples). Regarding the HTO films of these samples after annealing after HTO deposition, the film density in the range of 3 nm or more away from the interface (SiC / SiO2 interface) between the n-type epitaxial layer and the HTO film was measured by the XRR method (measurement error ±0.03 g / cm 3 ) and the results are shown in FIG. 6. - The results of measuring the film density in the range of 3 nm or more away from the interface (SiC / SiO2 interface) between the n-type epitaxial layer and the HTO film of the sample of the example before annealing after HTO deposition (the sample in the bottom row of FIG. 5, hereinafter referred to as the reference example) are also shown in FIG. 6.

[0072] In the example, according to the annealing conditions after HTO deposition in step S5, annealing after HTO deposition was performed at a temperature of 1300 ° C for about 30 minutes in a mixed gas atmosphere with the ratios of nitrogen monoxide, nitrogen, and oxygen being 6%, 92%, and 2% respectively. In the conventional example, the gas atmosphere for annealing after HTO deposition was a mixed gas atmosphere with the ratios of nitrogen monoxide and nitrogen being 10% (flow rate of 0.5 slm) and 90% (flow rate of 4.5 slm) respectively.

[0073] In the comparative example, the gas atmosphere for annealing after HTO deposition was a mixed gas atmosphere with the ratios of nitrogen and oxygen being 95% and 5% respectively. The temperature and time of annealing after HTO deposition in the conventional example and the comparative example were the same as those in the example. Also, FIG. 6 shows

[0074] From the results shown in FIG. 6, it was confirmed that by performing annealing after HTO deposition as in the examples, conventional examples, and comparative examples, the film density of the HTO film can be increased compared to the reference example where annealing after HTO deposition was not performed. Also, it was confirmed that the examples can achieve a higher film density of the HTO film than the conventional examples. The HTO film of the examples corresponds to the gate insulating film 7 in FIG. 1. It was confirmed that the film density of the HTO film in the comparative examples is almost the same as that of the conventional examples.

[0075] In the examples, conventional examples, and comparative examples, the total oxygen flow rate in the mixed gas atmosphere during annealing after HTO deposition is the same as 5%. Therefore, it was confirmed that what contributes to the improvement of the film density of the HTO film is not to adjust the total oxygen flow rate in the mixed gas atmosphere during annealing after HTO deposition, but rather it is necessary to introduce nitric oxide gas, nitrogen gas, and oxygen gas to generate a mixed gas atmosphere as in the annealing after HTO deposition in the examples.

[0076] However, it is advisable to minimize the oxygen partial pressure in the mixed gas atmosphere during annealing after HTO deposition to suppress the post-oxidation of SiC (n-type epitaxial layer) at the SiC / SiO2 interface. For example, in both the examples and the conventional examples, the total oxygen flow rate in the mixed gas atmosphere during annealing after HTO deposition is the same as 5%, but in the conventional examples, it has been confirmed by the inventor that SiC is post-oxidized to a thickness of about 4 nm at the SiC / SiO2 interface (not shown). - On the other hand, in the examples, even when the total oxygen flow rate in the mixed gas atmosphere is the same as that in the conventional examples, the thickness t21 of the post-oxidation of SiC at the SiC / SiO2 interface (corresponding to the SiC / SiO2 interface 20 in FIG. 1) can be made thinner than that in the conventional examples and be about 2 nm or less (see FIG. 7 described later). Therefore, the total oxygen flow rate in the mixed gas atmosphere for annealing after HTO deposition in step S5 is preferably set to about 5% at most, which is the same as the total oxygen flow rate for annealing after HTO deposition in the conventional examples.

[0077]

[0078] ​The results of simulating the secondary ion intensity distribution of oxygen in the HTO films of the examples and reference examples by secondary ion mass spectrometry (SIMS) are shown in FIG. 7. From the results shown in FIG. 7, in the examples, SiC was post-oxidized at a thickness t21 of about 2 nm or less at the SiC / SiO2 interface, and it was confirmed that the thickness of the SiO2 film (corresponding to the thickness t1 of the gate insulating film 7 in FIG. 1) was greater than that of the reference example.

[0079] In a conventional example (not shown), SiC was post-oxidized at a thickness of about 4 nm at the SiC / SiO2 interface. For this reason, it was confirmed that in the examples, post-oxidation of SiC during annealing after HTO deposition can be suppressed. In FIG. 7, since the interface between the n - type epitaxial layer and the HTO film (SiC / SiO2 interface) is used as a reference, the depth = 0 nm on the horizontal axis of FIG. 7 is the surface of the HTO film in the example, and the surface of the HTO film in the reference example is at the position of the depth = t21 on the horizontal axis of FIG. 7.

[0080] Also, in the examples, it was confirmed that by post-oxidizing SiC at the SiC / SiO2 interface, oxygen atoms can reach near the SiC / SiO2 interface during annealing after HTO deposition, and the densification of the HTO film can be advanced as a whole. Therefore, it was confirmed that the annealing after HTO deposition in step S5 has the effects of suppressing the post-oxidation of SiC and improving the film density of the HTO film near the SiC / SiO2 interface.

[0081] The results of simulating the nitrogen concentration distributions in the SiC / SiO2 interfaces and HTO films of the examples and conventional examples by SIMS are shown in FIG. 8. From the results shown in FIG. 8, it was confirmed that in the examples, the nitrogen concentration at the SiC / SiO2 interface is maintained at approximately the same level as in the conventional examples. Therefore, it was confirmed that the annealing after HTO deposition in step S5 can improve the film density of the gate insulating film 7 without adversely affecting the electrical characteristics.

[0082] Also, from the results shown in FIG. 8, it was confirmed that in the examples, the nitrogen concentration in the HTO film can be reduced compared to the conventional examples. Therefore, it was confirmed that the annealing after HTO deposition in step S5 also has the effect of reducing the nitrogen concentration in the gate insulating film 7. As a result, the gate threshold voltage can be made lower than in the conventional examples, and the variation in the gate threshold voltage can be suppressed and stabilized.

[0083] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be applied to a vertical IGBT (Insulated Gate Bipolar Transistor) or a vertical SJ-MOSFET that can adopt a trench gate structure instead of a vertical MOSFET. An SJ-MOSFET is a MOSFET having a super junction (SJ: Super Junction) structure in which a drift layer is formed as a parallel pn layer in which an n-type region and a p-type region with increased impurity concentration are alternately and repeatedly adjacent to each other in a direction parallel to the front surface of the semiconductor substrate.

Industrial Applicability

[0084] As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, etc., and particularly suitable for an element structure in which a gate insulating film is provided on an m-plane where the film density of the gate insulating film is relatively low (for example, a trench gate structure in which a channel is formed along the m-plane).

Explanation of Signs

[0085] 1 n + Type Drain Region 2 n - Type Drift Region 3 p-Type Base Region 4 n + Type Source Region 5 p ++ Type Contact Region 6 Trench 7 Gate Insulating Film (HTO Film) 7a Low-Density Film of Gate Insulating Film 7b High-Density Film of Gate Insulating Film 8 Gate Electrode 9 Interlayer Insulating Film 10 Silicon Carbide Semiconductor Device 11 Source Electrode 12 Drain Electrode 20 Junction Interface between Inner Wall of Trench and Gate Insulating Film (SiC / SiO2 Interface) 21, 22 p + -Type Region 23 n-Type Current Diffusion Region 30 Semiconductor Substrate 31 n + -Type Starting Substrate 32 n - -Type Epitaxial Layer 33 p-Type Epitaxial Layer t1 Thickness of Gate Insulating Film (HTO Film) t11 Thickness of Low-Density Film of Gate Insulating Film

Claims

1. A silicon carbide semiconductor device having an insulated gate composed of a three-layer structure of gate - oxide film - semiconductor, comprising: a semiconductor substrate made of silicon carbide, which constitutes the semiconductor; a trench having a predetermined depth extending in a direction perpendicular to the first main surface of the semiconductor substrate from the first main surface of the semiconductor substrate; a gate insulating film that forms the oxide film and is provided along the inner wall of the trench and contacts the semiconductor substrate at the inner wall of the trench; a gate electrode that forms the gate and is provided on the gate insulating film inside the trench; characterized in that: it is a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during on - state; the first main surface of the semiconductor substrate is an Si surface or a C surface; the side wall of the trench is an m surface; the gate insulating film is a silicon oxide film with a thickness of 50 nm or more deposited by high - temperature oxidation. The film density of the gate insulating film is 2.21 g / cm within the plane of the inner wall of the trench 3 or more and 2.38 g / cm 3 or less, and the film density on the bottom surface of the trench is higher than that on the side wall portion of the trench. A silicon carbide semiconductor device characterized by this.

2. The film density of the gate insulating film is 2.27 g / cm within the plane of the side wall of the trench. 3 The silicon carbide semiconductor device according to claim 1, characterized in that it is 3 or more.

3. The gate insulating film: is a low - density film within a range of 3 nm or less from the interface between the semiconductor substrate and the gate insulating film, which contacts the semiconductor substrate at the inner wall of the trench; and is a two - layer structure including a high - density film that is a portion more than 3 nm away from the interface between the semiconductor substrate and the gate insulating film, contacts the low - density film and the gate electrode, and has a higher film density than the low - density film. The silicon carbide semiconductor device according to claim 1 or 2.

4. The nitrogen concentration at the interface between the semiconductor substrate and the gate insulating film is 5×10 20 atoms / cm 3 or more. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that.

5. The average nitrogen concentration in the thickness direction of the gate insulating film from the interface between the semiconductor substrate and the gate insulating film to the contact surface with the gate electrode is 5×10 19 atoms / cm 3 or less. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that.

6. The thickness of the gate insulating film is thinner at the bottom surface portion than at the side wall portion on the side wall of the trench. The silicon carbide semiconductor device according to any one of claims 1 to 5.

7. A method for manufacturing a silicon carbide semiconductor device having an insulated gate composed of a three - layer structure of gate - oxide film - semiconductor, comprising: a first step of forming a trench having a predetermined depth extending in a direction perpendicular to the first main surface of a semiconductor substrate made of silicon carbide, which constitutes the semiconductor, from the first main surface of the semiconductor substrate; a second step of forming a gate insulating film that forms the oxide film along the inner wall of the trench on the inner wall of the trench; a third step of annealing the gate insulating film by heat treatment; a fourth step of forming a gate electrode that forms the gate on the gate insulating film inside the trench after the third step, thereby forming a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during on - state; including: The first main surface of the semiconductor substrate is set as an Si surface or a C surface, the side wall of the trench is set as an m surface, in the second step, as the gate insulating film, a silicon oxide film with a thickness of 50 nm or more is deposited by high-temperature oxidation, in the third step, the heat treatment is performed at a temperature of 1250°C or higher and 1300°C or lower in an atmosphere of a mixed gas of nitrogen monoxide, nitrogen, and oxygen, a method for manufacturing a silicon carbide semiconductor device, characterized in that the film density of the gate insulating film is in the range of 2.21 g / cm3 or more and 2.38 g / cm3 or less in the plane of the inner wall of the trench, and is higher at the bottom surface of the trench than at the portion on the side wall of the trench.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, characterized in that in the third step, the total oxygen flow rate in the mixed gas atmosphere is 5% or less.

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