Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of preventing displacement of mask alignment and suppressing increases of ON resistance and a forward voltage of a body diode.SOLUTION: A semiconductor device comprises an active region 40 in which a semiconductor element is provided, and a terminal region 42 enclosing the active region 40. The semiconductor element includes: an n- type drift layer 2; n+ type current diffusion regions (4a and 6a) which are provided on the drift layer 2 and of which the impurity density is higher than that of the drift layer 2; a p type base region 8 provided on the current diffusion regions (4a and 6a); a p+ type base contact region 9 which is provided on the base region 8 and of which the impurity density is higher than that of the base region 8; and an n+ type main electrode region 10 which is provided in contact with the base contact region 9 in an upper part of the base region 8 and of which the impurity density is higher than that of the drift layer 2. The impurity density of the base contact region 9 is higher than an impurity density of a source region 10.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that suppresses an increase in contact resistance and a method for manufacturing the same.

Background Art

[0002] In a MOS field effect transistor (MOSFET) using silicon (Si), an n+-type source region with high-concentration impurity addition is formed in a p-type well region by a double diffusion method. On the other hand, the diffusion coefficient of impurity atoms in a silicon carbide (SiC) substrate is extremely small, and the double diffusion method cannot be applied. Therefore, in a MOSFET using SiC, a p-type well region and an n+-type source region are formed in the well region by a double ion implantation method. In this method, a large number of crystal defects are induced by high-concentration ion implantation. As a result, an increase in contact resistance and on-resistance occurs. To solve such problems, a technique has been proposed in which a p-type well region is deposited and a high-concentration source region is selectively formed by an ion implantation method (see Patent Document 1).

[0003] In recent years, in a MOSFET using SiC, a p-type base contact layer and an n-type source region are formed adjacent to each other on a p-type base region. Usually, first, an n-type source region is selectively formed by an ion implantation method, and then a p-type base contact region is selectively formed by an ion implantation method so as to be in contact with the source region. The impurity density is on the order of several tens (in the tens) in both the source region and the base contact region. In this case, due to misalignment of the mask alignment for selective ion implantation of the base contact region, the base contact region may overlap with the source region. Since the impurity densities implanted into the source region and the base contact region are approximately the same, the overlapping portion becomes highly resistive due to carrier compensation. As a result, the contact resistance increases, leading to an increase in on-resistance and an increase in the forward voltage of the body diode. 20 , 20 , -3 , + , + , type base con tact layer and n + type source region are formed adjacent to each other. Usually, first, an n-type source region is selectively formed by an ion implantation method, and then a p-type base contact region is selectively formed by an ion implantation method so as to be in contact with the source region. The impurity density is on the order of several tens (in the tens) in both the source region and the base contact region. In this case, due to misalignment of the mask alignment for selective ion implantation of the base contact region, the base contact region may overlap with the source region. Since the impurity densities implanted into the source region and the base contact region are approximately the same, the overlapping portion becomes highly resistive due to carrier compensation. As a result, the contact resistance increases, leading to an increase in on-resistance and an increase in the forward voltage of the body diode. 20 cm -3 level (10 20 level). In this case, due to misalignment of the mask alignment for selective ion implantation of the base contact region, the base contact region may overlap with the source region. Since the impurity densities implanted into the source region and the base contact region are approximately the same, the overlapping portion becomes highly resistive due to carrier compensation. As a result, the contact resistance increases, leading to an increase in on-resistance and an increase in the forward voltage of the body diode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent misalignment of mask alignment and suppress an increase in on-resistance and the forward voltage of a body diode.

Means for Solving the Problems

[0006] One aspect of the present invention is a method for manufacturing a silicon carbide semiconductor device including an active region and a termination region surrounding the active region, the method including: (a) an ion implantation step of implanting an impurity element exhibiting a first conductivity type onto the surface of a base region of a second conductivity type provided above a drift layer of a first conductivity type to form an impurity element implantation region; (b) a step of selectively removing a semiconductor layer including the impurity element implantation region in the termination region; and (c) a step of selectively removing a semiconductor layer including the impurity element implantation region in the active region, and an etching step of forming a step in the termination region and a trench in the active region, and the gist is that it is a method for manufacturing a silicon carbide semiconductor device.

[0007] Another aspect of the present invention is a silicon carbide semiconductor device including a metal-containing layer containing a metal, a trench at least partially provided below the metal-containing layer via an interlayer insulating film, a drift layer of a first conductivity type, and a semiconductor region of a second conductivity type having at least a part of an upper surface in contact with the metal-containing layer and at least a part of a bottom surface in contact with the drift layer below the trench, the silicon carbide semiconductor device including: (a) an impurity element implantation region in which an impurity element exhibiting a first conductivity type is ion-implanted, the impurity element implantation region having at least a part of an upper surface in contact with the metal-containing layer and being adjacent to the trench; and (b) a step formed by removing a part of a semiconductor layer in a termination region surrounding an active region, the semiconductor region having a base region in contact with at least a part of a bottom surface of the impurity element implantation region, and a base contact region provided from an upper surface of the semiconductor region inward and having a higher impurity density than the impurity element implantation region, at least a part of the base contact region being doped with both an impurity element and a second impurity element exhibiting a second conductivity type, the impurity density of the second impurity element being higher than the impurity density of the impurity element. The gist of the invention is a silicon carbide semiconductor device in which the impurity element implantation region has a first side surface which is an inclined surface in contact with the step and a second side surface which is asymmetric with the first side surface and in contact with the trench.

Advantages of the Invention

[0008] According to the present invention, misalignment of mask alignment can be prevented, and a semiconductor device and a method for manufacturing the same can be provided.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, with reference to the drawings, the first and second embodiments of the present invention will be described. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different even between the drawings. Further, the first and second embodiments shown below illustrate apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as the following ones.

[0011] In this specification, the "first main electrode region" means a semiconductor region that becomes either the source region or the drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), it means a semiconductor region that becomes either the emitter region or the collector region. Also, in a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), it means a semiconductor region that becomes either the anode region or the cathode region. The "second main electrode region" means a semiconductor region that becomes either the source region or the drain region that is not the first main electrode region in an FET or an SIT. In an IGBT, it means a region that becomes either the emitter region or the collector region that is not the first main electrode region. In an SI thyristor or a GTO, it means a region that becomes either the anode region or the cathode region that is not the first main electrode region. Thus, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. If the bias relationship is exchanged, in an FET or the like, the functions of the "first main electrode region" and the "second main electrode region" can be exchanged.

[0012] In addition, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse. In the following description, the case where the first conductivity type is n-type and the second conductivity type, which is the opposite conductivity type to the first conductivity type, is p-type will be exemplified. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type, which is the opposite conductivity type to the first conductivity type, being n-type. Also, + and - attached to n and p mean semiconductor regions with relatively higher or lower impurity densities compared to the semiconductor regions without + and - attached. However, even for semiconductor regions with the same n attached, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same.

[0013] As described below, one of the features of the present invention is that it is characterized by preventing an increase in contact resistance due to misalignment of mask alignment. That is, the present invention exhibits a remarkable effect in preventing an increase in the on-resistance of an insulated-gate transistor such as a MOS transistor and the forward voltage of a body diode. The insulated-gate transistor can more comprehensively be referred to as a "MIS transistor", and MIS transistors include MISFETs and MISSITs. Note that since there is also a MIS composite type SI thyristor, the present invention can also be applied to SI thyristors. Also, it is possible to suppress the leakage current at the interface between the insulating film layer and the semiconductor layer, which is the breakdown voltage structure of the peripheral part of the power semiconductor device. In the following description of the embodiments, for convenience, as shown in FIG. 2, a MOS transistor having a trench gate structure will be exemplarily described as a representative example. However, for a planar structure such as a MOS transistor having a planar gate structure, it will be apparent to those skilled in the art from the following description that the same effect can be achieved if the gist of the present invention is understood.

[0014] (Embodiment) As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an active region 40 and a mesa-structured termination region 42 disposed around and surrounding the active region 40. In FIG. 1, a case is illustrated in which a MOSFET having a trench gate structure provided on the upper part of a drift layer 2 of the first conductivity type (n - type) is included as an active element.

[0015] In the active region 40, on the upper surface of the drift layer 2, n + type current spreading regions (CSL) (4a, 6a) having a higher impurity density than the drift layer 2 are disposed. On the upper surfaces of the current spreading regions (4a, 6a), a base region 8 of the second conductivity type (p-type) is disposed. The drift layer 2 and the base region 8 are each constituted by an epitaxial growth layer made of SiC (hereinafter abbreviated as "epitaxial layer"). The current spreading regions (4a, 6a) are constituted by implantation layers 4a, 6a formed by ion-implanting n-type impurities into the epitaxial layer.

[0016] On the upper part of the base region 8, a p+-type base contact region 9 having a higher impurity density than the base region 8 is selectively provided. On the upper part of the base region 8, an n + type first main electrode region (source region) 10 having a higher impurity density than the current spreading regions (4a, 6a) is selectively provided so as to be in contact with the base contact region 9. The base contact region 9 is formed by ion-implanting a p-type impurity, for example, aluminum (Al), to have an impurity density of 1×10 20 cm -3 ~10×10 20 cm -3 The source region 10 is formed by ion-implanting an n-type impurity, for example, phosphorus (P), to have an impurity density of 1×10 19 cm -3 ~10×10 19 cm -3It is provided by ion implantation so as to have an impurity density. The impurity density of the source region 10 is desirably about 1 / 2 or less of the impurity density of the base contact region 9. The depth Dp between the upper surface and the bottom surface of the base contact region 9 is about 0.4 μm to 0.6 μm, and the depth Dn between the upper surface and the bottom surface of the main electrode region 10 is about 0.2 μm to 0.5 μm.

[0017] A trench 11 is provided penetrating through the base region 8 from the upper surfaces of the source region 10 and the base region 8. A gate insulating film 12 is provided on the bottom surface and the side surfaces of the trench 11. As the gate insulating film 12, in addition to a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, any one of single-layer films or a composite film formed by laminating a plurality of these can be adopted.

[0018] A gate electrode 13 is embedded in the trench 11 via the gate insulating film 12. As the material of the gate electrode 13, for example, a polysilicon layer (doped polysilicon layer) doped with an impurity such as phosphorus (P) at a high impurity density can be used.

[0019] Inside the current diffusion regions (4a, 6a), a p + -type gate bottom protection region 5b is provided in contact with the bottom of the trench 11. Inside the current diffusion regions (4a, 6a), below the base contact region 9, at the same depth as the gate bottom protection region 5b and separated from the gate bottom protection region 5b, a first base bottom embedded region 5a is provided. Above the current diffusion regions (4a, 6a), a second base bottom embedded region 7a is provided so as to be sandwiched between the upper surface of the first base bottom embedded region 5a and the lower surface of the base region 8.

[0020] On the upper surface of the gate electrode 13, a source electrode (not shown) is disposed separately from a gate surface electrode (not shown) located behind the paper surface via an interlayer insulating film 14. As the interlayer insulating film 14, a non-doped silicon oxide film (SiO2 film) called "NSG" that does not contain phosphorus (P) or boron (B) can be adopted. However, as the interlayer insulating film 14, a silicon oxide film added with phosphorus (PSG), a silicon oxide film added with boron (BSG), a silicon oxide film added with boron and phosphorus (BPSG), a silicon nitride film (Si3N4), or the like may also be used. Below the source electrode, a source contact layer 15, a lower barrier metal layer 16, and an upper barrier metal layer 17 are disposed. The source contact layer 15 is disposed so as to be metallurgically in contact with each of the source region 8 and the base contact region 9. For example, a nickel (Ni) film can be used as the source contact layer 15, a titanium nitride (TiN) film can be used as the lower barrier metal layer 16, and a stacked structure of titanium (Ti) / TiN / Ti can be used as the upper barrier metal layer 16. As the source electrode, for example, an aluminum (Al) film can be used. The same material as the source electrode can be used for the gate surface electrode.

[0021] On the lower surface of the drift layer 2, an n + type second main electrode region (drain region) 1 is disposed. The drain region 1 is composed of a semiconductor substrate (SiC substrate) made of SiC. On the lower surface of the drain region 1, a second main electrode (drain electrode) 19 is disposed. As the drain electrode 19, for example, a single-layer film made of gold (Au) or a metal film stacked in the order of Al, nickel (Ni), and Au can be used, and a metal film such as molybdenum (Mo) or tungsten (W) can be further stacked on the lowermost layer thereof.

[0022] Focusing on the terminal region 42 side located on the right side of FIG. 1, an n-type mesa bottom layer 3 having the same thickness as the first base bottom implant region 5a, the gate bottom protection region 5b, etc. provided in the active region 40 is disposed on the upper surface of the drift layer 2 to form the bottom surface of the mesa structure. Along the bottom surface of the mesa structure, a channel stopper region (4b, 6b) of the first conductivity type with a higher impurity density than the mesa bottom layer 3 is provided from the mesa bottom layer 3 side toward the outer edge of the terminal region 42. On the mesa surface located on the active region 40 side of the terminal region 42, the base contact region 9 and the ends of the base region 8 are exposed. Between the upper surface of the drift layer 2 and the lower surface of the base region 9, a relaxation region (5c, 7b) of the second conductivity type with a higher impurity density than the base region 8 is inserted. The relaxation region (5c, 7b) extends toward the active region 40 side inside the portion of the mesa structure. A mesa slope is provided so as to descend from the base contact region 9 through the base region 8 to the relaxation region (5c, 7b). A junction termination extension (JTE) region 18 is provided inside the mesa bottom layer 3 from the lower end of the mesa slope toward the outer edge. The JTE region 18 includes a plurality of p-type spatially modulated portions 18a, 18b, 18c, 18d.

[0023] FIG. 2 is an impurity distribution measured from the upper surface of the base contact region 9 toward the base region 8. As shown in FIG. 2, in addition to p-type impurity Al, n-type impurity P implanted into the source region 10 is also simultaneously implanted into the base contact region 9. Note that an ion implantation mask for forming the base contact region 9 is prepared so that only P is implanted into the source region 10, and selective ion implantation is performed. Al is implanted at a depth of about 0.5 μm from the upper surface to have an impurity density of up to 3×10 20 cm -3 or so. P is implanted at a depth of about 0.4 μm from the upper surface to have an impurity density of up to 3×10 19 cm -3It is implanted so as to have an impurity density of a certain level. In the semiconductor device according to an embodiment of the present invention, the dose amount of impurity ions implanted into the source region 10 is adjusted so that the impurity density implanted into the source region 10 is 1 / 2 or less of the impurity density implanted into the base contact region 9. Preferably, the dose amount of impurity ions implanted into the source region 10 may be adjusted so that the impurity density implanted into the source region 10 is about 1 / 5 or less of the impurity density implanted into the base contact region 9. As can be seen from FIG. 2, more preferably, the dose amount is adjusted so that the impurity density implanted into the source region 10 is about 1 / 10 or less of the impurity density implanted into the base contact region 9. Also, the implantation depth of the source region 10 is made 0.05 μm or more shallower than the implantation depth of the base contact region 9. Therefore, the impurity density of the base contact region 9 is always higher than that of the source region 10 in the region reaching the base region 8. As a result, even if the ion implantation regions of the source region 10 and the base contact region 9 overlap, the overlapping portion does not become highly resistive due to carrier compensation. In the case of n-type, an ohmic contact can be formed even when the impurity density is about 1×10 19 cm -3 . On the other hand, in the case of p-type, when it is less than 1×10 20 cm -3 , it becomes difficult to form an ohmic contact.

[0024] FIG. 3 shows, as a comparative example, the impurity distribution of a base contact region in which p-type impurities and n-type impurities are implanted at about the same implantation amount as in the prior art. As shown in FIG. 3, both Al and P are implanted so as to have an implantation amount of about 3×10 20 cm -3 . The p-type Al impurity density is high from the surface to about 0.1 μm, but conversely, the n-type P impurity density becomes high from 0.1 μm deep. Thus, in the comparative example, the impurity densities of Al and P in the base contact region become about the same, and the resistance increases due to compensation.

[0025] As described above, in the semiconductor device according to the embodiment of the present invention, the impurity density in the base contact region 9 is always higher than that in the source region 10 in the region reaching the base region 8. Therefore, neither the base contact region 9 nor the source region 10 undergoes an increase in resistance due to carrier compensation, and an increase in the on-resistance and the forward voltage of the body diode can be suppressed. Further, since the termination region 42 is provided with the JTE region 18 having the relaxation regions (5c, 7b) and the spatial modulation portions 18a, 18b, 18c, 18d, the electric field concentration can be relaxed. Furthermore, since the channel stopper regions (4b, 6b) are provided at the outer edge portion of the termination region 42, a high voltage applied to the MOSFET can be held. Therefore, the breakdown voltage of the termination region 42 can be improved, and a high-voltage device can be realized.

[0026] Next, with reference to FIGS. 4 to 11, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described by taking the case of a trench gate type MOSFET as an example. Note that the method for manufacturing the trench gate type MOSFET described below is an example, and it goes without saying that various other manufacturing methods including this modification can be realized as long as they are within the scope of the gist described in the claims.

[0027] First, an n+-type semiconductor substrate (SiC substrate) doped with an n-type impurity such as nitrogen (N) is prepared. Using this n + -type SiC substrate as a drain region (not shown), an n - -type drift layer 2 is epitaxially grown on the upper surface of the drain region. Next, an n-type mesa bottom layer 3 is epitaxially grown on the upper surface of the drift layer 2. By using photolithography technology, ion implantation technology, etc., p-type impurity ions are implanted while masking the vicinity of the outer edge of the termination region 42. Next, n-type impurity ions are selectively implanted by using photolithography technology, ion implantation technology, etc. The implanted ions are activated, and as shown in FIG. 4, n + -implanted layers 4a, 4b, and p + -type implanted layers 5a, 5b, 5c are selectively formed.

[0028] An epitaxial growth layer 6 is epitaxially grown on the upper surface of the mesa bottom layer 3 that has been ion implanted. By using photolithography technology, ion implantation technology, etc., n-type impurity ions are selectively implanted into the growth layer 6. The implanted ions are activated, and as shown in FIG. 5, an n + type implanted layer 6a is formed in the active region 40, and an implanted layer 6b is formed in the termination region 42. The implanted layer 6b is provided on the upper surface of the implanted layer 4b.

[0029] By using photolithography technology, ion implantation technology, etc., p-type impurity ions are selectively implanted. The implanted ions are activated, and as shown in FIG. 6, a p + type implanted layer 7a is formed in the active region 40, and an implanted layer 7b is formed in the termination region 42. The implanted layer 7a is provided on the upper surface of the implanted layer 5a and constitutes the base bottom embedded region (5a, 7a). The implanted layer 7b is provided on the upper surface of the implanted layer 5c and constitutes the relaxation region (5c, 7b).

[0030] As shown in FIG. 7, a p-type base region 8 is epitaxially grown on the upper surface of the ion-implanted growth layer 6. Then, by using photolithography technology, ion implantation technology, etc., p-type impurity ions are implanted. The implanted ions are activated, and as shown in FIG. 8, a base contact region 9 is formed on the upper part of the base region 8. The base contact region 9 is arranged above the base bottom embedded region (5a, 7a). Note that the activation process of the implanted ions may be carried out simultaneously when the source region 10 is activated.

[0031] Next, using ion implantation technology, etc., n-type impurity ions are implanted over the entire surface of the base region 9 where the base contact region 9 is formed without using a mask. The implanted ions are activated, and as shown in FIG. 9, a source region 10 is formed between the base contact regions 9. The impurity implantation amount of the source region 10 is 1 / 2 or less of the impurity implantation amount of the base contact region 9. The implantation depth of the source region 10 is made 0.05 μm or more shallower than that of the base contact region 9.

[0032] By photolithography technology and dry etching technologies such as reactive ion etching (RIE), mesa etching is performed at the end portion to remove a part of the semiconductor layer in the terminal region 42 to form a step having a mesa slope. As shown in FIG. 10, the dry etching is performed at a depth at which the implanted layer 6b provided at the outer edge of the terminal region 42 remains. Further, the mask for mesa etching at the end portion is made narrower than the base contact region 9 in the terminal region 42 so that a part of the base contact region 9 is removed. As a result, the surface of the implanted layer 6b is exposed on the flat portion. On the mesa slope, the p + -type base contact region 9, the p-type base region 8, and the p + -type implanted layer 7b are exposed.

[0033] A trench 11 is formed by photolithography technology and dry etching technologies. Next, an insulating film is deposited by a method such as low-pressure chemical vapor deposition (CVD). Thereafter, a polysilicon layer is embedded in the trench 11 by photolithography technology and dry etching technologies to form a gate structure including a gate insulating film 12 and a gate electrode 13. Thereafter, by photolithography technology and ion implantation technology or the like, a JTE region 18 having spatially modulated portions 18a, 18b, 18c, 18d is provided inside the growth layer 6 from the lower end of the mesa slope formed in the terminal region 42 toward the outer edge of the terminal region 42.

[0034] Next, an interlayer insulating film 14 is formed over the gate structure and from the mesa slope of the terminal region 42 to the outer edge. Thereafter, a source contact layer 15, a lower barrier metal layer 16, and an upper barrier metal layer 17 are formed on the upper surface, and a drain electrode 19 is formed on the back surface, completing the MOSFET shown in FIG. 1.

[0035] Next, with reference to FIGS. 12 to 16, the manufacturing method of a conventional MOSFET will be mainly described with respect to the points different from the manufacturing method of the MOSFET according to the embodiment of the present invention. In the conventional manufacturing method, unlike the embodiment of the present invention shown in FIGS. 4 and 5, after the epitaxial growth of the mesa bottom layers 3 and 6, n +Ion implantation is not performed in the channel stopper regions (4b, 6b) of the type. Therefore, the mesa bottom layers 3 and 6 are left at the outer edge of the terminal region 42. As shown in FIG. 12, a p + type base region 8 is epitaxially grown on the upper surface of the growth layer 6 in which the type implantation layers 7a and 7b are formed.

[0036] Mesa etching of the terminal portion is performed by photolithography technology and dry etching technology such as reactive ion etching (RIE), etc., to remove a part of the semiconductor layer in the terminal region 42 to form a step having a mesa slope. As shown in FIG. 13, the dry etching is performed at a depth at which the growth layer 6 provided at the outer edge of the terminal region 42 remains. As a result, the surface of the growth layer 6 is exposed on the flat portion. On the mesa slope, the p-type base region 8 and the p + type implantation layer 7b are exposed.

[0037] Thereafter, n-type impurities are selectively ion-implanted by photolithography technology and ion implantation technology, etc. As shown in FIG. 14, a source region 10 is selectively formed on the upper part of the base region 8. At the same time, n-type impurities are implanted into the outer edge of the terminal region 42 to form an n + type channel stopper region 20. Thus, in the conventional manufacturing method, the source region 10 and the channel stopper region 20 are formed by selective ion implantation using a mask.

[0038] P-type impurity ions are selectively implanted by photolithography technology and ion implantation technology, etc. As shown in FIG. 15, a base contact region 9 is formed so as to sandwich the source region 10. The base contact region 9 extending to the terminal region 42 is not exposed on the mesa slope after terminal etching. The mask for ion implantation of the base contact region 9 is made narrower than the mask for terminal etching so that p-type impurities are not implanted on the surface of the n-type growth layer 6.

[0039] The trench 11 is formed by photolithography technology, dry etching technology, etc. Next, an insulating film is deposited by a low-pressure chemical vapor deposition (CVD) method or the like. Thereafter, a polysilicon layer is embedded in the trench 11 by photolithography technology, dry etching technology, etc. to form a gate structure including a gate insulating film 12 and a gate electrode 13. Thereafter, a JTE region 18 is provided inside the growth layer 6 from the lower end of the mesa slope formed in the terminal region 42 toward the outer edge of the terminal region 42 by photolithography technology, ion implantation technology, etc. At this time, p-type impurities are implanted into the mesa slope by ion implantation for forming the JTE region 18. For example, the impurity density in the p-type ion implantation for forming the JTE region 18 is about 2×10 17 cm -3 . The p-type base region 8 has an impurity density of about 4×10 17 cm -3 . Therefore, after the ion implantation for forming the JTE region 18, the p-type impurity density becomes about 6×10 17 cm -3 and does not reach a high impurity density.

[0040] As described above, the conventional method for manufacturing a MOSFET uses a mask in the ion implantation step of the source region 10. On the other hand, in the method for manufacturing a MOSFET according to the present invention, the source region 10 is formed by implanting ions over the entire surface without using a mask. Therefore, the number of mask layers is reduced and mask alignment is also unnecessary. As a result, the manufacturing process can be shortened and the manufacturing cost can be reduced.

[0041] (Other Embodiments) As described above, the present invention has been described by way of embodiments, but it should not be understood that the descriptions and drawings forming a part of this disclosure limit the present invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.

[0042] In the embodiment of the present invention, a MISFET having a trench structure is exemplified, but the present invention is not limited thereto, and the present invention is applicable to various semiconductor devices having a trench structure such as an IGBT having a trench structure. As for the trench gate type IGBT, the n + type source region 8 of the MISFET shown in FIG. 1 is used as the emitter region, and instead of the n + type drain region 1, a p + type collector region may be provided on the lower surface side of the drift layer 2.

[0043] In the embodiment of the present invention, a semiconductor device using SiC is exemplified, but the present invention can also be applied to a semiconductor device using other wide bandgap semiconductors such as gallium nitride (GaN) or diamond.

Description of Reference Numerals

[0044] 1... Drain region 2... Drift layer 3... Mesa bottom layer 4... First base bottom buried region (electric field relaxation layer) 4a, 4b, 5a, 5c, 6a, 6b, 7a, 7b... Implanted layer 4a, 6a... Current diffusion region 4b, 6b... Channel stopper region 5a, 7a... Base bottom buried region 5b... Gate bottom protection region 5c, 7b... Relaxation region 6... Growth layer 8... Base region 9... Base contact region 10... Source region 11... Trench 12... Gate insulating film 13... Gate electrode 14... Interlayer insulating film 15... Source contact layer 16... Lower barrier metal layer 16... Upper barrier metal layer 18... JFET region 18a, 18b, 18c, 18d... Spatial modulation section 19... Drain electrode 40... Active region 42... Terminal region

Claims

1. 1. A method for manufacturing a silicon carbide semiconductor device including an active region and a termination region surrounding the active region, comprising: an ion implantation step of ion-implanting an impurity element having a first conductivity type into a surface of a base region of a second conductivity type provided above a drift layer of a first conductivity type to form an impurity element implanted region; a step of selectively removing a semiconductor layer including the impurity element implanted region in the termination region; and a step of selectively removing a semiconductor layer including the impurity element implanted region in the active region, the step forming a step in the termination region and a trench in the active region; Including, In the etching step, a slope is formed by etching the termination region, the lower end of which is connected to a flat portion that is a bottom surface of the step, forming a junction termination extension region of a second conductivity type from the lower end of the slope toward the outer edge. A method for manufacturing a silicon carbide semiconductor device.

2. In the etching step, the inclined surface, which is a side surface of the impurity element implanted region that contacts the step, is formed asymmetrically with a side surface of the impurity element implanted region that contacts the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 1 .

3. In the ion implantation step, the impurity element is ion-implanted into the entire surface of the base region. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2.

4. In the etching step, the depth of the step is set to be different from the depth of the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 1 .

5. a second ion implantation step of selectively ion-implanting a second impurity element having a second conductivity type into a surface of the base region to form a second impurity element implanted region; The second impurity element has a higher impurity density than the first impurity element at an overlapping portion where the second impurity element implantation region overlaps the first impurity element implantation region. The method for manufacturing a silicon carbide semiconductor device according to claim 1 .

6. In the overlapping portion, the second impurity element has a higher impurity density than the first impurity element by at least two times. The method for manufacturing a silicon carbide semiconductor device according to claim 5 .

7. The second impurity element implantation region is deeper than the first impurity element implantation region. The method for manufacturing a silicon carbide semiconductor device according to claim 5 or 6.

8. forming an interlayer insulating film covering at least a portion of the overlapping portion and continuing up to the step in the termination region; The method for manufacturing a silicon carbide semiconductor device according to claim 5 .

9. forming a metal-containing layer containing a metal in contact with the impurity element implanted region and the overlapping portion; The overlapping portion, together with the base region, constitutes a part of a semiconductor region of a second conductivity type, at least a part of a bottom surface of which is in contact with the drift layer below the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 5 .

10. A method for manufacturing a silicon carbide semiconductor device including an active region and a termination region surrounding the active region, comprising: an ion implantation step of ion-implanting an impurity element having a first conductivity type into a surface of a base region of a second conductivity type provided above a drift layer of a first conductivity type to form an impurity element implanted region; a step of selectively removing a semiconductor layer including the impurity element implanted region in the termination region; and a step of selectively removing a semiconductor layer including the impurity element implanted region in the active region, the step forming a step in the termination region and a trench in the active region; Including, The active region is provided with a second conductivity type protection region in contact with a bottom of the trench. a relaxation region of a second conductivity type is provided in the termination region and faces the protection region in a horizontal direction; The relaxation region extends from the step side to the active region side in the horizontal direction. A method for manufacturing a silicon carbide semiconductor device.

11. a metal-containing layer that contains a metal; a trench having at least a portion thereof below the metal-containing layer via an interlayer insulating film; a drift layer of a first conductivity type; and a semiconductor region of a second conductivity type, the semiconductor region having at least a portion of an upper surface in contact with the metal-containing layer and at least a portion of a bottom surface in contact with the drift layer below the trench, an impurity element implanted region in which an impurity element exhibiting a first conductivity type is ion-implanted, the impurity element implanted region having at least a portion of an upper surface in contact with the metal-containing layer and adjacent to the trench; a step formed by removing a portion of a semiconductor layer in a termination region surrounding the active region; Including, the semiconductor region has a base region in contact with at least a part of a bottom surface of the impurity element implanted region, and a base contact region provided from an upper surface to an interior of the semiconductor region and having a higher impurity density than the impurity element implanted region; At least a portion of the base contact region is doped with both the impurity element and a second impurity element having a second conductivity type, and an impurity density of the second impurity element is higher than an impurity density of the first impurity element; The impurity element implanted region has a first side surface which is an inclined surface in contact with the step, and a second side surface which is asymmetric with the first side surface and in contact with the trench. Silicon carbide semiconductor devices.

12. The step has a depth different from that of the trench. The silicon carbide semiconductor device of claim 11.

13. a protection region of a second conductivity type in contact with a bottom of the trench in the active region; a relaxation region of a second conductivity type provided in the termination region and facing the protection region in a horizontal direction; a junction termination extension region of a second conductivity type provided from a lower end of the slope toward an outer edge portion; 13. The silicon carbide semiconductor device according to claim 11 or 12, comprising:

14. a metal-containing layer that contains a metal; a trench having at least a portion thereof below the metal-containing layer via an interlayer insulating film; a drift layer of a first conductivity type; and a semiconductor region of a second conductivity type, the semiconductor region having at least a portion of an upper surface in contact with the metal-containing layer and at least a portion of a bottom surface in contact with the drift layer below the trench, an impurity element implanted region in which an impurity element exhibiting a first conductivity type is ion-implanted, the impurity element implanted region having at least a portion of an upper surface in contact with the metal-containing layer and adjacent to the trench; a step having a different depth from the trench, the step being formed by removing a portion of the semiconductor layer in a termination region surrounding the active region; Including, the semiconductor region has a base region in contact with at least a part of a bottom surface of the impurity element implanted region, and a base contact region provided from an upper surface to an interior of the semiconductor region and having a higher impurity density than the impurity element implanted region; At least a portion of the base contact region is doped with both the impurity element and a second impurity element having a second conductivity type, and the impurity density of the second impurity element is higher than the impurity density of the first impurity element. Silicon carbide semiconductor devices.

15. The impurity element implantation region is provided on the entire surface of the base region, and a portion of the impurity element implantation region overlaps with the base contact region.

15. The silicon carbide semiconductor device according to claim 11.

16. a protection region of a second conductivity type in contact with a bottom of the trench in the active region; a relaxation region of a second conductivity type provided in the termination region and facing the protection region in a horizontal direction; a junction termination extension region of a second conductivity type provided from a lower end of the slope contacting the step toward an outer edge portion; The silicon carbide semiconductor device of claim 14 .

17. an interlayer insulating film covering at least a portion of the base contact region and continuing to the step in the termination region; 17. The silicon carbide semiconductor device according to claim 11.

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