Reverse-Conducting IGBT with Reduced Forward Recovery Voltage

Abstract

To provide a reverse-conducting IGBT having a reduced forward recovery voltage.SOLUTION: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.SELECTED DRAWING: None

Description

Background Art

[0001] A reverse-conducting insulated gate bipolar transistor (RC-IGBT) integrates an IGBT and a freewheel diode on a single chip (die). Many applications of IGBTs have a mode in which a freewheel current flows from the emitter to the collector. For such a freewheel operation, the freewheel diode is connected in anti-parallel to the IGBT.

[0002] At the anode of the integrated diode, a trench pattern formation process such as that of an IGBT can be used to improve the switching durability of the diode. The resulting trench electrodes formed in the diode region shield the anode of the integrated diode from high electric fields, thereby avoiding the punch-through phenomenon and thus realizing switching durability. An RC-IGBT with sufficiently high switching durability may be used in applications that utilize hard switching. When hard switching is used, both voltage and current are applied to the IGBT during the on / off transition. Therefore, when the IGBT is hard switched, the collector current and the collector-emitter voltage change rapidly.

[0003] However, increasing the durability of IGBT switching generally results in a higher forward recovery voltage (Vfr) in the integrated diode. When the IGBT is conducting, the diode is blocked. When the IGBT begins to turn off and the switching current of the IGBT starts to rectify to the diode, the collector-emitter voltage of the IGBT begins to rise, and conversely, the diode voltage begins to drop. When the current continues to rectify to the diode, an undershoot of the diode voltage occurs. This undershoot is generally referred to as the forward recovery voltage (Vfr) of the diode. The peak of the forward recovery voltage Vfr may become extremely high. For example, a Vfr of about 300V is not uncommon in 1200V technology. Such a Vfr may interfere with the operation of adjacent IGBTs and damage the gate driver circuit of the IGBT.

[0004] As described above, in order to improve switching durability, the diode of an RC-IGBT may include a trench electrode formed in a semiconductor substrate. Removing the trench electrode from the diode region of an RC-IGBT device significantly reduces the Vfr of the diode. In a diode without a trench electrode, reducing the anode efficiency, which is a preferable measure for improving the performance of the diode by degrading the switching durability, is limited. That is, the anode region of a highly doped diode achieves sufficient switching durability, but is highly efficient and increases switching losses. Therefore, an RC-IGBT device having an anode region that is not doped with a trench electrode and is doped to minimize switching losses can be used for soft-switching applications where the anode efficiency may become relatively large. However, in hard-switching applications, since switching durability is required, it is preferable to use a trench electrode in the diode region.

[0005] Therefore, there is a trade-off between anode efficiency and switching durability. A highly doped anode achieves sufficient switching durability at the expense of increased switching losses, so a trench electrode is not necessary when the anode region is highly doped. A relatively lowly doped anode region is relatively inefficient, which is good for reducing switching losses, but degrades switching durability, which is a problem in applications using hard-switching. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] Therefore, there is a need for an improved RC-IGBT with low anode efficiency and high switching durability. MEANS FOR SOLVING THE PROBLEMS

[0007] According to an embodiment of a power semiconductor device, this power semiconductor device includes a semiconductor substrate including an IGBT region containing an IGBT (Insulated Gate Bipolar Transistor) and a diode region containing a diode. In a top view, the IGBT region has a first area, and in the top view, the diode region has a second area. The semiconductor substrate includes a plurality of first trenches that include a first trench electrode and extend perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches that have a second trench electrode and extend perpendicular to the first main surface of the semiconductor substrate. In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate. In the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate. The capacitance density of the second capacitance per second area is lower than the capacitance density of the first capacitance per first area.

[0008] According to another embodiment of a power semiconductor device, this power semiconductor device includes a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches that extend perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches that extend perpendicular to the first main surface of the semiconductor substrate. The average lateral interval between adjacent trenches among the second trenches is wider than the average lateral interval between adjacent trenches among the first trenches.

[0009] According to one embodiment of a method for manufacturing a power semiconductor device, the method includes forming an IGBT in an IGBT region of a semiconductor substrate, where the IGBT region has a first area in a top view, and forming a diode in a diode region of the semiconductor substrate, where the diode region has a second area in a top view. Forming the IGBT includes forming, in the IGBT region, a plurality of first trenches having a first trench electrode and extending perpendicular to a first main surface of the semiconductor substrate. Forming the diode includes forming, in the diode region, a plurality of second trenches having a second trench electrode extending perpendicular to the first main surface of the semiconductor substrate. As a result, the capacitance density of the capacitance formed between the plurality of second trenches and the semiconductor substrate per second area is lower than the capacitance density of the capacitance formed between the plurality of first trenches and the semiconductor substrate per first area.

[0010] Additional features and advantages will be understood by those skilled in the art upon reading the following detailed description and viewing the accompanying drawings.

[0011] The elements of each drawing are not necessarily to scale with each other. The same reference numerals refer to corresponding like parts. The features of the various embodiments shown can be combined with each other as long as they do not exclude each other. The embodiments are shown in each drawing and will be described in detail in the following description.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0013] An RC-IGBT with low anode efficiency and high switching durability, and a corresponding manufacturing method are described herein. Some embodiments described herein achieve high switching durability without increasing the anode efficiency more than necessary. To further adjust the anode efficiency and switching durability, the anode contact region of the integrated diode may be adjusted as described herein. It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0014] FIG. 1 shows a top view of a power semiconductor device 100. This power semiconductor device 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may include one or more of various semiconductor materials used to form integrated circuit devices, such as, for example, but not limited to, silicon (Si), silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor substrate 102 may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material.

[0015] The power semiconductor device 100 includes a cell region 104 in which an RC-IGBT is formed, and a peripheral region 106 that laterally surrounds the cell region 104 and electrically insulates the RC-IGBT from the edge 108 of the semiconductor substrate 102. Within the cell region 104, the semiconductor substrate 102 includes an IGBT region 110 that includes an IGBT, and a diode region 112 that includes a diode. In FIG. 1, the IGBT region 110 and the diode region 112 are shown in a stripe layout. In this example, the cells of the IGBT and the diode are arranged alternately in stripes. This arrangement enables the heat mainly generated in the diode region 112 to be more evenly dispersed, and thus more efficient cooling becomes possible. Each of the IGBT stripes may include a plurality of trenches, for example, at least 2, at least 5, or at least 10 trenches that form each IGBT cell. Each IGBT cell includes at least one trench configured to control the IGBT current. In some embodiments, as will be described in more detail below, each IGBT cell may include a trench connected to the emitter potential and a trench connected to the gate potential. In some embodiments, the trenches connected to the emitter potential may be arranged alternately with the trenches connected to the gate potential. Each of the diode cells includes a plurality of trenches, for example, at least 2, at least 5, or at least 10 trenches. In one embodiment, the plurality of trenches may include trenches connected to the same potential, for example, the emitter potential. However, this is just an example, and other configurations are possible. In some embodiments, each IGBT stripe may include a plurality of IGBT cells, and each diode stripe may include a plurality of diode cells. The IGBT region 110 and the diode region 112 may each have any desired layout. In one embodiment, the diode area is incorporated within the IGBT. The IGBT region 110 may be adjacent to an edge termination structure formed within the peripheral region 106.

[0016] FIG. 2A shows a cross-sectional view of a portion of the diode region 112 as seen along the line labeled I-I in FIG. 1. FIG. 2B shows a cross-sectional view of a portion of the IGBT region 110 as seen along the line labeled I-I in FIG. 1 as well.

[0017] In the top view of FIG. 1, the IGBT region 110 has a first region, and the diode region 112 has a second region. Based on the striped layout shown in FIG. 1, the first region occupied by the IGBT region 110 is discontinuous and includes the regions of each IGBT stripe. The second region occupied by the diode region 112 is also discontinuous and similarly includes the regions of each diode stripe. Therefore, the IGBT region 110 may be formed by combining a plurality of discontinuous IGBT sub-regions (e.g., stripes) to form the IGBT region 110, and the diode region 112 may also be considered to be formed by combining a plurality of discontinuous diode sub-regions (e.g., stripes). That is, the first region occupied by the IGBT region 110 is the combined region of all IGBT sub-regions, and the second region occupied by the diode region 112 is the combined region of all diode sub-regions. In the first trench 114 arranged in a striped manner, the first region may be calculated by adding the top view region of each of the first trenches 114 and the top view region of the mesa-shaped portion formed between each of the first trenches 114. The discontinuous arrangement of the first region (IGBT) and the second region (diode) in FIG. 1 is caused by the fact that the "stripes" of the IGBT and the "stripes" of the diode are arranged alternately. The first region occupied by the IGBT region 110 and the second region occupied by the diode region 112 may instead be continuous respectively. For example, the IGBT region 110 may not be blocked by the diode region 112 and may be formed adjacent to the diode region 112 on the semiconductor substrate 102.

[0018] The IGBT region 110 includes a first trench 114 having a first trench electrode 116 insulated from the surrounding semiconductor substrate 102 by a first insulating layer 118. The first trench 114 of the IGBT region 110 extends perpendicular to the first major surface 103 of the semiconductor substrate 102 (in the direction "x" in FIG. 2B). According to embodiments, the number of first trenches formed in the first region may be 100 or more, 500 or more, or 1000 or more. According to embodiments, the number of second trenches formed in the second region may be 100 or more, 500 or more, or 1000 or more.

[0019] A part of the first trench electrode 116 is a gate (G) electrode for controlling the conductive channel 120 in the body region 122 of the IGBT. The other electrode of the first trench electrode 116 is a field (F) electrode for shaping the electric field potential in the semiconductor substrate 102 when controlling the operation of the RC-IGBT. The field electrode F may be electrically connected to a potential different from that of the gate electrode G. For example, the field electrode F may be electrically connected to the emitter potential, ground, or may be electrically floating.

[0020] The body region 122 separates the emitter region 124 of the IGBT from the drift region 126. When the conductive channel 120 is present, the emitter region 124 is electrically connected to the drift region 126. The conductive channel 120 is controlled by the voltage applied to the gate electrode G of the IGBT.

[0021] The IGBT also includes a collector region 128 on the opposite surface 105 of the semiconductor substrate 102 as the emitter region 124. The emitter region 124, the drift region 126, and the conductive channel 120 are of a first conductivity type, and the body region 122 and the collector region 128 are of a second conductivity type opposite to the first conductivity type. For example, in the case of an n-type conductive channel 120, the emitter region 124 and the drift region 126 are n-type, and the body region 122 and the collector region 128 are p-type. Conversely, in the case of a p-type conductive channel 120, the emitter region 124 and the drift region 126 are p-type, and the body region 122 and the collector region 128 are n-type. An optional field stop region 130 of the first conductivity type may be formed in the semiconductor substrate 102 between the drift region 126 and the collector region 128. This field stop region 130 may be excluded in the diode region 112 even when provided in the IGBT region 110. According to embodiments, the field stop regions 130 in the diode region 112 and the IGBT region 110 may have various doping concentrations, various doping profiles, or various thicknesses, or combinations thereof.

[0022] The diode region 112 of the power semiconductor device 100 includes a second trench 132 having a second trench electrode 134 insulated from the surrounding semiconductor substrate 102 by a second insulating layer 136. The second trench 132 of the diode region 112 extends perpendicular to the first main surface 103 of the semiconductor substrate 102 (in the direction "x" of FIG. 2A). In the case of the trenches 132 arranged in a stripe shape, the second region of the diode region 112 can be calculated by adding the top view region of the second trench 132 and the top view region of the mesa-shaped portion formed between each second trench 132.

[0023] The cell structure of the diode region 112 may be similar to the cell structure of the IGBT region 110. Alternatively, the emitter region 124 is excluded from the diode region 112. Also, the diode region 112 has a cathode region 138 of the first conductivity type on the second main surface 105 of the semiconductor substrate 102 instead of the collector region 128 of the second conductivity type. On the first main surface 103 of the semiconductor substrate 102, the first metallization 140 may be electrically connected to the body region 122, the emitter region 124, and the field electrode F in the IGBT region 110, or may be electrically connected to the second trench electrode 134 and the anode region 141 in the diode region 112. The gate electrode G of the IGBT region 110 is insulated from the first metallization 140 by an insulating material 142 such as a dielectric.

[0024] The electrical connection to the first metallization 140 may be formed by a first contact trench 144 that extends perpendicularly to the first main surface 103 of the semiconductor substrate 102 (in the direction "x" of FIG. 2B) in the IGBT region 110, and a second contact trench 146 that also extends perpendicularly to the first main surface 103 of the semiconductor substrate 102 (in the direction "x" of FIG. 2A) in the diode region 112. In the IGBT region 110, the first metallization 140 is electrically connected to the body region 122, the emitter region 124, and the field electrode F of the IGBT through the first contact trench 144. In the diode region 112, the first metallization 140 is electrically connected to the second trench electrode 134 and the anode region 141 of the diode through the second contact trench 146. The semiconductor substrate 102 may include a high-concentration doped region 148 of the second conductivity type adjacent to at least a part of the lower end and the sidewall of the first contact trench 144 and the second contact trench 146.

[0025] According to one embodiment, the doping concentration of the semiconductor substrate 102 via the high-concentration doped region 148 on the sidewall of at least the second contact trench 146 in the diode region 112 is lower than the doping concentration of the semiconductor substrate 102 at the lower part of the second contact trench 146. Such doping variation in the semiconductor substrate 102 may be implemented by appropriately controlling the doping profile of the high-concentration doped region 148.

[0026] When the doping concentration at the lower end of the second contact trench 146 in the diode region 112 is high, a good ohmic contact with the first metallization 140 is achieved. However, when the doping decreases along the sidewall, the anode efficiency that is good for reducing switching losses decreases.

[0027] The second metallization 150 contacts the collector region 128 of the IGBT and the cathode region 138 of the diode on the second main surface 105 of the semiconductor substrate 102.

[0028] FIG. 3 shows the waveforms of the voltage (V) and current (I) in the RC-IGBT when the IGBT transitions from the on state to the off state and the diode transitions from the blocking state to the freewheel (conducting) state. Before time point t1, the collector-emitter voltage V CE of the IGBT is zero volts or a voltage close thereto, the diode is in the blocking state, and during this time, the diode voltage V Diode is at the peak blocking level. When the IGBT starts to turn off at time point t1, the collector-emitter voltage V CE of the IGBT starts to rise, and the diode voltage V Diode starts to drop. At time point t2, the collector current I C of the IGBT starts to drop, and the diode voltage V Diode starts to undershoot. The undershoot of the diode voltage V Diode that occurs while the IGBT is off is generally referred to as the forward recovery voltage (V fr ) of the diode. The forward recovery voltage V frreaches the peak value V at time t3 fr_peak and at this time the undershoot begins to decrease. Eventually, the diode voltage V Diode reaches the forward voltage V f of the diode, and this diode becomes forward-biased. When the diode is forward-biased and the IGBT is off, the freewheel current flows through the diode.

[0029] All MOS (metal oxide semiconductor) interfaces of the RC-IGBT with the trenches 114, 132 have a certain capacitance. More specifically, the first trench 114 in the IGBT region 110 results in a first capacitance C1 between the first trench electrode 116 and the semiconductor substrate 102 in the IGBT region 110. Similarly, the second trench 132 in the diode region 112 results in a second capacitance C2 between the second trench electrode 134 and the semiconductor substrate 102 in the diode region 112. In this specification, the capacitance is calculated by C = kεA / d, where k is a constant, ε is the dielectric constant of the respective insulating layers 118, 136 that insulate the IGBT trench 114 or the diode trench 132 from the semiconductor substrate 102, A is the respective area of the capacitance, and d is the average thickness of the respective insulating layers 118, 136. The area A of each capacitance can be calculated by the surface area of the respective trench 114 / 132 that faces the semiconductor substrate 102 on one hand and faces the respective electrode 116 / 134 in the trench 114 / 132 from the semiconductor substrate 102 (through the insulating layers 118 / 136) on the other hand.

[0030] The capacitance density of the second capacitance C2 per second region of the diode region 112 may be lower than the capacitance density of the first capacitance C1 per first region of the IGBT region 110, so that the RC-IGBT surely has both a low anode efficiency and a high switching durability. That is, the ratio of C2 to F2 is smaller than the ratio of C1 to F1, C2 is the total capacitance in the diode region 112, F2 is the second region of the diode region, C1 is the total capacitance in the IGBT region 110, and F1 is the first region of the IGBT region 110. Reducing the capacitance density of the diode region 112 with respect to the capacitance density of the IGBT region 110 can reduce the undershoot of the forward recovery voltage V fr of the diode. However, in order to cope with hard switching applications, the second trench electrode 134 is still provided in the diode region 112.

[0031] In one embodiment, the capacitance density of the second capacitance C2 per second region of the diode region 112 is 1 / 1.5 to 1 / 10 of the capacitance density of the first capacitance C1 per first region of the IGBT region 110. In another embodiment, the capacitance density of the second capacitance C2 per second region of the diode region 112 is 1 / 1.5 to 1 / 4 of the capacitance density of the first capacitance C1 per first region of the IGBT region 110. Depending on the embodiment, the capacitance density of the second capacitance C2 per second region of the diode region 112 is 1 / 1.8 to 1 / 3 of the capacitance density of the first capacitance C1 per first region of the IGBT region 110.

[0032] For example, as shown in FIGS. 2A and 2B, in the semiconductor substrate 102, by terminating the second trench 132 in the diode region 112 shallower than the first trench 114 in the IGBT region 110, the capacitance density of the second capacitance C2 per second area of the diode region 112 may be made lower than the capacitance density of the first capacitance C1 per first area of the IGBT region 110. According to this embodiment, as measured from the first main surface 103 of the semiconductor substrate 102, the first trench 114 in the IGBT region 110 extends to a first depth D1 of the semiconductor substrate 102, and the second trench 132 in the diode region 112 extends to a second depth D2 of the semiconductor substrate 102, and this second depth D2 is shallower than the first depth D1 (i.e., D2 < D1).

[0033] Alternatively or in addition, for example, as shown in FIGS. 2A and 2B, by forming the number of second trenches 132 per unit area in the diode region 112 to be less than the number of first trenches 114 per unit area in the IGBT region 110, and / or by further spacing apart the second trenches 132 in the diode region 112 more than the first trenches 114 are spaced apart in the IGBT region 110, the capacitance density of the second capacitance C2 per second area of the diode region 112 may be made lower than the capacitance density of the first capacitance C1 per first area of the IGBT region 110. According to this embodiment, the average lateral spacing S L2 between adjacent trenches among the second trenches 132 in the diode region 112 L1 is wider than the average lateral spacing S L2 between adjacent trenches among the first trenches 114 in the IGBT region 110 (i.e., S L1 > S L2 ). In one embodiment, the average lateral spacing S L1is 1.5 to 30 times wider. In another embodiment, the average lateral spacing S between adjacent trenches among the second trenches 132 in the diode region 112 L2 is 1.5 to 10 times wider than the average lateral spacing S between adjacent trenches among the first trenches 114 in the IGBT region 110 L1 is 1.5 to 10 times wider. In another embodiment, the average lateral spacing S between adjacent trenches among the second trenches 132 in the diode region 112 L2 is wider than 0.3 μm and narrower than 20 μm, and the average lateral spacing S between adjacent trenches among the first trenches 114 in the IGBT region 110 L1 is 0.6 μm or less.

[0034] Alternatively or in addition, by separating the second trenches 132 in the diode region 112 along the direction (z-axis) of the longitudinal extension of this trench 132, the capacitance density of the second capacitance C2 per second area in the diode region 112 may be made lower than the capacitance density of the first capacitance C1 per first area in the IGBT region 110. Instead of having continuous trenches 132 substantially extending from one end to the other end of the diode region 112, each second trench 132 in the diode region 112 may be segmented into a plurality of trench portions formed along the direction of the longitudinal extension of this second trench 132. Adjacent trench portions among those second trenches 132 in the diode region 112 are separated from each other by the substrate area of the semiconductor substrate 102.

[0035] Alternatively or in addition, by making the insulating layer 136 separating the second trench electrode 134 from the semiconductor substrate 102 in the diode region 112 thicker than the insulating layer 118 separating the first trench electrode 116 from the semiconductor substrate 102 in the IGBT region 110, the capacitance density of the second capacitance C2 per second area in the diode region 112 may be made lower than the capacitance density of the first capacitance C1 per first area in the IGBT region 110.

[0036] Alternatively or in addition, by selecting the dielectric constant (ε) of the insulating layer separating the second trench electrode 134 from the semiconductor substrate 102 in the diode region 112 to be less than the dielectric constant of the insulating layer 118 separating the first trench electrode 116 and the semiconductor substrate 102 in the IGBT region 110, the capacitance density of the second capacitance C2 per second region of the diode region 112 may be made lower than the capacitance density of the first capacitance C1 per first region of the IGBT region 110. For example, the insulating layer 136 covering the sidewalls and the lower end of the second trench 132 in the diode region 112 may be a low dielectric constant dielectric material such as fluorine-doped silicon dioxide, carbon-doped oxide, porous silicon dioxide, etc., and the insulating layer 118 covering the sidewalls and the lower end of the first trench 114 in the IGBT region 110 may be silicon dioxide formed by thermal oxidation.

[0037] In addition to one, some or all of the embodiments described herein for making the capacitance density of the second capacitance C2 per second region of the diode region 112 lower than the capacitance density of the first capacitance C1 per first region of the IGBT region 110, the average density of the sidewall regions of the second contact trenches 146 between each adjacent second trench 132 in the diode region 112 may be higher than the average density of the sidewall regions of the first contact trenches 144 between each adjacent first trench 114 in the IGBT region 110. The sidewall regions of each contact trench 144, 146 are the surface regions occupied by the respective sidewalls of the contact trenches 144, 146. Alternatively or in combination therewith, the average density of the sidewall regions of the second contact trenches 146 per second region of the diode region 112 may be higher than the average density of the sidewall regions of the first contact trenches 144 per first region of the IGBT region 110.

[0038] The resulting relatively wide anode region 141 in the diode region 112 is occupied by the additional contact trenches 146, causing a reduction in current density at the contact with the first metallization 140. As a result, the anode efficiency is relatively low, but the switching durability is improved.

[0039] Figures 2A and 2B show an embodiment in which two second contact trenches 146 are disposed between adjacent second trenches 132 in the diode region 112, and a single first contact trench 144 is disposed between adjacent first trenches 114 in the IGBT region 110. By increasing the number of second contact trenches 146 disposed between adjacent second trenches 132 in the diode region 112, the paths for carriers to exit the diode are further increased, and the anode efficiency that reduces switching losses decreases.

[0040] Figure 4 shows an embodiment in which three second contact trenches 146 are disposed between adjacent second trenches 132 in the diode region 112. For example, as shown in Figure 2B, a single first contact trench 144 may be disposed between adjacent first trenches 114 in the IGBT region 110.

[0041] Figure 5 shows an embodiment in which four second contact trenches 146 are disposed between adjacent second trenches 132 in the diode region 112. For example, as shown in Figure 2B, a single first contact trench 144 may be disposed between adjacent first trenches 114 in the IGBT region 110. In further additional embodiments, five or more (>4) second contact trenches 146 may be disposed between adjacent second trenches 132 in the diode region 112.

[0042] In one embodiment, each of the second contact trenches 146 is connected at a predetermined position by one or more intersecting contact trenches extending in a direction perpendicular to the longitudinal extension of the second contact trench 146. In some embodiments, the intersecting contact trenches may extend at an oblique angle with respect to the second contact trench 146. By forming the intersecting contact trenches, a grid-like or mesh-like contact trench configuration may be formed in a top view. This grid-like or mesh-like contact trench configuration may maximize the contact area with equal critical dimensions. Also, with this grid-like or mesh-like contact trench configuration, among the anode regions formed by the high-concentration doped regions 148 of the second conductivity type, the area adjacent to at least a part of the lower end and the side walls of the second contact trench 146 may be enlarged. Further, with this grid-like or mesh-like contact trench configuration, the length around the second contact trench 146, and thus the side wall density, may be increased to obtain improved performance during the on-state.

[0043] FIG. 6 shows an embodiment in which a single second contact trench 146 is disposed between adjacent second trenches 132 in the diode region 112. As shown in FIG. 2B, a single first contact trench 144 may similarly be disposed between adjacent first trenches 114 in the IGBT region 110. According to the embodiment shown in FIG. 6, the second contact trench 146 in the diode region 112 has an average width W that is wider than the average width of the first contact trench 144 in the IGBT region 110. DIODE For example, the average width W of the second contact trench 146 in the diode region 112 DIODE may range from 100 nm to the full anode region 141 between adjacent second trenches 132. By providing a single but relatively wide contact 146 between adjacent second trenches 132 in the diode region 112, a relatively high anode efficiency with similar switching durability is achieved as compared to the multi-contact embodiments shown in FIGS. 2A, 4, and 5.

[0044] The present disclosure is not limited as such, and each of the following numbered examples illustrates one or more aspects of the present disclosure.

[0045] Example 1. A semiconductor substrate including an IGBT region including an IGBT (insulated gate bipolar transistor) and a diode region including a diode, the IGBT region having a first region in a top view, and the diode region having a second region in a top view, the semiconductor substrate comprising: the IGBT region including a first trench electrode and a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate; the diode region having a second trench electrode and a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate; in the IGBT region, the plurality of first trenches forming a first capacitance between the first trench electrode and the semiconductor substrate; in the diode region, the plurality of second trenches forming a second capacitance between the second trench electrode and the semiconductor substrate; and a power semiconductor device in which a capacitance density of the second capacitance per second region is lower than a capacitance density of the first capacitance per first region.

[0046] Example 2. The power semiconductor device according to Example 1, wherein a capacitance density of the second capacitance per second region is 1 / 1.5 to 1 / 10 of a capacitance density of the first capacitance per first region.

[0047] Example 3. The power semiconductor device according to Example 1 or Example 2, wherein the plurality of first trenches extend to a first depth of the semiconductor substrate, the plurality of second trenches extend to a second depth of the semiconductor substrate, and the second depth is shallower than the first depth.

[0048] Example 4. The power semiconductor device according to any one of Examples 1 to 3, wherein an insulating layer between the second trench electrode and the semiconductor substrate is thicker than an insulating layer between the first trench electrode and the semiconductor substrate.

[0049] Example 5. The power semiconductor device according to any one of Examples 1 to 4, wherein the dielectric constant of the insulating layer between the second trench electrode and the semiconductor substrate is lower than the dielectric constant of the insulating layer between the first trench electrode and the semiconductor substrate.

[0050] Example 6. The power semiconductor device according to any one of Examples 1 to 5, further comprising a plurality of first contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the IGBT region and a plurality of second contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the diode region, wherein the average density of the sidewall regions of the second contact trenches between adjacent second trenches in the diode region is higher than the average density of the sidewall regions of the first contact trenches between adjacent first trenches in the IGBT region.

[0051] Example 7. The power semiconductor device according to Example 6, wherein at least two second contact trenches are arranged between adjacent second trenches in the diode region, and a single first contact trench is arranged between adjacent first trenches in the IGBT region.

[0052] Example 8. The power semiconductor device according to Example 6, wherein at least four contact trenches are arranged between adjacent second trenches in the diode region, and a single first contact trench is arranged between adjacent first trenches in the IGBT region.

[0053] Example 9. The power semiconductor device according to any one of Examples 6 to 8, wherein the doping concentration of the semiconductor substrate on the sidewalls of the plurality of second contact trenches is lower than the doping concentration of the semiconductor substrate at the lower ends of the plurality of second contact trenches.

[0054] Example 10. The power semiconductor device according to any one of Examples 1 to 9, further comprising a plurality of first contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the IGBT region, and a plurality of second contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the diode region, wherein the average density of the sidewall regions of the second contact trenches per second region is higher than the average density of the sidewall regions of the first contact trenches per first region.

[0055] Example 11. The power semiconductor device according to any one of Examples 1 to 10, further comprising a plurality of first contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the IGBT region, and a plurality of second contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the diode region, wherein a single first contact trench is arranged between each adjacent first trench in the IGBT region, a single second contact trench is arranged between each adjacent second trench in the diode region, and the average width of the second contact trenches is wider than the average width of the first contact trenches.

[0056] Example 12. A power semiconductor device comprising a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode, wherein the IGBT region comprises a plurality of first trenches extending perpendicularly to the first main surface of the semiconductor substrate, the diode region comprises a plurality of second trenches extending perpendicularly to the first main surface of the semiconductor substrate, and the average lateral spacing between adjacent trenches among the second trenches is wider than the average lateral spacing between adjacent trenches among the first trenches.

[0057] Example 13. The power semiconductor device according to Example 12, wherein the average lateral spacing between adjacent trenches among the second trenches is 1.5 to 30 times wider than the average lateral spacing between adjacent trenches among the first trenches.

[0058] Example 14. The power semiconductor device according to Example 12 or Example 13, wherein the average lateral spacing between adjacent trenches among the second trenches is wider than 0.6 μm and narrower than 20 μm.

[0059] Example 15. The power semiconductor device according to any one of Examples 12 to 14, further comprising a plurality of first contact trenches extending on a first main surface of a semiconductor substrate in an IGBT region and a plurality of second contact trenches extending on the first main surface of the semiconductor substrate in a diode region, wherein an average density of sidewall regions of the second contact trenches between adjacent second trenches per second region is higher than an average density of sidewall regions of the first contact trenches between adjacent first trenches per first region.

[0060] Example 16. The power semiconductor device according to Example 15, wherein at least two second contact trenches are arranged between each adjacent second trench in the diode region, and a single first contact trench is arranged between each adjacent first trench in the IGBT region.

[0061] Example 17. The power semiconductor device according to Example 15, wherein at least four contact trenches are arranged between each adjacent second trench in the diode region, and a single first contact trench is arranged between each adjacent first trench in the IGBT region.

[0062] Example 18. The power semiconductor device according to any one of Examples 15 to 17, wherein a doping concentration of the semiconductor substrate on sidewalls of the plurality of second contact trenches is lower than a doping concentration of the semiconductor substrate at lower ends of the plurality of second contact trenches.

[0063] Example 19. The power semiconductor device according to any one of Examples 12 to 18, further comprising a plurality of first contact trenches extending perpendicularly to a first main surface of a semiconductor substrate in an IGBT region and a plurality of second contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in a diode region, wherein a single first contact trench is arranged between each adjacent first trench in the IGBT region, a single second contact trench is arranged between each adjacent second trench in the diode region, and an average width of the second contact trenches is wider than an average width of the first contact trenches.

[0064] Example 20. Each of the second trenches is segmented into trench portions along the direction of the longitudinal extension of the plurality of second trenches, and each adjacent trench portion of the second trenches is separated from each other by a substrate region of the semiconductor substrate. The power semiconductor device according to any one of Examples 12 to 19.

[0065] Example 21. The power semiconductor device according to any one of Examples 12 to 20, further comprising a plurality of contact trenches extending on the first main surface of the semiconductor substrate in the diode region, and the contact trenches are connected at a predetermined position by one or a plurality of cross-contact trenches extending in a direction perpendicular to the longitudinal extension of the contact trenches.

[0066] Example 22. A method of manufacturing a power semiconductor device, comprising forming an IGBT in the IGBT region of a semiconductor substrate, wherein the IGBT region has a first region in a top view, and forming a diode in the diode region of the semiconductor substrate, wherein the diode region has a second region in a top view. Forming the IGBT includes forming a plurality of first trenches having a first trench electrode and extending perpendicular to the first main surface of the semiconductor substrate in the IGBT region. Forming the diode includes forming a plurality of second trenches having a second trench electrode extending perpendicular to the first main surface of the semiconductor substrate in the diode region. As a result, the capacitance density of the capacitance formed between the plurality of second trenches and the semiconductor substrate per second region is lower than the capacitance density of the capacitance formed between the plurality of first trenches and the semiconductor substrate per first region.

[0067] Example 23. The method according to Example 22, wherein forming the plurality of second trenches includes forming a smaller number of second trenches per unit area in the diode region than the number of first trenches per unit area in the IGBT region.

[0068] Example 24. The method according to Example 22 or 23, wherein forming a plurality of second trenches includes terminating the second trenches shallower than the first trenches within a semiconductor substrate.

[0069] Example 25. The method according to any one of Examples 22 to 24, wherein forming a plurality of second trenches includes spacing the second trenches further apart in a diode region than the first trenches are spaced apart in an IGBT region.

[0070] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and these are not restrictive either. Throughout the description, the same terms refer to the same elements.

[0071] In this specification, terms such as "having", "containing", "including", "comprising", etc. are open - ended terms that indicate the presence of the indicated elements or features but do not exclude additional elements or features. The articles "a", "an", and "the" include not only the singular but also the plural unless the context clearly indicates otherwise.

[0072] Although specific embodiments have been illustrated and described in this specification, those skilled in the art will understand that various alternative implementations and / or equivalent implementations may be used instead of the specific embodiments illustrated and described without departing from the scope of the invention. This application encompasses any modifications or variations of the specific embodiments described herein. Therefore, the invention is limited only by the claims and their equivalents.

Description of Reference Numerals

[0073] 100 Power semiconductor device 102 Semiconductor substrate 103 First main surface 104 Cell region 105 Second main surface 106 Peripheral region 108 Edge 110 IGBT region 112 Diode region 114 First trench 116 First trench electrode 118 First insulating layer 120 Conductive channel 122 Body region 124 Emitter region 126 Drift region 128 Collector region 130 Field stop region 132 Second trench 134 Second trench electrode 136 Second insulating layer 138 Cathode region 140 First metallization 141 Anode region 142 Insulating material 144 First contact trench 146 Second contact trench 148 High concentration doped region 150 Second metallization

Claims

A semiconductor substrate comprising an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, wherein in a top view, the IGBT region has a first region, and the diode region has a second region in the top view. The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region has a second trench electrode and a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate. The capacitance density of the second capacitance per unit area of the second region is lower than the capacitance density of the first capacitance per unit area of the first region. The plurality of first trenches extend to a first depth of the semiconductor substrate, the plurality of second trenches extend to a second depth of the semiconductor substrate, and the second depth is shallower than the first depth, a power semiconductor device. A semiconductor substrate comprising an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, wherein in a top view, the IGBT region has a first region, and the diode region has a second region in the top view. The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region has a second trench electrode and a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate. The capacitance density of the second capacitance per the second region is lower than the capacitance density of the first capacitance per the first region, A power semiconductor device in which an insulating layer between the second trench electrode and the semiconductor substrate is thicker than the insulating layer between the first trench electrode and the semiconductor substrate. **Claim 3**: A semiconductor substrate including an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, the semiconductor substrate having a first region in a top view for the IGBT region and a second region in the top view for the diode region, The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicularly to a first main surface of the semiconductor substrate, The diode region has a second trench electrode and a plurality of second trenches extending perpendicularly to the first main surface of the semiconductor substrate, In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate, The capacitance density of the second capacitance per the second region is lower than the capacitance density of the first capacitance per the first region, A power semiconductor device in which a dielectric constant of an insulating layer between the second trench electrode and the semiconductor substrate is lower than a dielectric constant of an insulating layer between the first trench electrode and the semiconductor substrate. **Claim 4**: A power semiconductor device including a semiconductor substrate including an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, the semiconductor substrate having a first region in a top view for the IGBT region and a second region in the top view for the diode region, The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicularly to a first main surface of the semiconductor substrate, The diode region has a second trench electrode and a plurality of second trenches extending perpendicularly to the first main surface of the semiconductor substrate, In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate. The capacitance density of the second capacitance per second region is lower than the capacitance density of the first capacitance per first region. The power semiconductor device comprises a plurality of first contact trenches extending perpendicular to the first main surface of the semiconductor substrate in the IGBT region, and a plurality of second contact trenches extending perpendicular to the first main surface of the semiconductor substrate in the diode region. The power semiconductor device further comprises: a power semiconductor device in which an average density of sidewall regions of the second contact trenches between adjacent second trenches in the diode region is higher than an average density of sidewall regions of the first contact trenches between adjacent first trenches in the IGBT region. **Claim 5** The power semiconductor device according to claim 4, wherein at least two second contact trenches are arranged between adjacent second trenches in the diode region, and a single first contact trench is arranged between adjacent first trenches in the IGBT region. **Claim 6** The power semiconductor device according to claim 4, wherein at least four contact trenches are arranged between adjacent second trenches in the diode region, and a single first contact trench is arranged between adjacent first trenches in the IGBT region. **Claim 7** The power semiconductor device according to claim 4, wherein a doping concentration of the semiconductor substrate on sidewalls of the plurality of second contact trenches is lower than a doping concentration of the semiconductor substrate at lower ends of the plurality of second contact trenches. **Claim 8** A power semiconductor device comprising a semiconductor substrate including an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, wherein the IGBT region has a first region in a top view, and the diode region has a second region in the top view, the power semiconductor device comprising: The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicular to the first main surface of the semiconductor substrate. The diode region includes a second trench electrode and a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate, The capacitance density of the second capacitance per second region is lower than the capacitance density of the first capacitance per first region, The power semiconductor device, In the IGBT region, a plurality of first contact trenches extending perpendicular to the first main surface of the semiconductor substrate, In the diode region, a plurality of second contact trenches extending perpendicular to the first main surface of the semiconductor substrate further comprises, A power semiconductor device in which the average density of the sidewall regions of the second contact trenches per second region is higher than the average density of the sidewall regions of the first contact trenches per first region.

9. A semiconductor substrate including an IGBT region including an IGBT (Insulated Gate Bipolar Transistor) and a diode region including a diode, wherein the IGBT region has a first region in a top view, and the diode region has a second region in the top view. A power semiconductor device comprising a semiconductor substrate, The IGBT region includes a first trench electrode and a plurality of first trenches extending perpendicular to the first main surface of the semiconductor substrate, The diode region includes a second trench electrode and a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, In the IGBT region, the plurality of first trenches form a first capacitance between the first trench electrode and the semiconductor substrate, and in the diode region, the plurality of second trenches form a second capacitance between the second trench electrode and the semiconductor substrate, The capacitance density of the second capacitance per second region is lower than the capacitance density of the first capacitance per first region, The power semiconductor device, A plurality of first contact trenches extending perpendicular to the first major surface of the semiconductor substrate in the IGBT region; A plurality of second contact trenches extending perpendicular to the first major surface of the semiconductor substrate in the diode region further comprising: In the IGBT region, a single first contact trench is disposed between adjacent first trenches; In the diode region, a single second contact trench is disposed between adjacent second trenches; A power semiconductor device, wherein an average width of the second contact trench is wider than an average width of the first contact trench.

10. The power semiconductor device according to any one of claims 1 to 9, wherein a capacitance density of the second capacitance per second region is from one-fifteenth to one-tenth of a capacitance density of the first capacitance per first region.

11. A semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode, wherein the IGBT region has a first region in a top view, and the diode region has a second region in the top view; A plurality of first contact trenches extending on the first major surface of the semiconductor substrate in the IGBT region; A plurality of second contact trenches extending on the first major surface of the semiconductor substrate in the diode region, comprising: The IGBT region includes a plurality of first trenches extending perpendicular to the first major surface of the semiconductor substrate; The diode region includes a plurality of second trenches extending perpendicular to the first major surface of the semiconductor substrate; A lateral average spacing between adjacent ones of the second trenches is wider than a lateral average spacing between adjacent ones of the first trenches; A power semiconductor device, wherein an average density of sidewall regions of second contact trenches between adjacent second trenches per second region is higher than an average density of sidewall regions of first contact trenches between adjacent first trenches per first region.

12. The power semiconductor device according to claim 11, wherein the lateral average spacing between adjacent ones of the second trenches is from 1.5 times to 30 times as wide as the lateral average spacing between adjacent ones of the first trenches.

13. The power semiconductor device according to claim 11, wherein a lateral average interval between adjacent trenches among the second trenches is wider than 0.6 μm and narrower than 20 μm.

14. The power semiconductor device according to claim 11, wherein at least two second contact trenches are disposed between adjacent second trenches in the diode region, and a single first contact trench is disposed between adjacent first trenches in the IGBT region.

15. The power semiconductor device according to claim 11, wherein at least four contact trenches are disposed between adjacent second trenches in the diode region, and a single first contact trench is disposed between adjacent first trenches in the IGBT region.

16. The power semiconductor device according to claim 11, wherein a doping concentration of the semiconductor substrate on sidewalls of the plurality of second contact trenches is lower than a doping concentration of the semiconductor substrate at lower ends of the plurality of second contact trenches.

17. A semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode, a plurality of first contact trenches extending perpendicularly to a first main surface of the semiconductor substrate in the IGBT region, a plurality of second contact trenches extending perpendicularly to the first main surface of the semiconductor substrate in the diode region, comprising: the IGBT region includes a plurality of first trenches extending perpendicularly to the first main surface of the semiconductor substrate, the diode region includes a plurality of second trenches extending perpendicularly to the first main surface of the semiconductor substrate, a lateral average interval between adjacent trenches among the second trenches is wider than a lateral average interval between adjacent trenches among the first trenches, a single first contact trench is disposed between adjacent first trenches in the IGBT region, a single second contact trench is disposed between adjacent second trenches in the diode region, the power semiconductor device, wherein an average width of the second contact trench is wider than an average width of the first contact trench.

18. Comprising a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode, the IGBT region includes a plurality of first trenches extending perpendicularly to a first main surface of the semiconductor substrate, The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, wherein a lateral average spacing between adjacent trenches among the second trenches is wider than a lateral average spacing between adjacent trenches among the first trenches, each of the second trenches is segmented into trench portions along a direction of an extending portion in a longitudinal direction of the plurality of second trenches, and adjacent trench portions among the second trenches are separated from each other by a substrate region of the semiconductor substrate, a power semiconductor device.

19. A semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode, and a plurality of contact trenches extending on a first main surface of the semiconductor substrate in the diode region, wherein the IGBT region includes a plurality of first trenches extending perpendicular to the first main surface of the semiconductor substrate, the diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate, a lateral average spacing between adjacent trenches among the second trenches is wider than a lateral average spacing between adjacent trenches among the first trenches, the contact trenches are connected at a predetermined position by one or a plurality of cross contact trenches extending in a direction perpendicular to an extending portion in a longitudinal direction of the contact trenches, a power semiconductor device.

20. A method of manufacturing a power semiconductor device, comprising forming an IGBT in an IGBT region of a semiconductor substrate, wherein in a top view, the IGBT region has a first region, and forming a diode in a diode region of the semiconductor substrate, wherein in the top view, the diode region has a second region and including forming the IGBT includes forming, in the IGBT region, a plurality of first trenches having first trench electrodes and extending perpendicular to a first main surface of the semiconductor substrate, Forming the diode includes forming a plurality of second trenches having second trench electrodes extending perpendicular to the first main surface of the semiconductor substrate in the diode region, so that the capacitance density of the capacitance formed between the plurality of second trenches and the semiconductor substrate per second region is lower than the capacitance density of the capacitance formed between the plurality of first trenches and the semiconductor substrate per first region. A method, wherein forming the plurality of second trenches includes terminating the second trenches shallower than the first trenches within the semiconductor substrate. Claim 21 The method according to claim 20, wherein forming the plurality of second trenches includes forming a smaller number of second trenches per unit area in the diode region than the number of first trenches per unit area present in the IGBT region. Claim 22 The method according to claim 20, wherein forming the plurality of second trenches includes further spacing the second trenches in the diode region more than the first trenches are spaced apart in the IGBT region.

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