Semiconductor solid-state battery and method for determining the level of a semiconductor solid-state battery

Abstract

To provide a high-capacity semiconductor solid battery and a simulation method of the semiconductor solid battery.SOLUTION: There is provided a semiconductor solid battery which comprises: a P-type semiconductor layer; an N-type semiconductor layer; and an insulating layer. The insulating layer is provided between the P-type semiconductor layer and the N-type semiconductor layer. When an interface between the P-type semiconductor layer and the insulating layer is a first interface and an interface between the insulating layer and the N-type semiconductor layer is a second interface, a level E2 of un upper end of a valence band of the N-type semiconductor layer is lower than a level E1 of un upper end of the valence band of the insulating layer in the second interface.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor solid-state battery and a method for determining the level of a semiconductor solid-state battery.

Background Art

[0002] In recent years, from the viewpoints of the spread of electrical equipment and energy conservation, it has been required to efficiently utilize electric power. Along with this, the development of secondary batteries that can charge and discharge electricity has been promoted. As secondary batteries, various types such as lithium-ion secondary batteries, lead-acid batteries, and nickel-metal hydride batteries have been developed. For example, Japanese Patent Application Laid-Open No. 2001-338649 (Patent Document 1) discloses a lithium-ion secondary battery using a Li-containing transition metal composite oxide as a positive electrode active material. Since lithium-ion secondary batteries can also be miniaturized, they are used as batteries for electrical equipment.

[0003] On the other hand, lithium-ion secondary batteries have a configuration in which lithium ions are taken in and out through an electrolyte. Therefore, it is a battery that requires an electrolyte such as a liquid electrolyte (electrolyte solution). Lead-acid batteries and nickel-metal hydride batteries are also batteries that require an electrolyte solution. If the electrolyte solution leaks, it can cause fires and explosions. For this reason, lithium-ion secondary batteries have a sealed structure so as not to cause liquid leakage. However, problems such as liquid leakage occurring due to deterioration during long-term use, the way of using electrical equipment, and the usage environment have occurred.

[0004] In order to eliminate such problems caused by liquid leakage, the development of semiconductor solid-state batteries has been promoted. Semiconductor solid-state batteries capture electrons at energy levels and perform charging. Since it can be a fully solid secondary battery, there is no need to use an electrolyte solution.

[0005] Examples of semiconductor solid-state batteries include those disclosed in International Publication No. 2018 / 117235 (Patent Document 2). In Patent Document 2, the semiconductor solid-state battery has a three-layer structure of an N-type semiconductor layer, an insulating layer, and a P-type semiconductor layer. In Patent Document 2, by controlling the trapping levels of the semiconductor layer, the energy density is improved and the voltage drop is suppressed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] The problem to be solved by the present invention is to provide a high-capacity semiconductor solid-state battery and a method for determining the levels of a semiconductor solid-state battery.

Means for Solving the Problems

[0009] According to an embodiment, a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer is provided. The insulating layer is provided between the P-type semiconductor layer and the N-type semiconductor layer. The P-type semiconductor layer is made of nickel oxide, and the N-type semiconductor layer is made of titanium oxide. The insulating layer is selected from one or more of the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. made of a material having a band gap of 4.5 eV When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, in the state of thermal equilibrium or the state before charging, the energy level E2 of the valence band upper end of the N-type semiconductor layer is lower than the energy level E1 of the valence band upper end of the insulating layer at the second interface.

[0010] According to another embodiment, a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer is provided. The insulating layer is provided between the P-type semiconductor layer and the N-type semiconductor layer. The P-type semiconductor layer is made of nickel oxide, and the N-type semiconductor layer is made of titanium oxide. The insulating layer is selected from one or more of the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. made of a material having a band gap of 4.5 eV When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, in the state of thermal equilibrium or the state before charging, the energy level E-II of the conduction band lower end of the insulating layer is lower than the energy level E-I of the conduction band lower end of the P-type semiconductor layer at the first interface.

[0011] According to still another embodiment, a method for determining the energy levels of a semiconductor solid-state battery is provided. The semiconductor solid-state battery includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. In the semiconductor solid-state battery, the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface, and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface. The method for determining the energy levels includes obtaining the energy levels including the energy level E1 of the valence band upper end of the insulating layer and the energy level E2 of the valence band upper end of the N-type semiconductor layer at the second interface, and / or the energy level E-I of the conduction band lower end of the P-type semiconductor layer and the energy level E-II of the conduction band lower end of the insulating layer at the first interface. In the energy level determination method, the energy levels in the state of thermal equilibrium or the state before charging are obtained. The level determination method includes obtaining levels including level E1 and level E2 and / or level E-I and level E-II by calculating a self-consistent collisionless loop using Poisson's equation and the carrier continuity equation, determining the convergence of the calculation of the self-consistent collisionless loop by checking the consistency with an external circuit, and checking the levels of level E1 and level E2 and / or the levels of level E-I and level E-II.

Brief Description of Drawings

[0012] [Figure 1] Conceptual diagram showing an example of the band structure of a semiconductor solid-state battery according to an embodiment. [Figure 2] Graph showing an example of the relationship between the valence band top and the conduction band bottom levels of a semiconductor solid-state battery according to an embodiment. [Figure 3] Graph showing an example of the relationship between the valence band top and the conduction band bottom levels of a conventional semiconductor solid-state battery. [Figure 4] Schematic cross-sectional view showing an example of a semiconductor solid-state battery according to an embodiment. [Figure 5] Graph showing an example of the relationship between the valence band top and the conduction band bottom levels of a semiconductor solid-state battery according to another embodiment. [Figure 6] Diagram showing an example of a level determination method for a semiconductor solid-state battery according to an embodiment. [Figure 7] Diagram showing an overview of Non-Patent Document 1. [Figure 8] Graph showing an example of constant current discharge of a semiconductor solid-state battery having the relationship between the valence band top and the conduction band bottom levels of FIG. 2. [Figure 9] Graph showing an example of constant current discharge of a semiconductor solid-state battery having the relationship between the valence band top and the conduction band bottom levels of FIG. 3.

Embodiments for Carrying Out the Invention

[0013] In Patent Document 2, the value of the voltage drop is reduced by suppressing the internal resistance of the semiconductor layer. As a result, a rapid decrease in voltage is prevented. On the other hand, there was a limit to the improvement of capacitance. As a result of investigating the cause, it was found that it is necessary to control the level of the upper end of the valence band or the level of the lower end of the conduction band at the interface between the insulating layer and the semiconductor layer.

[0014] In the semiconductor solid-state battery according to the embodiment, by controlling the levels of the upper end of the valence band and the lower end of the conduction band at the interface between the insulating layer and the semiconductor layer, a high capacitance can be exhibited.

[0015] [First Embodiment] According to the first embodiment, a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer is provided. The insulating layer is located between the P-type semiconductor layer and the N-type semiconductor layer. Here, the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface. Also, the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface. The level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 of the upper end of the valence band of the insulating layer at the second interface. By making the level E2 of the upper end of the valence band of the N-type semiconductor layer lower than the level E1 of the upper end of the valence band of the insulating layer at the second interface, holes can be accumulated at the second interface. As a result, the capacitance can be improved.

[0016] Preferably, the level E6 of the lower end of the conduction band of the N-type semiconductor layer is lower than the level E5 of the lower end of the conduction band of the insulating layer at the second interface. By making the level E6 of the lower end of the conduction band of the N-type semiconductor layer lower than the level E5 of the lower end of the conduction band of the insulating layer at the second interface, electrons can be accumulated at the second interface. In the semiconductor solid-state battery in which holes can be accumulated at the second interface by satisfying the relationship E1>E2 as described above, by further satisfying the relationship E5>E6 so that electrons can be accumulated at the second interface, the capacitance of the semiconductor solid-state battery can be further improved.

[0017] Referring to FIGS. 1 to 3, the relationship of energy levels in the semiconductor solid-state battery according to the embodiment will be described. FIG. 1 is a conceptual diagram showing an example of the band structure of the semiconductor solid-state battery according to the embodiment. Further, FIG. 2 is a graph showing an example of the relationship of the levels of the upper end of the valence band and the lower end of the conduction band of the semiconductor solid-state battery according to the embodiment. FIG. 3 is a graph showing an example of the relationship of the levels of the upper end of the valence band and the lower end of the conduction band of a conventional semiconductor solid-state battery.

[0018] The semiconductor solid-state battery 1 shown in FIG. 1 includes a P-type semiconductor layer 2, an insulating layer 3, and an N-type semiconductor layer 4. The insulating layer 3 is between the P-type semiconductor layer 2 and the N-type semiconductor layer 4. In FIG. 1, the order of the P-type semiconductor layer 2 / insulating layer 3 / N-type semiconductor layer 4 is exemplified, but the P-type semiconductor layer 2 and the N-type semiconductor layer 4 may be reversed.

[0019] The following will be described by taking as an example the structure with the interface between the insulating layer 3 and the N-type semiconductor layer 4 as the second interface. That is, it is an explanation of the semiconductor solid-state battery 1 in which carriers (electrons or holes) are accumulated at the second interface.

[0020] The semiconductor solid-state battery 1 has an insulating layer 3 between the P-type semiconductor layer 2 and the N-type semiconductor layer 4. The P-type semiconductor layer 2 has holes as carriers. Further, the N-type semiconductor layer 4 has electrons as carriers. The insulating layer 3 has a function of suppressing the recombination of holes in the P-type semiconductor layer 2 and electrons in the N-type semiconductor layer 4. Also, the interface between the P-type semiconductor layer 2 and the insulating layer 3 is the first interface, and the interface between the insulating layer 3 and the N-type semiconductor layer 4 is the second interface.

[0021] In the semiconductor solid-state battery according to the embodiment, the level E2 of the upper end 12 of the valence band of the N-type semiconductor layer 4 at the second interface is lower than the level E1 of the upper end 11 of the valence band of the insulating layer 3 at the second interface. Also, preferably, the level E6 of the lower end 26 of the conduction band of the N-type semiconductor layer at the second interface is lower than the level E5 of the lower end 25 of the conduction band of the insulating layer 3 at the second interface.

[0022] Figure 2 shows an example of the relationship between the upper valence band edge and the lower conduction band edge of the semiconductor solid-state battery according to the embodiment. Figure 2 is a graph corresponding to the band diagram of the semiconductor solid-state battery 1 in a state of thermal equilibrium or before charging. In Figure 2, the horizontal axis represents the position, and the vertical axis represents the energy level. The solid line 10 at the lower part of Figure 2 indicates the upper valence band edge. Also, the solid line 20 at the upper part of Figure 2 indicates the lower conduction band edge. The dashed line 30 represents the Fermi level in the thermal equilibrium state. In the graph, the regions representing the P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4 are arranged in order along the horizontal axis from the 0 nm side. Also, the horizontal axis and the vertical axis in Figure 2 are provided with a memory for convenience in explaining the embodiment, and the positions and dimensions of each semiconductor layer and insulating layer are not limited to this range.

[0023] In Figure 2, there is a place where the level rises vertically at a position near 300 nm. This rising place corresponds to the first interface between the P-type semiconductor layer 2 and the insulating layer 3. Also, in Figure 2, there is a place where the level rises vertically at a position near 600 nm. This rising place corresponds to the second interface between the insulating layer 3 and the N-type semiconductor layer 4.

[0024] When the semiconductor solid-state battery 1 is charged, a part of the holes supplied to the P-type semiconductor layer 2 can overcome the barrier at the first interface and pass through the insulating layer 3 to move to the second interface by thermal excitation or tunneling effect, etc. The semiconductor solid-state battery according to the embodiment satisfies the relationship of E1>E2. By satisfying this relationship, holes can be stored at the second interface. Thereby, high capacity can be achieved.

[0025] FIG. 3 shows an example of the relationship between the upper level of the valence band and the lower level of the conduction band of a conventional semiconductor solid-state battery. FIG. 3 is a graph modeled with reference to FIG. 1 of Patent Document 2 and corresponds to the band diagram in the state of thermal equilibrium or before charging. The solid line 10 at the lower part of FIG. 3 indicates the upper level of the valence band, and the solid line 20 at the upper part indicates the lower level of the conduction band. The dashed line 30 represents the Fermi level in the state of thermal equilibrium. For FIG. 3 as well, the location where the level rises vertically near 300 nm is the first interface, and the location where the level rises vertically near 600 nm is the second interface.

[0026] In a conventional semiconductor solid-state battery, the relationship of E1 < E2 holds. Even with such a relationship, recombination of electrons and holes could be suppressed. On the other hand, the amount of holes gathering at the second interface was very small.

[0027] By satisfying E1 > E2, holes can be stored at the second interface. Also, it is preferable that E1 - E2 ≥ 0.1 eV. The difference in the levels of E1 and E2 allows more holes to be stored. Therefore, the larger "E1 - E2" is, the more preferable it is.

[0028] Also, when the level of the upper level 13 of the valence band of the P-type semiconductor layer 2 at the first interface is E3 and the level of the upper level 14 of the valence band of the insulating layer 3 is E4, it is preferable to satisfy |E3 - E4| ≤ 2 eV. The fact that |E3 - E4| ≤ 2 eV indicates that the difference in levels at the interface between the P-type semiconductor layer 2 and the insulating layer 3 is small. The difference in levels (|E3 - E4|) between the P-type semiconductor layer 2 and the insulating layer 3 at this interface (the first interface) can be a barrier at the first interface, but by reducing the value of |E3 - E4|, holes can more easily overcome the barrier, so the storage of holes at the second interface is promoted. As a result, further higher capacity can be achieved. For example, the accumulation amount of holes at the second interface can be made 1 × 10 19 cm -3 or more. On the other hand, if |E3 - E4| exceeds 2 eV and becomes too large, the barrier may become too large. The relationship where there is no difference in levels at the first interface (|E3 - E4| = 0), E3 = E4, may also be acceptable.

[0029] Note that since either E3 or E4 can be larger, the difference in the above levels is discussed in terms of the absolute value |E3 - E4|. Also, it is preferable that E3 > E4. By controlling the level at the first interface, the accumulation amount of carriers can be improved. Moreover, the recombination of electrons and holes can be suppressed. Further, by combining the relationship |E3 - E4| ≤ 2 eV with the relationship E1 > E2, more effective results can be obtained.

[0030] When the level E5 of the lower end 25 of the conduction band of the insulating layer 3 and the level E6 of the lower end 26 of the conduction band of the N-type semiconductor layer 4 at the second interface, which is the interface between the insulating layer 3 and the N-type semiconductor layer 4, it is preferable to satisfy the relationship E5 - E6 > 0. E5 and E6 are the levels of the lower end of the conduction band at the second interface. By making E5 larger than E6 (E5 > E6), electrons can be stored at the second interface. For this reason, it is preferable that E5 - E6 > 0, and further E5 - E6 ≥ 1.5 eV. By combining this relationship with the aforementioned relationship E1 > E2, the amount of stored electrons can be increased. Note that the relational expressions shown for E1 to E6 above represent the band diagram in the thermal equilibrium state or before charging. In other words, it is assumed that the above relational expressions do not need to be satisfied after charging. For example, in FIG. 2 showing the state of thermal equilibrium or before charging, the relationship E1 < E4 is shown, but as charging progresses and carriers are accumulated, the relationship E1 > E4 can be obtained. Also, after discharging, it returns to the relationship E1 < E4.

[0031] The above description relates to the semiconductor solid battery 1 having a structure for accumulating carriers at the second interface. When manufacturing the semiconductor solid battery 1 having a structure for accumulating carriers at the first interface, it will have the levels obtained by rotating FIG. 2 by 180°. For this reason, it is assumed that the simulation is performed by interchanging the relationship between the first interface and the second interface. Such a semiconductor solid battery 1 will be described in the second embodiment.

[0032] The P-type semiconductor layer 2 has holes as carriers. The N-type semiconductor layer 4 has electrons as carriers. Also, various semiconductor materials can be applied to the P-type semiconductor layer 2 or the N-type semiconductor layer 4. Examples of semiconductor materials include silicon semiconductors, compound semiconductors, oxide semiconductors, nitride semiconductors, amorphous semiconductors, etc. Examples of silicon semiconductors include metal silicides, amorphous silicon, polycrystalline silicon, crystalline silicon, single crystal silicon, etc. Also, examples of compound semiconductors include Group IV, I-VII, II-VI, III-V, chalcopyrite type, perovskite type, etc. Here, Group IV, Group I, Group VII, Group II, Group VI, Group III, and Group V are the families of elements shown in the periodic table. Also, examples of oxide semiconductors include metal oxides, metal composite oxides, metal oxynitrides, etc.

[0033] Also, the P-type semiconductor layer 2 or the N-type semiconductor layer 4 is preferably made of a metal oxide. This is because it is easier to control the carrier amount by introducing oxygen vacancies, metal vacancies, and impurity doping in the case of metal oxides.

[0034] For the metal oxide, it is preferable to use one or more selected from the group consisting of tungsten oxide (WO3), molybdenum oxide (MoO2, MoO3), titanium oxide (TiO2), tin oxide (SnO2, SnO), zinc oxide (ZnO), nickel oxide (NiO), copper oxide (Cu2O), cadmium oxide (CdO), aluminum oxide (Al2O3), and gallium oxide (Ga2O3).

[0035] The material of the insulating layer 3 is not particularly limited as long as it can suppress the recombination of electrons and holes. Also, the thickness of the insulating layer 3 is preferably 30 μm or less. Note that the lower limit of the thickness of the insulating layer 3 is not particularly limited, but 1 nm or more is preferable. If the thickness is 1 nm or more, the effect of suppressing recombination can be more surely exhibited. For this reason, the thickness of the insulating layer 3 is preferably 1 nm or more and 30 μm or less, and more preferably 10 nm or more and 20 μm or less.

[0036] For the insulating layer 3, it is preferable to use one or more selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. For the metal oxide, it is preferable to use one or more oxides (including composite oxides) selected from the group consisting of silicon, aluminum, tantalum, nickel, copper, and iron. Also, for the metal nitride, it is preferable to use one or more nitrides (including composite nitrides) selected from the group consisting of silicon and aluminum. Examples of the metal oxynitride include silicon oxynitride (SiON).

[0037] As described above, by controlling the energy levels at the second interface, or the second interface and the first interface, the capacitance of the semiconductor solid-state battery can be improved. Such a semiconductor solid-state battery can be manufactured, for example, using a film-forming method such as sputtering.

[0038] So far, the energy levels in the stacked structure of the P-type semiconductor layer 2 / insulating layer 3 / N-type semiconductor layer 4 have been described. When used as a semiconductor solid-state battery, for example, electrodes can be further provided. FIG. 4 shows a schematic cross-sectional view representing an example of the structure of a semiconductor solid-state battery according to an embodiment. The semiconductor solid-state battery 1 includes a P-type semiconductor layer 2, an insulating layer 3, an N-type semiconductor layer 4, a front-side electrode 5, a back-side electrode 6, and a substrate 7. With the substrate 7 side as the back side, the members of the semiconductor solid-state battery 1 are stacked in the order of front-side electrode 5 / P-type semiconductor layer 2 / insulating layer 3 / N-type semiconductor layer 4 / back-side electrode 6 / substrate 7 from the front side to the back side.

[0039] For the front-side electrode 5 and the back-side electrode 6, it is preferable to use a highly conductive metal material such as gold (Au), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo). Also, each electrode may be a transparent electrode material such as ITO (Indium-doped Tin Oxide). Each electrode may further have a multilayer structure combining these materials.

[0040] For the substrate 7, for example, an insulating substrate can be used. Examples of the insulating substrate include a glass substrate, a ceramic substrate, and a resin substrate. Further, a semiconductor substrate such as a silicon substrate provided with an insulating film may be used as the insulating substrate.

[0041] In FIG. 4, the front-side electrode 5 / P-type semiconductor layer 2 / insulating layer 3 / N-type semiconductor layer 4 / back-side electrode 6 / substrate 7 are shown in this order, but the positions of the P-type semiconductor layer 2 and the N-type semiconductor layer 4 may be reversed. Further, the front-side electrode 5 and the back-side electrode 6 can be provided on the entire surface or a part of the surface of the semiconductor layer.

[0042] As described above, it is important to control the energy levels in the semiconductor solid-state battery. For controlling the energy levels, it is preferable to use the simulation technique described in the third embodiment in the following. That is, the semiconductor solid-state battery according to the first embodiment is preferably manufactured based on the energy level determination according to the third embodiment.

[0043] The semiconductor solid-state battery according to the first embodiment includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. The energy level E2 of the valence band upper end of the N-type semiconductor layer is lower than the energy level E1 of the valence band upper end of the insulating layer at the second interface between the insulating layer and the N-type semiconductor layer. The semiconductor solid-state battery can exhibit a high capacitance.

[0044] [Second Embodiment] According to the second embodiment, a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer is provided. The insulating layer is located between the P-type semiconductor layer and the N-type semiconductor layer. Similar to the first embodiment, the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface. Also, the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface. The energy level E-II of the conduction band lower end of the insulating layer is lower than the energy level E-I of the conduction band lower end of the P-type semiconductor layer at the first interface. By making the energy level E-II of the conduction band lower end of the insulating layer lower than the energy level E-I of the conduction band lower end of the P-type semiconductor layer at the first interface, electrons can be accumulated at the first interface. Thereby, the capacitance can be improved.

[0045] When the level of the upper end of the valence band of the insulating layer at the first interface is E-V and the level of the upper end of the valence band of the P-type semiconductor layer is E-VI, it is preferable that [E-VI] - [E-V] ≥ 0.1 eV. The fact that [E-VI] - [E-V] ≥ 0.1 eV means that at the interface between the insulating layer and the P-type semiconductor layer, the level E-VI of the upper end of the valence band of the P-type semiconductor layer is higher than the level E-V of the upper end of the valence band of the insulating layer (E-VI > E-V), and there is a substantial level difference. Due to the level difference at this interface (the first interface), holes can be stored here. As a result, a higher capacitance can be achieved.

[0046] By controlling the levels at the first interface, the accumulation amount of carriers can be improved. Moreover, the recombination of electrons and holes can be suppressed. Also, by combining the relationship of [E-VI] - [E-V] ≥ 0.1 eV with the relationship of E-I > E-II, more effective results can be obtained. Also, by making E-VI larger than E-V, more effective results can be obtained. Therefore, the larger the difference between E-VI and E-V, the more preferable. If the difference between E-VI and E-V is small, holes are likely to accumulate at the second interface.

[0047] In a semiconductor solid-state battery capable of accumulating electrons at the first interface by satisfying the relationship of E-I > E-II as described above, by further satisfying the relationship of E-VI > E-V so that holes can be accumulated at the first interface, the capacitance of the semiconductor solid-state battery can be further improved.

[0048] With reference to FIG. 5, the relationship of energy levels in the semiconductor solid-state battery according to the embodiment will be described. FIG. 5 is a graph showing an example of the relationship of the levels of the upper end of the valence band and the lower end of the conduction band of the semiconductor solid-state battery according to the second embodiment. Note that the semiconductor solid-state battery according to the second embodiment may have a band structure similar to the band structure of the semiconductor solid-state battery according to the first embodiment. Since it overlaps with the description in the first embodiment, the details are omitted.

[0049] In the semiconductor solid-state battery according to the embodiment, the level E-II of the lower end 22 of the conduction band of the insulating layer 3 at the first interface is lower than the level E-I of the lower end 21 of the conduction band of the P-type semiconductor layer 2 at the first interface. Further, it is preferable that the level E-V of the upper end 15 of the valence band of the insulating layer 3 at the first interface and the level E-VI of the upper end 16 of the valence band of the P-type semiconductor layer 2 at the first interface satisfy the relationship [E-VI] - [E-V] ≧ 0.1 eV.

[0050] FIG. 5 shows an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of the semiconductor solid-state battery according to the second embodiment. FIG. 5 is a graph corresponding to the band diagram of the semiconductor solid-state battery 1 in a state of thermal equilibrium or before charging. In FIG. 5, the horizontal axis represents the position, and the vertical axis represents the energy level. The solid line 10 at the lower part of FIG. 5 indicates the upper end of the valence band, and the solid line 20 at the upper part indicates the lower end of the conduction band. The broken line 30 represents the Fermi level in the thermal equilibrium state. In the graph, the regions representing the P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4 are arranged in order along the horizontal axis from the 0 nm side. Also, the horizontal axis and the vertical axis in FIG. 5 are provided with memories for convenience in explaining the embodiment, and the positions and dimensions of each semiconductor layer and insulating layer are not limited to this range.

[0051] In FIG. 5, the location where the level rises vertically at around 300 nm corresponds to the first interface that is the interface between the P-type semiconductor layer 2 and the insulating layer 3. Also, the location where the level rises vertically at around 600 nm corresponds to the second interface that is the interface between the insulating layer 3 and the N-type semiconductor layer 4.

[0052] When the semiconductor solid-state battery 1 is charged, a part of the electrons supplied to the N-type semiconductor layer 4 can overcome the barrier at the second interface by thermal excitation or tunneling effect, etc., conduct within the insulating layer 3, and move to the first interface. In the semiconductor solid-state battery according to the second embodiment, since the relationship E-I > E-II is satisfied, electrons can be stored at the first interface. As a result, high capacity can be achieved.

[0053] It is preferable that {[E-I] - [E-II]} ≥ 0.1 eV. Since there is a difference in levels between E-I and E-II, more electrons can be stored. Therefore, the larger {[E-I] - [E-II]} is, the more preferable it is.

[0054] Also, when the level of the lower end 23 of the conduction band of the N-type semiconductor layer 4 at the second interface is E-III and the level of the lower end 24 of the conduction band of the insulating layer 3 is E-IV, it is preferable to satisfy |[E-III] - [E-IV]| ≤ 2 eV. The fact that |[E-III] - [E-IV]| ≤ 2 eV indicates that the difference in levels at the interface between the N-type semiconductor layer 4 and the insulating layer 3 is small. The difference in levels (|[E-III] - [E-IV]|) between the N-type semiconductor layer 4 and the insulating layer 3 at this interface (the second interface) can be a barrier at the second interface, but by reducing the value of |[E-III] - [E-IV]|, electrons can more easily overcome the barrier, so the storage of electrons at the first interface is promoted. As a result, further higher capacity can be achieved. On the other hand, if |[E-III] - [E-IV]| exceeds 2 eV and becomes too large, the barrier may become too large. The difference in levels at the second interface may be absent (|[E-III] - [E-IV]| = 0), that is, the relationship E-III = E-IV may hold.

[0055] Note that since either E-III or E-IV can be larger, the above difference in levels is discussed in terms of the absolute value |[E-III] - [E-IV]|. Also, it is preferable that E-IV > E-III. By controlling the levels at the second interface, the accumulation amount of carriers can be improved. Moreover, recombination of electrons and holes can be suppressed. Further, by combining the relationship |[E-III] - [E-IV]| ≤ 2 eV with the relationship E-I > E-II, more effective results can be obtained.

[0056] Note that the relational expressions shown in the above E-I to E-VI represent the band diagrams in the thermal equilibrium state or before charging. In other words, it is assumed that the above relational expressions do not need to be satisfied after charging. For example, in FIG. 5 showing the state of thermal equilibrium or the state before charging, the relationship E-II > E-IV is shown. However, when charging progresses and carriers are accumulated, the relationship E-II < E-IV may be established. After discharging, it returns to E-II > E-IV.

[0057] For each of the P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4, the same materials as those described in the first embodiment can be used respectively. Also, dimensions such as the thickness of each layer can be set in the same manner as in Example 1. Since the content is repetitive, the description is omitted.

[0058] As described above, by controlling the energy levels at the first interface, or the first interface and the second interface, the capacitance of the semiconductor solid-state battery can be improved. Such a semiconductor solid-state battery can be manufactured, for example, using a film-forming method such as sputtering.

[0059] Regarding the semiconductor solid-state battery according to the second embodiment as well, similar to the first embodiment, for example, electrodes can be further provided. Since the content is repetitive, the description is omitted.

[0060] As described above, controlling the energy levels is important in a semiconductor solid-state battery. For controlling the energy levels, it is preferable to use the simulation technique described in the subsequent third embodiment. That is, the semiconductor solid-state battery according to the second embodiment is preferably manufactured based on the energy level determination according to the third embodiment.

[0061] The semiconductor solid-state battery according to the second embodiment includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. At the first interface between the P-type semiconductor layer and the insulating layer, the energy level E-II of the upper end of the valence band of the insulating layer is lower than the energy level E-I of the upper end of the valence band of the P-type semiconductor layer. The semiconductor solid-state battery can exhibit a high capacitance.

[0062] [Embodiment 3] According to the third embodiment, a method for determining the levels of a semiconductor solid-state battery is provided. That is, by this method, it is possible to determine that a semiconductor solid-state battery exhibits battery operation with a combination of materials having levels such as level E1 and level E-I.

[0063] Here, the semiconductor solid-state battery includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. In the semiconductor solid-state battery, the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface. The interface between the insulating layer and the N-type semiconductor layer is defined as the second interface. The level determination method obtains the levels of the semiconductor solid-state battery, including the level E1 of the valence band top of the insulating layer at the second interface, the level E2 of the valence band top of the N-type semiconductor layer at the second interface, and / or the level E-I of the conduction band bottom of the P-type semiconductor layer at the first interface and the level E-II of the conduction band bottom of the insulating layer. The level determination method includes obtaining levels including level E1, level E2, and / or level E-I and level E-II by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation, determining the convergence of the calculation of the self-consistent collisionless loop by checking the consistency with an external circuit, and checking the relative levels of level E1 and level E2 and / or the relative levels of level E-I and level E-II. Also, the consistency with the external circuit is a process of checking whether the current and voltage at the electrodes controlled by the external circuit in a virtual device obtained by connecting the semiconductor solid-state battery to a virtual external circuit match those inside the semiconductor solid-state battery. If they match, it is determined that the calculation has converged, that is, a solution has been obtained. The determination of whether they match will be described in detail later.

[0064] In addition to the above levels E1 and E2, the levels obtained by the calculation of the self-aligned collisionless loop may include the level E3 at the upper end of the valence band of the P-type semiconductor layer at the first interface, the level E4 at the upper end of the valence band of the insulating layer at the first interface, the level E5 at the lower end of the conduction band of the insulating layer at the second interface, and the level E6 at the lower end of the conduction band of the N-type semiconductor layer at the second interface. Alternatively, in addition to the above levels E-I and E-II, the levels to be obtained may include the level E-III at the lower end of the conduction band of the N-type semiconductor layer at the second interface, the level E-IV at the lower end of the conduction band of the insulating layer at the second interface, the level E-V at the upper end of the valence band of the insulating layer, and the level E-VI at the upper end of the valence band of the P-type semiconductor layer at the first interface. By performing the calculation of the self-aligned collisionless loop, for example, band diagrams as shown in FIGS. 2, 3, and 5 can be obtained.

[0065] By performing a simulation in advance using the level determination method according to the embodiment, for example, when selecting materials to be used for each layer (N-type semiconductor layer, insulating layer, P-type semiconductor layer) of the semiconductor solid battery, the above levels E1 to E6 or levels E-I to E-VI in the case of combining the selected materials can be predicted. Therefore, it is possible to estimate before manufacturing whether a semiconductor solid battery according to the first embodiment or a semiconductor solid battery according to the second embodiment can be obtained by the combination of the selected materials. Also, based on the simulation, the physical properties of each material to be combined can be determined, and the material selection can be performed based on the result.

[0066] The simulation method is a method that combines the Poisson equation and the continuity equation of carriers, and generally conforms to a method called device simulation. More specifically, the simulation method corresponds to a simulation based on the drift-diffusion method.

[0067] FIG. 6 shows a rough flow of the level determination method (simulation method). Details will be described below.

[0068] The first step is the calculation of the initial conditions. The calculation of the initial conditions is a process of preparing the physical property values of the materials used for each layer of the semiconductor solid-state battery. The physical property values of the materials may use literature values. For example, in Non-Patent Document 1 (M. Wistey, "Bandgap+Workfunction Heaven (v3.8)") whose outline is shown in FIG. 7, the band gaps and work functions of various materials are summarized.

[0069] As the next second step, the bias voltages (V A , V C ) and time (t) are updated.

[0070] Subsequently, as the third step, the calculation of the self-consistent collisionless loop (i) using the Poisson equation and the carrier continuity equation is performed.

[0071] The Poisson equation is used as an equation showing the electrostatic potential when the charge distribution is given. The Poisson's equation is shown as the following equation (1). In the equation, e is the charge of an electron, p is the hole density, n is the electron density, N D + is the ionized donor density, N A - is the ionized acceptor density, respectively.

[0072]

Equation

[0073] Together with the Poisson equation, the continuity equations for electrons and holes shown by the following equations (2) and (3) are used to calculate each carrier concentration (electron density n and hole density p). Recombination can be, for example, of the SRH (Shockley-Read-Hall) type of the three-level model. Also, if necessary, recombination other than the SRH type may be considered. Also, the current components include the drift current and the diffusion current. In the equation, J n is the electron current, J p is the hole current, and R is the carrier recombination rate, respectively.

[0074]

Number

[0075]

Number

[0076] Here, the process of updating the bias voltages (V A , V C ) and time (t) in the second step will be described. The second step is the process of updating the time t and the electrode potentials (V A , V C ). At this time, the bias V(t) is obtained by the following formula (4). The symbol J Ext in the formula indicates the current flowing through the external circuit.

[0077]

Number

[0078] Formula (4) shows the treatment under the constant voltage boundary condition. Under the constant voltage boundary condition, the total charge amount injected (or released) by the potentials of both electrodes is controlled. The accumulated charge amount Q(t), which is the total charge amount, can be obtained by the following formula (5). Under the constant voltage boundary condition, there is no constraint condition for the electrode current. Therefore, the bias V(t) can be obtained by the calculation based on formulas (4) and (5). In the formulas, n(t) is the electron density at time t, n eq is the electron density in the equilibrium state, p(t) is the hole density at time t, p eq is the hole density in the equilibrium state, and R is the carrier recombination rate, respectively.

[0079]

Number

[0080] When the parasitic resistance cannot be ignored even under the constant voltage boundary condition, the influence of the voltage drop shall be considered by using the electrode current according to the following formula (6). In the formula, V Ext is the voltage applied to the external circuit, V A is the anode potential, V C is the cathode potential, J Ext A / C is the current flowing between the anode / cathode and the external circuit, R S is the resistance component such as the parasitic resistance that may occur due to the influence of poor electrodes, etc., respectively. Note that J Ext A / C is more specifically the symbol meaning "J Ext A or J Ext C ", and J Ext A is the current flowing into or out of the positive electrode from the external circuit, J Ext C is the current flowing into or out of the negative electrode from the external circuit, respectively.

[0081]

Equation

[0082] Next, as the fourth step, using the calculation result of the self-consistent collisionless loop (i), the consistency with the external circuit is confirmed.

[0083] The fourth step of confirming the consistency with the external circuit requires the handling under the constant current boundary condition. First, both electrode potentials are updated so that Equation (7) becomes zero using the Newton method.

[0084]

Equation

[0085] Next, the acceleration parameter corresponding to the time step based on the displacement current J D is obtained using the following formula (8). In the formula, J D(0) represents the mutant current density at the positive electrode, and D(0) represents the flux density at the positive electrode. Also, J D (L) represents the mutant current density at the negative electrode, and D(L) represents the flux density at the negative electrode.

[0086]

Number

[0087] Perform the above steps and conduct a convergence determination in two stages. The convergence determination is based on the convergence of the electrode current and the convergence of the voltage. At this time, set a threshold value for each. Also, for discharge by an external resistance, use the following formula (9). Here, the symbol R S represents the resistance that discharges or consumes power.

[0088]

Number

[0089] The electrode potential and voltage can be determined by the resistance and the electrode current. Also, assume that the convergence determination is performed using the electrode current. When convergence occurs, the relationship of the following formula (10) is obtained.

[0090]

Number

[0091] Update the electrode voltage using formula (7) (Newton's method). The fourth step is to perform this update operation and confirm the consistency between the external circuit and the semiconductor solid-state battery. Specifically, by confirming whether the current and voltage match between the external circuit and the inside of the semiconductor solid-state battery, it is confirmed whether the calculation of the electrode current and voltage has converged, that is, whether the solution of the calculation has been obtained.

[0092] As an example, for a semiconductor battery that is charged and not connected to an external circuit, the state after Δt seconds when a virtual external circuit with a resistance R S is connected and discharge is started will be described. Before starting the calculation, assume that in the initial situation, the semiconductor battery is charged and not connected to an external circuit (open state), so the electrode current is zero and the voltage is V0. The external resistance is R. S When an external resistance R is connected, a current of J0 = V0 / R is assumed to flow through the electrode. S is assumed to flow through the electrode. (2) Require the electrode current J0 as a boundary condition and perform the calculation for the third step. At this time, since a charge of J0×Δt is lost from inside the battery, the voltage inside the semiconductor battery shifts to V1 (V0 > V1). (3) Since the electrode voltage is V1, a current of J1 = V1 / R is assumed to flow out in the external circuit. S However, since the current J1 does not match the previous J0, there is no consistency between the external circuit and the inside of the semiconductor battery. (4) Now, when performing the calculation for the third step on the semiconductor battery with the current J1 as the boundary condition, a charge release of J1×Δt is assumed this time, and thus V2 is obtained as the electrode voltage. (5) By repeating (3) and (4), gradually the current and electrode voltage calculated in the external circuit will become consistent with those calculated from the semiconductor battery. When this consistency is achieved, it is considered that the calculation has converged, and the current and voltage after Δt from the connection can be obtained.

[0093] As a result of the fourth step, if the current and voltage at the electrode controlled by the external circuit match those inside the semiconductor solid battery, it is determined that consistency with the external circuit has been achieved. After the fourth step, as the fifth step, a determination will be made as to whether to recalculate under different conditions. For example, if a result that satisfies a necessary level such as the relationship E1 > E2 or the relationship E - I > E - II is obtained, it can be determined that the required battery operation has been obtained, so the calculation under different conditions can be omitted. If the necessary level of the relationship has not been obtained, recalculation may be performed to determine the conditions under which the necessary relationship can be obtained. Also, even if the necessary level of the relationship has been obtained, recalculation may be performed for the purpose of further verifying other conditions. If recalculation is to be performed under different conditions, return to the second step. If recalculation is not performed, end the calculation.

[0094] In the fourth step, if the current and voltage do not match, it is determined that the consistency with the external circuit is not achieved, and the process returns to the third step for recalculation. When recalculating in the third step, for each electrode, it is assumed that the calculation is performed under the conditions of the following formulas (11) and (12) using formula (7). Such trials at V A i+1 and V C i+1 are taken as the sixth step.

[0095]

Number

[0096]

Number

[0097] By performing the above steps, it is possible to simulate whether a semiconductor solid-state battery having the desired level can be obtained. By using this method, it is possible to determine whether the level can be controlled before manufacturing the semiconductor solid-state battery, so that efficient manufacturing can be performed.

[0098] x ), silicon oxynitride (SiON) as the insulating layer 3, and titanium oxide (TiO2) as the N-type semiconductor layer 4 are used. Assume that the thickness of each is unified at 300 nm. Also, the parameters related to the physical properties of each layer are shown in Table 1 below.

[0099]

Table 1

[0100] The parameters shown in Table 1 are an example of the parameters used in the simulation. For these parameters, for example, physical property values cited from known literature can be used.

[0101] As a result of performing the aforementioned simulation using the parameters in Table 1, the graph in FIG. 3 was obtained. FIG. 3 is a graph showing the relationship between the upper level of the valence band and the lower level of the conduction band of a conventional semiconductor solid-state battery. In FIG. 3, the relationship is E1 < E2.

[0102] By appropriately changing the values of the parameters shown in Table 1 and performing the simulation, it is possible to determine whether the graph in FIG. 2 can be obtained. By selecting the material of the semiconductor solid-state battery so as to satisfy the physical property values that can obtain the graph in FIG. 2, it is possible to increase the capacity. For example, when the combination shown in Table 1 is changed and a material having a band gap of about 4.5 eV is used instead of silicon oxynitride as the insulating layer 3, the graph in FIG. 2 can be obtained.

[0103] FIG. 8 shows an example of constant-current discharge of a semiconductor solid-state battery having the relationship between the upper level of the valence band and the lower level of the conduction band shown in FIG. 2. Further, FIG. 9 shows an example of constant-current discharge of a semiconductor solid-state battery having the relationship between the upper level of the valence band and the lower level of the conduction band shown in FIG. 3. In both FIGS. 8 and 9, after the target semiconductor solid-state battery is charged at a constant voltage of 2V, 10 μA / cm 2 shows the behavior when constant-current discharge is performed. In generating the graph, the Boltzmann distribution was used for the carrier distribution function. In FIGS. 8 and 9, the horizontal axis is the discharge time (s, ms). Also, the left vertical axis is the voltage (V), and the right vertical axis is the residual charge (cm -2 ). The solid lines 40 and 50 are discharge curves showing the change in voltage. The broken lines 41 and 51 indicate the residual charge. FIG. 8 is a simulation of the constant-current discharge behavior of a semiconductor solid-state battery having the level relationship of FIG. 2. Also, FIG. 9 is a simulation of the constant-current discharge behavior of a semiconductor solid-state battery having the level relationship of FIG. 3.

[0104] In FIG. 8, it takes 160 seconds for the residual charge to reach 0 cm -2 . In contrast, in FIG. 9, the residual charge reaches 0 cm in about 0.004 seconds -2 . From the comparison, it can be seen that the capacity increases by satisfying the relationship E1 > E2.

[0105] As described above, by using simulation, a good semiconductor solid-state battery can be designed. For example, by determining an N-type semiconductor material and performing simulation, parameters of a P-type semiconductor that satisfy the relationship E1 > E2 can be derived. Similarly, by determining a P-type semiconductor material and performing simulation, parameters of an N-type semiconductor that satisfy the relationship E1 > E2 can be derived. Also, by determining an insulating layer, parameters of a semiconductor that satisfy the relationship E1 > E2 can be derived. Similarly, by determining a semiconductor material, parameters of an insulating layer that satisfy the relationship E1 > E2 can be derived. Simulation can also be performed using literature values for the conduction band and valence band of the semiconductor material and the insulating layer. Similar simulations are possible for other energy level relationships described in the first and second embodiments, such as the energy level relationship E-I > E-II. In other words, the energy level determination method according to the embodiment is a simulation technique suitable for the manufacture of semiconductor solid-state batteries.

[0106] The energy level determination method of the semiconductor solid-state battery according to the third embodiment includes calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation, and confirming the consistency with an external circuit. The energy levels can be obtained by the self-consistent collisionless loop. The obtained energy levels include energy level E1 and energy level E2, and / or energy level E-I and energy level E-II. By confirming the consistency with the external circuit, it is determined whether the calculation has converged. For the obtained energy levels, the magnitudes of energy level E1 and energy level E2, and / or the magnitudes of energy level E-I and the said energy level E-II can be confirmed. By the said energy level determination method, in a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, energy levels such as energy level E1 and energy level E2 and / or energy level E-I and energy level E-II at the second interface between the insulating layer and the N-type semiconductor layer can be obtained, and their relationships can be known. The said simulation technique achieves high capacity of the semiconductor solid-state battery.

[0107] According to one or more of the embodiments described above, a semiconductor solid-state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, the energy level E2 of the valence band upper edge of the N-type semiconductor layer is lower than the energy level E1 of the valence band upper edge of the insulating layer at the second interface. In this semiconductor solid-state battery, a high capacitance is exhibited by controlling the energy levels at the interfaces of the three-layer structure of the P-type semiconductor layer, the insulating layer, and the N-type semiconductor layer.

[0108] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are also included in the invention described in the claims and the equivalent scope thereof. The invention described in the original claims of the present application is appended below. [1] A P-type semiconductor layer, an N-type semiconductor layer, an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, a semiconductor solid battery in which the energy level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the energy level E1 of the upper end of the valence band of the insulating layer at the second interface. [2] The semiconductor solid battery according to [1], wherein the energy level E3 of the upper end of the valence band of the P-type semiconductor layer at the first interface and the energy level E4 of the upper end of the valence band of the insulating layer at the first interface satisfy the relationship |E3 - E4| ≤ 2 eV. [3] The semiconductor solid battery according to [1] or [2], wherein the energy level E5 of the lower end of the conduction band of the insulating layer at the second interface and the energy level E6 of the lower end of the conduction band of the N-type semiconductor layer at the second interface satisfy the relationship E5 > E6. [4] The semiconductor solid battery according to any one of [1] to [3], wherein the energy levels E1 and E2 are obtained by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation. [5] A P-type semiconductor layer, an N-type semiconductor layer, an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, a semiconductor solid battery in which the energy level E-II of the lower end of the conduction band of the insulating layer is lower than the energy level E-I of the lower end of the conduction band of the P-type semiconductor layer at the first interface. [6] The semiconductor solid battery according to [5], wherein the energy level E-V of the upper end of the valence band of the insulating layer at the first interface and the energy level E-VI of the upper end of the valence band of the P-type semiconductor layer at the first interface satisfy the relationship [E-VI] - [E-V] ≥ 0.1 eV. [7] The semiconductor solid-state battery according to [5] or [6], wherein the level E-III at the lower end of the conduction band of the N-type semiconductor layer at the second interface and the level E-IV at the lower end of the conduction band of the insulating layer at the second interface satisfy the relationship |[E-III] - [E-IV]| ≤ 2 eV. [8] The semiconductor solid-state battery according to any one of [5] to [7], wherein the levels E-I and E-II are obtained by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation. [9] In a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, when the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, A level determination method for obtaining levels including the level E1 at the upper end of the valence band of the insulating layer and the level E2 at the upper end of the valence band of the N-type semiconductor layer at the second interface, and / or the level E-I at the lower end of the conduction band of the P-type semiconductor layer and the level E-II at the lower end of the conduction band of the insulating layer at the first interface, obtaining the levels including the levels E1 and E2 and / or the levels E-I and E-II by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation; determining the convergence of the calculation of the self-consistent collisionless loop by checking the consistency with an external circuit; checking the relative heights of the levels E1 and E2 and / or the relative heights of the levels E-I and E-II and including the level determination method for the semiconductor solid-state battery.

Explanation of Symbols

[0109] 1…Semiconductor solid battery, 2…P-type semiconductor layer, 3…Insulating layer, 4…N-type semiconductor layer, 5…Front electrode, 6…Back electrode, 7…Substrate, 10…Solid line (upper end of valence band), 11…Upper end of valence band of insulating layer at the second interface, 12…Upper end of valence band of N-type semiconductor layer at the second interface, 13…Upper end of valence band of P-type semiconductor layer at the first interface, 14…Upper end of valence band of insulating layer at the first interface, 15…Upper end of valence band of insulating layer at the first interface, 16…Upper end of valence band of P-type semiconductor layer at the first interface, 20…Solid line (lower end of conduction band), 21…Lower end of conduction band of P-type semiconductor layer at the first interface, 22…Lower end of conduction band of insulating layer at the first interface, 23…Lower end of conduction band of N-type semiconductor layer at the second interface, 24…Lower end of conduction band of insulating layer at the second interface, 25…Lower end of conduction band of insulating layer at the second interface, Lower end of conduction band of N-type semiconductor layer at the second interface, 30…Dashed line (Fermi level), 40…Solid line (discharge curve), 41…Dashed line (residual charge), 50…Solid line (discharge curve), 51…Dashed line (residual charge).

Claims

1. A P-type semiconductor layer made of nickel oxide, an N-type semiconductor layer made of titanium oxide, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, the insulating layer being made of one or two or more materials selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins and having a band gap of 4.5 eV, When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, in a thermally equilibrium state or a state before charging, the level E2 at the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 at the upper end of the valence band of the insulating layer at the second interface, A semiconductor solid battery, wherein the thickness of the insulating layer is 30 μm or less.

2. In a thermally equilibrium state or a state before charging, the level E3 at the upper end of the valence band of the P-type semiconductor layer at the first interface and the level E4 at the upper end of the valence band of the insulating layer at the first interface satisfy the relationship |E3 - E4| ≤ 2 eV. The semiconductor solid battery according to Claim 1.

3. In a thermally equilibrium state or a state before charging, the level E5 at the lower end of the conduction band of the insulating layer at the second interface and the level E6 at the lower end of the conduction band of the N-type semiconductor layer at the second interface satisfy the relationship E5 > E6. The semiconductor solid battery according to Claim 1 or 2.

4. The levels E1 and E2 are obtained by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation. The semiconductor solid battery according to any one of Claims 1 to 3.

5. A P-type semiconductor layer made of nickel oxide, an N-type semiconductor layer made of titanium oxide, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, the insulating layer being made of one or two or more materials selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins and having a band gap of 4.5 eV, When the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, in a thermally equilibrium state or a state before charging, the level E-II at the lower end of the conduction band of the insulating layer is lower than the level E-I at the lower end of the conduction band of the P-type semiconductor layer at the first interface, A semiconductor solid battery, wherein the thickness of the insulating layer is 30 μm or less.

6. In a state of thermal equilibrium or a state before charging, the level E-V at the upper end of the valence band of the insulating layer at the first interface and the level E-VI at the upper end of the valence band of the P-type semiconductor layer at the first interface satisfy the relationship [E-VI] - [E-V] ≥ 0.1 eV. The semiconductor solid-state battery according to claim 5.

7. In a state of thermal equilibrium or a state before charging, the level E-III at the lower end of the conduction band of the N-type semiconductor layer at the second interface and the level E-IV at the lower end of the conduction band of the insulating layer at the second interface satisfy the relationship |[E-III] - [E-IV]| ≤ 2 eV. The semiconductor solid-state battery according to claim 5 or 6.

8. The levels E-I and E-II are obtained by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation. The semiconductor solid-state battery according to any one of claims 5 to 7.

9. In a semiconductor solid-state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, when the interface between the P-type semiconductor layer and the insulating layer is defined as the first interface and the interface between the insulating layer and the N-type semiconductor layer is defined as the second interface, A level determination method for obtaining levels including the level E1 at the upper end of the valence band of the insulating layer at the second interface and the level E2 at the upper end of the valence band of the N-type semiconductor layer at the second interface, and / or the level E-I at the lower end of the conduction band of the P-type semiconductor layer and the level E-II at the lower end of the conduction band of the insulating layer at the first interface in a state of thermal equilibrium or a state before charging, Obtaining the levels including the levels E1 and E2 and / or the levels E-I and E-II by calculating a self-consistent collisionless loop using the Poisson equation and the carrier continuity equation, Determining the convergence of the calculation of the self-consistent collisionless loop by checking the consistency with an external circuit, Checking the levels of the level E1 and the level E2 and / or the levels of the level E-I and the level E-II Including the level determination method for the semiconductor solid-state battery.

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