Self-Aligned Edge Passivation for Robust Resistive Random-Access Memory Connections

Abstract

Provides self-aligned edge passivation for robust resistive random access memory connections. A resistive random access memory (RRAM) structure has top and bottom electrodes electrically coupled by first and second metal interconnect lines, respectively, which provide electrical connections to the RRAM structure, and a layer of resistive switching material disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under the influence of at least an electric field and heat. A dielectric spacer is formed on a sidewall of the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacer and covering at least a portion of the sidewall of the top electrode. The passivation layer is self-aligned to the first metal interconnect line.

Description

Technical Field

[0001] The present invention generally relates to electrical, electronic, and computer technologies, and more specifically, to resistive random access memory.

Background Art

[0002] Resistive random access memory (RRAM, or ReRAM) is considered a promising technology for more scalable, high-density, and high-performance non-volatile storage solutions. RRAM is particularly preferred for use as an electrical synaptic device or memristor for neuromorphic computing. Neuromorphic engineering incorporates ideas from a number of technical fields, including, for example, biology, physics, mathematics, computer science, and electrical engineering, to build artificial intelligence systems with physical architectures and design principles based on biological neural systems. In neuromorphic computing applications, resistive memory devices can be used as connections (i.e., synapses) between pre-neurons and post-neurons that represent connection weights in the form of device resistance.

[0003] In artificial neural system applications, a large number of pre-neurons and post-neurons can be connected through a crossbar array of RRAMs, which naturally represents a fully connected neural network. To create a large-scale crossbar array, it is preferable to minimize the voltage drop across the lines, and thus it is preferable to reduce the line resistance as much as possible. For this reason, copper lines are preferred. However, the integration of copper lines within RRAM pillars presents significant design and reliability challenges.

[0004] RRAM pillars / stacks typically include titanium nitride (TiN) electrodes for compatibility with complementary metal-oxide-semiconductor (CMOS) process flows. Integrating RRAM devices into a copper damascene process requires an additional metal mask layer (e.g., tantalum nitride (TaN)) on top of the RRAM stack to protect the stack during removal of the TiN hard mask. Additionally, since the dimensions of copper vias in a crossbar array are typically larger than those of the RRAM pillars, sidewall protection is generally required. Conventional spacers are often damaged during the formation of via openings, thereby creating undesirable weak spots for subsequent wet etching of TiN. Accordingly, techniques are needed to address the issues described above. Summary of the Invention

[0005] Viewed from a first aspect, the present invention provides a resistive random access memory (RRAM) comprising: a top electrode and a bottom electrode electrically coupled by first and second metal connection lines respectively, the first and second metal connection lines providing electrical connection to the RRAM structure; a layer of resistive switching material disposed between the top and bottom electrodes, the resistive switching material exhibiting a measurable change in resistance under the influence of at least one of an electric field and heat; a dielectric spacer formed on a sidewall of the bottom electrode; and a passivation layer formed on an upper surface of the dielectric spacer and covering at least a portion of a sidewall of the top electrode, the passivation layer being self-aligned to the first metal connection line.

[0006] Viewed from a first side, the present invention provides a method of forming a resistive random access memory (RRAM), the method comprising: forming a bottom electrode on an upper surface of a first metal connection line; forming a layer of a resistive switching material on at least a portion of the upper surface of the bottom electrode, the resistive switching material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; forming a top electrode on the upper surface of the layer of the resistive switching material; forming a dielectric spacer formed on at least a sidewall of the bottom electrode; and forming a passivation layer covering at least a portion of the sidewall of the electrode, the passivation layer self-aligning to a second metal connection line that is electrically connected to the top electrode.

[0007] As shown in one or more embodiments, the present invention advantageously provides a resistive random access memory (RRAM) structure and a method for manufacturing the RRAM structure, the method providing a reduced connection resistance and being particularly effective for use in a crossbar array. In one or more embodiments, the RRAM structure includes a feature of self-aligned passivation surrounding at least the bottom electrode of the RRAM structure. The passivation feature advantageously prevents the upper metal line from shorting to the bottom electrode, despite the erosion of the RRAM sidewall spacer that may occur during deep etching used to form vias for connecting the upper electrode and the lower electrode in the crossbar array.

[0008] According to an embodiment of the present invention, an RRAM structure includes a top and a bottom electrode electrically coupled to first and second metal connection lines, respectively, the first and the second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable resistance change under the influence of at least an electric field, or heat, or both. A dielectric spacer is formed on a sidewall of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacer and covering at least a portion of a sidewall of the top electrode. The passivation layer is self-aligned with the first metal connection line.

[0009] According to an embodiment of the present invention, a method of forming an RRAM structure includes: forming a bottom electrode on an upper surface of a first metal connection line; forming a layer of resistive switching material on at least a portion of the upper surface of the bottom electrode, the resistive switching material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat; forming a top electrode on the upper surface of the layer of resistive switching material; forming a dielectric spacer on at least a sidewall of the bottom electrode; and forming a passivation layer formed on the upper surface of the dielectric spacer and covering at least a portion of a sidewall of the top electrode, the passivation layer being self-aligned with a second metal connection line that is electrically connected to the top electrode.

[0010] As used herein, "facilitate" includes performing an operation, making an operation easier to perform, assisting in the accomplishment of an action, or directing an operation to be accomplished. Thus, for purposes of example only and without limitation, in the context of a semiconductor manufacturing method, a step performed by one entity facilitates an operation performed by another entity to direct or assist in a desired operation. To avoid doubt, where an actor facilitates an operation without performing the operation, the operation is nevertheless performed by some entity or combination of entities.

[0011] The technology of the present invention can provide substantially beneficial technical effects. For purposes of example only and not by way of limitation, the RRAM structure according to embodiments of the present invention, or the manufacture of the RRAM structure, or both, can provide one or more of the following advantages. · Reduced connection resistance between the RRAM structure and the corresponding metal connection line · Reduced likelihood of electrical shorts between the electrodes of the RRAM structure and the corresponding metal connection lines · Facilitating the integration of the RRAM structure using CMOS processing having copper damascene processing for metal connection lines formed within a crossbar array · Enabling the scaling of the size of the RRAM pillar to be less than or equal to the size of the corresponding contact

[0012] These and other features of the present invention will become apparent from the detailed description of its exemplary embodiments, which should be read in conjunction with the accompanying drawings.

[0013] The following drawings are provided for purposes of example only and not by way of limitation, and like reference numerals (if used) indicate corresponding elements throughout several drawings.

Brief Description of the Drawings

[0014]

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DETAILED DESCRIPTION OF THE INVENTION

[0015] The elements in the figures are to be understood as being shown for simplicity and clarity only. Ordinary, well-understood elements that may be useful or necessary in commercially available preferred embodiments may not be shown so as not to obscure the drawings of the illustrated embodiments.

[0016] The principles of the present invention, as shown in one or more of its embodiments, will be described herein with respect to exemplary resistive random access memory (RRAM, or ReRAM) structures, and specifically methods for fabricating such structures having self-aligned edge passivation to reduce contact resistance when, for example, the RRAM structure is used in a crossbar array. However, it should be recognized that the present invention is not limited to the specific structures, or methods, or both shown and described herein in the drawings. Rather, those skilled in the art having the teachings of this specification will recognize that various modifications can be made to the illustrated embodiments within the scope of the claimed invention. That is, no intent to limit, or be construed to limit, is intended or should be inferred with respect to the embodiments shown and described.

[0017] FIG. 1 is a perspective view showing at least a portion of a basic RRAM cell 100. The RRAM cell 100 is disposed between a bottom conductor 102 that can serve as a word line and a top conductor 104 that can serve as a bit line. The RRAM cell 100 includes a junction of a thin resistive switching material 106 sandwiched between a bottom electrode 108 and a top electrode 110 of the RRAM cell. Titanium nitride (TiN) is often used for the bottom and top electrodes 108, 110, and metal oxides (e.g., hafnium oxide (HfO)) are often used as the resistive sandwich material 106. The switching effect of the RRAM involves the generation of defects within the switching material 106, which can be referred to as oxygen vacancies (i.e., positions of oxide bonds from which oxygen has been removed), which can be charged and drift under the influence of an electric field, which can be generated by an applied bias potential 112 or heat. This applied electric field or heat causes the movement and vacancies of oxygen ions within the switching material 106 in a manner coordinated with the movement of electrons and holes in the semiconductor, which in turn causes a measurable change in the resistance of the device.

[0018] FIG. 2 is a perspective view showing at least a portion of a crossbar array 200 that can be used in the aspect of the present invention. The crossbar array 200 includes a plurality of RRAM cells 202, each RRAM cell being disposed between a unique intersection of a bottom conductor 204 that can serve as a corresponding word line and a top conductor 206 that can serve as a bit line. Although not explicitly shown (but implicitly), cell selection devices (e.g., transistors or diodes) are generally connected in series between each RRAM cell 202 and the corresponding top or bottom conductor 206, 204 and function for selective access to individual cells. The bottom conductor 204 is preferably disposed on a substrate 208 such as, for example, an interlayer dielectric layer (ILD).

[0019] As previously described, in order to fabricate a large-scale crossbar array, it is desirable to reduce the line resistance within the array and minimize the voltage drop across the lines. To achieve this goal, copper is preferably used to form the bottom and top conductors within the crossbar array, for example, by using a copper damascene process. However, integrating RRAM into a copper damascene process presents several challenges that have a significant impact on the reliability and cost of RRAM devices.

[0020] As previously described, RRAM pillars typically include TiN electrodes for compatibility with a CMOS process flow. Since copper damascene processing uses TiN as a mask, if the TiN mask is selectively removed during the copper damascene process, the TiN electrodes of the RRAN pillars will also be etched. Therefore, integrating RRAM into a copper damascene process generally requires an additional barrier layer formed on top of the RRAM pillar to protect the top electrode of the RRAM pillar from being etched during the removal of the TiN hard mask of the copper damascene.

[0021] Another challenge in integrating RRAM into a copper damascene process is that the dimensions of the upper copper lines are typically much larger than those of the RRAM pillars, and the upper copper lines tend to extend beyond and cover the sides of the RRAM pillars, thereby increasing the possibility of an electrical short between the upper copper line of the RRAM pillar and the bottom electrode. Dielectric spacers are therefore often formed on the sidewalls of the RRAM pillars to prevent the upper copper lines of the RRAM pillars from making electrical contact with the bottom electrodes. However, conventional sidewall spacers are often damaged during the etching used to form via openings, thereby creating unwanted weak spots for TiN wet etching. This results in a reduced yield of the RRAM crossbar array.

[0022] Embodiments of the present invention provide a novel RRAM pillar structure that advantageously addresses at least the above-described problems with integrating RRAM into copper damascene processing. Referring now to FIG. 3, a cross-sectional view shows at least a portion of an exemplary RRAM pillar structure 300 integrated into a corresponding copper line according to an embodiment of the present invention. The RRAM pillar structure 300 can be disposed, for example, in an RRAM region of a crossbar array. The RRAM pillar structure 300 includes a lower metal line (F2) 302 that includes copper in one or more embodiments, an upper metal line (F3) 304 that also includes copper in one or more embodiments, and an RRAM pillar (i.e., stack) disposed between the lower and upper metal lines as shown. The lower metal line 302 and the upper metal line 304 can be formed using copper damascene processing and are surrounded in one or more embodiments by a dielectric layer 306 that is an interlayer dielectric layer (ILD). The dielectric layer 306 can include, for example, silicon dioxide or an alternative low-k material.

[0023] In the context of copper damascene processing, each of the lower metal line 302 and the upper metal line 304 is preferably surrounded by a barrier layer 308 and 310, respectively, to prevent copper from diffusing into the surrounding dielectric layer 306. The barrier layers 308, 310 preferably include, for example, tantalum (Ta), tantalum nitride (TaN), TiN, etc., but embodiments of the present invention are not limited to any particular barrier material.

[0024] A capping layer 312 (e.g., silicon nitride (SiN)) is deposited over the lower metal line 302 and preferably extends across the structure, although not explicitly shown in FIG. 3. An opening is then etched through a pre-defined region of the capping layer 312 to expose the underlying lower metal line 302. The RRAM pillar is formed on top of the top corresponding to the opening in the capping layer 312 over at least a portion of the upper surface of the lower metal line 302.

[0025] In one or more embodiments, the RRAM pillar includes a multi-layer bottom electrode and a multi-layer top electrode. In some preferred embodiments, the top and bottom electrodes of the RRAM pillar are two-layer electrodes, but the embodiments of the present invention are not limited to electrodes having two layers. In particular, the bottom electrode of the RRAM pillar can be a first metal, which in this example is TaN, directly formed on the upper surface of the lower metal line 302, or a second metal / metal nitride layer 316, which in this example is TiN, formed on the upper surface of the first metal nitride layer. Similarly, the top electrode of the RRAM pillar in this exemplary embodiment includes a first metal, which in this example is TiN, or a metal nitride layer 318 and a second metal / metal oxide layer 320, which in this example is TaN. The second metal / metal oxide (TaN) layer 320 is electrically directly connected to the upper metal line 304. It should be recognized that not all material layers forming the top and bottom electrodes of the RRAM pillar need to include metal nitrides. For example, in one or more embodiments, at least one layer forming the top electrode includes TiN, and the other layers of the top electrode include metals such as tungsten (W) and iridium (Ir).

[0026] The RRAM pillar further includes a metal oxide layer 322 disposed between the bottom and top electrodes. More specifically, the metal oxide layer 322 is formed on at least a portion of the upper surface of the second metal nitride layer 316 of the bottom electrode, and the first metal nitride layer 318 of the top electrode is formed on at least a portion of the upper surface of the metal oxide layer 322. The metal oxide layer 322 used as the resistive switching material includes hafnium oxide (HfO) in one or more embodiments, but the embodiments of the present invention are not limited to a specific switching material.

[0027] The dielectric spacer 324 is preferably formed on the sidewall of the RRAM pillar and covers the TiN layer 316 of the bottom electrode of the RRAM pillar. The sidewall spacer 324, in one or more embodiments, comprises silicon nitride (SiN) and does not adequately protect the RRAM pillar during the formation of the upper metal line 304. As a result, a passivation layer 326 is formed on the sidewall spacer 324 that covers at least a portion of the multilayer top electrodes 318, 320. The sidewall spacer 324 is configured such that the passivation layer 326 does not connect to (i.e., is electrically isolated from) the metal oxide layer 322 of the RRAM pillar or the multilayer bottom electrodes 314, 316.

[0028] As shown in the region of interest 328 shown, the passivation layer 326 is self-aligned to the upper metal line 304, so that the edge of the upper metal line does not extend beyond the passivation layer and thereby does not cover around the RRAM pillar so as to create an electrical short of the RRAM pillar. The self-aligned passivation layer 326 comprises a dielectric material in one or more embodiments. In an alternative embodiment, the passivation layer 326 does not come into contact with the metal oxide layer 322 of the RRAM pillar or the multilayer bottom electrodes 314, 316, and the passivation layer can comprise a metal or another conductive material. The upper metal line 304 is formed self-alignedly on the passivation layer 326 of the RRAM pillar and on the upper surface of the second metal nitride layer 320 of the multilayer top electrode.

[0029] Thus, in contrast to conventional RRAM device manufacturing approaches, the RRAM pillar structure 300 according to one or more embodiments of the present invention advantageously provides a self-aligned passivation layer that is formed after via lithography and etching (for connecting the lower and upper metal lines within the peripheral region of the wafer on which the RRAM structure is formed), which prevents the bottom electrodes 314, 316 of the RRAM pillar from being electrically connected to the upper metal line 304. This unique arrangement enables the size of the RRAM pillar to be scaled down to be smaller than the size of the upper metal contact without the risk of electrical shorting occurring.

[0030] For illustrative purposes only and without limitation, FIGS. 4 - 26 are cross - sectional views showing exemplary processing steps / stages in the manufacture of an exemplary RRAM structure that provides a reduction in contact resistance, according to embodiments of the present invention. The overall manufacturing method and the structures formed thereby are completely novel, but the individual processing steps required to implement the method may include conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. These techniques and tools will already be well - known to those skilled in the relevant art who have received the teachings of this specification. Further, many of the processing steps and tools used to manufacture semiconductor devices are also described in many already - available publications, including, for example, P. Holloway et al., Compound Semiconductor Handbook: Growth, Processing, Characterization, and Devices, Cambridge University Press 2008, and R. K. Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001. Although some individual processing steps are described herein, these steps are merely illustrative, and it is emphasized that those skilled in the art may be familiar with several equivalently suitable alternatives that would fall within the scope of the present invention.

[0031] It should be recognized that the various layers, or regions, or both shown in the accompanying drawings may not be shown to scale. Further, one or more semiconductor layers of the type commonly used in such integrated circuit devices may not be explicitly shown in a given drawing for the sake of clarity of explanation. This does not mean that semiconductor layer(s) not explicitly shown are omitted in an actual integrated circuit device.

[0032] FIG. 4 is a cross-sectional view showing at least a portion of an exemplary semiconductor structure 400, where lower metal lines are formed. In particular, structure 400 includes a dielectric layer 402, which is preferably a low-k ILD layer. Lower metal lines 404 and 406 are formed within the ILD layer 402, such as by using standard photolithographic patterning and etching processes. In this example, structure 400 is divided into various regions, including a first (e.g., KW) alignment mark region, a D2 alignment mark region, a base technology region (where peripheral circuits are mainly formed), and a memory region (where RRAM cell(s) may be formed). In one or more embodiments of the present invention, lower metal lines 404, 406 include copper such that they can be formed by copper damascene processing. In the context of copper damascene processing, a barrier layer is generally formed surrounding the copper lines 404, 406 to prevent the diffusion of copper into the surrounding ILD layer 402.

[0033] FIG. 5 shows, in one or more embodiments, the formation of a capping (i.e., encapsulation) layer 502 containing SiN on at least a portion of the upper surface of structure 400. In particular, capping layer 502 is preferably formed using a deposition process (e.g., chemical vapor deposition (CVD)) on the upper surfaces of lower copper lines 404, 406 and on at least a portion of the upper surface of ILD layer 402, although embodiments of the present invention are not limited to any particular process for forming the capping layer.

[0034] In FIG. 6, an organic dielectric layer (ODL) 602 is formed on at least a portion of the upper surface of the capping layer 502. In one or more embodiments, an organic dielectric layer 602 having a thickness of about 135 nanometers (nm) is formed using a standard deposition process such as, for example, chemical vapor deposition (CVD). However, embodiments of the present invention are not limited to any particular thickness or deposition process for forming the organic dielectric layer 602. An anti-reflective coating (ARC) layer 604 is formed on at least a portion of the upper surface of the organic dielectric layer 602. A photoresist mask 606 is formed on at least a portion of the upper surface of the ARC layer 604. Structure 400 is then subjected to an optical lithography process where a pre-defined pattern is transferred to the photoresist mask 606 through exposure to light or another optical source. One or more openings 608 and 610 are then formed (e.g., by etching) in the photoresist mask 606 and subsequently define regions of structure 400 that are to be removed. One of the openings 608 is formed over the D2 alignment mark region and another opening 610 is formed over the memory region and aligned with the underlying copper line 406. Selective etching is then applied to remove the portion of the capping layer 502 directly below the openings 609, 610.

[0035] Referring to FIG. 7, openings 702 and 704 are etched through the SiN capping layer 502. The first of the openings 702 is etched in the D2 alignment mark region through the ARC layer 604, the organic dielectric layer 602, and at least partially through the ILD layer 402 to expose the underlying ILD layer 402. Similarly, the second of the openings 704 is etched in the memory region through the ARC layer 604, the organic dielectric layer 602, and at least partially through the underlying copper line 406, thereby exposing the underlying copper line; in this example, the underlying copper line 406 is useful as a landing pad for the RRAM pillars subsequently formed thereon. In one or more embodiments, reactive ion etching (RIE) is used to etch the openings 702, 704, but the present invention is not limited to RIE. After the formation of the openings 702, 704, the photoresist mask 606, the ARC layer 604, and the organic dielectric layer 602 are removed by wet etching, such as.

[0036] A metal nitride liner 802 is formed over the upper surface of the structure 400, including the openings 702, 704 as shown in FIG. 8. In one or more embodiments, the metal nitride liner 802 includes TaN, but embodiments of the present invention are not limited to TaN. The metal nitride liner 802 is preferably formed using a deposition process such as plasma vapor deposition (PVD), but is not limited thereto. In FIG. 9, the upper surface of the structure 400 is planarized, for example, using chemical mechanical planarization (CMP), and the portion of the metal nitride liner 802 on the upper surface of the capping layer 502 outside the openings 702, 704 is removed to form metal nitride plugs 902 and 904. The metal nitride plug 904 is electrically directly connected to the underlying copper line 406 and becomes one of the layers in the multi-layer bottom electrode of the RRAM pillar subsequently formed on top of the top of the underlying copper line 406, which will be described in detail hereinafter in this specification.

[0037] FIG. 10 shows the step of forming a second metal nitride layer 1002 on at least a portion of the upper surface of a structure 400 including the upper sides of the capping layer 502 and the metal nitride plugs 902 and 904. In one or more embodiments, the second metal nitride layer 1002 includes TiN, but embodiments of the present invention are not limited to TiN. The second metal nitride layer 1002 will form the bottom electrode of a subsequently formed RRAM pillar structure in combination with the metal nitride plug 904.

[0038] Figures 11 to 13 show exemplary semiconductor manufacturing steps for arbitrarily forming a kerf alignment structure. Referring to Figure 11, the hard mask layer 1102 is preferably deposited on at least a portion of the upper surface of the second metal nitride layer 1002, for example, using a CVD process. In Figure 12, the organic dielectric layer (ODL) 1202 is formed on at least a portion of the upper surface of the hard mask layer 1102. In one or more embodiments, the organic dielectric layer 1202 is formed to have a thickness of about 100 nm using a standard deposition process such as CVD. However, embodiments of the present invention are not limited to any specific thickness or deposition process for forming the organic dielectric layer 1202. Then, an ARC layer 1204 corresponding to the alignment marks at another level is formed on at least a portion of the upper surface of the organic dielectric layer 1202 using a standard CVD or similar process. A photoresist layer 1206 is formed on at least a portion of the upper surface of the ARC layer 1204. The photoresist layer 1206 is patterned and etched (e.g., RIE) using, for example, standard photolithographic processing, so that only the photoresist portion remains within the KW alignment mark region of the structure 400. After selective etching down to the second metal nitride layer 1002 and etching the photoresist layer 1206, the ARC layer 1204, and the organic dielectric layer 1202 (e.g., using plasma or wet etching), the hard mask structure 1302 (which is a portion of the hard mask layer 1102 shown in Figure 12) below the photoresist layer (1206 in Figure 12) remains within the KW alignment mark of the structure 400 as shown in Figure 13.

[0039] FIG. 14 shows a process for forming the remaining layers of the RRAM pillar. More specifically, the metal oxide layer 1402 is formed on at least a portion of the structure 400 including the upper surface and the surrounding hard mask structure 1302 of the second metal nitride layer 1002 that forms the bottom electrode of the RRAM pillar. The metal oxide layer 1402 is used as the resistive switching material of the RRAM pillar and includes HfO in one or more embodiments, but embodiments of the present invention are not limited to this particular resistive switching material. The third metal nitride layer 1404 is formed on at least a portion of the upper surface of the metal oxide layer 1402, and the fourth metal nitride layer 1406 is formed on at least a portion of the upper surface of the third metal nitride layer 1404. The third and fourth metal nitride layers 1404 and 1406 each include TiN and TaN in one or more embodiments and will form the multi-layer top electrode of the RRAM pillar. The metal oxide layer 1402, and the third and fourth metal nitride layers can be formed using standard deposition processes such as CVD, for example.

[0040] Continuing with reference to FIG. 14, a second hard mask layer 1408 is formed on the upper surface of the structure 400. Similar to the first hard mask layer 502 / 1302, the second hard mask layer 1408 includes SiN in one or more embodiments, but embodiments of the present invention are not limited to this particular material. As is apparent from FIG. 14, the presence of the first hard mask structure 1302 generates a stepped cross-sectional shape within the KW alignment mask region of the structure 400; this is used for alignment in one or more embodiments.

[0041] Figures 15 and 16 show exemplary steps in the formation of an RRAM pillar according to an embodiment of the present invention. As shown in FIG. 15, a third organic dielectric layer 1502 is formed on at least a portion of the upper surface of the second hard mask layer 1408 using a standard deposition process (such as CVD, PVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.). In one or more embodiments, the third organic dielectric layer 1502 is formed with a cross-sectional thickness of about 200 nm, but the present invention is not limited to any particular thickness. CMP or the like is preferably performed on the third organic dielectric layer 1502 to planarize the upper surface of the structure 400. Thereafter, a third ARC layer 1504 is formed on at least a portion of the upper surface of the third organic dielectric layer 1502, for example, using a standard deposition process.

[0042] A photoresist layer is deposited on the upper surface of the third ARC layer 1504. This photoresist layer is then tapered and etched using photolithography processing to form photoresist structures 1506 and 1508. The photoresist structures 1506 and 1508 are aligned with the underlying metal nitride plugs 902 and 904, respectively.

[0043] In FIG. 16, selective etching such as RIE is performed to form an RRAM pillar 1602 in the memory region and alignment structures 1604 and 1606 in the D2 alignment mark and KW alignment mark regions, respectively. In particular, in one or more embodiments, RIE is performed to etch through the third ARC layer 1504, the third organic dielectric layer 1502, the second hard mask layer 1408, the fourth metal nitride layer 1406, the third metal nitride layer 1404, the metal oxide layer 1402, and the second metal nitride layer 1002. The resulting RRAM pillar 1602 and alignment structures 1604, 1606 after removing the remaining photoresist structures 1506 and 1508, the third ARC layer 1504, and the third organic dielectric layer 1502 (see FIG. 15) are shown in FIG. 16.

[0044] As shown in FIG. 17, the encapsulation layer 1702 is formed over a structure 400 that includes the top and side walls of the RRAM pillar 1602, and the top and side walls of the alignment structures 1604 and 1606. In one or more embodiments, the encapsulation layer 1702 includes SiN, although other insulating (i.e., dielectric) materials for forming the encapsulation layer are equally contemplated by embodiments of the present invention. Selective etching, such as RIE, is then performed to deposit over the top surface of the RRAM pillar 1602, the alignment structures 1604, 1606, and the upper surface of the capping layer 502 between adjacent structures, as shown in FIG. 18, over the horizontal surfaces of the structure 400. Thus, the encapsulation layer 1702 is left only on the vertical side walls of the RRAM pillar 1602 and the alignment structures 1604, 1606 to form sidewall spacers.

[0045] In FIG. 19, the dielectric layer 1902 is deposited over at least a portion of the upper surface of a structure 400 that includes the upper surface of the capping layer 502 and the RRAM pillar 1602 and the alignment structures 1604, 1606 therearound. In one or more embodiments, the dielectric layer 1902 is a low-k ILD layer. CMP or an alternative planarization process is then performed to planarize the upper surface of the dielectric layer 1902. The upper metal wiring (F3) is then formed within this dielectric layer 1902, which will be described in more detail hereinbelow.

[0046] As shown in FIG. 20, in the formation of the upper metal wiring layer (F3), the sacrificial SiN layer 2002 is deposited on the upper surface of the dielectric layer 1902. A metal nitride (e.g., TiN) hard mask layer 2004 is then deposited on the upper surface of the sacrificial SiN layer 2002, and a tetraethyl orthosilicate (TEOS) layer 2006 is deposited on the upper surface of the TiN hard mask layer. One or more of the SiN layer 2002, the TiN hard mask layer 2004, and the TEOS layer 2006 can be deposited using, for example, a CVD or PECVD process. In FIG. 21, the TEOS layer 2006 is patterned and etched using standard photolithography and etching, and openings 2102 and 2104 are formed in the TiN hard mask layer 2004 to expose portions of the SiN layer 2002. The first of the openings 2102 is aligned perpendicular to the underlying lower metal line 404, and the second of the openings 2104 is aligned perpendicular to the underlying RRAM pillar 1602.

[0047] Here, referring to FIG. 22, deep RIE or a similar selective etching is performed to form trenches 2202 and 2204. The trench 2202 is etched through the sacrificial SiN layer 2002, the low-k dielectric layer 1902, and the capping layer 502 to expose at least a portion of the underlying copper line 404. This trench 2202 will form a via that electrically connects the underlying copper line 404 to a corresponding upper copper line that would be formed within the base technology region of the structure 400. Similarly, the trench 2204 is etched through the sacrificial SiN layer 2002 and through a portion of the low-k dielectric layer 1902 to expose the top electrode including the third and fourth metal nitride layers 1404 and 1406 of the RRAM pillar within the memory region of the structure 400.

[0048] To form the trench 2202, by using deep RIE, there will be a large over-etch amount that significantly etches the encapsulation layer 1702 to form sidewall spacers for protecting the RRAM pillars within the trench 2204. The erosion of the encapsulation layer 1702 that protects the RRAM pillars is shown in region 2206. This erosion generates a high risk of electrical short between the corresponding upper copper line where the RRAM pillar is to be formed, the metal oxide switching layer 1402, and the bottom electrode including the second metal nitride layer 1002.

[0049] To eliminate or at least substantially reduce the risk of short between the upper copper line of the RRAM pillar and the lower electrode, as shown in FIG. 23, a conformal dielectric liner (i.e., a passivation layer) 2302 is deposited on the upper surface of a structure 400 that includes at least the TiN hard mask layer 2004, the sidewalls of the trenches 2202 and 2204, and above at least a portion of the RRAM pillar. It should be recognized that a small space for forming the sidewall spacers of the RRAM pillar adjacent to the encapsulation layer 1702 will also be completely filled with the dielectric liner 2302. The dielectric liner 2302 can include, for example, silicon carbide (SiC), silicon carbonate (SiCO), SiO2, etc., but embodiments of the present invention are not limited to any specific dielectric liner material.

[0050] FIG. 24 shows an exemplary structure 400 after isotropic etch-back of conformal dielectric liner 2302 according to one or more embodiments of the present invention. As is apparent from FIG. 24, the isotropic etch-back process will remove conformal dielectric liner 2302 in the open regions on the upper surface of hard mask layer 2004, on the sidewalls and bottom of trench 2202, and on at least a portion of the sidewalls of trench 2204. The conformal dielectric liner 2302 is left in the pinch-off region between the RRAM pillar and trench 2204, except for the portion of the fourth metal nitride layer 1406 that forms the upper surface of the top electrode of the RRAM pillar exposed in the trench. This conformal dielectric liner 2302 prevents the switching material and bottom material of the RRAM pillar from shorting to the upper copper line to be formed in trench 2204. Subsequent to the isotropic etch-back process, at least a portion of the upper surface of top electrode 1406 of the RRAM pillar is exposed in the trench through the grooved conformal dielectric liner 2302. In one or more embodiments, the isotropic etch-back is performed by atomic layer etching (ALE) to achieve precise etch control, although embodiments of the present invention contemplate essentially any isotropic dry or wet etching process.

[0051] In FIG. 25, the sacrificial TiN hard mask layer (2004 in FIG. 24) is removed. In one or more embodiments, the removal of the sacrificial TiN hard mask layer is achieved using selective etching such as, for example, diluted hydrogen peroxide or SC1 chemistry. The TiN used to form the top and bottom electrodes of the RRAM pillar is advantageously protected from damage during TiN hard mask removal by a self-aligned conformal dielectric liner 2302; this dielectric liner material pinches off the lower edge of the RRAM pillar and shields any exposed TiN. FIG. 26 shows, in one or more embodiments, the metallization process for the upper level (F3) when copper fills trenches 2202 and 2204 to form upper copper lines 2602 and 2604, respectively. A planarization process (e.g., CMP) is then performed to planarize the upper copper lines 2602 and 2604 and to remove the sacrificial SiN layer (2002 in FIG. 25) down to the low-k dielectric layer 1902. As described above, the addition of the self-aligned conformal dielectric liner 2302 at the bottom of the upper copper line 2604 effectively prevents damage to the TiN electrodes to the RRAM pillar, as highlighted in region 2606, and prevents an electrical short between the upper copper line 2604 of the RRAM pillar and the bottom electrode, as highlighted in region 2608.

[0052] In an alternative embodiment of the present invention, referring to FIG. 27, if the metal over-etch used to form trenches 2202 and 2204 is not too deep, the bottom of trench 2204 does not extend below the top electrode of the RRAM pillar, and thus, the self-aligned conformal liner 2302 can include a metal or a similar electrically conductive material. As is apparent from FIG. 27, the conformal liner 2302 is configured on the upper surface of the encapsulation layer 1702 that forms a sidewall spacer for protecting the RRAM pillar as shown in FIG. 2702. In this embodiment, the conformal liner 2302 preferably includes, for example, TaN, rhenium, etc. In this way, the metal liner 2302 is again self-aligned with the bottom of the upper copper line 2604, not only preventing damage to the TiN electrode under the RRAM pillar, but also providing a connection with a lower resistance between the top electrode of the RRAM pillar and the upper copper line 2604 because the connection joint will have a larger surface area.

[0053] At least a portion of the technology of the present invention can be implemented in an integrated circuit. In the formation of an integrated circuit, identical dies are typically manufactured in an apparent repeating pattern on a semiconductor wafer. Each die can include the devices described herein and can also include other structures, or circuits, or both. Individual dies are cut or diced from the wafer and then packaged as an integrated circuit. Those skilled in the art will know how to dice and package the wafer to manufacture an integrated circuit. Any of the exemplary structures described in the accompanying drawings or portions thereof can be part of the integrated circuit. The integrated circuit manufactured in this way is contemplated as part of the present invention.

[0054] Those skilled in the art will recognize that the exemplary structures described above can be distributed as bare dies, in packaged form, or as added components of intermediate products, or as end products having RRAM devices formed by one or more embodiments of the present invention, in a rough form (i.e., a single wafer having a number of unpackaged chips).

[0055] Integrated circuits according to aspects of the present disclosure can be used in any application that includes RRAM, such as, but not limited to, essentially crossbar arrays, or in electrical systems, or both. Suitable systems for implementing embodiments of the present invention include, but are not limited to, neuro-morphic computing systems. Such systems to which such integrated circuits are added are contemplated as part of the present invention. Given the teachings of the present disclosure herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0056] The examples of embodiments of the present invention herein are intended to provide a general understanding of the various embodiments, and these are not intended to provide all elements and features of the devices and systems that would be enabled by the structures and semiconductor manufacturing methods described herein. Many other embodiments will be apparent to those skilled in the art who have received the teachings of this specification; since other embodiments are used and derived therefrom, structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. The drawings are also merely illustrative and not drawn to scale. Therefore, the specification and drawings should be considered illustrative rather than limiting in nature.

[0057] Embodiments of the present invention are referred to herein by the term "embodiment" and, when one or more are actually shown, are referred to individually, collectively, or both, without intending to limit the scope of the present application to any single embodiment or inventive concept. Thus, while specific embodiments have been shown and described herein, it should be understood that configurations that achieve the same purpose may replace the specific embodiments shown, i.e., the present disclosure is intended to cover any and all adaptations and variations of the various embodiments. Combinations of the above-described embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art having the benefit of the teachings herein.

[0058] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprising" and "including" as used herein specify the presence of the recited features, integers, steps, operations, elements, and components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and groups thereof or combinations thereof. Terms such as "upper", "lower", "above", "below", "top", and "bottom" are used herein to indicate a relative position of an element or structure rather than an absolute position as may be used.

[0059] All equivalent ranges obtained by adding functional elements to the corresponding structures, materials, operations, and means, or steps, in the claims are intended to include any structures, materials, or operations for functioning in combination with elements described in other claims as if they were particularly described in the claims. The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to exhaust or limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The embodiments were selected and described to best explain the principles of the present invention, its practical applications, and to enable others skilled in the art to understand the present invention with various modifications suitable for the specific uses contemplated by others.

[0060] Additionally, in the above detailed description, it is understood that various features have been grouped together in a single embodiment for the purpose of streamlining the specification. The disclosed method should not be construed as reflecting an intention that the claimed embodiments require more features than are explicitly recited in each claim. Rather, the appended claims reflect that the inventive subject matter lies in less than all of the features of a single embodiment. Accordingly, the claims that follow are hereby incorporated into the detailed description, with each claim standing on its own as a separately claimed means.

[0061] Given the teachings of the embodiments of the present invention provided herein, those skilled in the art will be able to envision other implementations and applications of the technology of the embodiments of the present invention. The exemplary embodiments of the present invention have been described herein with reference to the accompanying drawings, but it should be understood that the embodiments of the present invention are not limited to those exact embodiments and that various other changes and modifications may be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A resistive random access memory (RRAM) structure, including top and bottom electrodes electrically coupled by first and second metal connection lines respectively, the first and second metal connection lines providing electrical connection to the RRAM structure, a layer of resistive switching material disposed between the top and bottom electrodes, the resistive switching material exhibiting a measurable resistance change under the influence of at least one of an electric field and heat, a dielectric spacer formed on a sidewall of the bottom electrode, a passivation layer formed on an upper surface of the dielectric spacer and covering at least a portion of a sidewall of the top electrode, the passivation layer being conformal to the first metal connection line as a mask, an upper surface of the passivation layer being self-aligned with a bottom surface of the first metal connection line as a mask, the RRAM structure.

2. At least one of the top and bottom electrodes includes a multilayer electrode, the RRAM structure according to Claim 1.

3. At least one of the top and bottom electrodes includes a first metal nitride layer, at least one second metal nitride layer, and a first metal layer formed on an upper surface of the first metal nitride layer, the RRAM structure according to Claim 2.

4. One of the first and second metal nitride layers includes titanium nitride, and the other of the first and second metal nitride layers includes tantalum nitride, the RRAM structure according to Claim 3.

5. The first metal layer includes at least one of tungsten and iridium, the RRAM structure according to Claim 3.

6. The layer of resistive switching material includes hafnium oxide, the RRAM structure according to any one of Claims 1 to 5.

7. The passivation layer includes at least one of silicon carbide, silicon dioxide, and silicon carbonate, the RRAM structure according to any one of Claims 1 to 6.

8. The passivation layer includes a conformal dielectric liner, the RRAM structure according to any one of Claims 1 to 7.

9. The passivation layer includes an electrically conductive material, the dielectric spacer is formed on sidewalls and on a bottom electrode of the layer of resistive switching material, and is configured to electrically isolate the resistive switching material and the bottom electrode from the passivation layer, the RRAM structure according to Claim 1.

10. The passivation layer is electrically connected to the top electrode, The RRAM structure according to claim 9.

11. The overall width of the top and bottom electrodes and the resistive switching layer is smaller than the width of the first metal connection line, thereby enabling the RRAM structure to be scaled to a size smaller than the size of the first metal connection line. The RRAM structure according to any one of claims 1 to 10.

12. A method of forming a resistive random access memory (RRAM) structure, the method comprising: Forming a bottom electrode on the upper surface of a first metal connection line; Forming a layer of a resistive switching material on at least a portion of the upper surface of the bottom electrode, wherein the resistive switching material exhibits a measurable resistance change under the influence of at least one of an electric field and heat; Forming a top electrode on the upper surface of the layer of the resistive switching material; Forming a dielectric layer surrounding the RRAM structure; Forming a trench passing at least partially through the dielectric layer; Forming a dielectric spacer formed on at least the sidewalls of the bottom electrode, and Forming, on the upper surface of the dielectric spacer, a passivation layer covering at least a portion of the sidewall of the top electrode, as a mask conformal to a second metal connection line electrically connected to the top electrode; comprising The dielectric spacer is formed on at least the sidewalls of the bottom electrode and on the layer of the resistive switching material, the passivation layer includes an electrically conductive material, and the passivation layer electrically isolates the resistive switching material and the bottom electrode. Method.

13. The passivation layer includes a conformal dielectric liner, and the method further comprises: Forming the trench passing at least partially through the dielectric layer, thereby exposing the top electrode of the RRAM structure and at least a portion of the dielectric spacer; Depositing the conformal dielectric liner in the trench and filling an over-etch region of the trench; and Performing an isotropic etch-back of the conformal dielectric liner to remove the conformal dielectric liner on the sidewalls of the trench and leaving the conformal dielectric liner in the over-etch region of the trench, with at least a portion of the upper surface of the top electrode being exposed in the trench through the grooved conformal dielectric liner. The method according to claim 12.

14. The second metal connection line is formed by depositing a metal over the trench of the RRAM structure and over the upper surfaces of the conformal dielectric liner and the top electrode, The method according to claim 13. **Claim 15** The first and second metal connection lines are formed by a copper damascene process, The method according to claim 12. **Claim 16** At least one of the top and bottom electrodes includes forming a multi-layer electrode, The method according to any one of claims 12 to 15. **Claim 17** The multi-layer electrode includes a first metal nitride layer, at least one second metal nitride layer, and a first metal layer formed on the upper surface of the first metal nitride layer, The method according to claim 16. **Claim 18** The overall width of the top and bottom electrodes and the resistive switching material layer is smaller than the width of the second metal connection line, The method according to any one of claims 12 to 17.

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