Phase change device

Abstract

According to some embodiments of the present invention, a phase change device (PCD) includes first and second semiconductor layers. The first semiconductor layer is made of a first semiconductor material and has a first semiconductor thickness, a first interface, and a first electrode surface. The first interface and the first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material is capable of transitioning between a first amorphous state and a first crystalline state under one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface, and a second electrode surface. The second interface and the second electrode surface are on opposite sides of the second semiconductor layer. The first interface and the second interface are in electrical, physical, and chemical contact with each other at the interface. The second semiconductor material is capable of transitioning between a second amorphous state and a second crystalline state under one or more second conditions. The first electrode is in physical and electrical contact with the first electrode surface of the first semiconductor layer, and the second electrode is in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first condition and the second condition are different. Thus, in some embodiments, the first and second semiconductor materials can be in different amorphous and / or crystalline states. The layers can have an amorphous / crystalline separation. By controlling how the layers separate, the PCD can be in different resistance states.

Description

Technical Field

[0001] The present invention relates to a phase change device. More particularly, the present invention relates to a phase change device having multiple states.

Background Art

[0002] Some phase change devices (PCDs) can operate in two states, for example, a high resistive state (HRS) and a low resistive state (LRS). Other PCDs can operate at multiple states, for example, at a resistance value between HRS and LRS. By applying different voltages to these devices, the states of the devices can be set or reset.

[0003] In some devices, an insulator that is normally insulating can be made conductive (to a low resistive state (LRS)) through one or more filaments or conductive paths by applying a sufficiently high voltage. Once the filament / conductive path is formed, a voltage change can "reset" the insulator (for example, by interrupting the filament / conductive path to make it HRS) or "set" it (by reforming the filament / conductive path to make it LRS). It is also possible to form / memorize an intermediate state between LRS and HRS by changing the configuration of the filament by an electrical bias.

[0004] Phase change devices (PCDs), such as resistive random-access memory (RRAM(R)), are being considered as a promising technology not only for high-density and high-speed non-volatile memory applications but also for electronic synapse devices or memristors used in neuromorphic computing. In neuromorphic computing applications, resistive change memory devices can be used as connections (synapses) between pre-neurons and post-neurons, and the connection weights are represented in the form of device resistance. Multiple pre-neurons and post-neurons can be connected by a crossbar array of RRAM(R), naturally representing a fully connected neural network.

[0005] Fabricating PCDs in the back-end-of-line (BEOL) wiring process can pose challenges. Device circuits are generally placed in the lower layers of the circuit in the front-end-of-line (FEOL) substrate process, but BEOL generally has multiple insulator substrate layers and can be difficult to use when manufacturing phase change devices, especially when forming high-density arrays of PCDs such as large-scale memory structures.

[0006] In particular, in the BEOL region, there is a need for structures and methods that enable the construction of PCDs and high-density PCD arrays. Furthermore, there is a need for multi-state PCD structures and methods for manufacturing these multi-state PCD structures. SUMMARY OF THE INVENTION

[0007] According to some embodiments of the present invention, a phase change device (PCD) has first and second semiconductor layers. The first semiconductor layer is made of a first semiconductor material and has a first semiconductor thickness, a first interface, and a first electrode surface. The first interface and the first electrode surface are on opposite sides of the first semiconductor layer from each other. The first semiconductor material can transition between a first amorphous state and a first crystalline state under one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface, and a second electrode surface. The second interface and the second electrode surface are on opposite sides of the second semiconductor layer from each other. The first interface and the second interface are in electrical, physical, and chemical contact with each other at the boundary. The second semiconductor material can transition between a second amorphous state and a second crystalline state under one or more second conditions. The first electrode is in physical and electrical contact with the first electrode surface of the first semiconductor layer, and the second electrode is in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first condition and the second condition are different. Thus, in some embodiments, the first and second semiconductor materials can be in different amorphous states or crystalline states or both.

[0008] In some embodiments, the first semiconductor layer is divided or separated into a first epitaxial crystal layer and a first amorphous residual layer. The first epitaxial crystal layer has an epitaxial thickness and an epitaxial resistance, and the first amorphous residual layer has a residual thickness and a residual resistance. By controlling the epitaxial thickness, the resistance between the two ends of the first semiconductor, and thus the total resistance between the two ends of the device (electrodes), is controlled to produce a plurality of resistance states from LRS to a plurality of HRS.

[0009] Disclosed are a method of manufacturing and a method of using a PCD.

[0010] Various embodiments of the present invention will be described in more detail later with reference to the accompanying drawings, but will be briefly described here. The figures show various devices, structures, and related method steps of the present invention.

Brief Description of the Drawings

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Modes for Carrying Out the Invention

[0012] Embodiments of the present invention are not limited to the exemplary methods, apparatuses, structures, systems, and devices disclosed herein, but rather, as will be apparent to those skilled in the art given this disclosure, are more generally applicable to other alternative and broader methods, apparatuses, structures, systems, and devices.

[0013] In addition, the various layers, structures, or regions shown in the accompanying drawings, or combinations thereof, are not drawn to scale, and it should be understood that one or more layers, structures, or regions of a generally used type, or combinations thereof, may not be explicitly shown in a given drawing. This does not mean that layers, structures, or regions, or combinations thereof, that are not explicitly shown are omitted from an actual device.

[0014] In addition, when the description unavoidably focuses on such omitted elements, specific elements may be omitted from the figures for clarity or simplicity, or both. Further, the same or similar reference numbers used throughout the drawings are used to indicate the same or similar features, elements, or structures, and thus, detailed descriptions of the same or similar features, elements, or structures are not repeated for each of the drawings.

[0015] The semiconductor devices, structures, and methods disclosed by embodiments of the present invention may be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., cell and smartphones), solid state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, and the like. Systems and hardware incorporating such semiconductor devices and structures are contemplated as embodiments of the present invention.

[0016] As used herein, "height" refers to the vertical dimension of an element (e.g., a layer, trench, hole, opening, etc.) measured from the bottom surface to the top surface of the element, or measured with reference to the surface on which the element is placed, or both, in a cross-sectional view or a front view.

[0017] Conversely, "depth" refers to the vertical dimension of an element (e.g., a layer, trench, hole, opening, etc.) measured from the top surface to the bottom surface of the element in a cross-sectional view or a front view. When terms such as "thick", "thickness", "thin", or their derivatives are described, they may be used in place of "height".

[0018] As used herein, "lateral", "lateral side", "side", and "lateral surface" refer to the side surface of an element (e.g., a layer, opening, etc.), such as the left-side surface or the right-side surface in a drawing.

[0019] As used herein, "width" or "length" refers to the dimension of an element (e.g., a layer, trench, hole, opening, etc.) measured from one side surface to the opposite side surface in a drawing. When terms such as "thick", "thickness", "thin", or their derivatives are described, they may be used in place of "width" or "length".

[0020] As used herein, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof relate to the disclosed structures and methods as oriented in the drawings. For example, as used herein, "vertical" refers to a direction perpendicular to the upper surface of the substrate in a front view, and "horizontal" refers to a direction parallel to the upper surface of the substrate in a front view.

[0021] As used herein, unless otherwise specified, terms such as "on", "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element is present on a second element, and there may be intervening elements between the first element and the second element. As used herein, unless otherwise specified, terms such as "on", "overlying", "atop", "on top", "positioned on", or "positioned atop", "disposed on", or the term "directly" used in connection with the terms "in contact" or "direct contact" mean that the first element and the second element are connected without intervening elements therebetween, such as, for example, an intermediate conductive layer, an insulator layer, or a semiconductor layer.

[0022] It should be understood that these terms may be affected by the orientation of the described device. For example, the meaning of these descriptions may change if the device is rotated upside down, but the descriptions remain valid as they describe the relative relationships between the features of the present invention.

[0023] Disclosed are embodiments of a phase change device (PCD) structure and processes for manufacturing and operating a PCD.

[0024] Non-limiting examples of PCD structures include a first semiconductor layer and a second semiconductor layer sandwiched between a top electrode and a bottom electrode. The first semiconductor layer and the second semiconductor layer have a boundary where each of one of the surfaces (the interface surface) of the first semiconductor layer and the second semiconductor layer is physically in contact with the other interface surface. In some embodiments, a thin anti-diffusion layer exists between the first interface and the second interface. Each of the first semiconductor layer and the second semiconductor layer has an electrode surface which is the surface of the semiconductor layer on the side opposite to the interface surface of the respective semiconductor layer. The first electrode surface on the first semiconductor layer is physically and electrically in contact with the bottom or the first electrode, and the second electrode surface on the second semiconductor layer is physically and electrically in contact with the top or the second electrode.

[0025] The materials that make up the first semiconductor layer and the second semiconductor layer have different, distinguishable thermal properties such that each semiconductor changes from an amorphous structure to a crystalline structure upon different, distinguishable thermal changes such as thermal changes in temperature.

[0026] Thermal heating and cooling steps, such as annealing, are performed to bring both the first and second semiconductor layers to a crystalline state.

[0027] The "set" step enables the formation of a first epitaxial crystal layer that starts from the boundary within the (separated) first semiconductor layer and penetrates the first semiconductor layer for epitaxial crystal growth or change in the first crystal layer. Thus, the first semiconductor layer is divided or separated into a first epitaxial crystal layer and a first amorphous residual layer. The first epitaxial crystal layer has an epitaxial thickness and an epitaxial resistance, and the first amorphous residual layer has a residual thickness and a residual resistance.

[0028] For example, by changing the characteristics of the set pulse or by changing how the set step is executed, the epitaxial thickness and the residual thickness change. Accordingly, the epitaxial resistance and the residual resistance can be changed, and different totals (total resistance) of the resistance between both ends of the structure, for example, different (resistance) states of the structure, can be predetermined, controlled, and enabled.

[0029] Please refer to the figure here.

[0030] FIG. 1 is a front view of the configuration of a preparatory stacked structure 100 in an initial step of an exemplary process for manufacturing a phase change device (PCD).

[0031] The structure 100 has a substrate 105. The insulator layer 110 is disposed on the substrate 105. In some embodiments, for example, in the back-end-of-line (BEOL) process, the substrate 105 may be omitted. The bottom electrode 115 is disposed on the insulator layer 110.

[0032] The substrate 105 can be made of a single element (e.g., silicon or germanium); mainly a single element (e.g., with doping), such as silicon; or a compound semiconductor, such as gallium arsenide (GaAs), or a semiconductor alloy, such as silicon germanium (SiGe). In some embodiments, the substrate 105 includes one or more semiconductor materials including, but not limited to, silicon (Si), SiGe, Si:C (carbon-doped silicon), germanium (Ge), carbon-doped silicon germanium (SiGe:C), Si alloy, Ge alloy, group III-V materials (e.g., GaAs, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.), group II-V materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS) or a combination thereof), or other like semiconductors. Additionally, a plurality of layers of semiconductor materials can be used as the semiconductor material of the substrate 105. In some embodiments, the substrate 105 includes both a semiconductor material and an insulator material. In some silicon-on-insulator (SOI) implementations, a buried oxide layer, BOX (buried oxide) (e.g., SiO2) is embedded in the substrate 105.

[0033] In some embodiments, the insulator layer 110 is made of a low-k insulator. The term "low-k insulator" generally refers to an insulating material having a dielectric constant smaller than that of silicon oxide, e.g., smaller than 3.9. By way of non-limiting example, the insulator layer 110 is made of a material including a dielectric oxide (e.g., silicon oxide, SiOx); a dielectric nitride (e.g., silicon nitride, SiN; boron carbon nitride silicon, SiBCN; carbon nitride silicon, SiCN; and boron nitride silicon, SiBN); a dielectric oxynitride (e.g., silicon oxycarbonitride, SiOCN, and silicon oxynitride, SiON); silicon carbide (SiC); silicon carbon oxide (SiCO); or any combination or the like thereof.

[0034] The insulator layer 110 can be deposited by known deposition techniques including atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), radio frequency chemical vapor deposition (RFCVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), or liquid source misted chemical deposition (LSMCD), or a combination thereof.

[0035] In some embodiments, the insulator layer 110 has an insulator layer thickness 111 between 50 nanometers (nm) and 100 nm. Other thicknesses 111 are also contemplated.

[0036] The first or bottom electrode 115 is made of a conductive material, such as a metal. Non-limiting examples of metals include copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), thallium nitride (Tl3N), and titanium nitride (TiN). In some embodiments, the first / bottom electrode 115 is made of Al.

[0037] The first / bottom electrode 115 can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, LSMCD, or sputtering, or a combination thereof.

[0038] In some embodiments, the thickness 116 of the first electrode 115 is between 50 nanometers (nm) and 100 nm. Other thicknesses 116 are also contemplated.

[0039] FIG. 2 is a schematic front view of a preparatory stacked structure 200 after the addition of two semiconductor layers (250, 225) and an optional anti-diffusion layer 285.

[0040] The first semiconductor layer 250 is made of a first semiconductor material that can take an amorphous form (a first amorphous form) and a crystalline form (a first crystalline form). The second semiconductor layer 225 is made of a second semiconductor material that can take an amorphous form (a second amorphous form) and a crystalline form (a second crystalline form). The amorphous form can transition to the crystalline form under various physical conditions (and vice versa). The first semiconductor material has the property of transitioning the first semiconductor material from the amorphous form to the crystalline form under conditions different from those under which the second semiconductor transitions from the amorphous form to the crystalline form (e.g., application of temperature or voltage or both).

[0041] In some embodiments, the material of the first semiconductor layer 250 is germanium (Ge), and the material of the second semiconductor layer 225 is silicon (Si). Other materials are also contemplated.

[0042] The first semiconductor layer 250 has a thickness 251 of the first semiconductor layer 250 between 20 nm and 50 nm. Similarly, the second semiconductor layer 225 has a thickness 226 of the second semiconductor layer 225 between 20 nm and 50 nm.

[0043] The first semiconductor layer 250 has a first interface 257 and a first electrode surface 258. The first interface 257 and the first electrode surface 258 are on opposite sides of each other, i.e., on opposite sides of the first semiconductor layer 250.

[0044] The second semiconductor layer 225 has a second interface 227 and a second electrode surface 228. The second interface 227 and the second electrode surface 228 are on opposite sides of each other, i.e., on opposite sides of the second semiconductor layer 225.

[0045] The first electrode surface is in physical and electrical contact with the first / bottom electrode 115. In some embodiments, the first interface 257 is in physical, chemical, and electrical contact with the second interface 227. In alternative embodiments, an optional diffusion blocking layer (DBL) 285 is present "sandwiched" between the first interface 257 and the second interface 227. The second electrode surface 228 is in physical and electrical contact with the second / top electrode 515, as shown below, for example in FIG. 5.

[0046] The DBL 285 prevents the diffusion of the first semiconductor layer 250 material (e.g., Ge) into the second semiconductor layer 225 material (e.g., Si). The DBL can be made of titanium nitride (TiN) or carbon (C). Other known barrier, diffusion preventing materials can also be used.

[0047] The DBL 285 is a thin layer having a thickness 286 between 1 nm and 10 nm.

[0048] The first semiconductor layer 250, the second semiconductor layer 225, and the DBL 285 can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, or LSMCD, or a combination thereof. The order of deposition is not important. However, if an optional DBL layer 285 is placed, the DBL layer 285 will be present between the first interface 257 and the second interface 227. Reversing the order of deposition of the semiconductor layers (250, 225), the second electrode surface 228 is in physical and electrical contact with the first / bottom electrode 115, and the first electrode surface 258 is in physical and electrical contact with the second / top electrode 515. However, in either case, as will be explained below, without loss of generality, the first semiconductor layer 250 is a semiconductor layer with epitaxial growth.

[0049] Figure 3 is a front view of the structure of a preparatory stacked structure 300 after a known mask etching step that defines the footprint of the PCD, for example, directional reactive ion etching (RIE). During 310 where a large amount of semiconductor layers (225, 250) around the remaining semiconductor layers (350, 325) (left and right - as well as front and back, not shown) are removed, the mask protects a portion of the semiconductor layers (225, 250). One or more known chemicals suitable for removing the unmasked first semiconductor layer 250 and second semiconductor layer 225 can be used. In some embodiments, the etching stops at a barrier layer, for example, the first / bottom electrode 115.

[0050] In this structure 300 and the following structures, DBL285 may or may not be included in the structure, and for clarity, DBL285 is not shown. The etching using this mask defines the dimensions or area or both that the PCD uses on the surface of the first / bottom electrode 115, that is, the footprint of the PCD.

[0051] Figure 4 is a front view of the structure of a preparatory stacked structure 400 covered with an insulator 410.

[0052] In some embodiments, the insulator 410 can be of the same type as that in the insulator layer 110, or arranged by the same method, or both. In some embodiments, the insulator 410 can be an interlayer dielectric (ILD). The ILD410 can be formed from a low - k insulator material (with k < 4.0) including, but not limited to, silicon oxide, spin - on glass, flowable oxide, high - density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD410 is deposited by a deposition process including, but not limited to, CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or similar processes.

[0053] FIG. 5 is a front view of the structure 500 of the stacked structure including the second / upper electrode 515. Although the structure 500 is complete, the structure 500 is the initial structure of the PCD in that, as will be described later, the chemical structure of the semiconductor layers (325, 350) needs to be transformed for the semiconductor layers (325, 350) to operate efficiently as a PCD.

[0054] The second / upper electrode 515 is formed by performing etching using a mask, such as directional RIE, through the ILD / insulator layer 410 above the second semiconductor layer 325. In some embodiments, the etching stops at the second electrode surface 228. Using the same materials and methods as those used to deposit the first electrode layer 115, the second / upper electrode 515 is deposited to physically and electrically contact the second electrode surface 228.

[0055] FIG. 6 is a front view of the initial structure PCD embodiment 600 after the first semiconductor layer 350 and the second semiconductor layer 325 are heated and cooled to form crystal structures (650, 625).

[0056] A physical process is performed such that both the first semiconductor layer 350 and the second semiconductor layer 325 experience one or more changed physical conditions that transform the first semiconductor structure 350 to the first crystalline state 650 and the second semiconductor structure 325 to the second crystalline state 625.

[0057] In some embodiments, the changing physical condition is thermal annealing. In other words, both semiconductor layers (350, 325) are heated to a temperature above the temperature at which they melt and then cooled over time, resulting in the formation of both a first crystalline semiconductor layer 650 and a second crystalline semiconductor layer 625. The time and temperature levels for crystallizing both the first crystal layer 650 and the second crystal layer 625 depend on the type of material within the layer and the volume of material within the layer. The actual time and temperature values need to be determined according to specific circumstances, but as a non-limiting example, the temperature can be locally raised within the device to a temperature between 900 degrees Celsius (°C) and 1000 °C and cooled over a period between 1 microsecond and 10 microseconds to room temperature.

[0058] In a non-limiting example, by the annealing step, amorphous Ge (α-Ge) in the first semiconductor layer 350 is changed to crystalline Ge (c-Ge) 650, and amorphous Si (α-Si) in the second semiconductor layer 325 is changed to crystalline Si (c-Si) 625.

[0059] FIG. 7 is a front configuration view of an embodiment 700 of a PCD after the first crystalline semiconductor layer 650 has been reset to an amorphous structure 750.

[0060] The first crystalline semiconductor layer 650 is "reset" to an amorphous structure 750 without changing the structure of the second crystalline semiconductor layer 625. This is due to the property that each of the first semiconductor layer (350, 650) and the second semiconductor layer (325, 625) can undergo a transition from amorphous to crystalline (and back again) under one or more different distinguishable physical conditions. Thus, the transition from amorphous to crystalline (and back again) can be performed in the first semiconductor layer structure (350, 650) without affecting the second semiconductor layer structure (325, 625).

[0061] In a non-limiting example, Ge transitions from amorphous to crystalline (and back again) at a lower temperature than Si. By applying one or more electrical / voltage pulses between the first / bottom electrode 115 and the second / top electrode 515, current flows through the first (350, 650) and second (325, 625) semiconductor layers, heating them up. The pulses are designed to heat Ge to a temperature higher than Ge's transition point (temperature) but lower than Si's transition point. Thus, the first crystalline semiconductor layer 650 (e.g., c-Ge) melts, while the second crystalline semiconductor layer 625 does not melt. There is a quenching period that is too rapid to reform the first amorphous semiconductor layer 750 into a crystalline state. The second crystalline 625 semiconductor layer 625 (e.g., c-Si) does not change from its crystalline state 625 due to this temperature / voltage change.

[0062] The structure 700 is now "reset" and has a first semiconductor layer 350 in a high-resistance amorphous state 750. Thus, due to the increased resistance of the first amorphous semiconductor layer 750, the overall resistance of the structure 700 is high. The structure 700 is reset to the HRS by the amorphous structure of the first semiconductor layer 350. As will be described later, "setting" the first semiconductor layer 350 back to a crystalline structure reduces the resistance between the two ends of the first semiconductor layer (350, 650) and places the structure 700, which is a PCD with two or more states, an LRS and multiple HRSs, in multiple HRSs until it reaches the LRS.

[0063] The material type, layer volume, and other factors in the first semiconductor layer 350 and the second semiconductor layer 325 are used to design the timing, shape, and magnitude of the voltage pulse. Examples of the pulse timing, shape, and magnitude of the voltage pulse used to "reset" are provided later in FIG. 10(A). In some embodiments, in the reset state, the entire volume of the first semiconductor layer 350 is in an amorphous state.

[0064] FIG. 8 is a front view of the configuration of the PCD embodiment 800 after the first amorphous semiconductor layer 850 is "set" to one of a plurality of two-layer structures (850A, 850B), i.e., the first semiconductor crystal layer 850A and the first semiconductor amorphous layer 850B.

[0065] In one embodiment, the set pulse (see FIG. 10(B)) changes the first amorphous semiconductor layer (e.g., after the reset pulse has reset the first semiconductor layer to the completely amorphous state 750) into the separated first semiconductor layer 850 that is separated into two layers: 1. the first epitaxial crystal layer 850A having an epitaxial thickness 865 and an epitaxial resistance, and 2. the first amorphous residual layer 850B having a residual thickness 860 and a residual resistance. The residual layer 850B is what remains of the amorphous layer 750 of the first semiconductor amorphous layer 750 after the set pulse.

[0066] The shape, duration, timing, and magnitude of the set pulse determine, for example, the thicknesses 865 and 860 of the first epitaxial crystal layer 850A and the first amorphous residual layer 850B, respectively. Thus, the epitaxial resistance and the residual resistance can be controlled by the design of the set pulse that controls the respective thicknesses (865, 860) of the epitaxial crystal layer 850A and the residual layer 850B. Thus, the resistance of the separated first semiconductor layer 850 in the set state and the total resistance of the entire device 800 (measured between the first electrode 115 and the second electrode 515), i.e., the total of the resistances of the HRSs, is controlled by the design of the set pulse.

[0067] The total resistance of the device 800 in one of the plurality of HRSs and other factors that affect how the set pulse is designed include the materials and thicknesses (251, 226) of the first semiconductor layer 250 and the second semiconductor layer 225, and, if present, the type and thickness 286 of the material of the DBL layer 285.

[0068] As a result, with other external physical conditions of the first semiconductor layer 250 and the second semiconductor layer 225 being constant, by changing the shape, duration, timing, and magnitude of the set pulse, a plurality of high-resistance states in the set state, for example, values of the total resistance of the device 800, can be generated. Therefore, by changing the set pulse, the structure 800 can be a PCD having a plurality of (resistance) set states.

[0069] By changing how the set step is executed, for example, by changing the characteristics of the set pulse, the epitaxial thickness and the residual thickness will change. Therefore, the epitaxial resistance and the residual resistance can be changed, and different totals of the resistance between both ends of the structure, for example, different states of the structure, can be predetermined, controlled, and made possible.

[0070] The design of the set pulse determines how the first epitaxial crystal layer 850A is formed.

[0071] The term "epitaxial growth" means the growth of a semiconductor material on the contact surface of a semiconductor material, and the semiconductor material to be grown has the same crystal characteristics as the semiconductor material of the deposition surface. Where epitaxial growth is ongoing, material parameters can be generated so that the atoms at the surface 875 of the growth layer 850A have enough energy to move around on the surface 875 and arrange themselves in the crystal arrangement of the atoms.

[0072] For example, when the set pulse is designed to heat and melt the first amorphous semiconductor layer 750, the atoms in the first amorphous semiconductor layer 750 will have enough energy to move around. In addition, if the first amorphous semiconductor layer 750 can be slowly cooled by the set pulse, the moving atoms (for example, of Ge) will move in the crystal axis direction of the crystal plane with which the atoms are in contact.

[0073] When there is DBL985, DBL985 can act as a template for Ge crystallization.

[0074] Continuing with this non - limiting example, when the set of pulses melts the first amorphous semiconductor layer 750 material (Ge), the material (Si) in the second semiconductor layer 625 remains in a crystalline structure. As the atoms in the first amorphous semiconductor layer 750 are slowly cooled, the atoms arrange themselves along the crystal order of the second semiconductor layer 625 starting from the boundary 825. As layer 850 continues to be slowly cooled, more atoms in the first amorphous semiconductor layer 750 arrange themselves along the crystal order, thus increasing the thickness 865 of the growing first epitaxial crystal layer 850A and moving the boundary 875 of the first amorphous semiconductor layer 750 deeper. As the thickness 865 of the first epitaxial crystal layer 850A increases, the thickness 860 of the residual layer 850B decreases.

[0075] By varying the thickness 865 of the first epitaxial crystal layer 850A and the thickness 860 of the residual layer 850B, the resistance values of these layers change, and thus, by controlling the set of pulses, the overall resistance of the device 800 changes.

[0076] In some embodiments, by gradually decreasing the value of the set of pulses over time, for example, by reducing the rate of change of cooling, or by increasing the cooling time of the separated first semiconductor layer 850, or both, the thickness 865 of the first epitaxial crystal layer 850A will increase and the thickness 860 of the residual layer 850B will decrease.

[0077] FIG. 9 is a front - view configuration of an alternative PCD embodiment 900 having a diffusion - barrier layer (DBL) 985. The barrier layer 985 is formed by depositing the optional layer 285 shown in FIG. 2 and continuing the process steps that would be performed if DBL285 could not be deposited.

[0078] Figure 10(A) is a plot 1000 of voltage 1030 versus time 1035, showing one or more reset pulses, typically 1025. The reset pulse 1025 has a duration 1010 and a height 1020 that is high enough to melt the material (e.g., Ge) in the first semiconductor layer 250 but not high enough for the material (e.g., Si) in the second semiconductor layer 225. However, the duration 1010 is short enough so that the first semiconductor layer material 250 does not have time to crystallize, and in particular the fall time 1026 is fast enough. Thus, the first semiconductor layer material 250 remains in the amorphous structure / state 750 or returns to the amorphous structure / state 750 when the device 800 / 900 is reset.

[0079] Figure 10(B) is a voltage 1030 versus time 1035 plot 1050 showing one or more set pulses, typically 1070. The set pulse has a magnitude 1055 and a duration 1060 with a time rate of fall 1065 that falls gently over the fall time 1075 of the set pulse. For example, the time rate of fall 1065 is the magnitude 1055 of the pulse 1070 divided by the set pulse fall time 1075.

[0080] As discussed, the design of, among other things, the magnitude (1020, 1055), timing (1010, 1060, 1075), duration (1010, 1080), and shape (1025, 1070) of these pulses depends on the type and thickness (251, 226) of the materials of the first semiconductor layer 350 and the second semiconductor layer 325.

[0081] However, in some embodiments, the reset pulse 1025 has a reset pulse magnitude 1020 between 7 volts and 10 volts, for example, a reset pulse magnitude of 8 volts; a reset pulse rise time 1024 between 2.0 nanoseconds (ns) and 3.0 ns, for example, 2.5 ns; and a reset pulse fall time 1026 between 2.0 nanoseconds (ns) and 3.0 ns, for example, 2.5 ns. The shape of the reset pulse can be rectangular or other shapes. However, the fall time 1026 of the reset pulse must be fast enough so that the material does not crystallize. The magnitude 1020 of the reset pulse 1025 must be low enough so that the crystal structure of the material of the second semiconductor layer 625 does not change.

[0082] In some embodiments, by way of non-limiting example, the set pulse 1070 has a magnitude 1069 between 4 volts and 6 volts, for example, 5 volts; a set pulse rise time 1069 between 2.0 nanoseconds (ns) and 3.0 ns, for example, 2.5 ns; and a long set pulse fall time 1075 between 0.8 milliseconds (ms) and 1.5 ms, for example, 1.0 ms. Some set pulse shapes have a gentle fall time greater than, for example, 1.0 ms to give time to form a crystal structure in the first semiconductor crystal layer 850A. The duration 1080 of the set pulse 1070 is long enough to include the long fall time 1075, for example, 1.0 ms or more.

[0083] FIG. 11 is a flowchart showing one embodiment 1100 of a process for manufacturing a PCD.

[0084] Step 1105 of the method begins with the deposition of the first electrode 115 onto the insulator layer 110 or the substrate 105 or both. Next, the first semiconductor layer 250 and the second semiconductor layer 225 are deposited. In some embodiments, the diffusion prevention layer 285 is deposited between the electrically first semiconductor layer 250 and the second semiconductor layer 225.

[0085] As defined in FIGS. 3 through 5, step 1110 deposits the second electrode 515 after performing etching and other lithography steps that define the footprint of the PCD.

[0086] As described with respect to FIG. 6, step 1115 crystallizes the first semiconductor layer 250 and the second semiconductor layer 225 with thermal heating and cooling steps, such as annealing. Other crystallization methods are possible.

[0087] Step 1120 amorphizes the first semiconductor layer by changing physical conditions, for example with a reset voltage pulse 1025, to place the device in a reset state or LRS.

[0088] Step 1125 separates the first semiconductor layer 850 into a first semiconductor crystalline layer 850A and a first semiconductor amorphous layer 850B by changing physical conditions, for example with a set voltage pulse 1075. This places the device 800 in one of a plurality of resistance states (measured by the total resistance between the first electrode 115 and the second electrode 515) selected by the design of the set voltage pulse 1075. The resistance state will have the total resistance across the device 800 having one of a plurality of values between the LRS and the HRS. In the LRS, the first semiconductor crystalline layer 850A has a width or epitaxial thickness 865 equal to the full width 251 of the first semiconductor layer 250.

[0089] FIG. 12 is a flowchart showing one embodiment 1200 of a process for operating a PCD.

[0090] Process 1200 begins with step 1205, which resets the first semiconductor layer 850 to an amorphous state in which all of the first semiconductor 850 material is in an amorphous state 750. In some embodiments, this step is performed with a reset pulse 1025.

[0091] In step 1210, a device, such as 800, is set to separate the first semiconductor layer 850 into a first semiconductor crystal layer 850A and a residual layer 850B.

[0092] In step 1215, as described with reference to FIG. 10(B), the total resistance between both ends of a device, such as 800, is selected by a set pulse. The total resistance is a resistance value measured between the first electrode 115 and the second electrode 515. The total resistance is greatly affected by the resistance of the first semiconductor layer 850. Similarly, the resistance of the first semiconductor layer 850 is affected by the width or epitaxial thickness 865 of the first semiconductor crystal layer 850A. The larger the epitaxial thickness 865, the larger the volume of the first semiconductor layer 850 material in a crystalline state with a lower resistance state. Therefore, by controlling the epitaxial thickness 865, the total resistance can be changed to one of a plurality of values between the LRS and the HRS, or between a structure in which the first semiconductor layer 850 material is completely amorphous and a structure in which it is completely crystalline. The design of the set pulse determines how much of the first semiconductor layer 850 material grows epitaxially, increases the epitaxial thickness 865, and decreases the total resistance.

[0093] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. For example, the semiconductor devices, structures, and methods disclosed in accordance with the embodiments of the present invention may be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing the embodiments of the present invention include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., cells and smartphones), solid state media storage devices, expert and artificial intelligence systems, functional circuits, and the like. Systems and hardware incorporating the present semiconductor device are contemplated as embodiments of the present invention.

[0094] The terms used in this specification are chosen either to explain the principles of the embodiments and the practical implementation or technological improvement of the techniques found in the market, or in other respects, to enable other persons skilled in the art to understand the embodiments disclosed in this specification. Devices, components, elements, features, apparatuses, systems, structures, techniques, and methods described in different terms that perform substantially the same function, operate in substantially the same manner, have substantially the same utility, or perform similar steps, or combinations thereof, are contemplated as embodiments of the present invention.

Claims

Claim 1 A phase change device (PCD), comprising: A first semiconductor layer made of a first semiconductor material and having a first semiconductor thickness, the first semiconductor layer further having a first interface and a first electrode surface, the first interface and the first electrode surface being on opposite sides of the first semiconductor layer, the first semiconductor material having a property of transitioning between a first amorphous state and a first crystalline state under a first condition of temperature, voltage, or both, and configured such that a plurality of states of the phase change device (PCD) occur according to the degree of the first crystalline state in the first semiconductor layer; the first semiconductor layer; A second semiconductor layer made of a second semiconductor material and having a second semiconductor thickness, the second semiconductor layer further having a second interface and a second electrode surface, the second interface and the second electrode surface being on opposite sides of the second semiconductor layer, the first interface and the second interface being in electrical, physical, and chemical contact with each other at the boundary, the second semiconductor material having a property of transitioning between a second amorphous state and a second crystalline state under a second condition of temperature, voltage, or both, and the second semiconductor layer being configured such that when the first semiconductor layer transitions to the first amorphous state at the first semiconductor thickness, the second semiconductor material in the second semiconductor layer is maintained in the second crystalline state; the second semiconductor layer; A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer; A second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer A phase change device (PCD), wherein the first condition and the second condition are distinguishable and different from each other. Claim 2 The PCD according to claim 1, wherein the first condition is a lower temperature and the second condition is a higher temperature. Claim 3 The PCD according to claim 2, wherein the lower temperature and the higher temperature are caused by a voltage pulse between the first electrode and the second electrode. Claim 4 The PCD according to claim 3, wherein the voltage pulse is a reset pulse having a voltage magnitude high enough to cause the first semiconductor material to transition to the first amorphous state without causing the second semiconductor material to transition from the second crystalline state. Claim 5 The PCD according to claim 4, wherein the reset pulse has a reset pulse fall time that is sufficiently fast so that the first amorphous state does not transition to the first crystalline state.

6. The PCD according to claim 5, wherein the entire first semiconductor material is in the first amorphous state, and a first resistance between both ends of the first semiconductor material in the first amorphous state is greater than the first resistance when a part of the first semiconductor material is in the first crystalline state.

7. The PCD according to claim 3, wherein the voltage pulse is a set pulse having a voltage magnitude that is sufficiently high for the first semiconductor material to transition from the first amorphous state.

8. The PCD according to claim 7, wherein the set pulse has a sufficiently slow and gentle set pulse fall time so that the first semiconductor crystal layer epitaxially grows from the boundary to separate the first semiconductor layer into the first semiconductor crystal layer having an epitaxial thickness smaller than the first semiconductor thickness and a first amorphous residual layer having a residual thickness.

9. The PCD according to claim 8, wherein the epitaxial thickness is determined by the set pulse fall time.

10. The PCD according to claim 1, wherein the first semiconductor layer is separated into a first semiconductor crystal layer having an epitaxial thickness smaller than the first semiconductor thickness and a first amorphous residual layer having a residual thickness, and a first resistance between both ends of the first semiconductor material is smaller than the first resistance when the first semiconductor material is in the first amorphous state and greater than the first resistance when the first semiconductor material is in the first crystalline state.

11. A phase change device (PCD), comprising: A first semiconductor layer made of a first semiconductor material and having a first semiconductor thickness, wherein the first semiconductor layer further has a first boundary surface and a first electrode surface, the first boundary surface and the first electrode surface are on opposite sides of the first semiconductor layer, the first semiconductor material has a characteristic of transitioning between a first amorphous state and a first crystalline state under a first condition of temperature, voltage, or both, and the phase change device (PCD) is configured to generate a plurality of states according to the degree of the first crystalline state in the first semiconductor layer. The first semiconductor layer, A second semiconductor layer made of a second semiconductor material and having a second semiconductor thickness, the second semiconductor layer further having a second interface and a second electrode surface, the second interface and the second electrode surface being on opposite sides of the second semiconductor layer from each other, the second semiconductor material having a property of transitioning between a second amorphous state and a second crystalline state under a second condition of temperature, voltage, or both, the second semiconductor layer being configured such that when the first semiconductor layer transitions to the first amorphous state at the first semiconductor thickness, the second semiconductor material in the second semiconductor layer is maintained in the second crystalline state, the second semiconductor layer, A first electrode physically and electrically contacting the first electrode surface of the first semiconductor layer, A second electrode physically and electrically contacting the second electrode surface of the second semiconductor layer, An anti-diffusion layer at the boundary between the first semiconductor layer and the second semiconductor layer, Comprising, the first interface and the second interface being in electrical, physical, and chemical contact with each other at the anti-diffusion layer, the first condition and the second condition being distinctively different, a phase change device (PCD).

12. A phase change device (PCD), A first semiconductor layer made of a first semiconductor material and having a first semiconductor thickness, the first semiconductor layer further having a first interface and a first electrode surface, the first interface and the first electrode surface being on opposite sides of the first semiconductor layer from each other, the first semiconductor material having a property of transitioning between a first amorphous state and a first crystalline state under a first condition of temperature, voltage, or both, the first semiconductor material being separated into a first semiconductor crystal layer having an epitaxial thickness smaller than the first semiconductor thickness and a first amorphous residual layer having a residual thickness, and configured such that a plurality of states of the phase change device (PCD) occur according to the epitaxial thickness in the first semiconductor layer, the first semiconductor layer, A second semiconductor layer made of a second semiconductor material and having a second semiconductor thickness, wherein the second semiconductor layer further has a second interface and a second electrode surface, the second interface and the second electrode surface are on opposite sides of the second semiconductor layer, the first interface and the second interface are in electrical, physical and chemical contact with each other at the boundary, the second semiconductor material has a property of transitioning between a second amorphous state and a second crystalline state under a second condition that is distinguishable from the first condition in terms of temperature, voltage or both, and the second semiconductor layer is configured such that when the first semiconductor layer is transitioned to the first amorphous state at the first semiconductor thickness, the second semiconductor material in the second semiconductor layer is maintained in the second crystalline state, the second semiconductor layer, A first electrode physically and electrically contacting the first electrode surface of the first semiconductor layer, A second electrode physically and electrically contacting the second electrode surface of the second semiconductor layer Comprising, A phase change device (PCD) having a total resistance measured between the first electrode and the second electrode.

13. The PCD according to claim 12, wherein the total resistance decreases as the epitaxial thickness increases.

14. The PCD according to claim 12, having a plurality of total resistance states by changing the epitaxial thickness, and one of the plurality of total resistance states being selected by a set voltage pulse.

15. The PCD according to any one of claims 1 to 14, wherein the first semiconductor material is germanium and the second semiconductor material is silicon.

16. A method of manufacturing a phase change device (PCD), comprising: Depositing a first electrode on an insulator layer; Depositing a first semiconductor layer on the first electrode, wherein the material of the first semiconductor layer has a property of transitioning between a first amorphous state and a first crystalline state under a first condition of temperature, voltage or both, the depositing step, Depositing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer has a property of transitioning between a second amorphous state and a second crystalline state under a second condition of temperature, voltage, or both, which is distinguishable from the first condition, and the depositing step; Crystallizing the first semiconductor layer and the second semiconductor layer; Amorphizing the first semiconductor layer while maintaining the material of the second semiconductor layer in the second crystalline state; A method, wherein the phase change device (PCD) separates the first semiconductor layer into a first semiconductor crystal layer in the first crystalline state and a first semiconductor amorphous layer in the first amorphous state with a set voltage pulse, and is configured to be in one of a plurality of states of the phase change device (PCD) according to the degree of the separation.

17. The method according to claim 16, wherein heating and cooling annealing crystallize the entire first semiconductor layer and the entire second semiconductor layer.

18. The method according to claim 16, wherein the first semiconductor layer is heated to enable the first semiconductor layer to cool during a cooling time period, and during the cooling time period, the first semiconductor crystal layer epitaxially grows to an epitaxial thickness determined by the length of the cooling time period, thereby separating the first semiconductor layer.

19. The method according to claim 18, wherein the resistance state of the PCD is determined by a cooling time period determined by a set voltage pulse.

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