Nitride semiconductor device and method for manufacturing the same

Abstract

To provide a nitride semiconductor device having a high activation rate of a source region.SOLUTION: A nitride semiconductor device 1 comprises: a drift region 12 of a first conductivity type of a nitride semiconductor; a body region 13 of a second conductivity type of the nitride semiconductor provided on the drift region; a source region 16 of the first conductivity type separated from the drift region by the body region; an insulation gate 30 opposed to the body region and located between the drift region and the source region; and a source electrode 24 electrically connected to the body region and the source region. The source region is constituted by a deposited film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a nitride semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 discloses an example of a method for manufacturing a nitride semiconductor device. In this manufacturing method, n-type impurities are ion-implanted into a p-type body region to form an n-type source region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When an n-type source region is formed using ion implantation technology, due to defects formed during ion implantation and the coexistence of p-type impurities (such as magnesium), the activation rate of the n-type source region is low. This specification provides a nitride semiconductor device with a high activation rate of the source region and a method for manufacturing the same.

Means for Solving the Problems

[0005] The nitride semiconductor device (1, 2) disclosed in this specification includes a drift region (12, 112) of a first conductivity type of a nitride semiconductor, a body region (13, 113) of a second conductivity type of a nitride semiconductor provided on the drift region, a source region (16, 116) of the first conductivity type separated from the drift region by the body region, an insulating gate (30, 130) facing the body region located between the drift region and the source region, and a source electrode (24, 124) electrically connected to the body region and the source region. In this nitride semiconductor device, the source region is composed of a deposited film. Therefore, in the source region, problems such as defects during ion implantation and the mixing of second conductivity type impurities in the body region do not occur. The source region can have a high activation rate. Note that the method of forming the deposited film referred to here is not particularly limited, and various deposition techniques (CVD, PVD, etc.) can be used.

[0006] The manufacturing method of the nitride semiconductor device (1, 2) disclosed in this specification includes a step of depositing a body region (13, 113) of a second conductivity type of a nitride semiconductor on a drift region (12, 112) of a first conductivity type of a nitride semiconductor, a step of performing a dehydrogenation annealing treatment to remove hydrogen from the body region, a step of depositing a source region (16, 116) of a first conductivity type on the body region after removing hydrogen from the body region, a step of forming an insulating gate (30, 130) facing the body region located between the drift region and the source region, and a step of forming a source electrode (24, 14) electrically connected to the body region and the source region. According to this manufacturing method, the source region is composed of a deposited film. Therefore, in the source region, problems such as defects during ion implantation and the mixing of second conductivity type impurities in the body region do not occur. The source region can have a high activation rate. Further, according to this manufacturing method, after removing hydrogen from the body region, the source region is deposited. Therefore, hydrogen can be sufficiently removed from the body region, so that the body region can have a high activation rate. According to this manufacturing method, a nitride semiconductor device having the source region and the body region with high activation rates can be manufactured.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] (First Embodiment) As shown in FIG. 1, the nitride semiconductor device 1 according to the first embodiment is a type of semiconductor device called an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10, a drain electrode 22 covering the back surface of the semiconductor layer 10, a source electrode 24 covering the front surface of the semiconductor layer 10, and a trench gate 30 provided in the upper layer portion of the semiconductor layer 10. The semiconductor layer 10 includes an n + -type drain region 11, an n-type drift region 12, a p-type body region 13, a p-type electric field relaxation region 14, a p + -type body contact region 15, an n +It has a source region 16 of a certain type. The n-type impurity contained in the semiconductor layer 10 is not particularly limited, and for example, it may be silicon (Si). The p-type impurity contained in the semiconductor layer 10 is not particularly limited, and for example, it may be magnesium (Mg).

[0009] The drain region 11 is provided in the lower layer portion of the semiconductor layer 10 and contains a high concentration of n-type impurities. The drain region 11 is exposed on the lower surface of the semiconductor layer 10 and is in ohmic contact with the drain electrode 22. As will be described later, the drain region 11 is prepared as an n-type GaN substrate and is also a base substrate for crystal growth of the drift region 12 and the body region 13.

[0010] The drift region 12 is provided on the drain region 11 and is in contact with the upper surface of the drain region 11. The drift region 12 is disposed between the drain region 11 and the body region 13 and separates the drain region 11 and the body region 13. The drift region 12 is in contact with the bottom surface of the trench gate 30 and a part of the lower end of the side surface. The concentration of the n-type impurity in the drift region 12 is lower than the concentration of the n-type impurity in the drain region 11. The drift region 12 is a nitride semiconductor and is not particularly limited, and for example, it may be gallium nitride.

[0011] The body region 13 is provided on the drift region 12 and is in contact with the upper surface of the drift region 12. The body region 13 is disposed between the drift region 12 and the source region 16 and separates the drift region 12 and the source region 16. The body region 13 is in contact with the side surface of the trench gate 30. The body region 13 is a nitride semiconductor and is not particularly limited, and for example, it may be gallium nitride.

[0012] The electric field relaxation region 14 is provided so as to protrude from the body region 13 to the drift region 12, and extends to a position deeper than the bottom surface of the trench gate 30. The electric field relaxation region 14 is arranged away from the trench gate 30 in one direction parallel to the plane direction of the semiconductor layer 10. The p-type impurity concentration of the electric field relaxation region 14 is not particularly limited, but may be, for example, of the same degree as that of the body region 13. The electric field relaxation region 14 is a nitride semiconductor, and is not particularly limited, but may be, for example, gallium nitride.

[0013] The body contact region 15 is provided on the electric field relaxation region 14 and is in contact with the side surface of the body region 13 and the upper surface of the electric field relaxation region 14. The concentration of p-type impurities in the body contact region 15 is higher than the concentration of p-type impurities in the body region 13 and the electric field relaxation region 14. The body contact region 15 is a nitride semiconductor, and is not particularly limited, but may be, for example, gallium nitride. As will be described later, the body contact region 15 is substantially ohmic - contacted with the source region 16 by tunneling phenomenon, and is substantially ohmic - contacted with the source electrode 24 through the source region 16.

[0014] The source region 16 is provided on the body region 13 and the body contact region 15, and is in contact with the upper surfaces of the body region 13 and the body contact region 15. The source region 16 is provided in the upper layer portion of the semiconductor layer 10, is interposed between the body region 13 and the body contact region 15 and the source electrode 24, and separates the body region 13 and the body contact region 15 from the source electrode 24. The source region 16 is in contact with a part of the upper end of the side surface of the trench gate 30. The source region 16 is exposed on the surface of the semiconductor layer 10 and is in ohmic contact with the source electrode 24. The source region 16 is a nitride semiconductor, and although not particularly limited, for example, it may be gallium nitride. Instead of gallium nitride, the source region 16 may be another nitride semiconductor such as indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN). Alternatively, the source region 16 may be another semiconductor material having an electron affinity close to 4.1 eV of gallium nitride, for example, rhombohedral indium tin oxide (rh-ITO) or body-centered cubic indium tin oxide (bcc-ITO).

[0015] The carrier concentration of the source region 16 is 1×10 19 cm -3 or more. Since the carrier concentration of the source region 16 is sufficiently high, the source region 16 and the body contact region 15 are substantially in ohmic contact by the tunneling phenomenon. Even when the source region 16 is indium tin oxide, when the carrier concentration of the source region 16 is sufficiently high, the source region 16 and the body contact region 15 can be substantially in ohmic contact by the tunneling phenomenon as well.

[0016] The trench gate 30 extends from the surface of the semiconductor layer 10 through the source region 16 and the body region 13 to reach the drift region 12, and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 faces the drift region 12, the body region 13, and the source region 16 through the gate insulating film 34.

[0017] Next, the operation of the nitride semiconductor device 1 will be described. When a voltage higher than that of the source electrode 24 is applied to the drain electrode 22 and a voltage higher than the threshold voltage is applied to the gate electrode 32, the nitride semiconductor device 1 turns on. At this time, a channel (inversion layer) is formed in a part of the body region 13 facing the trench gate 30 between the drift region 12 and the source region 16. Electrons injected from the source region 16 move to the drift region 12 through the channel, flow vertically through the drift region 12, and reach the drain region 11. Due to such a flow of electron current, conduction is established between the drain electrode 22 and the source electrode 24, and the nitride semiconductor device 1 turns on. When the voltage applied to the gate electrode 32 is lower than the threshold voltage, the channel disappears and the nitride semiconductor device 1 turns off.

[0018] Next, with reference to FIGS. 2 to 6, a method for manufacturing the nitride semiconductor device 1 will be described. First, as shown in FIG. 2, a drain region 11 which is an n-type GaN substrate is prepared. Next, as shown in FIG. 3, for example, by using metal organic chemical vapor deposition (MOCVD), an n-type GaN drift region 12 and a p-type GaN body region 13 are sequentially grown in crystal form from the upper surface of the drain region 11.

[0019] Next, as shown in FIG. 4, a mask 42 is formed on the upper surface of the body region 13. The mask 42 has an opening such that a part of the surface of the body region 13 is exposed. Next, using ion implantation technology, ions of a p-type impurity (magnesium in this example) are channel implanted through the opening of the mask 42 to form an electric field relaxation region 14 extending so as to protrude from the body region 13 into the drift region 12. Next, using ion implantation technology, ions of a p-type impurity (magnesium in this example) are randomly implanted through the opening of the mask 42 to form a body contact region 15 in the upper layer portion of the body region 13. After the ion implantation is completed, the mask 42 is removed.

[0020] Next, as shown in FIG. 5, a protective film 44 is formed on the upper surfaces of the body region 13 and the body contact region 15. The protective film 44 is also formed on the lower surface of the drain region 11. The protective film 44 is used for the purpose of suppressing the release of nitrogen from the upper surfaces of the body region 13 and the body contact region 15 and the lower surface of the drain region 11 during the dehydrogenation and activation annealing processes described later. The material of the protective film 44 is not particularly limited, and for example, aluminum nitride (AlN) may be used. Next, dehydrogenation and activation annealing processes are performed. The annealing temperature is not particularly limited, and for example, it may be 800 °C or higher. As described above, when the body region 13 is formed using a deposition technique, hydrogen derived from a material (for example, Cp2Mg) for adding magnesium, which is a p-type impurity, is contained in a high concentration in the body region 13, and the activation of magnesium is inhibited by this hydrogen. When the dehydrogenation and activation annealing processes are performed, hydrogen is released from the body region 13. In this example, the hydrogen concentration contained in the body region 13 is reduced to 1×10 18 cm -3 or less by the dehydrogenation and activation annealing processes. Thereby, magnesium contained in the body region 13 can be activated well. After the dehydrogenation and activation annealing processes are completed, the protective film 44 is removed.

[0021] Next, as shown in FIG. 6, for example, using metalorganic chemical vapor deposition, a source region 16 of n-type GaN is grown in crystal form from the upper surfaces of the body region 13 and the body contact region 15. The source region 16 is grown in crystal form so that the carrier concentration becomes 1×10 19 cm -3 or more.

[0022] Next, a trench gate 30 is formed using known manufacturing techniques. Thereafter, a drain electrode 22 is formed on the back surface of the semiconductor layer, and a source electrode 24 is formed on the surface of the semiconductor layer, whereby the nitride semiconductor device 1 shown in FIG. 1 is completed.

[0023] The above manufacturing method of the nitride semiconductor device 1 has at least the following advantages. (1) In the above manufacturing method, the source region 16 is formed by using a deposition technique. Therefore, compared with the case where the source region 16 is formed by using an ion implantation technique, the source region 16 has fewer defects. Thus, the nitride semiconductor device 1 can have a low on-resistance. Also, compared with the case where the source region 16 is formed by using an ion implantation technique, the defects in the body region 13 below the source region 16 are also fewer. For example, the defect density in the body region 13 has decreased to 16 cm -3 or less. Therefore, the nitride semiconductor device 1 has a small trap level density and can suppress threshold voltage variation. (2) In the above manufacturing method, the source region 16 is formed so as to be interposed between the body contact region 15 and the source electrode 24. The body contact region 15 is not in contact with the source electrode 24. In the prior art, in order to make an ohmic contact between the p-type body contact region 15 and the metal source electrode 24, a metal electrode (such as nickel or gold) having a large work function is often interposed. The nitride semiconductor device 1 does not require such a metal electrode. (3) In the above manufacturing method, the source region 16 is formed after performing dehydrogenation and activation annealing processes. Therefore, since the source region 16 does not exist on the surface of the body region 13 during the dehydrogenation and activation annealing processes, hydrogen can be effectively removed from the body region 13. As a result, the body region 13 can have a high activation rate.

[0024] (Second Embodiment) As shown in FIG. 7, the nitride semiconductor device 2 of the second embodiment is a type of semiconductor device called an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 100, a drain electrode 122 covering the lower surface of the semiconductor layer 100, a source electrode 124 covering the upper surface of the semiconductor layer 100, and a planar gate 130 provided on the upper surface of the semiconductor layer 100. The semiconductor layer 100 includes an n + -type drain region 111, an n-type drift region 112, a p-type body region 113, and a p+ type of body contact region 115 and n + type of source region 116, and has. The n-type impurity contained in the semiconductor layer 100 is not particularly limited, but may be, for example, silicon (Si). The p-type impurity contained in the semiconductor layer 100 is not particularly limited, but may be, for example, magnesium (Mg).

[0025] The drain region 111 is provided in the lower layer portion of the semiconductor layer 100 and contains a high concentration of n-type impurities. The drain region 111 is exposed on the lower surface of the semiconductor layer 100 and is in ohmic contact with the drain electrode 122. The drain region 111 is prepared as an n-type GaN substrate, as will be described later, and is also a base substrate for crystal growth of the drift region 112.

[0026] The drift region 112 is provided on the drain region 111 and is in contact with the upper surface of the drain region 111. The drift region 112 is disposed between the drain region 111 and the body region 113 and separates the drain region 111 and the body region 113. The concentration of the n-type impurity in the drift region 112 is lower than the concentration of the n-type impurity in the drain region 111. The drift region 112 is a nitride semiconductor and is not particularly limited, but may be, for example, gallium nitride.

[0027] The drift region 112 has a JFET region 112a sandwiched by the body region 113 in one direction parallel to the plane direction of the semiconductor layer 100. The JFET region 112a extends so as to penetrate the body region 113 from the surface of the semiconductor layer 100. The JFET region 112a is in contact with a part of the bottom surface of the planar gate 130.

[0028] The body region 113 is provided on the drift region 112 and is in contact with the upper surface of the drift region 112. The body region 113 is also disposed adjacent to the JFET region 112a of the drift region 112 and is in contact with the side surface of the JFET region 112a. The body region 13 is disposed between the JFET region 112a of the drift region 112 and the source region 116, separating the JFET region 112a of the drift region 112 from the source region 116. The body region 113 is in contact with a part of the bottom surface of the planar gate 130. The body region 113 is a nitride semiconductor and is not particularly limited, and may be, for example, gallium nitride.

[0029] The body contact region 115 is provided on the body region 113 and is in contact with the upper surface of the body region 113. The concentration of p-type impurities in the body contact region 115 is higher than the concentration of p-type impurities in the body region 113. The body contact region 115 is a nitride semiconductor and is not particularly limited, and may be, for example, gallium nitride. As will be described later, the body contact region 115 is substantially ohmic - contacted with the source region 116 by tunneling phenomenon, and is substantially ohmic - contacted with the source electrode 124 through the source region 116.

[0030] The source region 116 is provided on the body region 113 and the body contact region 115, and is in contact with the upper surfaces of the body region 113 and the body contact region 115. The source region 116 is provided in the surface layer portion of the semiconductor layer 100, is interposed between the body region 113 and the body contact region 115 and the source electrode 124, and separates the body region 113 and the body contact region 115 from the source electrode 124. The source region 116 is in contact with a part of the bottom surface of the planar gate 130. The source region 116 is exposed on the surface of the semiconductor layer 100 and is in ohmic contact with the source electrode 124. The source region 116 is a nitride semiconductor, and although not particularly limited, it may be, for example, gallium nitride. Instead of gallium nitride, the source region 116 may be another nitride semiconductor such as indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN). Alternatively, the source region 116 may be another semiconductor material having an electron affinity close to 4.1 eV of gallium nitride, for example, rhombohedral indium tin oxide (rh-ITO) or body-centered cubic indium tin oxide (bcc-ITO).

[0031] The carrier concentration of the source region 116 is 1×10 19 cm -3 or more. Since the carrier concentration of the source region 116 is sufficiently high, the source region 116 and the body contact region 115 are substantially in ohmic contact due to the tunneling phenomenon. Even when the source region 116 is indium tin oxide, when the carrier concentration of the source region 116 is sufficiently high, the source region 116 and the body contact region 115 can be substantially in ohmic contact due to the tunneling phenomenon.

[0032] The planar gate 130 is provided on the upper surface of the semiconductor layer 100, extends from a part of the source region 116 over the body region 113 to reach the JFET region 112a of the drift region 112, and has a gate electrode 132 and a gate insulating film 134. The gate electrode 132 faces the JFET region 112a of the drift region 112, the body region 113, and the source region 116 through the gate insulating film 134.

[0033] Next, the operation of the nitride semiconductor device 1 will be described. When a voltage higher than the threshold voltage is applied to the gate electrode 132 while a voltage higher than that of the source electrode 124 is applied to the drain electrode 122, the nitride semiconductor device 2 turns on. At this time, a channel (inversion layer) is formed in a part of the body region 113 facing the planar gate 130 between the JFET region 112a of the drift region 112 and the source region 116. Electrons injected from the source region 116 move through the channel to the JFET region 112a of the drift region 112, flow vertically through the drift region 112, and reach the drain region 111. Due to such a flow of electron current, conduction is established between the drain electrode 122 and the source electrode 124, and the nitride semiconductor device 2 turns on. When the voltage applied to the gate electrode 132 is lower than the threshold voltage, the channel disappears and the nitride semiconductor device 2 turns off.

[0034] Next, with reference to FIGS. 8 to 14, a method for manufacturing the nitride semiconductor device 2 will be described. First, as shown in FIG. 8, for example, using metalorganic chemical vapor deposition, the drift region 112 is grown epitaxially on the upper surface of the drain region 111, which is an n-type GaN substrate.

[0035] Next, as shown in FIG. 9, a mask 142 is formed on the upper surface of the drift region 112. The mask 142 has an opening so that a part of the upper surface of the drift region 112 is exposed. Next, using ion implantation technology, ions of a p-type impurity (magnesium in this example) are implanted through the opening of the mask 142 to form the body region 113. The portion of the drift region 112 sandwiched by the body region 113 becomes the JFET region 112a. After the ion implantation is completed, the mask 142 is removed.

[0036] Next, as shown in FIG. 10, a mask 144 is formed on the upper surfaces of the JFET region 112a of the drift region 112 and the body region 113. The mask 144 has an opening so that a part of the upper surface of the body region 113 is exposed. Next, using ion implantation technology, ions of a p-type impurity (magnesium in this example) are implanted through the opening of the mask 144 to form the body contact region 115. After the ion implantation is completed, the mask 144 is removed.

[0037] Next, as shown in FIG. 11, a protective film 146 is formed on the upper surfaces of the JFET region 112a of the drift region 112, the body region 113, and the body contact region 115. The protective film 146 is also formed on the lower surface of the drain region 111. The material of the protective film 146 is not particularly limited, and for example, aluminum nitride (AlN) may be used. Next, an activation annealing process is performed. The annealing temperature is not particularly limited, and for example, it may be 800 °C or higher. After the activation annealing process is completed, the protective film 146 is removed.

[0038] Next, as shown in FIG. 12, using dry etching technology, a part of the body region 113 and the body contact region 115 is removed to form a groove 117 having a depth such that a part of the body contact region 115 remains.

[0039] Next, as shown in FIG. 13, for example, using metalorganic chemical vapor deposition, an n-type GaN source region 116 is crystal-grown so as to fill the groove 117. The source region 116 is also deposited on the upper surfaces of the JFET region 112a of the drift region 112 and the body region 113 in the convex portion sandwiched by the groove 117.

[0040] Next, as shown in FIG. 14, using chemical mechanical polishing (CMP), a part of the source region 116 is removed to expose the JFET region 112a of the drift region 112 and the body region 113 in the convex portion.

[0041] Next, a planar gate 130 is formed using known manufacturing techniques. Thereafter, a drain electrode 122 is formed on the back surface of the semiconductor layer, and a source electrode 124 is formed on the front surface of the semiconductor layer, thereby completing the nitride semiconductor device 2 shown in FIG. 7.

[0042] The manufacturing method of the nitride semiconductor device 2 has at least the following advantages. (1) In the above manufacturing method, the source region 116 is formed by a deposition technique. Therefore, compared with the case where the source region 116 is formed by an ion implantation technique, the source region 116 has fewer defects. Accordingly, the nitride semiconductor device 2 can have a low on-resistance. Also, compared with the case where the source region 116 is formed by an ion implantation technique, the body region 113 below the source region 116 also has fewer defects. For example, the defect density of the body region 113 has decreased to 16 cm -3 or less. Therefore, an increase in leakage current and a decrease in breakdown voltage due to defects are improved. (2) In the above manufacturing method, the source region 116 is formed to be interposed between the body contact region 115 and the source electrode 124. The body contact region 115 is not in contact with the source electrode 124. In the prior art, in order to ohmically contact the p-type body contact region 115 and the metal source electrode 124, a metal electrode having a large work function (such as nickel or gold) is often interposed. The nitride semiconductor device 2 does not require such a metal electrode. (3) In the above manufacturing method, the body region 113 was formed using ion implantation technology. Instead of this example, a groove may be formed in a predetermined region of the drift region 112, and the body region 113 may be formed in the groove using deposition technology. In this case, hydrogen contained in the body region 113 during the deposition of the body region 113 can be removed when the above-described activation annealing treatment is performed. Also, in the above manufacturing method, the source region 116 is formed after the activation annealing treatment. Therefore, in the manufacturing method in which the formation method of the body region 113 is changed to a deposition method, since the source region 116 does not exist on the surface of the body region 113 during the activation annealing treatment, hydrogen can be effectively removed from the body region 113. As a result, the body region 113 can have a high activation rate.

[0043] As described above, specific examples of the present invention have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Also, the technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology illustrated in this specification or the drawings can achieve a plurality of purposes simultaneously, and has technical utility by achieving one of those purposes itself.

Explanation of Reference Numerals

[0044] 1,2: Nitride semiconductor device, 10,110: Semiconductor layer, 11,111: Drain region, 12,112: Drift region, 13,113: Body region, 14: Electric field relaxation region, 15,115: Body contact region, 16,116: Source region, 22,122: Drain electrode, 24,124: Source electrode, 30: Trench-type gate, 32,132: Gate electrode, 34,134: Gate insulating film, 130: Planar-type gate

Claims

1. A nitride semiconductor device (1, 2), comprising: a first conductivity type drift region (12, 112) of a nitride semiconductor; a second conductivity type body region (13, 113) of a nitride semiconductor provided on the drift region; a first conductivity type source region (16, 116) separated from the drift region by the body region; an insulating gate (30, 130) facing the body region located between the drift region and the source region; a source electrode (24, 124) electrically connected to the body region and the source region, wherein the source region is composed of a deposited film, the carrier concentration of the source region is 1×10 19 cm -3 or more, and the source region is indium tin oxide, a nitride semiconductor device.

2. The nitride semiconductor device according to claim 1, wherein the source region is interposed between the body region and the source electrode.

3. The hydrogen concentration in the body region is 1 × 10 18 cm -3 or less. The nitride semiconductor device according to claim 1 or 2.

4. A method for manufacturing a nitride semiconductor device (1, 2), comprising: a step of depositing a second conductivity type body region (13, 113) of a nitride semiconductor on a first conductivity type drift region (12, 112) of a nitride semiconductor; a step of performing a dehydrogenation annealing treatment to remove hydrogen from the body region; a step of depositing a first conductivity type source region (16, 116) on the body region after removing hydrogen from the body region; a step of forming an insulating gate (30, 130) facing the body region located between the drift region and the source region; a step of forming a source electrode (24, 124) electrically connected to the body region and the source region, wherein the carrier concentration of the source region is 1×10 19 cm -3 or more, and the source region is indium tin oxide, a manufacturing method.

5. The manufacturing method according to claim 4, wherein the source region is interposed between the body region and the source electrode.

6. The hydrogen concentration in the body region is 1 × 10 18 cm -3 or less. The manufacturing method according to claim 4 or 5.

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