Silicon Carbide Semiconductor Device and Method for Manufacturing the Same This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on November 17, 2021, with an application number of 202111363503.1 and an invention title of "Silicon Carbide Semiconductor Device and Method for Manufacturing the Same", and all of its contents are incorporated herein by reference. This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on November 17, 2021, with an application number of 202122827400.8 and an invention title of "Silicon Carbide Semiconductor Device", and all of its contents are incorporated herein by reference.

Abstract

The present application discloses a silicon carbide semiconductor device and a method for manufacturing the same, which provide an epitaxial wafer including a semiconductor substrate, a first epitaxial layer disposed on a surface of the semiconductor substrate, a second epitaxial layer disposed on one side of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer disposed on one side of the second epitaxial layer away from the first epitaxial layer. Not only is a gate formed by a trench disposed in the third epitaxial layer, but ions are implanted into the second epitaxial layer based on the trench before the gate is formed, so that a doped region that is inverted from the second epitaxial layer can be formed in the second epitaxial layer, thereby solving the difficult problem that it is difficult to form a deep doped region in a silicon carbide semiconductor power device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a silicon carbide (SiC) semiconductor device and a method for manufacturing the same.

Background Art

[0002] With the continuous development of science and technology, more and more electronic devices have been applied to people's daily lives and work, bringing great convenience to people's daily lives and work and becoming an indispensable and important tool for people today.

[0003] The main component for realizing various functions of an electronic device is an integrated circuit, and a semiconductor device is an important component of the integrated circuit. Since a silicon carbide semiconductor device has excellent characteristics in high-power application fields, it has become the main development direction in the semiconductor field.

[0004] Due to the characteristics of the silicon carbide material, when attempting to achieve doping with a large implantation depth, its lattice is damaged by high-energy ion implantation. Therefore, in the conventional manufacturing method, when fabricating a silicon carbide semiconductor device having a deep doped region, in the manufacturing process of the epitaxial wafer, first, a desired doped region is formed in the previously formed epitaxial layer by etching and ion implantation, and then, it is necessary to form a subsequent epitaxial layer.

Summary of the Invention

[0005] In view of such a situation, the present application provides a silicon carbide semiconductor device and a method for manufacturing the same.

[0006] A method for manufacturing a silicon carbide semiconductor device, comprising:

[0007] A semiconductor substrate, a first epitaxial layer disposed on the surface of the semiconductor substrate, a second epitaxial layer disposed on one side of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer disposed on one side of the second epitaxial layer away from the first epitaxial layer, to provide an epitaxial wafer including:

[0008] A well region, a source region, and a trench are formed in the third epitaxial layer.

[0009] Based on the trench, ion implantation is performed on the second epitaxial layer to form a doped region that is inverted with respect to the second epitaxial layer, and the doped region penetrates the second epitaxial layer.

[0010] A method for manufacturing a silicon carbide semiconductor device, in which a gate is formed in the trench. Preferably, in the above manufacturing method, the second epitaxial layer has an injection target region and a first layer well region surrounding the injection target region.

[0011] A well region, a source region, and a trench are formed in the third epitaxial layer.

[0012] By ion implantation, a second layer well region, a third layer well region, and a source region are sequentially formed in the third epitaxial layer, the second layer well region is located between the first layer well region and the third layer well region, and the source region is located on one side of the third layer well region away from the second layer well region.

[0013] A trench is formed on one side of the third epitaxial layer away from the second epitaxial layer, and the bottom of the trench is located between the second epitaxial layer and the third layer well region.

[0014] Here, both the source region and the third-layer well region are in contact with the sidewall of the trench, and the second-layer well region has a gap from the sidewall of the trench, including the step of.

[0015] Preferably, in the above manufacturing method, the manufacturing method of the epitaxial wafer is

[0016] On the surface of the semiconductor substrate, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially formed epitaxially.

[0017] Here, the doping types of the first epitaxial layer and the third epitaxial layer are the same, and it includes the step of being counter-doped with the second epitaxial layer.

[0018] Preferably, in the above manufacturing method,

[0019] The step of forming a metal source connected to the source region.

[0020] The step of forming a metal drain electrode on one side of the semiconductor substrate away from the first epitaxial layer is further included.

[0021] The present application further provides a silicon carbide semiconductor device manufactured by the above manufacturing method.

[0022] An epitaxial wafer, including a semiconductor substrate, a first epitaxial layer disposed on the surface of the semiconductor substrate, a second epitaxial layer disposed on one side of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer disposed on one side of the second epitaxial layer away from the first epitaxial layer.

[0023] A well region, a source region, and a trench disposed in the third epitaxial layer.

[0024] A doped region that penetrates the second epitaxial layer, wherein the doped region and the second epitaxial layer are counter-doped, and the doped region formed by ion implantation based on the trench,

[0025] and a gate electrode disposed in the trench.

[0026] Preferably, in the silicon carbide semiconductor device, the second epitaxial layer has an implantation target region and a first layer well region surrounding the implantation target region. Inside the third epitaxial layer, there are a second layer well region, a third layer well region, and the source region. The second layer well region is located between the first layer well region and the third layer well region. The source region is located on one side away from the second layer well region of the third layer well region. Both the source region and the third layer well region are in contact with the sidewall of the trench. The second layer well region has a gap with the sidewall of the trench. The trench is located on one side surface of the third epitaxial layer away from the semiconductor substrate. The bottom of the trench is located between the second epitaxial layer and the third layer well region.

[0027] The thickness of the third epitaxial layer is 1 μm or less, and the distance between the bottom of the trench and the first epitaxial layer is less than 1 μm.

[0028] Preferably, in the silicon carbide semiconductor device, in the direction in which the bottom of the trench faces the opening, the width of the trench satisfies a uniform condition.

[0029] Preferably, in the silicon carbide semiconductor device, in the direction in which the bottom of the trench faces the opening, the width of the trench is gradually increasing.

[0030] Preferably, in the silicon carbide semiconductor device, the width of the doped region is less than or equal to the width of the trench.

[0031] Preferably, in the silicon carbide semiconductor device, the doping types of the doped region, the first epitaxial layer, and the third epitaxial layer are the same,

[0032] and the doping concentration of the doped region is higher than the doping concentrations of the first epitaxial layer and the third epitaxial layer.

[0033] As is apparent from the above description, in the silicon carbide semiconductor device and its manufacturing method provided by the technical solution of the present application, the epitaxial wafer includes a semiconductor substrate, a first epitaxial layer provided on the surface of the semiconductor substrate, a second epitaxial layer provided on one side surface of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer provided on one side surface of the second epitaxial layer away from the first epitaxial layer. By forming a gate only by a trench provided in the third epitaxial layer and performing ion implantation on the second epitaxial layer based on the trench before forming the gate, a doped region that is inverted with the second epitaxial layer can be formed in the second epitaxial layer, and the problem that it is difficult for a silicon carbide semiconductor power device to form a deep doped region can be solved.

Brief Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings that need to be used in the following description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are only the embodiments of the present application, and those skilled in the art can also obtain other drawings based on the provided drawings without creative efforts.

[0035] The structures, ratios, sizes, etc. shown in the drawings of this specification are merely references to the content disclosed in this specification, and for those skilled in the art, they are not for limiting the implementable limiting conditions of this application. Therefore, they have no substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size will not affect the effects provided by this application and the achievable objectives, and all shall fall within the scope covered by the technical content disclosed in this application.

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Embodiment for Carrying out the Invention

[0036] Hereinafter, with reference to the drawings in the embodiments of the present application, the embodiments in the present application will be clearly and completely described. It is clear that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope protected by the present application.

[0037] Due to its excellent properties, the SiC material has a high output and a strong attractive force, and has become one of the suitable materials for high-performance power MOSFETs. The SiC vertical power MOSFET device mainly includes a lateral double-diffused DMOSFET and a UMOSFET with a vertical gate trench structure.

[0038] As shown in FIG. 1, FIG. 1 includes an n+ (n-type high-concentration doped) base 2, an n- (n-type low-concentration doped) drift region 3 installed on the surface of the base 2, a p-type well region 4 located in the drift region 3, and a source region 5 located in the p-type well region. The source region 5 includes an n+ doped region 51 and a p+ (p-type high-concentration doped) doped region 52, and is a structural schematic diagram of a DMOSFET. A gate electrode layer 7 is installed on the surface of the drift region 3, and a gate electrode 8 is provided on the surface of the gate dielectric layer 7. The substrate 2 has a drain electrode 1 on one side surface away from the drift region 3.

[0039] The DMOSFET structure adopts a planar diffusion technology, uses a refractory material such as polysilicon gate as a mask, and defines a p-base region and an n+ source region at the edge of the polysilicon gate. The name of DMOS is derived from such a double-diffusion process. The surface channel region is formed by the lateral diffusion difference between the p-type base region and the n+ source region.

[0040] As shown in FIG. 2, FIG. 2 is a schematic structural diagram of a UMOSFET. The difference from the structure shown in FIG. 1 is that a U-shaped groove is provided in the UMOSFET, the surface of the U-shaped groove is covered with a gate dielectric layer 7, and the gate electrode 8 is filled in the U-shaped groove. The UMOSFET with a vertical gate recess structure is derived from a U-shaped trench structure. This U-shaped trench structure is formed in the gate region by reactive ion etching. The U-shaped trench structure has a high channel density (the channel density is defined as the active region channel width), whereby the on-resistance of the device is significantly reduced.

[0041] Planar SiC MOSFETs have been studied in the industry for many years, and some manufacturers have already launched commercial products earlier. Regarding the general lateral DMOSFET structure, the progress of modern technology has reached the level where the MOS cell size cannot be reduced to reduce the on-resistance. Mainly due to the limitation of the neck area resistance of the JFET, even if smaller photolithography dimensions are adopted, the on-resistance per unit area is difficult to decrease to 2 2 mΩ-cm, because the trench structure can effectively solve this problem. As shown in FIG. 2, the U-shaped trench structure adopts trench etching technology in each process of the memory storage capacitor, changes the conductive channel from horizontal to vertical, eliminates the neck resistance of the JFET compared with the normal structure, greatly increases the cell density, and improves the current handling ability of the power semiconductor.

[0042] However, SiC UMOSFETs still have some problems in the actual process manufacturing and application.

[0043] 1) Due to the high electric field in the SiC drift region, the electric field in the gate dielectric layer becomes high. As this problem progresses at the trench corner, the gate dielectric layer is quickly broken down at high drain voltages, resulting in poor electrostatic effect against harsh environments and poor high-voltage spike resistance in the circuit.

[0044] 2) Since SiC power MOSFETs are mainly applied in the high-voltage, high-frequency, and high-current regions, the parasitic parameters in the circuit generate spike-like glitches during the high-frequency switching process. As shown in Figure 3, Figure 3 is a waveform diagram of the voltage overshoot and oscillation phenomenon at the switching instant of the MOSFET. Based on Figure 3, the instantaneous overvoltage in the current path of the device increases the loss during the switching process, or a large surge voltage is formed due to changes such as in the power load. Therefore, the surge voltage tolerance and overvoltage protection of the MOSFET are also very important.

[0045] Conventional MOSFET devices themselves do not have the surge voltage self-suppression ability and overvoltage protection ability. Therefore, in normal applications, it is necessary to design complex snubber circuits, surge voltage suppression circuits, and overvoltage protection circuits. Such external matching suppression and overvoltage protection circuits often have a time delay. The high-frequency spike voltage surge in the actual switching process is still received by the device itself, which may cause breakdown failures in the device channel region, and the gradual failure of the gate structure and the electrode ohmic contact region, leading to reliability problems of the device.

[0046] 3) The ion implantation depth is limited, and many needle-exchangeable trench gate protection structures and surge-resistant designs are difficult in the process. Generally, the depth of the trench for forming the gate electrode is 1 μm - 2 μm or more. To protect the gate structure in the trench, the actual manufacturing process of the embedded protection structure cannot be completed directly by ion implantation because in the silicon carbide process, it is difficult for the ion implantation depth to exceed 1 μm. The prior art generally first forms a desired doped region in the previously formed epitaxial layer by etching and ion implantation, and then forms a P-type epitaxial layer with a specific structure in two layers. The manufacturing process is complex and the manufacturing cost is high.

[0047] To more clearly understand the above objects, features, and advantages of the present application, the present application will be described in more detail below with reference to the drawings and specific embodiments.

[0048] As shown in FIGS. 4 to 10, FIGS. 4 to 10 are process flow diagrams of a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present application, and the manufacturing method includes the following steps.

[0049] Step S11: As shown in FIG. 4, provide an epitaxial wafer including a semiconductor substrate 10, a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10, a second epitaxial layer 12 disposed on one side surface of the first epitaxial layer 11 away from the semiconductor substrate 10, and a third epitaxial layer 13 disposed on one side surface of the second epitaxial layer 12 away from the first epitaxial layer 11.

[0050] Here, the epitaxial layer is a silicon carbide epitaxial wafer, and the semiconductor substrate 10 and each epitaxial layer on its surface are all made of silicon carbide material.

[0051] Step S12: As shown in FIGS. 5 to 8, form a well region, a source region 15 and a trench 20 in the third epitaxial layer 13.

[0052] Step S13: As shown in FIG. 9, based on the trench 20, perform ion implantation on the second epitaxial layer 12 to form a doped region 17 of the opposite type to the second epitaxial layer 12, and the doped region 17 penetrates the second epitaxial layer 12.

[0053] Step S14: As shown in FIG. 10, form a gate electrode 18 in the trench 20.

[0054] Here, only the cell structure of the semiconductor device is shown in FIG. 10. The semiconductor device may be a silicon carbide MOSFET device. In an actual product, the semiconductor device may have a plurality of cell structures. The number of cells and the layout method can be set as required, and the embodiments of the present application do not specifically limit this.

[0055] In the manufacturing method according to the embodiment of the present application, in the manufacturing method of the epitaxial wafer, the first epitaxial layer 11, the second epitaxial layer 12, and the third epitaxial layer 13 are sequentially formed epitaxially on the surface of the semiconductor substrate 10. Here, the doping types of the first epitaxial layer 11 and the third epitaxial layer 13 are the same, and are counter-doped with the second epitaxial layer 12.

[0056] The semiconductor substrate 10 can be provided as an n+-type doped silicon carbide substrate. Both the first epitaxial layer 11 and the third epitaxial layer 13 are n-type doped silicon carbide epitaxial layers, and the second epitaxial layer 12 is a p-type doped silicon carbide epitaxial layer. If so, the p-type doped second epitaxial layer 12 is an embedded layer. By skillfully adopting an epitaxial wafer having the embedded layer and performing ion implantation using the trench 20 required for the gate electrode 8 to form the doped region 17, the shielding of the trench gate structure and the difficulty of the implantation process of the silicon carbide material are solved. Further, the doped region 17 can form a JFET structure adjustable in the device current path, automatically adjust the device resistance and the self-locking protection effect, and can also have a small device unit cell size.

[0057] In the semiconductor device, the well region structure includes a first layer well region 141, a second layer well region 142, and a third layer well region 143. The second epitaxial layer 12 has an implantation target region and a first layer well region 141 surrounding the implantation target region, and the implantation target region is used to form the doped region 17.

[0058] In step S12, a well region, a source region 15, and a trench 20 are formed in the third epitaxial layer 13, including the following steps.

[0059] First, as shown in FIGS. 5 to 7, by ion implantation, a second-layer well region 142, a third-layer well region 143, and a source region 15 are sequentially formed in the third epitaxial layer 13. The second-layer well region 142 is located between the first-layer well region 141 and the third-layer well region 143, and the source region 15 is located on one side of the third-layer well region 143 away from the second-layer well region 142.

[0060] Specifically, as shown in FIG. 5, ion implantation is performed based on the mask layer 01 to form a second-layer well region 142 in the third epitaxial layer 13. The second-layer well region 142 surrounds the non-implanted region. A desired non-implanted region is formed based on the patterned mask layer 01. The vertical projections of the trench 20 and the doped region 17 are both within the non-implanted region and have a pitch with the non-implanted region in a direction parallel to the epitaxial wafer (i.e., the horizontal direction in FIGS. 5 to 8). Further, as shown in FIG. 6, again by ion implantation, a third-layer well region 143 is formed on the second-layer well region 142, and the third-layer well region 143 covers the second-layer well region 142 and the non-implanted region surrounded thereby. Further, as shown in FIG. 7, again by ion implantation, a source region 15 is formed on the third-layer well region 143.

[0061] Next, as shown in FIG. 8, the trench 20 is formed on one side surface of the third epitaxial layer 13 away from the second epitaxial layer 12, and the bottom of the trench 20 is located between the second epitaxial layer 12 and the third-layer well region 143.

[0062] Here, both the source region 15 and the third-layer well region 143 are in contact with the sidewall of the trench 20. When forming the source region 15 by ion implantation, since the ion implantation region covers the region for forming the trench 20, after the trench is formed later, the source region 15 that has not been removed can be directly brought into contact with the sidewall of the trench 20. Similarly, when forming the third-layer well region 143 by ion implantation, since the ion implantation region covers the region for forming the trench 20, after the trench is subsequently formed, the third-layer well region 143 that is not removed can be directly brought into contact with the sidewall of the trench 20.

[0063] The second-layer well region 142 has a spacing from the sidewall of the trench 20. The size of the non-implanted region surrounded by the second-layer well region 142 is larger than the size of the trench 20, and the vertical projection of the trench 20 is located within the non-implanted region and has a spacing from the non-implanted region, that is, the second-layer well region 142 and the sidewall of the trench 20 do not contact each other and a spacing can be provided therebetween.

[0064] As shown in FIG. 10, the manufacturing method includes

[0065] a step of forming a metal source 21 connected to the source region 15,

[0066] a step of forming a metal drain 19 on one side surface of the semiconductor substrate 10 away from the first epitaxial layer 11.

[0067] The source region 15 includes a first region 151 and a second region 152 having opposite doping types, and the source region 15 contacts both the first region 151 and the second region 152. The first region 151 may be an n+-type doped region, and the second region 152 may be a p+-type doped region.

[0068] In the silicon carbide semiconductor device formed by the manufacturing method according to the embodiment of the present application, the well region structure includes three layers, namely the first layer well region 141, the second layer well region 142, and the third layer well region 143. The uppermost third layer well region 143 is located on both the left and right sides of the trench 20 and is in contact with the sidewalls of the trench 20. The middle layer second layer well region 142 includes two parts located on both the left and right sides of the trench 20 and does not contact the sidewalls of the trench 20. The lowermost first layer well region 141 is located below the trench 20 and does not contact the trench 20.

[0069] The distance between the two left and right parts of the second layer well region 142 and the vertical central axis of the cell structure is greater than the distance between the left and right side parts of the first layer well region 141 and the vertical central axis of the cell structure. Specifically, the axis in the vertical direction of the cell structure is the central axis of the trench 20. As shown by the dotted line in FIG. 10, with respect to the second layer well region 142, the first layer well region 141 is closer to the central axis.

[0070] A specific JFET structure can be formed on the current path between the source and the drain by the doping region 17, and the on characteristics of the JFET structure are optimized by the pattern design, ion implantation concentration, and pattern profile of the doping region 17, and the performance of the semiconductor device can be improved.

[0071] The technical solution of the present application skillfully involves the second epitaxial layer 12 and the doping region 17 penetrating the second epitaxial layer 12 in the epitaxial wafer, thereby solving the problems of shielding the gate oxide structure of the SiC trench MOSFET and the deep implantation process in the silicon carbide material. At the same time, the doping region 17 can introduce a JFET structure that can be modulated by ion implantation into the current path of the device, automatically adjusting the on-resistance and self-locking protection effect of the device, and at the same time, it can also maintain a small device unit cell size.

[0072] As can be seen from the above description, the silicon carbide semiconductor device formed based on the manufacturing method according to the embodiments of the present application has at least the following beneficial effects.

[0073] One JFET structure can be introduced into the current path of the cell structure of the silicon carbide semiconductor device, automatically adjusting the on-resistance of the device and the self-lock protection effect, and capable of maintaining a small device unit cell size. Moreover, the on-characteristics of the JFET structure are optimized by the pattern design, ion implantation concentration, and pattern profile of the doping region 17, with flexible design and process and good manufacturability.

[0074] Inject an epitaxial wafer having an embedded layer (the second epitaxial layer 12) and the JFET structure modulated by the doping region 17, which can automatically expand the depletion regions on both sides at a large surge voltage to increase the on-resistance of the JFET structure, corresponding to one buffer circuit structure to self-suppress the spike of the surge. When the surge voltage is too large, the depletion regions on both sides expand and overlap with each other to achieve a blocking effect, protecting the gate dielectric layer on the inner trench surface, and achieving a certain spike voltage overvoltage protection effect.

[0075] When introduced into the JFET structure, although a certain on-resistance increases, there are switching buffer and self-suppression effects of the surge voltage.

[0076] The silicon carbide semiconductor device can increase the self-suppression resistance of the device against surge voltage and overvoltage, and avoid damage to the device and reduction in reliability due to the delay in the actual operation of the overvoltage protection circuit and overcurrent protection circuit.

[0077] At the same time, it also has a buffering effect on the spike jitter in the switching process of the circuit, reduces the switching loss, reduces the snubber circuit and the structure of the snubber circuit in the circuit design, reduces discrete components, reduces costs, reduces the actual module volume, and improves reliability.

[0078] Based on the above embodiments, another embodiment of the present application further provides a silicon carbide semiconductor device, and the silicon carbide semiconductor device can be manufactured by using the manufacturing method described in the above embodiments. Its structure is as shown in FIG. 10,

[0079] an epitaxial wafer, wherein the epitaxial wafer includes a semiconductor substrate 10, a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10, a second epitaxial layer 12 disposed on a side surface of the first epitaxial layer 11 away from the semiconductor substrate 10, and a third epitaxial layer 13 disposed on a side surface of the second epitaxial layer 12 away from the first epitaxial layer 11,

[0080] a well region, a source region 15 and a trench disposed in the third epitaxial layer,

[0081] a doped region 17 penetrating through the second epitaxial layer 12, wherein the doped region 17 and the second epitaxial layer are counter-doped, and the doped region 17 formed by ion implantation based on the trench,

[0082] and a gate electrode 18 disposed in the trench. The gate electrode 18 includes a filling medium in which the trench is embedded and a metal gate located on its surface. The surface of the trench has a gate dielectric layer. After forming the gate dielectric layer, the gate electrode 18 is formed in the trench. The filling medium may be polysilicon or the like. Before forming the gate dielectric layer in the trench, the doped region 17 is formed.

[0083] Here, the second epitaxial layer 12 has an implantation target region and a first layer well region 141 surrounding the implantation target region. In the third epitaxial layer 13, there are a second layer well region 142, a third layer well region 143, and the source region 15. The second layer well region 142 is located between the first layer well region 141 and the third layer well region 143. The source region 15 is located on one side of the third layer well region 143 away from the second layer well region 142. Both the source region 15 and the third layer well region 143 are in contact with the sidewall of the trench. The bottom of the trench is located between the second epitaxial layer 12 and the third layer well region 143. The second layer well region 142 is located on both sides of the trench and has a spacing from the sidewall of the trench.

[0084] In the silicon carbide semiconductor device, the thickness of the third epitaxial layer 13 is 1 μm or less. In this way, the ion implantation depths of both the second layer well region 142 and the third layer well region 143 do not exceed 1 μm, and the second layer well region 142 and the third layer well region 143 can be formed in the third epitaxial layer 13 of the silicon carbide material by ion implantation without causing lattice damage.

[0085] In the embodiment of the present application, since the distance between the bottom of the trench and the first epitaxial layer 11 is less than 1 μm, when forming the doped region 17 by ion implantation based on the trench, the ion implantation depth of the doped region 17 can be made less than 1 μm, and the doped region 17 can be formed in the second epitaxial layer 12 of the silicon carbide material by ion implantation without causing lattice damage. The doped region 17 and the bottom of the trench have a non-zero pitch.

[0086] Optionally, in the direction in which the bottom of the trench faces the opening (the direction from bottom to top in FIG. 10), the width of the trench satisfies a uniform condition, that is, the width of the trench is the same or substantially the same in this direction, that is, the trench is a rectangular trench. The general second epitaxial layer 12 is an epitaxial layer with a uniform thickness, and is arranged so that the width of the trench satisfies the uniform condition, and it is easy to form a doped region 17 with a uniform width in the said direction.

[0087] In other forms, as shown in FIG. 11, the structure of the electronic device is a schematic structural diagram of a silicon carbide semiconductor device according to an embodiment of the present application. Its form is different from the structure shown in FIG. 10. In the direction in which the bottom of the trench faces the opening, the width of the trench gradually increases, that is, the trench is a V-shaped trench or an inverted trapezoidal trench. If it is a V-shaped trench, the doped region 17 has a V-shaped structure. If it is an inverted trapezoidal trench, when the ion implantation window is larger than the trench bottom, the doped region has an inverted trapezoidal structure as shown in FIG. 11. If the ion implantation window is not larger than the trench bottom, the doped region has a rectangular structure.

[0088] In the embodiment of the present application, since the width of the doped region 17 is not larger than the width of the trench, the doped region 17 can be formed by ion implantation based on the trench, reducing the depth of ion implantation, and the doping types of the doped region 17, the first epitaxial layer 11, and the third epitaxial layer 13 are the same.

[0089] The silicon carbide semiconductor device is an NMOS. The semiconductor substrate 10 is an n+-type substrate. Both the first epitaxial layer 11 and the third epitaxial layer 13 are n--type doping, the second epitaxial layer 12 is p--type doping, and the doped region 17 is n-type doping. In the embodiments of the present application, the magnitude relationship of the doping concentrations is n+>n>n--, p+>p>p--. n--, n, and n+ are homodoping and are all doping of the first type. p--, p, and p+ are homodoping and are all doping of the second type. The doping of the first type and the doping of the second type are counterdoping.

[0090] Obviously, the silicon carbide semiconductor device may also be a PMOS. The doping type can be set as needed to form an NMOS or a PMOS.

[0091] The doping concentration of the doped region 17 is higher than the doping concentrations of the first epitaxial layer 11 and the third epitaxial layer 13. The doped region 17 is n+-type doping.

[0092] As shown in FIG. 12, FIG. 12 is a schematic diagram of the main current path at the turn-on instant of the silicon carbide semiconductor device shown in FIG. 10. There is a current path between the source and the drain. The curve of the middle broken line shown in FIG. 12 indicates the circuit path, and the current passes through the JFET structure formed based on the doped region 17. When the current changes rapidly, a high-frequency spike voltage is generated in the circuit. At the same time, since the voltage in the current path changes rapidly, the depletion region of the JFET structure (the region between the two dotted curves on the left and right in FIG. 12) corresponds to different voltage changes and expands or contracts rapidly. In this case, the JFET structure is equivalent to a parallel structure of one variable resistor R and one junction capacitance C. As shown in FIG. 13, FIG. 13 is a schematic diagram of the equivalent parasitic parameters of the silicon carbide semiconductor device shown in FIG. 12.

[0093] By means of specific circuit applications and device electrical model simulations, select and optimize the appropriate thickness d and doping concentration of the second epitaxial layer 12, as well as the pattern design, concentration, and pattern profile design of the ion implantation structure of the doped region 17, so as to obtain appropriate parasitic parameter values (desired variable resistance R and one junction capacitance C). When actually applied to different switching frequency circuit modules, it can achieve an effective voltage spike suppression effect and at the same time reduce the turn-on loss.

[0094] In this embodiment of the present application, the silicon carbide semiconductor device is described with a single cell structure. Obviously, when manufacturing the semiconductor device, a plurality of cell structures are simultaneously fabricated based on the wafer-level process, and then the silicon carbide semiconductor device is formed, and the silicon carbide semiconductor device has a plurality of cell structures.

[0095] As shown in FIG. 14, FIG. 14 is a layout diagram of the trench design and the ion implantation area of the doped region of the silicon carbide semiconductor device according to the embodiment of the present application. The implantation window of the doped region 17 is located within the trench 20, and the channel characteristics of the JFET structure can be adjusted by the pattern design, ion implantation concentration, and pattern profile design of the doped region 17. The implantation window area of the doped region 17 may be less than or equal to the area of the trench 20.

[0096] Each embodiment in this specification is described by adopting a progressive, parallel, or forward and parallel combination method. Each embodiment focuses on explaining the differences from other embodiments, and the same or similar parts between each embodiment may be referred to each other.

[0097] In the description of the present application, the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is merely for simplifying the description and explanation of the present application, and does not indicate or imply that the recited device or component has a specific orientation, nor that it must be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present application. When one component is considered to "connect" to another component, it may be directly connected to another component, or there may be components installed in between simultaneously.

[0098] In this specification, relational terms such as first and second are merely for distinguishing one entity or operation from another entity or operation, and do not necessarily require or imply that there is any actual relationship or order between these entities or operations. Further, the term "comprising", "containing" or any other variation thereof is intended to cover non-exclusive inclusion, whereby an article or facility containing a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such article or facility. Without more limitations, the element defined by the phrase "comprising one..." does not exclude the presence of further identical elements in the article or facility containing the above elements.

[0099] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to these embodiments shown herein, but conforms to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, comprising: providing an epitaxial wafer including a semiconductor substrate, a first epitaxial layer disposed on a surface of the semiconductor substrate, a second epitaxial layer disposed on one side surface of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer disposed on one side surface of the second epitaxial layer away from the first epitaxial layer; forming a well region, a source region, and a trench in the third epitaxial layer; performing ion implantation on the second epitaxial layer based on the trench to form a doped region that is inverted with the second epitaxial layer, and the doped region penetrates the second epitaxial layer; forming a gate in the trench, wherein the method for manufacturing a silicon carbide semiconductor device is characterized by the above.

2. The second epitaxial layer has an implantation target region and a first layer well region surrounding the implantation target region; a well region, a source region, and a trench are formed in the third epitaxial layer; by ion implantation, a second layer well region, a third layer well region, and a source region are sequentially formed in the third epitaxial layer, the second layer well region is located between the first layer well region and the third layer well region, and the source region is located on one side of the third layer well region away from the second layer well region; forming a trench on one side surface of the third epitaxial layer away from the second epitaxial layer, and a bottom of the trench is located between the second epitaxial layer and the third layer well region; wherein the source region and the third layer well region both contact a sidewall of the trench, and the second layer well region has a gap from the sidewall of the trench, and the method for manufacturing a silicon carbide semiconductor device according to claim 1 is characterized by including the above steps.

3. The method for manufacturing the epitaxial wafer includes: sequentially and epitaxially forming the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer on a surface of the semiconductor substrate; wherein a doping type of the first epitaxial layer and the third epitaxial layer is the same, and the second epitaxial layer is counter-doped with the first epitaxial layer and the third epitaxial layer, and the method for manufacturing a silicon carbide semiconductor device according to claim 1 is characterized by including the above step.

4. A step of forming a metal source connected to the source region; A step of forming a metal drain electrode on one side surface of the semiconductor substrate away from the first epitaxial layer, further comprising the method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3.

5. An epitaxial wafer, A semiconductor substrate, a first epitaxial layer provided on the surface of the semiconductor substrate, a second epitaxial layer provided on one side surface of the first epitaxial layer away from the semiconductor substrate, and a third epitaxial layer provided on one side surface of the second epitaxial layer away from the first epitaxial layer, an epitaxial wafer including; A well region, a source region, and a trench provided in the third epitaxial layer; A doped region penetrating the second epitaxial layer, wherein the doped region and the second epitaxial layer are counter-doped, and the doped region formed by ion implantation based on the trench; A gate electrode provided in the trench, further comprising the method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4.

6. The second epitaxial layer has an injection target region and a first layer well region surrounding the injection target region. Inside the third epitaxial layer, there are a second layer well region, a third layer well region, and the source region. The second layer well region is located between the first layer well region and the third layer well region. The source region is located on one side of the third layer well region away from the second layer well region. Both the source region and the third layer well region are in contact with the sidewall of the trench. The second layer well region has a gap from the sidewall of the trench. The trench is located on one side surface of the third epitaxial layer away from the semiconductor substrate. The bottom of the trench is located between the second epitaxial layer and the third layer well region. The thickness of the third epitaxial layer is 1 μm or less, and the distance between the bottom of the trench and the first epitaxial layer is less than 1 μm, further comprising the method for manufacturing a silicon carbide semiconductor device according to claim 5.

7. The doping types of the doped region, the first epitaxial layer, and the third epitaxial layer are the same. The manufacturing method of the silicon carbide semiconductor device according to claim 5, characterized in that the doping concentration of the doped region is higher than the doping concentrations of the first epitaxial layer and the third epitaxial layer.

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