Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a reverse recovery loss.SOLUTION: A semiconductor device 1 includes: a semiconductor layer 2 that includes a first principal surface 3 and a second principal surface 4; an IGBT region 8 that includes an FET structure 35 including a body region 45, an emitter region 46, a gate insulating layer 40, and a gate electrode layer 41, and a collector region 34; a diode region 9 that includes an anode region 62 and a cathode region 61; a boundary region 10 that includes a well region 71 formed on a surface layer part of the first principal surface 3 of the semiconductor layer 2, in a region between the IGBT region 8 and the diode region 9; an emitter terminal electrode 13 electrically connected with the emitter region 46, the anode region 62, and the well region 71; and a collector terminal electrode 32 electrically connected with the collector region 34 and the cathode region 61.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses an RC-IGBT (Reverse Conducting - Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT and a diode formed in a common semiconductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, carriers accumulate in a boundary region between an IGBT region and a diode region in a semiconductor layer during the reverse recovery operation of the diode. Therefore, the reverse recovery loss increases due to an increase in the reverse recovery current.

[0005] One embodiment of the present invention provides a semiconductor device capable of reducing the reverse recovery loss.

Means for Solving the Problems

[0006] One embodiment of the present invention includes a semiconductor layer of a first conductivity type including a first main surface on one side and a second main surface on the other side, a body region of a second conductivity type formed in a surface layer portion of the first main surface, an emitter region of the first conductivity type formed in a surface layer portion of the body region, and a gate electrode facing the body region and the emitter region via a gate insulating layer, an IGBT region including a collector region of the second conductivity type formed in a surface layer portion of the second main surface, a diode region including a second impurity region of the second conductivity type formed in a surface layer portion of the first main surface and a first impurity region of the first conductivity type formed in a surface layer portion of the second main surface, a boundary region including a well region of the second conductivity type formed in a surface layer portion of the first main surface in a region between the IGBT region and the diode region, and a first main surface electrode electrically connected to the emitter region, the first impurity region, and the well region on the first main surface.

[0007] According to this semiconductor device, carriers existing in the boundary region can be quickly discharged by the well region during the reverse recovery operation of the diode. As a result, the retention of carriers in the boundary region can be suppressed, so that the reverse recovery current can be suppressed. Consequently, the reverse recovery loss can be reduced.

[0008] The above-mentioned, or further other objects, features, and effects in the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0009]

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DETAILED DESCRIPTION OF THE INVENTION

[0010] FIG. 1 is a top view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is an enlarged view of a region II shown in FIG. 1. FIG. 3 is an enlarged view of a region III shown in FIG. 2. FIG. 4 is an enlarged view of a region IV shown in FIG. 3. FIG. 5 is an enlarged view of a region V shown in FIG. 3. FIG. 6 is an enlarged view of a region VI shown in FIG. 3.

[0011] The semiconductor device 1 is an electronic component having an RC-IGBT (Reverse Conducting - Insulated Gate Bipolar Transistor) that integrally includes an IGBT and a diode.

[0012] Referring to FIGS. 1 to 6, the semiconductor device 1 includes a chip-shaped semiconductor layer 2. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

[0013] The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z. The side surfaces 5A and 5C extend along the first direction X and face each other in a second direction Y intersecting the first direction X. The side surfaces 5B and 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0014] The semiconductor device 1 includes an active region 6 and an outer region 7 formed in the semiconductor layer 2. The active region 6 and the outer region 7 are formed on the first main surface 3. The active region 6 is a region including an RC-IGBT.

[0015] The active region 6 is formed at the center of the semiconductor layer 2 at an interval from the side surfaces 5A to 5D of the semiconductor layer 2 in an inner region in a plan view. The active region 6 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0016] The outer region 7 is a region outside the active region 6. The outer region 7 extends in a band shape along the periphery of the active region 6 in a plan view. More specifically, the outer region 7 is formed in an endless shape (square ring shape) surrounding the active region 6 in a plan view.

[0017] The active region 6 includes an IGBT region 8, a diode region 9, a boundary region 10, and a sensor region 11. The IGBT region 8 is a region including an IGBT. The diode region 9 is a region including a diode. The boundary region 10 is a region between the IGBT region 8 and the diode region 9. The sensor region 11 is a region including a temperature sensing device.

[0018] A plurality of IGBT regions 8 are formed at intervals in the first direction X and the second direction Y. In this form, the plurality of IGBT regions 8 are arranged in a matrix in a plan view. A plurality of diode regions 9 are formed at intervals in the first direction X and the second direction Y. In this form, the plurality of diode regions 9 are arranged in a matrix in a plan view. More specifically, the plurality of diode regions 9 are respectively formed in regions between two adjacent IGBT regions 8 in the first direction X.

[0019] The boundary region 10 is interposed in a region between the IGBT region 8 and the diode region 9. A plurality of boundary regions 10 are formed at intervals along the first direction X and the second direction Y. In this form, the plurality of boundary regions 10 are arranged in a matrix in a plan view.

[0020] The active region 6 includes an RC-IGBT array 12 (device region). The RC-IGBT array 12 includes an IGBT region 8, a diode region 9, and a boundary region 10 arranged along the first direction X. More specifically, the RC-IGBT array 12 has a loop array that repeatedly includes an IGBT region 8, a boundary region 10, a diode region 9, a boundary region 10, an IGBT region 8, a boundary region 10, a diode region 9... arranged in a row along the first direction X.

[0021] The active region 6 includes a plurality (six in this form) of RC-IGBT arrays 12 formed at intervals in the second direction Y. The RC-IGBT array 12 has a starting point located on the side surface 5B side and an ending point located on the side surface 5D side.

[0022] The starting point of the RC-IGBT array 12 is formed by the IGBT region 8 in this form. The starting point of the RC-IGBT array 12 is not limited to the IGBT region 8. The starting point of the RC-IGBT array 12 may be the diode region 9 or the boundary region 10. The ending point of the RC-IGBT array 12 is formed by the IGBT region 8 in this form. The ending point of the RC-IGBT array 12 is not limited to the IGBT region 8. The ending point of the RC-IGBT array 12 may be the diode region 9 or the boundary region 10.

[0023] The width WI of the IGBT region 8 may be 10 μm or more and 1000 μm or less. The width WI is the width of the IGBT region 8 in the first direction X. The width WI may be 10 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less.

[0024] The width WD of the diode region 9 may be 10 μm or more and 1000 μm or less. The width WD is the width of the diode region 9 in the first direction X. The width WD may be 10 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The width WD is preferably 100 μm or more. The width WD is more preferably 200 μm or more.

[0025] The width WB of the boundary region 10 may be 1 μm or more and 100 μm or less. The width WB is the width of the boundary region 10 in the first direction X. The width WB may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, or 90 μm or more and 100 μm or less.

[0026] The sensor region 11 is formed in the region between two RC-IGBT arrays 12 adjacent to each other in the second direction Y. In this form, the sensor region 11 is formed in the central part of the active region 6. That is, the temperature-sensitive device is formed in the region between two adjacent RC-IGBT arrays 12 at the central part of the active region 6. The central part of the active region 6 is likely to have an increase in temperature. By disposing the temperature-sensitive device at the central part of the active region 6, the temperature of the active region 6 can be appropriately detected.

[0027] The semiconductor device 1 includes an emitter terminal electrode 13 (see the broken line part in FIG. 1) formed on the first main surface 3 in the active region 6. The emitter terminal electrode 13 transmits an emitter signal to the active region 6 (IGBT region 8). The emitter signal may be a reference voltage (for example, a ground voltage).

[0028] In the outer region 7, a plurality (five in this embodiment) of terminal electrodes 14, 15, 16, 17, 18 are formed on the first main surface 3. The plurality of terminal electrodes 14 to 18 are respectively arranged in the region on the side surface 5D side in a plan view. The plurality of terminal electrodes 14 to 18 are arranged at intervals along the side surface 5D. The plurality of terminal electrodes 14 to 18 are formed in a rectangular shape in a plan view.

[0029] The plurality of terminal electrodes 14 to 18 include a gate terminal electrode 14, a first sense terminal electrode 15, a second sense terminal electrode 16, a current detection terminal electrode 17, and an open terminal electrode 18. The gate terminal electrode 14 transmits a gate signal to the active region 6 (IGBT region 8). The first sense terminal electrode 15 and the second sense terminal electrode 16 transmit an electrical signal to the sensor region 11 (temperature sensing device). The current detection terminal electrode 17 is an electrode for detecting the current in the active region 6 and taking it out to the outside. The open terminal electrode 18 is formed in an electrically floating state.

[0030] The arrangement of the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17, and the open terminal electrode 18 is arbitrary. In this embodiment, the open terminal electrode 18, the current detection terminal electrode 17, the gate terminal electrode 14, the first sense terminal electrode 15, and the second sense terminal electrode 16 are arranged in this order from the side surface 5A side to the side surface 5C side.

[0031] A gate wiring 19 is electrically connected to the gate terminal electrode 14. The gate wiring 19 is also referred to as a gate finger. The gate wiring 19 extends from the outer region 7 toward the active region 6. The gate wiring 19 transmits the gate signal applied to the gate terminal electrode 14 to the active region 6 (IGBT region 8).

[0032] More specifically, the gate wiring 19 includes a first region 19a located in the outer region 7 and a second region 19b located in the active region 6. The first region 19a is electrically connected to the gate terminal electrode 14. In this embodiment, the first region 19a is selectively routed to the region on the side surface 5D side of the outer region 7.

[0033] The second region 19b is formed in a plurality (five in this form) in the active region 6. The plurality of second regions 19b extend in a strip shape along the first direction X and are formed at intervals in the second direction Y. The plurality of second regions 19b are respectively formed in the regions between two adjacent RC-IGBT arrays 12.

[0034] The plurality of second regions 19b extend from the region on the side surface 5D side to the region on the side surface 5B side of the outer region 7. The plurality of second regions 19b may cross the boundary between the active region 6 and the outer region 7. The plurality of second regions 19b are continuous with the first region 19a in the outer region 7.

[0035] The gate signal applied to the gate terminal electrode 14 is transmitted to the second region 19b through the first region 19a. Thereby, the gate signal is transmitted to the active region 6 (IGBT region 8) through the second region 19b.

[0036] A first sense wiring 20 is electrically connected to the first sense terminal electrode 15. The first sense wiring 20 extends from the outer region 7 toward the sensor region 11. The first sense wiring 20 transmits the electrical signal applied to the first sense terminal electrode 15 to the sensor region 11.

[0037] More specifically, the first sense wiring 20 includes a first region 20a located in the outer region 7 and a second region 20b located in the active region 6. The first region 20a is electrically connected to the first sense terminal electrode 15. In this form, the first region 20a is selectively routed to the region on the side surface 5D side of the outer region 7.

[0038] The second region 20b is formed in the region between two adjacent RC-IGBT arrays 12 in which the sensor region 11 is formed. The second region 20b extends in a strip shape along the first direction X from the outer region 7 toward the sensor region 11. The second region 20b is electrically connected to the temperature sensing device in the sensor region 11. The second region 20b is continuous with the first region 20a in the outer region 7.

[0039] The electrical signal applied to the first sense terminal electrode 15 is transmitted to the second region 21b through the first region 20a. Thereby, the electrical signal is transmitted to the sensor region 11 through the second region 21b.

[0040] A second sense wiring 21 is electrically connected to the second sense terminal electrode 16. The second sense wiring 21 extends from the outer region 7 toward the sensor region 11. The second sense wiring 21 transmits the electrical signal applied to the second sense terminal electrode 16 to the sensor region 11.

[0041] More specifically, the second sense wiring 21 includes a first region 21a located in the outer region 7 and a second region 21b located in the active region 6. The first region 21a is electrically connected to the second sense terminal electrode 16. In this form, the first region 21a is selectively routed to the region on the side surface 5D side of the outer region 7.

[0042] The second region 21b is formed in the region between two adjacent RC-IGBT arrays 12 in which the sensor region 11 is formed. The second region 21b extends in a strip shape along the first direction X from the outer region 7 toward the sensor region 11. The second region 21b is electrically connected to the temperature sensing device in the sensor region 11. The second region 21b is continuous with the first region 21a in the outer region 7.

[0043] The electrical signal applied to the second sense terminal electrode 16 is transmitted to the second region 21b through the first region 21a. Thereby, the electrical signal is transmitted to the sensor region 11 through the second region 21b.

[0044] In the region between two adjacent RC-IGBT arrays 12 where the sensor region 11 is formed, a gate wiring 19, a first sense wiring 20, and a second sense wiring 21 are formed. The gate wiring 19, the first sense wiring 20, and the second sense wiring 21 extend in parallel in the region between two adjacent RC-IGBT arrays 12.

[0045] According to such a structure, in the active region 6 including the sensor region 11, it is possible to reduce the wiring formation area. That is, by reducing the wiring formation area, it is possible to expand the active region 6.

[0046] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 5. FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 6.

[0047] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 4. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 5. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 6. Hereinafter, FIGS. 1 to 6 are also referred to as necessary.

[0048] Referring to FIGS. 7 to 13, the semiconductor layer 2 has a single-layer structure including an n - -type semiconductor substrate 31. The semiconductor substrate 31 may be a silicon FZ substrate formed through the FZ (Floating Zone) method. The semiconductor substrate 31 is formed as a drift layer.

[0049] The n-type impurity concentration of the semiconductor substrate 31 may be 4×10 13 cm -3 or more and 2×10 14 cm -3 or less. The thickness of the semiconductor substrate 31 may be 50 μm or more and 200 μm or less. The thickness of the semiconductor substrate 31 may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, or 150 μm or more and 200 μm or less.

[0050] The semiconductor device 1 includes a collector terminal electrode 32 formed on the second main surface 4. The collector terminal electrode 32 is electrically connected to the second main surface 4. The collector terminal electrode 32 forms an ohmic contact with the second main surface 4. The collector terminal electrode 32 transmits a collector signal to the active region 6.

[0051] The semiconductor device 1 includes an n-type buffer layer 33 formed in the surface layer portion of the second main surface 4. The buffer layer 33 may be formed over the entire surface layer portion of the second main surface 4. The n-type impurity concentration of the buffer layer 33 exceeds the n-type impurity concentration of the semiconductor substrate 31. The n-type impurity concentration of the buffer layer 33 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less.

[0052] The thickness of the buffer layer 33 may be 0.5 μm or more and 30 μm or less. The thickness of the buffer layer 33 may be 0.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less.

[0053] Referring to FIGS. 3, 4, 7, and 8, each IGBT region 8 includes a p-type collector region 34 formed in the surface layer portion of the second main surface 4. More specifically, the collector region 34 is formed in the surface layer portion on the second main surface 4 side in the buffer layer 33. The collector region 34 is exposed from the second main surface 4. The collector region 34 forms an ohmic contact with the collector terminal electrode 32. The p-type impurity concentration of the collector region 34 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less.

[0054] Each IGBT region 8 includes a FET structure 35 formed on the first main surface 3. In this form, each IGBT region 8 includes a trench gate type FET structure 35. The FET structure 35 includes a trench gate structure 36 formed on the first main surface 3. In FIGS. 3 and 4, the trench gate structure 36 is indicated by hatching.

[0055] In this form, a plurality of trench gate structures 36 are formed at intervals in the first direction X in the IGBT region 8. The plurality of trench gate structures 36 are each formed in a strip shape extending along the second direction Y in plan view. The plurality of trench gate structures 36 are formed in a stripe shape as a whole. Each trench gate structure 36 has one end on one side and the other end on the other side with respect to the second direction Y.

[0056] The distance between two adjacent trench gate structures 36 in the first direction X may be 1 μm or more and 8 μm or less. The distance between the trench gate structures 36 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, or 7 μm or more and 8 μm or less.

[0057] The FET structure 35 includes a first outer trench gate structure 37 and a second outer trench gate structure 38 formed on the first main surface 3. The first outer trench gate structure 37 extends along the first direction X. The first outer trench gate structure 37 is connected to one end of each trench gate structure 36. The second outer trench gate structure 38 extends along the first direction X. The second outer trench gate structure 38 is connected to the other end of each trench gate structure 36.

[0058] The first outer trench gate structure 37 and the second outer trench gate structure 38 form one trench gate structure among a plurality of trench gate structures 36. The first outer trench gate structure 37 and the second outer trench gate structure 38 have the same structure as the trench gate structure 36 except that their extending directions are different. Hereinafter, the trench gate structure 36 will be described, and the descriptions of the structure of the first outer trench gate structure 37 and the second outer trench gate structure 38 will be omitted.

[0059] Referring to FIG. 8, each trench gate structure 36 includes a gate trench 39, a gate insulating layer 40, and a gate electrode 41. The gate trench 39 is formed on the first main surface 3. The gate trench 39 includes side walls and a bottom wall. The side walls of the gate trench 39 may be formed perpendicular to the first main surface 3.

[0060] The side walls of the gate trench 39 may slope downward from the first main surface 3 toward the bottom wall. That is, the gate trench 39 may be formed in a tapered shape with an opening area larger than the bottom area. The bottom wall of the gate trench 39 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 39 may be formed in a curved shape toward the second main surface 4.

[0061] The gate trench 39 includes an opening edge portion and a bottom wall edge portion. The opening edge portion of the gate trench 39 connects the side wall of the gate trench 39 and the first main surface 3. The bottom wall edge portion of the gate trench 39 connects the side wall and the bottom wall of the gate trench 39.

[0062] The opening edge portion of the gate trench 39 has an inclined portion that slopes downward from the first main surface 3 toward the side wall of the gate trench 39. The opening edge portion of the gate trench 39 is formed in a curved shape that is recessed toward the second main surface 4. Thereby, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the gate trench 39.

[0063] The opening edge portion of the gate trench 39 may be formed in a curved shape toward the inside of the gate trench 39. The bottom wall edge portion of the gate trench 39 may be formed in a curved shape toward the second main surface 4.

[0064] The depth of the gate trench 39 may be 3 μm or more and 7 μm or less. The depth of the gate trench 39 may be 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less.

[0065] The width of the gate trench 39 may be 0.5 μm or more and 3 μm or less. The width of the gate trench 39 is the width in the first direction X of the gate trench 39. The width of the gate trench 39 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0066] The gate insulating layer 40 is formed in a film shape along the inner wall of the gate trench 39. The gate insulating layer 40 partitions a recessed space in the gate trench 39. The gate insulating layer 40 includes a silicon oxide layer. The gate insulating layer 40 may include a silicon nitride layer instead of or in addition to the silicon oxide layer.

[0067] The gate insulating layer 40 includes a first region 40a, a second region 40b, and a third region 40c. The first region 40a covers the side wall of the gate trench 39. The second region 40b covers the bottom wall of the gate trench 39. The third region 40c covers the opening edge portion of the gate trench 39.

[0068] The thickness of the second region 20b may be equal to or greater than the thickness of the first region 40a. The thickness of the second region 40b may exceed the thickness of the first region 40a. The thickness of the third region 40c may be equal to or greater than the thickness of the first region 40a. The thickness of the third region 40c may exceed the thickness of the first region 40a.

[0069] The third region 40c includes a bulging portion that bulges inward toward the inside of the gate trench 39 at the opening edge of the gate trench 39. The third region 40c protrudes in a curved shape toward the inside of the gate trench 39. The third region 40c narrows the opening of the gate trench 39 at the opening edge of the gate trench 39. Of course, a gate insulating layer 40 having a uniform thickness may be formed on the inner wall of the gate trench 39.

[0070] The gate electrode 41 is embedded in the gate trench 39 with the gate insulating layer 40 interposed therebetween. More specifically, the gate electrode 41 is embedded in a recessed space partitioned by the gate insulating layer 40 in the gate trench 39. The gate electrode 41 is controlled by a gate signal.

[0071] The gate electrode 41 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The gate electrode 41 has an upper end portion located on the opening side of the gate trench 39. The upper end portion of the gate electrode 41 is located on the bottom wall side of the gate trench 39 with respect to the first main surface 3.

[0072] The upper end portion of the gate electrode 41 has a constricted portion constricted along the third region 40c of the gate insulating layer 40. A depression is formed in the upper end portion of the gate electrode 41 toward the bottom wall of the gate trench 39. The depression in the upper end portion of the gate electrode 41 is formed in a tapered shape toward the bottom wall of the gate trench 39.

[0073] The FET structure 35 includes a p-type body region 45 formed in the surface layer portion of the first main surface 3. The p-type impurity concentration of the body region 45 may be 1×10 17 cm -3 or more and 1×10 18 cm -3 or less. In this form, a plurality of body regions 45 are formed on both sides of the trench gate structure 36, respectively.

[0074] The body region 45 is formed in a strip shape extending along the trench gate structure 36 in plan view. The body region 45 is exposed from the side wall of the gate trench 39. The bottom of the body region 45 is formed at a depth position between the first main surface 3 and the bottom wall of the gate trench 39 with respect to the normal direction Z.

[0075] The FET structure 35 includes an n-type emitter region 46 formed in the surface layer portion of the body region 45. + The n-type impurity concentration of the emitter region 46 exceeds the n-type impurity concentration of the semiconductor layer 2. The n-type impurity concentration of the emitter region 46 is 1×10 19 cm -3 or more and may be 1×10 20 cm -3 or less.

[0076] In this form, a plurality of emitter regions 46 are respectively formed on both sides of the trench gate structure 36. The emitter region 46 is formed in a strip shape extending along the trench gate structure 36 in plan view. The emitter region 46 is exposed from the first main surface 3. The emitter region 46 is exposed from the side wall of the gate trench 39. The bottom of the emitter region 46 is formed at a depth position between the upper end portion of the gate electrode 41 and the bottom of the body region 45 with respect to the normal direction Z.

[0077] In this form, the FET structure 35 includes an n-type carrier storage region 47 formed in a region on the second main surface 4 side with respect to the body region 45 in the semiconductor layer 2. + The n-type impurity concentration of the carrier storage region 47 exceeds the n-type impurity concentration of the semiconductor layer 2. The n-type impurity concentration of the carrier storage region 47 is less than the n-type impurity concentration of the emitter region 46. The n-type impurity concentration of the carrier storage region 47 is 1×10 15 cm -3 or more and may be 1×10 17 cm -3 or less.

[0078] In this form, a plurality of carrier storage regions 47 are formed on both sides of the trench gate structure 36, respectively. The carrier storage regions 47 are formed in a strip shape extending along the trench gate structure 36 in a plan view. The carrier storage regions 47 are exposed from the side walls of the gate trench 39. The bottom of the carrier storage region 47 is formed at a depth position between the bottom of the body region 45 and the bottom wall of the gate trench 39 with respect to the normal direction Z.

[0079] The carrier storage regions 47 suppress the holes (carriers) supplied to the semiconductor layer 2 from being drawn back (discharged) to the body region 45. As a result, holes are accumulated in the region directly below the FET structure 35 in the semiconductor layer 2, and a reduction in on-resistance and a reduction in on-voltage are achieved.

[0080] In this form, the FET structure 35 includes an emitter trench 48 formed on the first main surface 3. In this form, a plurality of emitter trenches 48 are formed on both sides of the trench gate structure 36, respectively. The emitter trench 48 is formed at a distance from the trench gate structure 36 in the first direction X. The emitter trench 48 extends in a strip shape along the trench gate structure 36 in a plan view.

[0081] The emitter trench 48 exposes the emitter region 46. The emitter trench 48 may penetrate the emitter region 46. With respect to the second direction Y, the length of the emitter trench 48 is equal to or less than the length of the trench gate structure 36. Preferably, the length of the emitter trench 48 is less than the length of the trench gate structure 36.

[0082] The FET structure 35 includes a p-type contact region 49 formed in the body region 45 in a region along the bottom wall of the emitter trench 48. The p-type impurity concentration of the contact region 49 exceeds the p-type impurity concentration of the body region 45. The p-type impurity concentration of the contact region 49 is 1×10 + type, and is 1×10 19 cm -3 or more and 1×10 20cm -3 It may be as follows.

[0083] The contact region 49 is exposed from the bottom wall of the emitter trench 48. The contact region 49 extends in a strip shape along the emitter trench 48 in a plan view. The bottom of the contact region 49 is formed at a depth position between the bottom wall of the emitter trench 48 and the bottom of the body region 45 with respect to the normal direction Z.

[0084] In the FET structure 35, the gate electrode 41 faces the body region 45 and the emitter region 46 with the gate insulating layer 40 interposed therebetween. In this form, the gate electrode 41 also faces the carrier storage region 47 with the gate insulating layer 40 interposed therebetween. In the body region 45, a channel of the IGBT is formed in the region between the emitter region 46 and the carrier storage region 47. The on / off of the channel is controlled by a gate signal.

[0085] Referring to FIGS. 4 and 8, the semiconductor device 1 includes a region isolation structure 50 formed on the first main surface 3 in the IGBT region 8. The region isolation structure 50 partitions the FET structure 35 from other regions. The region isolation structure 50 is formed in a region adjacent to the FET structure 35 on the first main surface 3.

[0086] In this form, a plurality of region isolation structures 50 are respectively formed on both sides of the FET structure 35. More specifically, the region isolation structures 50 are respectively formed in the regions between adjacent plurality of FET structures 35. Thereby, the plurality of FET structures 35 are respectively separated by the region isolation structures 50.

[0087] In this form, the region isolation structure 50 forms an IE (Injection Enhanced) structure 51 with the FET structure 35. In the IE structure 51, a plurality of FET structures 35 are arranged in a manner separated by the region isolation structure 50. In the region isolation structure 50, holes injected into the semiconductor layer 2 flow around the region isolation structure 50 and into the FET structure 35. That is, the region isolation structure 50 restricts the movement of holes. As a result, holes are accumulated in the region directly under the FET structure 35 in the semiconductor layer 2, and the hole density is increased. Consequently, a reduction in on-resistance and a reduction in on-voltage can be achieved.

[0088] More specifically, each region isolation structure 50 is formed in a region adjacent to the FET structure 35 in the surface layer portion of the first main surface 3 and includes a p + -type floating region 52. The floating region 52 is formed in an electrically floating state.

[0089] The p-type impurity concentration of the floating region 52 may be equal to or higher than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the floating region 52 may exceed the p-type impurity concentration of the body region 45. The p-type impurity concentration of the floating region 52 may be 1×10 16 cm -3 or more and 1×10 20 cm -3 or less. The p-type impurity concentration of the floating region 52 is preferably 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0090] The floating region 52 is formed in a strip shape extending along the FET structure 35 in a plan view. In the second direction Y, the length of the floating region 52 is preferably less than the length of the gate trench 39.

[0091] The bottom of the floating region 52 is formed at a depth position between the bottom of the body region 45 and the second main surface 4 with respect to the normal direction Z. More specifically, the bottom of the floating region 52 is formed at a depth position between the bottom of the carrier storage region 47 and the second main surface 4. In this form, the bottom of the floating region 52 is formed at a depth position between the bottom wall of the gate trench 39 and the second main surface 4.

[0092] Each region isolation structure 50 includes a region isolation trench structure 53 that partitions the floating region 52 from the FET structure 35. The region isolation trench structure 53 is formed in an annular shape (a square annular shape in this form) surrounding the floating region 52 in a plan view.

[0093] The region isolation trench structure 53 includes a region isolation trench 54, a region isolation insulating layer 55, and a region isolation electrode layer 56. The region isolation trench 54 is formed on the first main surface 3. The region isolation trench 54 includes side walls and a bottom wall. The side walls of the region isolation trench 54 may be formed perpendicular to the first main surface 3. The side walls of the region isolation trench 54 may be inclined downward from the first main surface 3 toward the bottom wall. That is, the region isolation trench 54 may be formed in a tapered shape with an opening area larger than the bottom area.

[0094] The side walls of the region isolation trench 54 include an outer wall facing the FET structure 35 and an inner wall facing the floating region 52. The outer wall of the region isolation trench 54 exposes the emitter region 46, the body region 45, and the carrier storage region 47. The inner wall of the region isolation trench 54 exposes the floating region 52.

[0095] The bottom wall of the region isolation trench 54 may be formed parallel to the first main surface 3. The bottom wall of the region isolation trench 54 may be formed in a curved shape toward the second main surface 4. The bottom wall of the region isolation trench 54 is covered by the bottom of the floating region 52. That is, the floating region 52 has a covering portion that covers the bottom wall of the region isolation trench 54.

[0096] The region separation trench 54 includes an opening edge portion and a bottom wall edge portion. The opening edge portion of the region separation trench 54 connects the side wall of the region separation trench 54 and the first main surface 3. The bottom wall edge portion of the region separation trench 54 connects the side wall and the bottom wall of the region separation trench 54.

[0097] The opening edge portion of the region separation trench 54 has an inclined portion that slopes downward from the first main surface 3 toward the side wall of the region separation trench 54. The opening edge portion of the region separation trench 54 is formed in a curved shape that is recessed toward the second main surface 4. As a result, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the region separation trench 54.

[0098] The opening edge portion of the region separation trench 54 may be formed in a curved shape that curves inward of the region separation trench 54. The bottom wall edge portion of the region separation trench 54 may be formed in a curved shape that curves toward the second main surface 4.

[0099] The depth of the region separation trench 54 may be 3 μm or more and 7 μm or less. The depth of the region separation trench 54 may be 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less. The depth of the region separation trench 54 may be equal to the depth of the gate trench 39.

[0100] The width of the region separation trench 54 may be 0.5 μm or more and 3 μm or less. The width of the region separation trench 54 is the width in the first direction X of the region separation trench 54. The width of the region separation trench 54 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the region separation trench 54 may be equal to the width of the gate trench 39.

[0101] The isolation insulating layer 55 is formed in a film shape along the inner wall of the isolation trench 54. The isolation insulating layer 55 partitions a recess space in the isolation trench 54. In this form, the isolation insulating layer 55 includes a silicon oxide layer. The isolation insulating layer 55 may include a silicon nitride layer instead of or in addition to the silicon oxide layer.

[0102] The isolation insulating layer 55 includes a first region 55a, a second region 55b, and a third region 55c. The first region 55a covers the side wall of the isolation trench 54. The second region 55b covers the bottom wall of the isolation trench 54. The third region 55c covers the opening edge portion of the isolation trench 54.

[0103] The thickness of the second region 20b may be equal to or greater than the thickness of the first region 55a. The thickness of the second region 55b may exceed the thickness of the first region 55a. The thickness of the third region 55c may be equal to or greater than the thickness of the first region 55a. The thickness of the third region 55c may exceed the thickness of the first region 55a.

[0104] The third region 55c includes a bulging portion that bulges inward of the isolation trench 54 at the opening edge portion of the isolation trench 54. The third region 55c projects in a curved shape toward the inside of the isolation trench 54. The third region 55c narrows the opening of the isolation trench 54 at the opening edge portion of the isolation trench 54. Of course, an isolation insulating layer 55 having a uniform thickness may be formed on the inner wall of the isolation trench 54.

[0105] The isolation electrode layer 56 is embedded in the isolation trench 54 with the isolation insulating layer 55 interposed therebetween. More specifically, the isolation electrode layer 56 is embedded in the recess space partitioned by the isolation insulating layer 55 in the isolation trench 54. The isolation electrode layer 56 is controlled by an emitter signal.

[0106] The region separation electrode layer 56 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The region separation electrode layer 56 has an upper end portion located on the opening side of the region separation trench 54. The upper end portion of the region separation electrode layer 56 is located on the bottom wall side of the region separation trench 54 with respect to the first main surface 3.

[0107] The upper end portion of the region separation electrode layer 56 has a constricted portion constricted along the third region 55c of the region separation insulating layer 55. A depression is formed in the upper end portion of the region separation electrode layer 56 toward the bottom wall of the region separation trench 54. The depression in the upper end portion of the region separation electrode layer 56 is formed in a tapered shape toward the bottom wall of the region separation trench 54.

[0108] Referring to FIGS. 3, 5, 7, and 9, each diode region 9 includes an n-type cathode region 61 formed in the surface layer portion of the second main surface 4. + More specifically, the cathode region 61 is formed in the surface layer portion on the second main surface 4 side in the buffer layer 33. The cathode region 61 is exposed from the second main surface 4. The cathode region 61 forms an ohmic contact with the collector terminal electrode 32.

[0109] The n-type impurity concentration of the cathode region 61 exceeds the n-type impurity concentration of the semiconductor layer 2. The n-type impurity concentration of the cathode region 61 further exceeds the n-type impurity concentration of the buffer layer 33. The n-type impurity concentration of the cathode region 61 may be 1×10 19 cm -3 or more and 1×10 20 cm -3 or less.

[0110] The cathode region 61 is electrically connected to the collector region 34 at the side along the second direction Y. In this form, the cathode region 61 is surrounded by the collector region 34. That is, the cathode region 61 is electrically connected to the collector region 34 at the side along the first direction X and the side along the second direction Y. The collector region 34 may be formed over the entire region other than the cathode region 61 in the surface layer portion of the second main surface 4.

[0111] Each diode region 9 includes a p-type anode region 62 formed in the surface layer portion of the first main surface 3. The anode region 62 is controlled by an emitter signal. The p-type impurity concentration of the anode region 62 is 1×10 16 cm -3 or more and 1×10 18 cm -3 or less may be sufficient. The p-type impurity concentration of the anode region 62 may be equal to the p-type impurity concentration of the body region 45. The p-type impurity concentration of the anode region 62 may be less than the p-type impurity concentration of the body region 45.

[0112] In this form, a plurality of anode regions 62 are formed at intervals along the first direction X in a plan view. The plurality of anode regions 62 are each formed in a strip shape extending along the second direction Y in a plan view. The plurality of anode regions 62 are formed in a stripe shape as a whole. The anode region 62 is formed in a region that overlaps the cathode region 61 in the normal direction Z. In this form, all the anode regions 62 overlap the cathode region 61 in the normal direction Z.

[0113] The anode region 62 forms a pn junction with the semiconductor layer 2. Thereby, a pn junction diode D having the anode region 62 as an anode and the semiconductor layer 2 (cathode region 61) as a cathode is formed.

[0114] Regarding the second direction Y, the length of the anode region 62 may be equal to or less than the length of the trench gate structure 36. Preferably, the length of the anode region 62 is less than the length of the trench gate structure 36.

[0115] The distance between two adjacent anode regions 62 in the first direction X may be 0.5 μm or more and 3 μm or less. The distance between the anode regions 62 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0116] Each diode region 9 includes an anode isolation structure 63 that partitions the anode region 62 from other regions. More specifically, each diode region 9 includes a plurality of anode isolation structures 63 that respectively partition a plurality of anode regions 62. In FIGS. 3 and 5, the anode isolation structure 63 is indicated by hatching.

[0117] The plurality of anode isolation structures 63 are respectively formed in regions between adjacent anode regions 62. More specifically, the plurality of anode isolation structures 63 are respectively formed in an annular shape (a square annular shape in this form) that surrounds the anode region 62 in a plan view.

[0118] The anode isolation structure 63 that partitions one anode region 62 and the anode isolation structure 63 that partitions the other anode region 62 are integrally formed in a region between adjacent anode regions 62.

[0119] Each anode isolation structure 63 includes an anode isolation trench 64, an anode isolation insulating layer 65, and an anode isolation electrode layer 66. The anode isolation trench 64 is formed on the first main surface 3. The anode isolation trench 64 includes side walls and a bottom wall. The side walls of the anode isolation trench 64 may be formed perpendicular to the first main surface 3. The side walls of the anode isolation trench 64 may be inclined downward from the first main surface 3 toward the bottom wall. The anode isolation trench 64 may be formed in a tapered shape with an opening area larger than the bottom area.

[0120] The bottom wall of the anode isolation trench 64 may be formed parallel to the first main surface 3. The bottom wall of the anode isolation trench 64 may be formed in a curved shape toward the second main surface 4.

[0121] The anode isolation trench 64 includes an opening edge portion and a bottom wall edge portion. The opening edge portion of the anode isolation trench 64 connects the side wall of the anode isolation trench 64 and the first main surface 3. The bottom wall edge portion of the anode isolation trench 64 connects the side wall and the bottom wall of the anode isolation trench 64.

[0122] The opening edge portion of the anode isolation trench 64 has an inclined portion that slopes downward from the first main surface 3 toward the side wall of the anode isolation trench 64. The opening edge portion of the anode isolation trench 64 is formed in a curved shape that is recessed toward the second main surface 4. As a result, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the anode isolation trench 64.

[0123] The opening edge portion of the anode isolation trench 64 may be formed in a curved shape that faces inward of the anode isolation trench 64. The bottom wall edge portion of the anode isolation trench 64 may be formed in a curved shape that faces the second main surface 4.

[0124] The depth of the anode isolation trench 64 may be 3 μm or more and 7 μm or less. The depth of the anode isolation trench 64 may be 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less. The depth of the anode isolation trench 64 may be equal to the depth of the gate trench 39. The depth of the anode isolation trench 64 may be equal to the depth of the region isolation trench 54.

[0125] The width of the anode isolation trench 64 may be 0.5 μm or more and 3 μm or less. The width of the anode isolation trench 64 is the width in the first direction X of the anode isolation trench 64. The width of the anode isolation trench 64 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the anode isolation trench 64 may be equal to the width of the gate trench 39. The width of the anode isolation trench 64 may be equal to the width of the region isolation trench 54.

[0126] The anode separation insulating layer 65 is formed in a film shape along the inner wall of the anode separation trench 64. The anode separation insulating layer 65 partitions a recessed space within the anode separation trench 64. In this form, the anode separation insulating layer 65 includes a silicon oxide layer. The anode separation insulating layer 65 may include a silicon nitride layer instead of or in addition to the silicon oxide layer.

[0127] The portion of the anode separation insulating layer 65 that covers the side wall of the anode separation trench 64 includes the upper end portion located on the opening side of the anode separation trench 64. The upper end portion of the anode separation insulating layer 65 is located on the bottom wall side of the anode separation trench 64 with respect to the first main surface 3.

[0128] The anode separation insulating layer 65 includes a first region 65a, a second region 65b, and a third region 65c. The first region 65a covers the side wall of the anode separation trench 64. The second region 65b covers the bottom wall of the anode separation trench 64. The second region 65b forms the upper end portion of the anode separation insulating layer 65. In this form, the third region 65c covers the opening edge portions of the anode separation trench 64 at both ends in the second direction Y in the anode separation trench 64 (see also FIG. 12).

[0129] The thickness of the second region 65b may be equal to or greater than the thickness of the first region 65a. The thickness of the second region 65b may exceed the thickness of the first region 65a. The thickness of the third region 65c may exceed the thickness of the first region 65a. The portion of the first region 65a located on the opening side of the anode separation trench 64 may bulge inward toward the inside of the anode separation trench 64.

[0130] The third region 65c includes a bulging portion that bulges inwardly of the anode isolation trench 64 at the opening edge portion of the anode isolation trench 64. The third region 65c projects in a curved shape inwardly of the anode isolation trench 64. The third region 65c narrows the opening of the anode isolation trench 64 at the opening edge portion of the gate trench 39. Of course, an anode isolation insulating layer 65 having a uniform thickness may be formed on the inner wall of the anode isolation trench 64.

[0131] The anode isolation electrode layer 66 is embedded in the anode isolation trench 64 with the anode isolation insulating layer 65 interposed therebetween. More specifically, the anode isolation electrode layer 66 is embedded in a recessed space partitioned by the anode isolation insulating layer 65 in the anode isolation trench 64. The anode isolation electrode layer 66 is controlled by an emitter signal.

[0132] The anode isolation electrode layer 66 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The anode isolation electrode layer 66 has an upper end portion located on the opening side of the anode isolation trench 64. The upper end portion of the anode isolation electrode layer 66 is located on the bottom wall side of the anode isolation trench 64 with respect to the first main surface 3.

[0133] The upper end portion of the anode isolation electrode layer 66 is formed in a tapered shape toward the first main surface 3 side. A depression is formed in the upper end portion of the anode isolation electrode layer 66 that faces the bottom wall of the anode isolation trench 64. The depression of the anode isolation electrode layer 66 is formed in a tapered shape toward the bottom wall of the anode isolation trench 64.

[0134] On the opening side of the anode isolation trench 64, a recess 67 is defined by the anode isolation trench 64, the anode isolation electrode layer 66, and the anode isolation insulating layer 65. More specifically, the recess 67 is defined within the anode isolation trench 64 by the sidewall of the anode isolation trench 64, the upper end of the anode isolation electrode layer 66, and the upper end of the anode isolation insulating layer 65. The widened portion of the anode isolation trench 64 is formed by the recess 67. The sidewall of the anode isolation trench 64 (the sidewall of the recess 67) exposes the anode region 62.

[0135] The bottom of the anode region 62 is formed at a depth position between the first main surface 3 and the bottom wall of the anode isolation trench 64 with respect to the normal direction Z. That is, the bottom of the anode region 62 is formed at a depth position between the first main surface 3 and the bottom wall of the gate trench 39 with respect to the normal direction Z. Also, the bottom of the anode region 62 is formed in a region on the first main surface 3 side with respect to the bottom of the carrier storage region 47 with respect to the normal direction Z.

[0136] Referring to FIGS. 3, 6, 7, 9, and 10, each boundary region 10 includes a collector region 34 formed in the surface layer portion of the second main surface 4. That is, the collector region 34 is drawn from the IGBT region 8 to the boundary region 10 in the surface layer portion of the second main surface 4 and is connected to the cathode region 61.

[0137] Each boundary region 10 includes a p + -type well region 71 formed in the surface layer portion of the first main surface 3. The well region 71 is controlled by an emitter signal. The p-type impurity concentration of the well region 71 may be 1×10 16 cm -3 or more and 1×10 20 cm -3 or less. The p-type impurity concentration of the well region 71 is preferably 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0138] The p-type impurity concentration in the well region 71 may be equal to or higher than the p-type impurity concentration in the body region 45. The p-type impurity concentration in the well region 71 may exceed the p-type impurity concentration in the body region 45. The p-type impurity concentration in the well region 71 may be equal to the p-type impurity concentration in the floating region 52.

[0139] In this form, a plurality of well regions 71 are formed at intervals along the first direction X in a plan view. The plurality of well regions 71 are each formed in a strip shape extending along the second direction Y in a plan view. The plurality of well regions 71 are formed in a stripe shape as a whole. The plurality of well regions 71 are formed in a region overlapping the collector region 34 with respect to the normal direction Z. In this form, all the well regions 71 overlap the collector region 34 in the normal direction Z.

[0140] The bottom of the well region 71 is formed at a depth position between the bottom of the carrier storage region 47 and the second main surface 4 with respect to the normal direction Z. In this form, the bottom of the well region 71 is formed at a depth position between the bottom wall of the gate trench 39 and the second main surface 4 with respect to the normal direction Z.

[0141] Each well region 71 has one end portion on one side and the other end portion on the other side with respect to the second direction Y. With respect to the second direction Y, the length of the well region 71 is equal to or less than the length of the trench gate structure 36. Preferably, the length of the well region 71 is less than the length of the trench gate structure 36.

[0142] The distance between two adjacent well regions 71 in the first direction X may be 1 μm or more and 10 μm or less. The distance between the well regions 71 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less.

[0143] Each boundary region 10 includes a well separation structure 72 that partitions the well region 71. In FIGS. 3, 5, and 6, the well separation structure 72 is shown by hatching. In this form, a plurality of well separation structures 72 that partition the plurality of well regions 71 are formed. The plurality of well separation structures 72 are each formed in an annular shape (a square annular shape in this form) that surrounds the well region 71 in plan view.

[0144] The well separation structure 72 includes a well separation trench 73, a well separation insulating layer 74, and a well separation electrode layer 75. The well separation trench 73 is formed on the first main surface 3. The well separation trench 73 includes side walls and a bottom wall.

[0145] The side walls of the well separation trench 73 may be formed perpendicular to the first main surface 3. The side walls of the well separation trench 73 may be inclined downward from the first main surface 3 toward the bottom wall. The well separation trench 73 may be formed in a tapered shape in which the opening area is larger than the bottom area.

[0146] The bottom wall of the well separation trench 73 may be formed parallel to the first main surface 3. The bottom wall of the well separation trench 73 may be formed in a curved shape toward the second main surface 4. The bottom wall of the well separation trench 73 is covered by the bottom of the well region 71. That is, the well region 71 has a covering portion that covers the bottom wall of the well separation trench 73.

[0147] The well separation trench 73 includes an opening edge portion and a bottom wall edge portion. The opening edge portion of the well separation trench 73 connects the side wall of the well separation trench 73 and the first main surface 3. The bottom wall edge portion of the well separation trench 73 connects the side wall and the bottom wall of the well separation trench 73.

[0148] The opening edge portion of the well isolation trench 73 has an inclined portion that slopes downward from the first main surface 3 toward the side wall of the well isolation trench 73. The opening edge portion of the well isolation trench 73 is formed in a curved shape that is recessed toward the second main surface 4. As a result, a widened portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the well isolation trench 73.

[0149] The opening edge portion of the well isolation trench 73 may be formed in a curved shape that curves inward of the well isolation trench 73. The bottom wall edge portion of the well isolation trench 73 may be formed in a curved shape that curves toward the second main surface 4.

[0150] The depth of the well isolation trench 73 may be 3 μm or more and 7 μm or less. The depth of the well isolation trench 73 may be 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less. The depth of the well isolation trench 73 may be equal to the depth of the gate trench 39. The depth of the well isolation trench 73 may be equal to the depth of the region isolation trench 54. The depth of the well isolation trench 73 may be equal to the depth of the anode isolation trench 64.

[0151] The width of the well isolation trench 73 may be 0.5 μm or more and 3 μm or less. The width of the well isolation trench 73 is the width in the first direction X of the well isolation trench 73. The width of the well isolation trench 73 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the well isolation trench 73 may be equal to the width of the gate trench 39. The width of the well isolation trench 73 may be equal to the width of the region isolation trench 54. The width of the well isolation trench 73 may be equal to the width of the anode isolation trench 64.

[0152] The well isolation insulating layer 74 is formed in a film shape along the inner wall of the well isolation trench 73. The well isolation insulating layer 74 partitions a recess space within the well isolation trench 73. In this form, the well isolation insulating layer 74 includes a silicon oxide layer. The well isolation insulating layer 74 may include a silicon nitride layer instead of or in addition to the silicon oxide layer.

[0153] The well isolation insulating layer 74 includes a first region 74a, a second region 74b, and a third region 74c. The first region 74a covers the side wall of the well isolation trench 73. The second region 74b covers the bottom wall of the well isolation trench 73. The third region 74c covers the opening edge portion of the well isolation trench 73.

[0154] The thickness of the second region 74b may be equal to or greater than the thickness of the first region 74a. The thickness of the second region 74b may exceed the thickness of the first region 74a. The thickness of the third region 74c may be equal to or greater than the thickness of the first region 74a. The thickness of the third region 74c may exceed the thickness of the first region 74a.

[0155] The third region 74c includes a bulging portion that bulges inwardly of the well isolation trench 73 at the opening edge portion of the well isolation trench 73. The third region 74c projects in a curved shape inwardly of the well isolation trench 73. The third region 74c narrows the opening of the well isolation trench 73 at the opening edge portion of the well isolation trench 73. Of course, a well isolation insulating layer 74 having a uniform thickness may be formed on the inner wall of the well isolation trench 73.

[0156] The well isolation electrode layer 75 is embedded in the well isolation trench 73 with the well isolation insulating layer 74 interposed therebetween. More specifically, the well isolation electrode layer 75 is embedded in the recess space partitioned by the well isolation insulating layer 74 in the well isolation trench 73. The well isolation electrode layer 75 is controlled by an emitter signal.

[0157] The well separation electrode layer 75 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The well separation electrode layer 75 has an upper end portion located on the opening side of the well separation trench 73. The upper end portion of the well separation electrode layer 75 is located on the bottom wall side of the well separation trench 73 with respect to the first main surface 3.

[0158] The upper end portion of the well separation electrode layer 75 has a constricted portion constricted along the third region 74c of the well separation insulating layer 74. A depression is formed in the upper end portion of the well separation electrode layer 75 toward the bottom wall of the well separation trench 73. The depression of the well separation electrode layer 75 is formed in a tapered shape toward the bottom wall of the well separation trench 73.

[0159] Referring to FIG. 7, in each boundary region 10, the plurality of well regions 71 include a first adjacent well region 71A and a second adjacent well region 71B. The first adjacent well region 71A is the well region 71 closest to the IGBT region 8. The second adjacent well region 71B is the well region 71 closest to the diode region 9. The second adjacent well region 71B defines the boundary region 10 with the first adjacent well region 71A.

[0160] In this form, the second adjacent well region 71B is partitioned from the anode region 62 using the anode separation structure 63. That is, the boundary region separation structure 76 formed in the region closest to the diode region 9 includes the second adjacent well region 71B and the anode separation structure 63 in this form. The entire area of the second adjacent well region 71B overlaps with the collector region 34 in the normal direction Z. Of course, the second adjacent well region 71B may be partitioned from other regions by the well separation structure 72.

[0161] Thus, each boundary region 10 includes a boundary region separation structure 76 including a well region 71 and a well separation structure 72. The boundary region separation structure 76 has a structure corresponding to the region separation structure 50 except that it includes the well region 71 instead of the floating region 52.

[0162] Each boundary region 10 includes a boundary FET structure 77 formed in a region adjacent to the boundary region separation structure 76. In this form, a plurality of boundary FET structures 77 are formed on both sides of the boundary region separation structure 76, respectively. The plurality of boundary FET structures 77 are formed in the regions between the plurality of boundary region separation structures 76, respectively. Thereby, the plurality of boundary FET structures 77 are separated by the boundary region separation structure 76.

[0163] The boundary FET structure 77 has a structure corresponding to the FET structure 35. That is, the boundary FET structure 77 includes, similarly to the FET structure 35, a trench gate structure 36, a body region 45, an emitter region 46, a carrier storage region 47, an emitter trench 48, and a contact region 49. For a specific description of the boundary FET structure 77, the description of the FET structure 35 shall apply mutatis mutandis. For the structures corresponding to the structures described for the FET structure 35 in the boundary FET structure 77, the same reference numerals are given and the description is omitted.

[0164] The well separation trench 73 includes an outer wall facing the boundary FET structure 77 and an inner wall facing the well region 71. The outer wall of the well separation trench 73 exposes the emitter region 46, the body region 45, and the carrier storage region 47. The inner wall of the well separation trench 73 exposes the well region 71.

[0165] Referring to FIGS. 7 to 10, the semiconductor device 1 includes a main surface insulating layer 79 formed on the first main surface 3. The main surface insulating layer 79 is formed in a film shape along the first main surface 3. The main surface insulating layer 79 selectively covers the first main surface 3. More specifically, the main surface insulating layer 79 selectively covers the IGBT region 8, the diode region 9, and the boundary region 10.

[0166] In this form, the main surface insulating layer 79 includes a silicon oxide layer. The main surface insulating layer 79 may include a silicon nitride layer instead of or in addition to the silicon oxide layer. The main surface insulating layer 79 is continuous with the gate insulating layer 40, the region separation insulating layer 55, the anode separation insulating layer 65, and the well separation insulating layer 74.

[0167] Referring to FIG. 11, the gate electrode 41 of the IGBT region 8 has a gate lead portion 41a drawn out onto the first main surface 3 from the gate trench 39. More specifically, the gate lead portion 41a is drawn out onto the main surface insulating layer 79 from the gate trench 39 of the first outer trench gate structure 37 (second outer trench gate structure 38). The gate lead portion 41a is drawn out along the second direction Y.

[0168] The gate lead portion 41a is electrically connected to the gate wiring 19. The gate signal applied to the gate terminal electrode 14 is transmitted to the gate electrode 41 through the gate wiring 19 and the gate lead portion 41a.

[0169] Referring to FIG. 11, the region separation electrode layer 56 of the region separation structure 50 has a separation lead portion 56a drawn out onto the first main surface 3 from the region separation trench 54. More specifically, the separation lead portion 56a is drawn out onto the main surface insulating layer 79 from the region separation trench 54. The separation lead portion 56a is drawn out along the second direction Y.

[0170] The separation lead portion 56a is electrically connected to the emitter terminal electrode 13. The emitter signal applied to the separation lead portion 56a is transmitted to the region separation electrode layer 56 through the separation lead portion 56a.

[0171] Referring to FIG. 12, the anode separation electrode layer 66 of the anode separation structure 63 has an anode lead portion 66a drawn out onto the first main surface 3 from the anode separation trench 64. More specifically, the anode lead portion 66a is drawn out onto the main surface insulating layer 79 from the anode separation trench 64. The anode lead portion 66a is drawn out along the second direction Y.

[0172] The anode lead-out portion 66a is electrically connected to the emitter terminal electrode 13. The emitter signal applied to the anode lead-out portion 66a is transmitted to the anode separation electrode layer 66 via the anode lead-out portion 66a.

[0173] Referring to FIG. 13, the well separation electrode layer 75 of the well separation structure 72 has a well lead-out portion 75a drawn out onto the first main surface 3 from the well separation trench 73. The well lead-out portion 75a is more specifically drawn out onto the main surface insulating layer 79 from the well separation trench 73. The well lead-out portion 75a is drawn out along the second direction Y.

[0174] The well lead-out portion 75a is electrically connected to the emitter terminal electrode 13. The emitter signal applied to the well lead-out portion 75a is transmitted to the well separation electrode layer 75 via the well lead-out portion 75a.

[0175] Referring to FIGS. 7 to 10, the semiconductor device 1 includes an interlayer insulating layer 80 formed on the first main surface 3. The interlayer insulating layer 80 is more specifically formed on the main surface insulating layer 79. The interlayer insulating layer 80 is formed in a film shape along the first main surface 3. The interlayer insulating layer 80 selectively covers the first main surface 3. The interlayer insulating layer 80 more specifically selectively covers the IGBT region 8, the diode region 9, and the boundary region 10.

[0176] The interlayer insulating layer 80 may contain silicon oxide or silicon nitride. The interlayer insulating layer 80 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0177] In this form, the interlayer insulating layer 80 has a laminated structure including a first interlayer insulating layer 81 and a second interlayer insulating layer 82 laminated in this order from the side of the first main surface 3. The first interlayer insulating layer 81 may contain PSG or BPSG. The second interlayer insulating layer 82 contains an insulating material different from that of the first interlayer insulating layer 81. The second interlayer insulating layer 82 may contain PSG or BPSG.

[0178] Referring to FIGS. 8 to 10, the interlayer insulating layer 80 includes an emitter opening 83, an anode opening 84, and a well opening 85. Also, referring to FIGS. 11 to 13, the interlayer insulating layer 80 includes a first opening 86, a second opening 87, and a third opening 88.

[0179] Referring to FIG. 8, the emitter opening 83 exposes the emitter trench 48. In this form, the emitter trench 48 is formed on the first main surface 3 through the first interlayer insulating layer 81 and the main surface insulating layer 79. The emitter opening 83 penetrates the second interlayer insulating layer 82 and communicates with the emitter trench 48. The emitter opening 83 has an opening width exceeding the opening width of the emitter trench 48. The opening edge portion of the emitter opening 83 is formed in a curved shape toward the inside of the interlayer insulating layer 80.

[0180] Referring to FIG. 9, the anode opening 84 exposes the diode region 9. More specifically, the anode opening 84 penetrates the interlayer insulating layer 80 and the main surface insulating layer 79, and exposes the anode isolation structure 63 and the anode region 62.

[0181] The anode opening 84 further exposes the second proximity well region 71B. In this form, the anode opening 84 exposes a part of the second proximity well region 71B. A part of the inner wall of the anode opening 84 is located directly above the second proximity well region 71B.

[0182] The anode opening 84 is formed such that the opening width narrows from the opening side toward the bottom wall side. More specifically, the anode opening 84 has a wide portion and a narrow portion. The wide portion of the anode opening 84 is formed in the second interlayer insulating layer 82. The narrow portion of the anode opening 84 has an opening width smaller than that of the wide portion. The narrow portion of the anode opening 84 is formed in the first interlayer insulating layer 81.

[0183] Referring to FIG. 10, the well opening 85 exposes the well region 71. In this configuration, a plurality of well openings 85 are formed in the interlayer insulating layer 80. The plurality of well openings 85 expose the plurality of well regions 71 in a one-to-one correspondence.

[0184] More specifically, each well opening 85 penetrates the interlayer insulating layer 80 and the main surface insulating layer 79 to expose the well region 71. Each well opening 85 is formed such that the opening width narrows from the opening side toward the bottom wall side. More specifically, each well opening 85 has a wide portion and a narrow portion. The wide portion of each well opening 85 is formed in the second interlayer insulating layer 82. The narrow portion of each well opening 85 has an opening width smaller than that of the wide portion. The narrow portion of each well opening 85 is formed in the first interlayer insulating layer 81.

[0185] Referring to FIGS. 11 to 13, the first opening 86 exposes the separation lead-out portion 56a of the IGBT region 8. The first opening 86 is formed such that the opening width narrows from the opening side toward the bottom wall side. The second opening 87 exposes the anode lead-out portion 66a of the diode region 9. The second opening 87 is formed such that the opening width narrows from the opening side toward the bottom wall side. The third opening 88 exposes the well lead-out portion 75a of the boundary region 10. The third opening 88 is formed such that the opening width narrows from the opening side toward the bottom wall side.

[0186] Referring to FIGS. 8 to 10, the semiconductor device 1 includes an emitter plug electrode 91 embedded in the emitter trench 48. The emitter plug electrode 91 is electrically connected to the emitter region 46 and the contact region 49 in the emitter trench 48.

[0187] In this form, the emitter plug electrode 91 has a laminated structure including a barrier electrode layer 92 and a main electrode layer 93. The barrier electrode layer 92 is formed in a film shape along the inner wall of the emitter trench 48. The barrier electrode layer 92 partitions a recess space in the emitter trench 48.

[0188] The barrier electrode layer 92 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 92 may have a laminated structure including a titanium layer and a titanium nitride layer. In this case, the titanium nitride layer may be laminated on the titanium layer.

[0189] The main electrode layer 93 is embedded in the emitter trench 48 with the barrier electrode layer 92 interposed therebetween. More specifically, the main electrode layer 93 is embedded in the recess space partitioned by the barrier electrode layer 92 in the emitter trench 48. The main electrode layer 93 may contain tungsten.

[0190] Referring to FIG. 11, the semiconductor device 1 includes a first plug electrode 94 embedded in the first opening 86. The first plug electrode 94 is electrically connected to the separation extraction portion 56a of the IGBT region 8 in the first opening 86.

[0191] The first plug electrode 94 has a structure corresponding to that of the emitter plug electrode 91. The description of the first plug electrode 94 shall be applied mutatis mutandis to the description of the emitter plug electrode 91. For the structure corresponding to the structure described for the emitter plug electrode 91 in the first plug electrode 94, the same reference numerals are attached and the description is omitted.

[0192] Referring to FIG. 12, the semiconductor device 1 includes a second plug electrode 95 embedded in the second opening 87. The second plug electrode 95 is electrically connected to the anode lead-out portion 66a of the diode region 9 within the second opening 87.

[0193] The second plug electrode 95 has a structure corresponding to the emitter plug electrode 91. Regarding the description of the second plug electrode 95, the description of the emitter plug electrode 91 shall apply mutatis mutandis. For the structure corresponding to the structure described for the emitter plug electrode 91 in the second plug electrode 95, the same reference numerals shall be used and the description shall be omitted.

[0194] Referring to FIG. 13, the semiconductor device 1 includes a third plug electrode 96 embedded in the third opening 88. The third plug electrode 96 is electrically connected to the well lead-out portion 75a of the boundary region 10 within the third opening 88.

[0195] The third plug electrode 96 has a structure corresponding to the emitter plug electrode 91. Regarding the description of the third plug electrode 96, the description of the emitter plug electrode 91 shall apply mutatis mutandis. For the structure corresponding to the structure described for the emitter plug electrode 91 in the third plug electrode 96, the same reference numerals shall be used and the description shall be omitted.

[0196] Referring to FIGS. 7 to 13, the aforementioned emitter terminal electrode 13 is formed on the interlayer insulating layer 80. The emitter terminal electrode 13 may contain at least one of aluminum, copper, an AlSiCu (aluminum silicon copper) alloy, an AlSi (aluminum silicon) alloy, and an AlCu (aluminum copper) alloy.

[0197] The emitter terminal electrode 13 may have a single-layer structure composed of any one of these conductive materials. The emitter terminal electrode 13 may have a laminated structure in which at least two of these conductive materials are laminated in an arbitrary order. The emitter terminal electrode 13 enters the emitter opening 83, the anode opening 84, and the well opening 85 from above the interlayer insulating layer 80.

[0198] Referring to FIG. 8, the emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 at the emitter opening 83. More specifically, the emitter terminal electrode 13 is electrically connected to the emitter plug electrode 91 within the emitter opening 83. The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91.

[0199] Referring to FIG. 9, the emitter terminal electrode 13 is electrically connected to the anode region 62 and the anode isolation electrode layer 66 at the anode opening 84. More specifically, the emitter terminal electrode 13 enters the recess 67 from above the first main surface 3 within the anode opening 84.

[0200] The emitter terminal electrode 13 is electrically connected to the anode isolation electrode layer 66 within the recess 67. Also, the emitter terminal electrode 13 is electrically connected to the anode region 62 on the first main surface 3 and the sidewall of the recess 67. The emitter terminal electrode 13 forms an ohmic contact with the anode region 62.

[0201] Also, the emitter terminal electrode 13 is electrically connected to the second proximity well region 71B at the anode opening 84. The emitter terminal electrode 13 forms an ohmic contact with the second proximity well region 71B. That is, the anode region 62, the anode isolation electrode layer 66, and the second proximity well region 71B are each emitter grounded. The emitter terminal electrode 13 functions as an anode terminal electrode in the diode region 9.

[0202] Referring to FIGS. 8 and 10, the emitter terminal electrode 13 is electrically connected to a plurality of well regions 71 at a plurality of well openings 85. That is, the plurality of well regions 71 are emitter grounded.

[0203] On one hand, the emitter terminal electrode 13 faces the floating region 52 via the interlayer insulating layer 80 in the IGBT region 8. The floating region 52 is insulated from the emitter terminal electrode 13. That is, the floating region 52 is different from the well region 71 in that it is electrically formed in a floating state. A region including one or more floating regions 52 that is close to the diode region 9 and electrically connected to the emitter terminal electrode 13 in the IGBT region 8 can also be regarded as the boundary region 10.

[0204] Referring to FIGS. 11 to 13, the emitter terminal electrode 13 is electrically connected to the first plug electrode 94, the second plug electrode 95, and the third plug electrode 96, respectively. As a result, the separated extraction portion 56a, the well separation electrode layer 75, and the anode separation electrode layer 66 are each emitter grounded. That is, the region separation structure 50, the well separation structure 72, and the anode separation structure 63 are each emitter grounded.

[0205] When the emitter terminal electrode 13 is connected to a conducting wire (for example, a bonding wire), it is preferable that a pad electrode including either or both of a nickel layer and a gold layer is formed on the emitter terminal electrode 13. When the pad electrode includes a nickel layer and a gold layer, the gold layer is preferably formed on the nickel layer.

[0206] Although specific illustrations are omitted, the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17, and the open terminal electrode 18 are also formed on the interlayer insulating layer 80, similar to the emitter terminal electrode 13.

[0207] The plurality of terminal electrodes 14 to 18 may each contain at least one of aluminum, copper, an AlSiCu (aluminum silicon copper) alloy, an AlSi (aluminum silicon) alloy, and an AlCu (aluminum copper) alloy.

[0208] The plurality of terminal electrodes 14 to 18 may each have a single-layer structure made of any one of these conductive materials. The plurality of terminal electrodes 14 to 18 may each have a laminated structure in which at least two of these conductive materials are laminated in an arbitrary order.

[0209] When the plurality of terminal electrodes 14 to 18 are connected by a conducting wire (for example, a bonding wire), it is preferable that a pad electrode including either one or both of a nickel layer and a gold layer is formed on the plurality of terminal electrodes 14 to 18. When the pad electrode includes a nickel layer and a gold layer, the gold layer is preferably formed on the nickel layer.

[0210] FIG. 14 is an enlarged view of region XIV shown in FIG. 1. FIG. 15 is a circuit diagram showing the electrical structure of the region shown in FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 14.

[0211] Referring to FIGS. 14 and 15, the semiconductor device 1 includes a temperature-sensitive diode sensor 100 as an example of a temperature-sensitive device formed in the sensor region 11. The temperature-sensitive diode sensor 100 has a parallel circuit 103 including a first diode 101 and a second diode 102. The cathode of the first diode 101 is connected to the anode of the second diode 102. The anode of the first diode 101 is connected to the cathode of the second diode 102.

[0212] More specifically, the parallel circuit 103 has a form in which a first series circuit 104 including a plurality (four in this form) of first diodes 101 connected in forward series and a second series circuit 105 including a plurality (four in this form) of second diodes 102 connected in forward series are connected in reverse parallel.

[0213] Referring to FIGS. 16 and 17, the temperature-sensitive diode sensor 100 includes a polysilicon layer 106 formed on the first main surface 3. The temperature-sensitive diode sensor 100 is formed by selectively introducing n-type impurities and p-type impurities into the polysilicon layer 106. The polysilicon layer 106 may be impurity-free.

[0214] More specifically, the polysilicon layer 106 is formed on the main surface insulating layer 79. The polysilicon layer 106 has a first surface 107 on one side, a second surface 108 on the other side, and a side surface 109 connecting the first surface 107 and the second surface 108. The first surface 107 and the second surface 108 are formed in a rectangular shape (a rectangular shape in this form) in plan view. The second surface 108 of the polysilicon layer 106 is connected to the main surface insulating layer 79. The polysilicon layer 106 is electrically insulated from the semiconductor layer 2 by the main surface insulating layer 79.

[0215] The thickness of the polysilicon layer 106 may be 0.2 μm or more and 1 μm or less. The thickness of the polysilicon layer 106 may be 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0216] The temperature-sensitive diode sensor 100 includes a first circuit region 111 and a second circuit region 112 formed in the polysilicon layer 106. The first circuit region 111 and the second circuit region 112 are formed at intervals in the short side direction of the polysilicon layer 106.

[0217] In this form, the first circuit region 111 includes a plurality (four in this form) of first diode regions 113. The first diode region 113 is a region where the first diode 101 is formed. The plurality of first diode regions 113 are formed at intervals in the longitudinal direction (the first direction X in this form) of the polysilicon layer 106.

[0218] In this form, each first diode region 113 is formed in a square shape in plan view. Each first diode region 113 is partitioned into a cell shape from other regions by a slit formed in the polysilicon layer 106. Each first diode region 113 may be partitioned into a cell shape from other regions by an impurity-free region of the polysilicon layer 106.

[0219] In this form, the second circuit region 112 includes a plurality (four in this form) of second diode regions 114. The second diode region 114 is a region where the second diode 102 is formed. The plurality of second diode regions 114 are formed at intervals in the longitudinal direction (the first direction X in this form) of the polysilicon layer 106.

[0220] In this form, each second diode region 114 is formed in a square shape in plan view. Each second diode region 114 is partitioned into a cell shape from other regions by a slit formed in the polysilicon layer 106. Each second diode region 114 may be partitioned into a cell shape from other regions by an impurity-free region of the polysilicon layer 106.

[0221] Each first diode region 113 includes a p-type first anode region 115 and an n-type first cathode region 116. The first anode region 115 is formed at the center of the first diode region 113. In this form, the first anode region 115 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0222] The first anode region 115 is formed in a circular shape in plan view. The planar shape of the first anode region 115 is arbitrary. The first anode region 115 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or an elliptical shape in plan view.

[0223] The first cathode region 116 is formed along the periphery of the first anode region 115. In this form, the first cathode region 116 is formed in an annular shape surrounding the first cathode region 116 in plan view. In this form, the first cathode region 116 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0224] The first cathode region 116 is electrically connected to the first anode region 115. The first cathode region 116 is electrically connected to the first anode region 115 throughout the thickness direction of the polysilicon layer 106. The first cathode region 116 forms a pn junction with the first anode region 115. As a result, each first diode region 113 includes one first diode 101 having the first anode region 115 as an anode and the first cathode region 116 as a cathode.

[0225] Each second diode region 114 includes a p-type second anode region 117 and an n-type second cathode region 118. The second anode region 117 is formed at the center of the second diode region 114. In this form, the second anode region 117 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0226] The second anode region 117 is formed in a circular shape in plan view. The planar shape of the second anode region 117 is arbitrary. The second anode region 117 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or an elliptical shape in plan view.

[0227] The second cathode region 118 is formed along the periphery of the second anode region 117. In this form, the second cathode region 118 is formed in an annular shape surrounding the second cathode region 118 in plan view. In this form, the second cathode region 118 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0228] The second cathode region 118 is electrically connected to the second anode region 117. The second cathode region 118 is electrically connected to the second anode region 117 throughout the entire thickness direction of the polysilicon layer 106. The second cathode region 118 forms a pn junction with the second anode region 117. Thereby, each second diode region 114 includes one second diode 102 having the second anode region 117 as an anode and the second cathode region 118 as a cathode.

[0229] Referring to FIGS. 16 and 17, the above-described interlayer insulating layer 80 covers the polysilicon layer 106. The portion of the interlayer insulating layer 80 covering each first diode region 113 includes a first anode opening 121 and a first cathode opening 122. Also, the portion of the interlayer insulating layer 80 covering each second diode region 114 includes a second anode opening 123 and a second cathode opening 124.

[0230] In this form, one first anode opening 121 is formed in each first diode region 113. The number of the first anode openings 121 is arbitrary. Therefore, a plurality of first anode openings 121 may be formed at intervals in each first diode region 113.

[0231] The first anode opening 121 exposes the first anode region 115. The first anode opening 121 is formed by penetrating the interlayer insulating layer 80 and digging down the surface layer portion of the polysilicon layer 106. The bottom of the first anode opening 121 is located within the first anode region 115.

[0232] The first anode opening 121 extends in a strip shape along the periphery of the first anode region 115 in a plan view. More specifically, the first anode opening 121 is formed in an annular shape in a plan view. The planar shape of the first anode opening 121 is arbitrary. The first anode opening 121 may be formed in a polygonal annular shape such as a triangular annular shape, a square annular shape, a hexagonal annular shape, or an elliptical annular shape, or in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, a circular shape, or an elliptical shape in a plan view.

[0233] In this embodiment, the first cathode openings 122 are formed one by one in each of the first diode regions 113. The number of the first cathode openings 122 is arbitrary. Therefore, a plurality of the first cathode openings 122 may be formed in each of the first diode regions 113 at intervals.

[0234] The first cathode opening 122 exposes the first cathode region 116. The first cathode opening 122 is formed by penetrating the interlayer insulating layer 80 and digging down the surface layer portion of the polysilicon layer 106. The bottom of the first cathode opening 122 is located within the first cathode region 116.

[0235] The first cathode opening 122 extends in a strip shape along the periphery of the first anode region 115 in a plan view. The first cathode opening 122 is formed in a C shape in a plan view. The planar shape of the first cathode opening 122 is arbitrary. The first cathode opening 122 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or an elliptical shape in a plan view.

[0236] In this embodiment, the second anode openings 123 are formed one by one in each of the second diode regions 114. The number of the second anode openings 123 is arbitrary. Therefore, a plurality of the second anode openings 123 may be formed in each of the second diode regions 114 at intervals.

[0237] The second anode opening 123 exposes the second anode region 117. The second anode opening 123 is formed by penetrating the interlayer insulating layer 80 and digging down the surface layer portion of the polysilicon layer 106. The bottom of the second anode opening 123 is located within the second anode region 117.

[0238] The second anode opening 123 extends in a strip shape along the periphery of the second anode region 117 in a plan view. More specifically, the second anode opening 123 is formed in an annular shape in a plan view. The planar shape of the second anode opening 123 is arbitrary. The second anode opening 123 may be formed in a polygonal annular shape such as a triangular annular shape, a square annular shape, a hexagonal annular shape, or an elliptical annular shape, or in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or in a circular shape or an elliptical shape in a plan view.

[0239] In this form, the second cathode opening 124 is formed one by one in each second diode region 114. The number of the second cathode openings 124 is arbitrary. Therefore, a plurality of second cathode openings 124 may be formed at intervals in each second diode region 114.

[0240] The second cathode opening 124 exposes the second cathode region 118. The second cathode opening 124 is formed by penetrating the interlayer insulating layer 80 and digging down the surface layer portion of the polysilicon layer 106. The bottom of the second cathode opening 124 is located within the second cathode region 118.

[0241] The second cathode opening 124 extends in a strip shape along the periphery of the second anode region 117 in a plan view. The second cathode opening 124 is formed in a C shape in a plan view. The planar shape of the second cathode opening 124 is arbitrary. The second cathode opening 124 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or in a circular shape or an elliptical shape in a plan view.

[0242] The temperature-sensitive diode sensor 100 includes a first diode wiring 131 formed on a portion of the interlayer insulating layer 80 that covers the first circuit region 111. The first diode wiring 131 connects a plurality of first diodes 101 in forward series between the first sense wiring 20 and the second sense wiring 21. The first diode wiring 131 has one end connected to the first sense wiring 20 and the other end connected to the second sense wiring 21.

[0243] More specifically, the first diode wiring 131 includes a plurality of first anode electrodes 133, a plurality of first cathode electrodes 134, and a plurality of first connection electrodes 135. Each first anode electrode 133 is formed on a portion of the interlayer insulating layer 80 that covers the corresponding first diode region 113.

[0244] Each first anode electrode 133 is formed in a circular shape in plan view. The planar shape of each first anode electrode 133 is arbitrary. Each first anode electrode 133 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or an elliptical shape in plan view.

[0245] Each first anode electrode 133 enters the corresponding first anode opening 121 from above the interlayer insulating layer 80. Each first anode electrode 133 is electrically connected to the first anode region 115 within the corresponding first anode opening 121.

[0246] Each first cathode electrode 134 is formed on a portion of the interlayer insulating layer 80 that covers the corresponding first diode region 113. Each first cathode electrode 134 extends in a strip shape along the corresponding first anode electrode 133 in plan view.

[0247] In this form, each first cathode electrode 134 is formed in a C shape in plan view. The planar shape of each first cathode electrode 134 is arbitrary. The first cathode electrode 134 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or a circular or elliptical shape in plan view.

[0248] Each first cathode electrode 134 enters the corresponding first cathode opening 122 from above the interlayer insulating layer 80. Each first cathode electrode 134 is electrically connected to the first cathode region 116 within the corresponding first cathode opening 122.

[0249] Each first connection electrode 135 is formed on a portion covering the region between a plurality of adjacent first diode regions 113 in the interlayer insulating layer 80. Each first connection electrode 135 connects the corresponding first anode electrode 133 and first cathode electrode 134. That is, each first connection electrode 135 is drawn from the first cathode electrode 134 of one first diode region 113 and connected to the first anode electrode 133 of the other first diode region 113.

[0250] In this form, each first connection electrode 135 is formed in a strip shape extending along the longitudinal direction (the first direction X in this form) of the polysilicon layer 106 in a plan view. Each first connection electrode 135 may be routed in a line shape through the region between a plurality of adjacent first diode regions 113.

[0251] One first connection electrode 135 located on one end side in the longitudinal direction of the polysilicon layer 106 is connected to the second sense wiring 21. One first connection electrode 135 located on the other end side in the longitudinal direction of the polysilicon layer 106 is connected to the first sense wiring 20.

[0252] As a result, a first series circuit 104 including a plurality (four in this form) of first diodes 101 connected in forward series with respect to the first sense wiring 20 is formed in the region between the first sense wiring 20 and the second sense wiring 21.

[0253] The first diode wiring 131 may contain at least one of aluminum, copper, an AlSiCu (aluminum silicon copper) alloy, an AlSi (aluminum silicon) alloy, and an AlCu (aluminum copper) alloy.

[0254] The temperature-sensitive diode sensor 100 includes a second diode wiring 132 formed on a portion of the interlayer insulating layer 80 that covers the second circuit region 112. The second diode wiring 132 serially connects a plurality of second diodes 102 in forward direction between the first sense wiring 20 and the second sense wiring 21. The second diode wiring 132 has one end connected to the first sense wiring 20 and the other end connected to the second sense wiring 21.

[0255] More specifically, the second diode wiring 132 includes a plurality of second anode electrodes 136, a plurality of second cathode electrodes 137, and a plurality of second connection electrodes 138. Each second anode electrode 136 is formed on a portion of the interlayer insulating layer 80 that covers the corresponding second diode region 114.

[0256] Each second anode electrode 136 is formed in a circular shape in plan view. The planar shape of the second anode electrode 136 is arbitrary. Each second anode electrode 136 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or an elliptical shape in plan view.

[0257] Each second anode electrode 136 enters the corresponding second anode opening 123 from above the interlayer insulating layer 80. Each second anode electrode 136 is electrically connected to the second anode region 117 within the corresponding second anode opening 123.

[0258] Each second cathode electrode 137 is formed on a portion of the interlayer insulating layer 80 that covers the corresponding second diode region 114. Each second cathode electrode 137 extends in a strip shape along the second anode electrode 136 in plan view.

[0259] In this form, each second cathode electrode 137 is formed in a C shape in plan view. The planar shape of each second cathode electrode 137 is arbitrary. Each second cathode electrode 137 may be formed in a polygonal shape such as a triangular shape, a square shape, a hexagonal shape, or a circular or elliptical shape in plan view.

[0260] Each second cathode electrode 137 enters the corresponding second cathode opening 124 from above the interlayer insulating layer 80. Each second cathode electrode 137 is electrically connected to the second cathode region 118 within the corresponding second cathode opening 124.

[0261] Each second connection electrode 138 is formed on a portion covering the region between a plurality of adjacent second diode regions 114 in the interlayer insulating layer 80. Each second connection electrode 138 connects the corresponding second anode electrode 136 and second cathode electrode 137. That is, each second connection electrode 138 is drawn out from the second cathode electrode 137 of one second diode region 114 and connected to the second anode electrode 136 of the other second diode region 114.

[0262] In this form, each second connection electrode 138 is formed in a strip shape extending along the longitudinal direction (the first direction X in this form) of the polysilicon layer 106 in a plan view. Each second connection electrode 138 may be routed in a line shape through the region between a plurality of adjacent second diode regions 114.

[0263] One second connection electrode 138 located on one end side in the longitudinal direction of the polysilicon layer 106 is connected to the second sense wiring 21. One second connection electrode 138 located on the other end side in the longitudinal direction of the polysilicon layer 106 is connected to the first sense wiring 20.

[0264] Thereby, a second series circuit 105 including a plurality (four in this form) of second diodes 102 connected in forward series with respect to the second sense wiring 21 is formed in the region between the first sense wiring 20 and the second sense wiring 21.

[0265] The second diode wiring 132 may contain at least one of aluminum, copper, an AlSiCu (aluminum silicon copper) alloy, an AlSi (aluminum silicon) alloy, and an AlCu (aluminum copper) alloy.

[0266] FIG. 18 is an enlarged view of region XVIII shown in FIG. 1. FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18.

[0267] Referring to FIGS. 18 and 19, in this embodiment, the gate wiring 19 includes a low-resistance wiring portion 150, a first high-resistance wiring portion 151, and a second high-resistance wiring portion 152.

[0268] The low-resistance wiring portion 150 has a relatively low resistance value and forms the main current path of the gate wiring 19. The low-resistance wiring portion 150 is formed on the first main surface 3 (interlayer insulating layer 80) at a distance from the gate terminal electrode 14. The low-resistance wiring portion 150 is formed along the periphery of the gate terminal electrode 14 and is selectively routed on the first main surface 3 (interlayer insulating layer 80).

[0269] The low-resistance wiring portion 150 may include at least one of aluminum, copper, an AlSiCu (aluminum silicon copper) alloy, an AlSi (aluminum silicon) alloy, and an AlCu (aluminum copper) alloy. The low-resistance wiring portion 150 may be formed of the same metal material as the gate terminal electrode 14.

[0270] The first high-resistance wiring portion 151 has a resistance value exceeding that of the low-resistance wiring portion 150. The first high-resistance wiring portion 151 may include conductive polysilicon. The first high-resistance wiring portion 151 is interposed between the gate terminal electrode 14 and the low-resistance wiring portion 150 and is electrically connected to the gate terminal electrode 14 and the low-resistance wiring portion 150. The gate signal input to the gate terminal electrode 14 is transmitted to the low-resistance wiring portion 150 via the first high-resistance wiring portion 151.

[0271] More specifically, the first high-resistance wiring portion 151 is formed in the lower layer region of the gate terminal electrode 14 and the low-resistance wiring portion 150. The first high-resistance wiring portion 151 is formed in the region between the first main surface 3 and the interlayer insulating layer 80. The first high-resistance wiring portion 151 is formed on the main surface insulating layer 79.

[0272] The first high-resistance wiring portion 151 includes a first lead-out portion 151a and a second lead-out portion 151b. The first lead-out portion 151a is led out from above the main surface insulating layer 79 to the region directly below the gate terminal electrode 14. The second lead-out portion 151b is led out from above the main surface insulating layer 79 to the region directly below the low-resistance wiring portion 150.

[0273] The region covering the first high-resistance wiring portion 151 in the interlayer insulating layer 80 includes a first opening 153 and a second opening 154. The first opening 153 exposes the first lead-out portion 151a of the first high-resistance wiring portion 151. The second opening 154 exposes the second lead-out portion 151b of the second high-resistance wiring portion 152.

[0274] A first plug electrode 155 is embedded in the first opening 153. The first lead-out portion 151a is electrically connected to the gate terminal electrode 14 via the first plug electrode 155. The description of the first plug electrode 155 is applied mutatis mutandis to the description of the emitter plug electrode 91. For the structure corresponding to the structure described for the emitter plug electrode 91 in the first plug electrode 155, the same reference numerals are given and the description is omitted.

[0275] A second plug electrode 156 is embedded in the second opening 154. The second lead-out portion 151b is electrically connected to the low-resistance wiring portion 150 via the second plug electrode 156. The description of the second plug electrode 156 is applied mutatis mutandis to the description of the emitter plug electrode 91. For the structure corresponding to the structure described for the emitter plug electrode 91 in the second plug electrode 156, the same reference numerals are given and the description is omitted.

[0276] The second high-resistance wiring portion 152 has a resistance value exceeding that of the low-resistance wiring portion 150. The second high-resistance wiring portion 152 may contain conductive polysilicon. The second high-resistance wiring portion 152 is interposed in the region between the gate extraction portion 41a and the low-resistance wiring portion 150 and is electrically connected to the gate extraction portion 41a and the low-resistance wiring portion 150. The gate signal transmitted to the low-resistance wiring portion 150 is transmitted to the gate extraction portion 41a via the second high-resistance wiring portion 152.

[0277] More specifically, the second high-resistance wiring portion 152 is formed in the lower layer region of the low-resistance wiring portion 150. The second high-resistance wiring portion 152 is formed in the same layer as the gate extraction portion 41a. The second high-resistance wiring portion 152 is formed in the region between the first main surface 3 and the interlayer insulating layer 80. The second high-resistance wiring portion 152 is formed on the main surface insulating layer 79.

[0278] The second high-resistance wiring portion 152 has a lead portion 152a drawn from above the main surface insulating layer 79 to the region directly below the low-resistance wiring portion 150. Also, the second high-resistance wiring portion 152 has a connection portion continuous with the gate extraction portion 41a in a region not shown.

[0279] The region covering the second high-resistance wiring portion 152 in the interlayer insulating layer 80 includes the third opening 157. The third opening 157 exposes the lead portion 152a of the second high-resistance wiring portion 152.

[0280] A third plug electrode 158 is embedded in the third opening 157. The lead portion 152a is electrically connected to the low-resistance wiring portion 150 via the third plug electrode 158. The description of the third plug electrode 158 is applied mutatis mutandis to the description of the emitter plug electrode 91. For the structure corresponding to the structure described for the emitter plug electrode 91 in the third plug electrode 158, the same reference numerals are given and the description is omitted.

[0281] The shorter the distance between the low-resistance wiring portion 150 and the gate extraction portion 41a, the lower the wiring resistance can be reduced. The connection position of the extraction portion 152a and the low-resistance wiring portion 150 is arbitrary, but it is preferably set in consideration of the wiring resistance between the low-resistance wiring portion 150 and the gate extraction portion 41a.

[0282] As described above, the gate wiring 19 includes a first high-resistance wiring portion 151 interposed between the low-resistance wiring portion 150 and the gate terminal electrode 14. The gate signal input to the gate terminal electrode 14 is transmitted to the gate extraction portion 41a via the first high-resistance wiring portion 151, the low-resistance wiring portion 150, and the second high-resistance wiring portion 152. The gate signal transmitted to the gate extraction portion 41a is transmitted to the gate electrode 41.

[0283] The first high-resistance wiring portion 151 suppresses the inflow of an inrush current from the gate terminal electrode 14 into the low-resistance wiring portion 150. On the other hand, the low-resistance wiring portion 150 transmits the gate signal to the FET structure 35 while suppressing the voltage drop of the gate signal. Thereby, the malfunction of the FET structure 35 due to the inrush current can be suppressed. Further, since the malfunction of the FET structure 35 can be suppressed, the switching noise can also be reduced.

[0284] On the other hand, the second high-resistance wiring portion 152 suppresses the inflow of an inrush current from the low-resistance wiring portion 150 into the gate extraction portion 41a. Thereby, the malfunction of the FET structure 35 due to the inrush current can be appropriately suppressed. Further, since the malfunction of the FET structure 35 can be appropriately suppressed, the switching noise can be appropriately reduced.

[0285] FIG. 20 is a graph obtained by simulating the forward characteristics of the pn junction diode D. In FIG. 20, the vertical axis represents the current density [A·cm -2 , and the horizontal axis represents the voltage [V].

[0286] FIG. 20 shows a first characteristic A and a second characteristic B. The first characteristic A shows the forward characteristic of the semiconductor device according to the reference example. The second characteristic B shows the forward characteristic of the semiconductor device 1. The semiconductor device according to the reference example has the same structure as the semiconductor device 1 except that it does not have the boundary region 10. A specific description of the semiconductor device according to the reference example is omitted.

[0287] Referring to the first characteristic A and the second characteristic B, the forward characteristic of the semiconductor device 1 has been improved as compared with the forward characteristic of the semiconductor device according to the reference example.

[0288] FIG. 21A is a diagram showing the hole density of the semiconductor device according to the reference example examined by simulation. FIG. 21B is a diagram showing the hole current density of the semiconductor device according to the reference example examined by simulation.

[0289] FIGS. 21A and 21B show the hole density and the hole current density, respectively, when the pn junction diode D is operated in the forward direction. Also, in FIGS. 21A and 21B, regions with high density are indicated by hatching.

[0290] Referring to FIG. 21A, in the semiconductor device according to the reference example, holes are distributed at a relatively high density in the IGBT region 8 and the diode region 9. The hole density is particularly high in the region near the FET structure 35 in the IGBT region 8.

[0291] Referring to FIG. 21B, in the semiconductor device according to the reference example, a large bias is formed in the hole current density between the IGBT region 8 and the diode region 9. More specifically, the hole current density in the diode region 9 is larger than the hole current density in the IGBT region 8. In the IGBT region 8, the hole current density is relatively high in the region near the FET structure 35, but the hole current density in other regions is relatively low.

[0292] FIG. 22A is a diagram showing the hole density of the semiconductor device 1 investigated by simulation. FIG. 22B is a diagram showing the hole current density of the semiconductor device 1 investigated by simulation. FIGS. 22A and 22B show the hole density and the hole current density, respectively, when the pn junction diode D is operated in the forward direction. Also, in FIGS. 22A and 22B, regions with high density are indicated by hatching.

[0293] Referring to FIG. 22A, in the semiconductor device 1, an increase in the hole density in the diode region 9 is suppressed. Also, in the semiconductor device 1, an increase in the hole density in the region near the boundary FET structure 77 in the boundary region 10 is suppressed.

[0294] Referring to FIG. 22B, in the semiconductor device 1, the bias of the hole current density is suppressed between the boundary region 10 and the diode region 9. Such hole density and hole current density are due to holes being injected from the emitter-grounded well region 71 into the semiconductor layer 2.

[0295] Thus, in the semiconductor device 1, the emitter-grounded well region 71 can suppress the bias of the hole density and the bias of the hole current density. Also, when the pn junction diode D is operated in the forward direction, holes are also injected from the well region 71, so that the hole current density can be increased. Thereby, the forward characteristics of the semiconductor device 1 can be improved.

[0296] FIG. 23 is a graph showing the reverse recovery characteristics of the pn junction diode D investigated by simulation. In FIG. 23, the left vertical axis indicates the current density [A·cm -2 , the right vertical axis indicates the voltage [V], and the horizontal axis indicates the time [μs].

[0297] When the pn junction diode D switches from the on state to the off state, a reverse recovery current flows through the pn junction diode D, and a reverse recovery voltage is generated. In Fig. 23, the first reverse recovery current characteristic IA and the first reverse recovery voltage characteristic VA are respectively shown by dashed lines, and the second reverse recovery current characteristic IB and the second reverse recovery voltage characteristic VB are respectively shown by solid lines.

[0298] The first reverse recovery current characteristic IA and the first reverse recovery voltage characteristic VA indicate the characteristics of the pn junction diode D of the semiconductor device according to the reference example. The second reverse recovery current characteristic IB and the second reverse recovery voltage characteristic VB indicate the characteristics of the pn junction diode D of the semiconductor device 1.

[0299] Referring to the first reverse recovery current characteristic IA and the second reverse recovery current characteristic IB, the reverse recovery current of the semiconductor device 1 is lower than that of the semiconductor device according to the reference example. Also, the reverse recovery time of the semiconductor device 1 is shorter than that of the semiconductor device according to the reference example.

[0300] Referring to the first reverse recovery voltage characteristic VA and the second reverse recovery voltage characteristic VB, the reverse recovery voltage of the semiconductor device 1 becomes smaller than that of the semiconductor device according to the reference example as the reverse recovery current decreases. That is, the reverse recovery loss of the semiconductor device 1 is smaller than that of the semiconductor device according to the reference example.

[0301] Figs. 24A to 24C are diagrams showing the hole current density of the semiconductor device according to the reference example at the first measurement point P1, the second measurement point P2, and the third measurement point P3 shown in Fig. 23 by simulation. In Figs. 24A to 24C, the regions with high density are indicated by hatching.

[0302] The first measurement point P1 is the phase in which a forward current flows through the pn junction diode D after the pn junction diode D switches from the on state to the off state. The second measurement point P2 is the phase in which a reverse current flows through the pn junction diode D. The third measurement point P3 is the phase in which the reverse current peaks.

[0303] Referring to FIG. 24A, at the first measurement point P1, a forward voltage flows through the pn junction diode D, while the holes distributed in the IGBT region 8 and the diode region 9 are drawn back to the FET structure 35 and the anode region 62. In the IGBT region 8, since the drawn-back holes stay near the FET structure 35, a relatively high hole density is formed. In particular, in the IGBT region 8 where the IE structure 51 is introduced, a significant increase in the hole density due to the drawn-back holes is observed.

[0304] Referring to FIG. 24B, at the second measurement point P2, holes are staying in the IGBT region 8. The holes are staying in the region between the FET structure 35 and the collector region 34 in the semiconductor layer 2. Also, at the second measurement point P2, the formation of depletion layers is observed in the IGBT region 8 and the diode region 9. However, the formation of the depletion layer on the IGBT region 8 side is inhibited by the staying holes. Therefore, the depletion layer on the IGBT region 8 side is smaller than the depletion layer on the diode region 9 side.

[0305] Referring to FIG. 24C, at the third measurement point P3, the holes staying in the IGBT region 8 are drawn back, and the depletion layer extends to the middle part in the depth direction of the semiconductor layer 2.

[0306] FIGS. 25A to 25C are diagrams obtained by simulating the hole current density of the semiconductor device 1 at the first measurement point P1, the second measurement point P2, and the third measurement point P3 shown in FIG. 23, respectively. In FIGS. 25A to 25C, the regions with high density are indicated by hatching.

[0307] Referring to FIG. 25A, in the semiconductor device 1 at the first measurement point P1, the retention of holes is suppressed as compared with the semiconductor device according to the reference example. This is because when the pn junction diode D switches from the on state to the off state, the holes distributed in the boundary region 10 and the diode region 9 are drawn back to the boundary FET structure 77, the well region 71, and the anode region 62.

[0308] In the boundary region 10 of the semiconductor device 1, since the well region 71 is introduced, it is considered that the hole density increases. However, the well region 71 in the boundary region 10 is emitter-grounded. Therefore, during the reverse recovery operation of the pn junction diode D, the holes staying in the semiconductor layer 2 are quickly discharged by this well region 71, so the increase in the hole density is suppressed.

[0309] Referring to FIG. 25B, at the second measurement point P2, there is almost no retention of holes in the boundary region 10 and the diode region 9. In the semiconductor device 1, depletion layers are quickly formed in the boundary region 10 and the diode region 9 as the holes are discharged. Variations in the depletion layer formed in the boundary region 10 and the depletion layer formed in the diode region 9 are suppressed.

[0310] Referring to FIG. 25C, at the third measurement point P3, the depletion layer extends to the middle part in the depth direction of the semiconductor layer 2.

[0311] As described above, according to the semiconductor device 1, the IGBT region 8, the diode region 9, and the boundary region 10 are formed in the semiconductor layer 2. The IGBT region 8 and the diode region 9 are adjacent to each other. The boundary region 10 is formed in the region between the IGBT region 8 and the diode region 9.

[0312] The IGBT region 8 includes the FET structure 35 and the collector region 34. The FET structure 35 includes the body region 45, the emitter region 46, the gate insulating layer 40, and the gate electrode 41. The diode region 9 includes the cathode region 61 and the anode region 62. The boundary region 10 includes the well region 71.

[0313] The emitter region 46 of the IGBT region 8, the anode region 62 of the diode region 9, and the well region 71 of the boundary region 10 are electrically connected to the emitter terminal electrode 13. The emitter region 46 of the IGBT region 8 and the cathode region 61 of the diode region 9 are electrically connected to the collector terminal electrode 32.

[0314] Thus, during the reverse recovery operation of the pn junction diode D, holes existing in the boundary region 10 can be quickly discharged by the well region 71. As a result, the retention of holes in the boundary region 10 can be suppressed, so that the reverse recovery current can be suppressed. Therefore, the reverse recovery loss can be reduced.

[0315] Further, according to the semiconductor device 1, the boundary region 10 includes a well region 71 formed in a region overlapping with the collector region 34 in a plan view. Thereby, the accumulation of holes in the region between the well region 71 and the collector region 34 in the semiconductor layer 2 can be appropriately suppressed. Therefore, the reduction of the reverse recovery loss can be appropriately achieved.

[0316] Further, according to the semiconductor device 1, a plurality of well regions 71 are formed in the surface layer portion of the first main surface 3. The plurality of well regions 71 are electrically connected to the emitter terminal electrode 13, respectively. Thereby, holes existing in the boundary region 10 can be efficiently discharged by the plurality of well regions 71. Therefore, the reduction of the reverse recovery loss can be efficiently achieved.

[0317] Further, according to the semiconductor device 1, the boundary region 10 includes a boundary FET structure 77 formed in a region adjacent to the well region 71 on the first main surface 3. More specifically, the boundary region 10 includes a plurality of boundary FET structures 77. The plurality of boundary FET structures 77 are respectively formed in the regions between the plurality of well regions 71. Each boundary FET structure 77 has a structure corresponding to the FET structure 35 of the IGBT region 8. Thereby, in the boundary region 10, the IGBT characteristics by the boundary FET structure 77 and the hole discharge effect by the well region 71 can be obtained.

[0318] Further, according to the semiconductor device 1, the IGBT region 8 includes a floating region 52 adjacent to the FET structure 35 in the surface layer portion of the first main surface 3. The floating region 52 is electrically insulated from the emitter terminal electrode 13.

[0319] The bottom of the floating region 52 is formed in a region on the side of the second main surface 4 with respect to the bottom of the body region 45 in the normal direction Z. By forming the floating region 52 deeper than the body region 45, the pressure resistance can be improved. On the other hand, since it is not necessary to form the body region 45 deeply, the on-voltage can be reduced by shortening the channel length.

[0320] Also, according to the semiconductor device 1, the IGBT region 8 includes the region isolation structure 50. The region isolation structure 50 includes the floating region 52 and the region isolation trench structure 53. The region isolation trench structure 53 partitions the floating region 52 from the FET structure 35.

[0321] As a result, the IE structure 51 including the FET structure 35 and the region isolation structure 50 is formed in the IGBT region 8. In the IE structure 51, a plurality of FET structures 35 are formed in a manner separated by the region isolation structure 50. The FET structure 35 and the region isolation structure 50 are alternately formed along the first direction X in this form.

[0322] The region isolation structure 50 restricts the movement of holes injected into the semiconductor layer 2. That is, the holes flow into the boundary FET structure 77 by bypassing the region isolation structure 50. As a result, the hole density in the region directly below the FET structure 35 in the semiconductor layer 2 is increased. As a result, in the IGBT region 8, the on-resistance and the on-voltage can be reduced.

[0323] On the other hand, the boundary region 10 includes the well region 71 and the well isolation structure 72 formed in the same manner as the IE structure 51. According to such a structure, it is also considered that the hole density increases in the region directly below the well region 71 in the semiconductor layer 2.

[0324] However, unlike the floating region 52, the well region 71 is emitter - grounded. Therefore, during the reverse - recovery operation of the pn - junction diode D, holes trapped in the semiconductor layer 2 by this well region 71 can be quickly discharged outside the semiconductor layer 2. As a result, an increase in the hole density in the semiconductor layer 2 can be suppressed.

[0325] In the semiconductor device 1, an RC - IGBT array 12 (device region) is formed by IGBT regions 8, diode regions 9, and boundary regions 10 arranged along the first direction X. More specifically, the RC - IGBT array 12 has a loop array that repeatedly includes IGBT regions 8, boundary regions 10, diode regions 9, boundary regions 10, IGBT regions 8, boundary regions 10, diode regions 9, ···

[0326] In the semiconductor device 1, a plurality of RC - IGBT arrays 12 are formed at intervals along the second direction Y. Thereby, a plurality of different regions can be appropriately formed in a limited region of the semiconductor layer 2, and at the same time, the above - mentioned effects can be achieved in different regions of the semiconductor layer 2.

[0327] In the semiconductor device 1, a temperature - sensitive diode sensor 100 is formed in the region between two adjacent RC - IGBT arrays 12 along the second direction Y. In the region between adjacent RC - IGBT arrays 12, a gate wiring 19, a first sense wiring 20, and a second sense wiring 21 are formed.

[0328] The gate wiring 19, the first sense wiring 20, and the second sense wiring 21 run parallel along the RC - IGBT array 12. The gate wiring 19 transmits gate signals to the IGBT regions 8 of two adjacent RC - IGBT arrays 12 along the second direction Y. The first sense wiring 20 and the second sense wiring 21 transmit electrical signals to the temperature - sensitive diode sensor 100. According to this structure, the wiring formation area can be appropriately reduced. That is, by reducing the wiring formation area, the expansion of the active region 6 can be achieved.

[0329] FIG. 26 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view showing a semiconductor device 161 according to the second embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0330] Referring to FIG. 26, the boundary region 10 related to the semiconductor device 161 includes a well region 71 formed in a region overlapping the cathode region 61 of the diode region 9 in a plan view. More specifically, a part of the second proximity well region 71B among the plurality of well regions 71 is formed in a region overlapping the cathode region 61 in a plan view. A part of the second proximity well region 71B is formed in a region overlapping the collector region 34 in a plan view.

[0331] As described above, the semiconductor device 161 can also achieve the same effects as those described for the semiconductor device 1.

[0332] FIG. 27 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view showing a semiconductor device 162 according to the third embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0333] Referring to FIG. 27, the boundary region 10 related to the semiconductor device 162 includes a well region 71 formed in a region overlapping the cathode region 61 of the diode region 9 in a plan view. More specifically, the entire second proximity well region 71B among the plurality of well regions 71 is formed in a region overlapping the cathode region 61 in a plan view. The second proximity well region 71B does not overlap the collector region 34 in a plan view.

[0334] As described above, the semiconductor device 162 can also achieve the same effects as those described for the semiconductor device 1.

[0335] FIG. 28 is a cross-sectional view of a portion corresponding to FIG. 7, and is a cross-sectional view showing a semiconductor device 163 according to the fourth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0336] Referring to FIG. 28, the boundary region 10 related to the semiconductor device 163 includes a well region 71 formed in a region overlapping with the cathode region 61 of the diode region 9 in a plan view. More specifically, the entire area of the second proximity well region 71B among the plurality of well regions 71 is formed in a region overlapping with the cathode region 61 in a plan view. The second proximity well region 71B does not overlap with the collector region 34 in a plan view.

[0337] Also, a part of the well region 71 adjacent to the second proximity well region 71B is formed in a region overlapping with the cathode region 61 in a plan view. A part of the well region 71 adjacent to the second proximity well region 71B is formed in a region overlapping with the collector region 34 in a plan view.

[0338] As described above, the semiconductor device 163 can also achieve the same effects as those described for the semiconductor device 1.

[0339] FIG. 29 is a cross-sectional view of a portion corresponding to FIG. 7, and is a cross-sectional view showing a semiconductor device 164 according to the fifth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0340] Referring to FIG. 29, the boundary region 10 related to the semiconductor device 164 includes a well region 71 formed in a region overlapping with the cathode region 61 of the diode region 9 in a plan view. The boundary region 10 may include a plurality (two or more) of well regions 71 formed in a region overlapping with the cathode region 61 in a plan view.

[0341] In this form, the entire area of the second adjacent well region 71B among the plurality of well regions 71 is formed in a region that overlaps with the cathode region 61 in a plan view. The second adjacent well region 71B does not overlap with the collector region 34 in a plan view.

[0342] Also, in this form, the entire area of the well region 71 adjacent to the second adjacent well region 71B is formed in a region that overlaps with the cathode region 61 in a plan view. The well region 71 adjacent to the second adjacent well region 71B does not overlap with the collector region 34 in a plan view.

[0343] As described above, the semiconductor device 164 can achieve the same effects as those described for the semiconductor device 1.

[0344] FIG. 30 is a cross-sectional view of a portion corresponding to FIG. 10, and is a cross-sectional view showing a semiconductor device 165 according to the sixth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0345] Referring to FIG. 30, each well opening 85 according to the semiconductor device 165 exposes the entire area of the portion exposed from the first main surface 3 in the corresponding well region 71. More specifically, each well opening 85 exposes, in addition to the corresponding well region 71, the well isolation structure 72 that partitions the corresponding well region 71. Each well opening 85 exposes the boundary region isolation structure 76 including the corresponding well region 71 in a one-to-one correspondence.

[0346] Each well opening 85 may expose the emitter plug electrodes 91 formed on both sides of the boundary region isolation structure 76. Each well opening 85 may expose the upper surface of the emitter plug electrode 91 and the side surface of the emitter plug electrode 91 that faces the boundary region isolation structure 76.

[0347] The emitter terminal electrode 13 covers the entire portion exposed from the first main surface 3 in the well region 71 within each well opening 85 and is electrically connected to the well region 71. The emitter terminal electrode 13 covers the well isolation electrode layer 75 within each well opening 85 and is electrically connected to the well isolation electrode layer 75. The emitter terminal electrode 13 covers the upper surface and the side surface of the emitter plug electrode 91 within each well opening 85 and is electrically connected to the emitter plug electrode 91.

[0348] As described above, the semiconductor device 165 can achieve the same effects as those described for the semiconductor device 1.

[0349] FIG. 31 is a cross-sectional view of a portion corresponding to FIG. 7 and shows a cross-sectional view of a semiconductor device 166 according to the seventh embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0350] Referring to FIG. 31, the boundary region 10 related to the semiconductor device 166 includes one or more well regions 71 that are electrically insulated from the emitter terminal electrode 13. That is, the boundary region 10 includes a plurality of well regions 71 and one or more floating regions 52. The boundary region 10 may include one or more floating regions 52 formed in the region between the first adjacent well region 71A and the second adjacent well region 71B.

[0351] As described above, the semiconductor device 166 can achieve the same effects as those described for the semiconductor device 1.

[0352] FIG. 32 is a cross-sectional view of a portion corresponding to FIG. 7 and shows a cross-sectional view of a semiconductor device 167 according to the eighth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0353] Referring to FIG. 32, in this form, the boundary region 10 related to the semiconductor device 167 does not have a well isolation structure 72. In this form, a plurality of well regions 71 are formed at intervals along the first direction X in a plan view. The plurality of well regions 71 face each other in the lateral direction parallel to the first main surface 3 with a part of the semiconductor layer 2 interposed therebetween.

[0354] As described above, the semiconductor device 167 can also achieve the same effects as those described for the semiconductor device 1.

[0355] FIG. 33 is a cross-sectional view of a part corresponding to FIG. 7, and is a cross-sectional view showing a semiconductor device 168 according to the ninth embodiment of the present invention. Hereinafter, the structures corresponding to the structures described for the semiconductor device 1 will be denoted by the same reference numerals and the description thereof will be omitted.

[0356] Referring to FIG. 33, the boundary region 10 related to the semiconductor device 168 includes one well region 71. One well region 71 is partitioned from the IGBT region 8 and the diode region 9 by the region isolation structure 50. That is, the boundary region 10 has a structure in which the first adjacent well region 71A and the second adjacent well region 71B are integrally formed.

[0357] The entire area of one well region 71 overlaps with the collector region 34 in a plan view. One well region 71 may have a portion overlapping with the collector region 34 and a portion overlapping with the cathode region 61 in a plan view.

[0358] In this form, the anode opening 84 exposes the anode region 62 and the well region 71. The emitter terminal electrode 13 is electrically connected to the anode region 62 and the well region 71 at the anode opening 84.

[0359] As described above, the semiconductor device 168 can also achieve the same effects as those described for the semiconductor device 1.

[0360] FIG. 34 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view showing a semiconductor device 169 according to the tenth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0361] Referring to FIG. 34, the diode region 9 according to the semiconductor device 169 does not have an anode separation structure 63 in this embodiment. In this embodiment, a plurality of anode regions 62 are formed at intervals along the first direction X in a plan view.

[0362] The plurality of anode regions 62 face each other in the lateral direction parallel to the first main surface 3 with a part of the region of the semiconductor layer 2 interposed therebetween. In this embodiment, a plurality of anode openings 84 are formed in the interlayer insulating layer 80. The plurality of anode openings 84 expose the plurality of anode regions 62 in a one-to-one correspondence.

[0363] More specifically, each anode opening 84 penetrates the interlayer insulating layer 80 and the main surface insulating layer 79 and exposes the anode region 62. Each anode opening 84 is formed such that the opening width narrows from the opening side toward the bottom wall side.

[0364] More specifically, each anode opening 84 has a wide portion and a narrow portion. The wide portion of each anode opening 84 is formed in the second interlayer insulating layer 82. The narrow portion of each anode opening 84 has an opening width smaller than that of the wide portion. The narrow portion of each anode opening 84 is formed in the first interlayer insulating layer 81. The emitter terminal electrode 13 is electrically connected to the plurality of anode regions 62 at the plurality of anode openings 84.

[0365] As described above, the semiconductor device 169 can also achieve the same effects as those described for the semiconductor device 1.

[0366] FIG. 35 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view showing a semiconductor device 170 according to the 11th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0367] Referring to FIG. 35, the diode region 9 of the semiconductor device 170 includes one anode region 62. One anode region 62 is partitioned from an adjacent boundary region 10 by an anode isolation structure 63.

[0368] As described above, the semiconductor device 170 can also achieve the same effects as those described for the semiconductor device 1.

[0369] FIG. 36 is a plan view of a portion corresponding to FIG. 2, and is a plan view showing a semiconductor device 171 according to the 12th embodiment of the present invention. FIG. 37 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view for explaining the structure of the semiconductor device 171 shown in FIG. 36. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted. In FIG. 36, the collector region 34 formed in the surface layer portion of the second main surface 4 is indicated by dot-shaped hatching.

[0370] Referring to FIGS. 36 to 38, the semiconductor device 171 does not include the boundary region 10 in this embodiment. That is, the RC-IGBT array 12 includes IGBT regions 8 and diode regions 9 arranged along the first direction X in this embodiment.

[0371] More specifically, the RC-IGBT array 12 has a loop array that repeatedly includes IGBT regions 8, diode regions 9, IGBT regions 8, diode regions 9,... arranged in a row along the first direction X.

[0372] In the active region 6, a plurality (six in this form) of RC-IGBT arrays 12 having such a structure are formed at intervals in the second direction Y (see also FIG. 1). The RC-IGBT array 12 has a starting point located on the side surface 5B side and an end point located on the side surface 5D side. The starting point of the RC-IGBT array 12 may be the IGBT region 8 or the diode region 9. The end point of the RC-IGBT array 12 may be the IGBT region 8 or the diode region 9.

[0373] Referring to FIG. 37, each IGBT region 8 includes a collector region 34 formed in the surface layer portion of the second main surface 4. In this form, the collector region 34 extends from the IGBT region 8 to the diode region 9 across the boundary between the IGBT region 8 and the diode region 9. That is, the collector region 34 includes a drawn-out collector region 172 drawn from the IGBT region 8 to the diode region 9 along the first direction X.

[0374] In this form, the drawn-out collector region 172 is formed in a strip shape extending along the periphery of the diode region 9 in plan view. More specifically, the drawn-out collector region 172 is formed in an annular shape surrounding the inner region of the diode region 9 in plan view. Even more specifically, the drawn-out collector region 172 is formed in an endless shape surrounding the inner region of the diode region 9 in plan view.

[0375] In the surface layer portion of the second main surface 4 in the diode region 9, a cathode region 61 is formed in a region other than the drawn-out collector region 172. That is, in this form, the cathode region 61 is surrounded by the collector region 34 (drawn-out collector region 172) in the diode region 9.

[0376] The extraction collector region 172 overlaps the diode region 9 with a predetermined overlap width W in a plan view. The starting point of the overlap width W is set at the boundary between the IGBT region 8 and the diode region 9. In this form, the starting point of the overlap width W is set at the center of the anode separation trench 64 that is closest to the IGBT region 8 and contacts the anode region 62. The ending point of the overlap width W is set at the boundary between the extraction collector region 172 and the cathode region 61.

[0377] The ratio W / WD of the overlap width W to the width WD of the diode region 9 may be 0.001 or more and 0.5 or less. The ratio W / WD may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and 0.5 or less.

[0378] The overlap width W may be 1 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm, or 150 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less.

[0379] The overlapping width W may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, 140 μm or more and 150 μm or less, 150 μm or more and 160 μm or less, 160 μm or more and 170 μm or less, 170 μm or more and 180 μm or less, 180 μm or more and 190 μm or less, or 190 μm or more and 200 μm or less.

[0380] The extraction collector region 172 preferably faces at least one anode region 62 in the normal direction Z. The extraction collector region 172 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode regions 62.

[0381] The extraction collector region 172 preferably faces at least one anode isolation trench 64 in the normal direction Z. The extraction collector region 172 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode isolation trenches 64.

[0382] FIG. 38 is a graph showing the reverse recovery characteristics of the pn junction diode D investigated by simulation. In FIG. 38, the vertical axis represents the current density [A·cm -2 , and the horizontal axis represents the time [μs].

[0383] FIG. 38 shows a first characteristic α, a second characteristic β, and a third characteristic γ. The first characteristic α shows the reverse recovery current characteristics of the pn junction diode D when the overlap width W is 0 μm. The second characteristic β shows the reverse recovery current characteristics of the pn junction diode D when the overlap width W is 100 μm. The third characteristic γ shows the reverse recovery current characteristics of the pn junction diode D when the overlap width W is 150 μm.

[0384] Referring to the first characteristic α, the second characteristic β, and the third characteristic γ, the reverse recovery current of the pn junction diode D decreased as the overlap width W increased. Also, the reverse recovery time of the pn junction diode D became shorter as the overlap width W increased. That is, the reverse recovery loss decreased as the overlap width W increased.

[0385] FIGS. 39A to 39C are diagrams obtained by simulating the hole current density at the measurement point P shown in FIG. 36 when the overlap width W is 0 μm, 100 μm, and 150 μm, respectively. In FIGS. 39A to 39C, regions of high density are indicated by hatching.

[0386] Referring to FIG. 39A, when the overlap width W is 0 μm, during the reverse operation of the pn junction diode D, the holes being pulled back stay near the boundary between the IGBT region 8 and the diode region 9. Therefore, a relatively high hole current density is formed near the boundary between the IGBT region 8 and the diode region 9. In particular, in the IGBT region 8 where the IE structure 51 is introduced, an increase in the hole current density due to the holes being pulled back is significantly observed near the boundary between the IGBT region 8 and the diode region 9.

[0387] Referring to FIG. 39B, when the overlap width W is 100 μm, the hole current density near the boundary between the IGBT region 8 and the diode region 9 decreases compared to when the overlap width W is 0 μm. This is because the holes injected into the semiconductor layer 2 decrease near the boundary between the IGBT region 8 and the diode region 9.

[0388] Referring to FIG. 39C, when the overlap width W is 150 μm, the hole current density near the boundary between the IGBT region 8 and the diode region 9 further decreases compared to the case where the overlap width W is 100 μm.

[0389] As described above, according to the semiconductor device 171, each IGBT region 8 includes, in the surface layer portion of the second main surface 4, a collector region 34 drawn from the IGBT region 8 to the diode region 9 across the boundary between the IGBT region 8 and the diode region 9. That is, the collector region 34 includes a drawn collector region 172 drawn from the IGBT region 8 to the diode region 9 along the first direction X. The cathode region 61 of the diode region 9 is formed in a region other than the drawn collector region 172 in the surface layer portion of the second main surface 4.

[0390] Thereby, during the reverse recovery operation of the pn junction diode D, the density of holes near the boundary between the diode region 9 and the boundary region 10 can be reduced. As a result, the retention of holes near the boundary between the diode region 9 and the boundary region 10 can be suppressed, so that the reverse recovery current of the pn junction diode D can be suppressed. Therefore, the reverse recovery loss can be reduced.

[0391] Further, according to the semiconductor device 171, the drawn collector region 172 is formed in a strip shape along the periphery of the diode region 9 near the boundary between the IGBT region 8 and the diode region 9 in plan view. Thereby, the hole current density near the boundary between the IGBT region 8 and the diode region 9 can be appropriately reduced.

[0392] Further, the drawn collector region 172 is formed in an annular shape surrounding the inner region of the diode region 9 in plan view. Thereby, an undesired increase in the hole current density at the periphery of the diode region 9 can be appropriately suppressed.

[0393] FIG. 40 is a plan view of a portion corresponding to FIG. 2, and is a plan view showing a semiconductor device 173 according to the 13th embodiment of the present invention. FIG. 41 is a cross-sectional view of a portion corresponding to FIG. 9, and is a cross-sectional view for explaining the structure of the semiconductor device 173 shown in FIG. 40. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals are given and the description is omitted. In FIG. 40, the collector region 34 formed in the surface layer portion of the second main surface 4 is shown by dot-shaped hatching.

[0394] Referring to FIGS. 40 and 41, the semiconductor device 173 has a structure in which the semiconductor device 1 according to the first embodiment and the semiconductor device 171 according to the 12th embodiment are combined.

[0395] In this embodiment, the collector region 34 includes a drawn-out collector region 172 that is drawn from the IGBT region 8 across the boundary region 10 to the diode region 9 along the first direction X.

[0396] The drawn-out collector region 172 faces all the well regions 71 in the normal direction Z in the boundary region 10. Further, the drawn-out collector region 172 faces all the well isolation trenches 73 in the normal direction Z. Further, the drawn-out collector region 172 faces all the boundary FET structures 77 in the normal direction Z.

[0397] The drawn-out collector region 172 is formed in a strip shape along the periphery of the diode region 9 in plan view. More specifically, the drawn-out collector region 172 is formed in an annular shape surrounding the inner region of the diode region 9 in plan view. More specifically, the drawn-out collector region 172 is formed in an endless shape surrounding the inner region of the diode region 9 in plan view.

[0398] In the surface layer portion of the second main surface 4 in the diode region 9, a cathode region 61 is formed in a region other than the drawn-out collector region 172. That is, in this embodiment, the cathode region 61 is surrounded by the collector region 34 (drawn-out collector region 172) in the diode region 9.

[0399] The extraction collector region 172 overlaps the diode region 9 with a predetermined overlap width W in a plan view. In this form, the starting point of the overlap width W is set at the boundary between the boundary region 10 and the diode region 9. In this form, the starting point of the overlap width W is set at the center of the anode isolation trench 64 that is closest to the boundary region 10 and contacts the anode region 62. The ending point of the overlap width W is set at the boundary between the extraction collector region 172 and the cathode region 61.

[0400] The ratio W / WD of the overlap width W to the width WD of the diode region 9 may be 0.001 or more and 0.5 or less. The ratio W / WD may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and 0.5 or less.

[0401] The overlap width W may be 1 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm, or 150 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less.

[0402] The overlapping width W may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, 140 μm or more and 150 μm or less, 150 μm or more and 160 μm or less, 160 μm or more and 170 μm or less, 170 μm or more and 180 μm or less, 180 μm or more and 190 μm or less, or 190 μm or more and 200 μm or less.

[0403] The extraction collector region 172 preferably faces at least one anode region 62 in the normal direction Z. The extraction collector region 172 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode regions 62.

[0404] The extraction collector region 172 preferably faces at least one anode separation trench 64 in the normal direction Z. The extraction collector region 172 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode separation trenches 64.

[0405] As described above, according to the semiconductor device 173, the effects described for the semiconductor device 1 according to the first embodiment can be achieved. Also, according to the semiconductor device 173, the effects described for the semiconductor device 171 according to the twelfth embodiment can be achieved.

[0406] That is, according to the semiconductor device 173, during the reverse recovery operation of the pn junction diode D, holes existing in the boundary region 10 can be quickly discharged by the well region 71. As a result, the retention of holes in the boundary region 10 can be suppressed, so that the reverse recovery current can be suppressed. Consequently, the reverse recovery loss can be reduced.

[0407] Further, according to the semiconductor device 173, the collector region 34 includes a drawn collector region 172 that is drawn from the IGBT region 8 across the boundary region 10 to the diode region 9 along the first direction X. Thereby, during the reverse recovery operation of the pn junction diode D, the density of holes in the vicinity of the boundary between the diode region 9 and the boundary region 10 can be reduced. As a result, the retention of holes in the vicinity of the boundary between the diode region 9 and the boundary region 10 can be suppressed, so that the reverse recovery current can be suppressed. Therefore, the reverse recovery loss can be reduced.

[0408] In this embodiment, the structure in which the drawn collector region 172 is combined with the semiconductor device 1 according to the first embodiment has been described. However, the drawn collector region 172 may be combined with the semiconductor device 165 according to the sixth embodiment. Further, the drawn collector region 172 may be combined with the semiconductor device 166 according to the seventh embodiment.

[0409] Further, the drawn collector region 172 may be combined with the semiconductor device 167 according to the eighth embodiment. Also, the drawn collector region 172 may be combined with the semiconductor device 168 according to the ninth embodiment.

[0410] Further, the drawn collector region 172 may be combined with the semiconductor device 169 according to the tenth embodiment. Also, the drawn collector region 172 may be combined with the semiconductor device 170 according to the eleventh embodiment.

[0411] FIG. 42 is a perspective view showing an exemplary form of the semiconductor module 201.

[0412] Referring to FIG. 42, one or more semiconductor chips 202 are incorporated in the semiconductor module 201. In this form, the semiconductor module 201 has a structure in which two semiconductor chips 202 are incorporated. Hereinafter, for convenience, the two semiconductor chips 202 are referred to as a first semiconductor chip 202A and a second semiconductor chip 202B, respectively.

[0413] Any one of the semiconductor devices 1, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 173 according to the above-described first to thirteenth embodiments is applied to the first semiconductor chip 202A. Any one of the semiconductor devices 1, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 173 according to the above-described first to thirteenth embodiments is applied to the second semiconductor chip 202B.

[0414] The semiconductor module 201 includes a housing 203 that houses the first semiconductor chip 202A and the second semiconductor chip 202B. The housing 203 includes a resin case 204 and a support substrate 205. The support substrate 205 is a substrate for supporting the first semiconductor chip 202A and the second semiconductor chip 202B.

[0415] The resin case 204 includes a bottom wall 206 and side walls 207A, 207B, 207C, 207D. The bottom wall 206 is formed in a rectangular shape (a rectangular shape in this form) in a plan view seen from the normal direction thereof.

[0416] A through hole 208 is formed in the bottom wall 206. The through hole 208 is formed in a region of the bottom wall 206 that is spaced inward from the peripheral edge. The through hole 208 is formed in a rectangular shape (a rectangular shape in this form) in a plan view.

[0417] The side walls 207A to 207D are erected from the peripheral edge of the bottom wall 206 toward the side opposite to the bottom wall 206. The side walls 207A and 207C extend along the short side direction of the bottom wall 206 and face the long side direction of the bottom wall 206. The side walls 207B and 207D extend along the long side direction of the bottom wall 206 and face the short side direction of the bottom wall 206. The side walls 207A to 207D partition the opening 209 on the side opposite to the bottom wall 206. The side walls 207A to 207D partition the internal space 210 with the bottom wall 206.

[0418] At the four corners of the internal space 210, bolt insertion holes 211, 212, 213, and 214 are respectively formed. The internal space 210 is closed by a lid member (not shown). The lid member is bolted to the bolt insertion holes 211, 212, 213, and 214 by bolts.

[0419] The resin case 204 includes a plurality of terminal support portions 215, 216, 217, and 218. In this form, the plurality of terminal support portions 215 to 218 include a first terminal support portion 215, a second terminal support portion 216, a third terminal support portion 217, and a fourth terminal support portion 218.

[0420] The first terminal support portion 215 and the second terminal support portion 216 are attached to the outer wall of the side wall 207A. In this form, the first terminal support portion 215 and the second terminal support portion 216 are integrally formed with the outer wall of the side wall 207A. The first terminal support portion 215 and the second terminal support portion 216 are formed at intervals in the short side direction. The first terminal support portion 215 and the second terminal support portion 216 are formed in a block shape. The first terminal support portion 215 and the second terminal support portion 216 protrude outward in the long side direction from the outer wall of the side wall 207A.

[0421] The third terminal support portion 217 and the fourth terminal support portion 218 are attached to the outer wall of the side wall 207C. In this form, the third terminal support portion 217 and the fourth terminal support portion 218 are integrally formed with the outer wall of the side wall 207C. The third terminal support portion 217 and the fourth terminal support portion 218 are formed at intervals in the short direction. The third terminal support portion 217 and the fourth terminal support portion 218 are formed in a block shape. The third terminal support portion 217 and the fourth terminal support portion 218 project outward in the longitudinal direction from the outer wall of the side wall 207C.

[0422] The first terminal support portion 215, the second terminal support portion 216, the third terminal support portion 217, and the fourth terminal support portion 218 each have a support wall 219. The support wall 219 is located in a region closer to the opening 209 than the bottom wall 206. Each support wall 219 is formed in a rectangular shape in plan view.

[0423] A first bolt insertion hole 221 is formed in the region between the first terminal support portion 215 and the second terminal support portion 216. A second bolt insertion hole 222 is formed in the region between the third terminal support portion 217 and the fourth terminal support portion 218.

[0424] The support substrate 205 includes a heat dissipation plate 225, an insulating material 226, and a circuit portion 227. The support substrate 205 is attached to the outer surface of the resin case 204 such that the circuit portion 227 is exposed from the through hole 208 of the bottom wall 206. The support substrate 205 may be attached to the outer surface of the resin case 204 by adhering the heat dissipation plate 225 to the outer surface of the resin case 204.

[0425] The heat dissipation plate 225 may be a metal plate. The heat dissipation plate 225 may be an insulating plate coated with a metal film. The heat dissipation plate 225 is formed in a rectangular shape (a rectangular shape in this form) in plan view as viewed from its normal direction.

[0426] The insulating material 226 is formed on the heat sink 225. The insulating material 226 may be a mounting substrate containing an insulating material. The insulating material 226 may be an insulating film formed in a film shape on the heat sink 225.

[0427] The circuit section 227 is formed on the heat sink 225 via the insulating material 226. The circuit section 227 includes a plurality of wirings 231, 232, 233, a first semiconductor chip 202A, and a second semiconductor chip 202B. In this form, the wirings 231 to 233 include a first collector wiring 231, a second collector wiring 232, and an emitter wiring 233.

[0428] The first collector wiring 231 is formed in a plate shape or a film shape. The first collector wiring 231 is formed in a rectangular shape in a plan view. The first collector wiring 231 is disposed in regions on one side in the longitudinal direction (side wall 207A side) and one side in the short direction (side wall 207D side) of the heat sink 225.

[0429] The second collector wiring 232 is formed in a plate shape or a film shape. The second collector wiring 232 is formed in a rectangular shape in a plan view. The second collector wiring 232 is disposed in regions on the other side in the longitudinal direction (side wall 207C side) and one side in the short direction (side wall 207D side) of the heat sink 225, spaced apart from the first collector wiring 231.

[0430] The emitter wiring 233 is formed in a plate shape or a film shape. The emitter wiring 233 is formed in a rectangular shape in a plan view. The emitter wiring 233 is disposed in a region on the other side in the short direction (side wall 207B side) of the heat sink 225, spaced apart from the first collector wiring 231 and the second collector wiring 232. In this form, the emitter wiring 233 is formed in a rectangular shape extending along the longitudinal direction of the heat sink 225.

[0431] The first semiconductor chip 202A is disposed on the first collector wiring 231 in a posture where the collector terminal electrode 32 faces the heat sink. The collector terminal electrode 32 of the first semiconductor chip 202A is joined to the first collector wiring 231 via a conductive bonding material. The collector terminal electrode 32 of the first semiconductor chip 202A is electrically connected to the first collector wiring 231. The conductive bonding material may include solder or a conductive paste.

[0432] The second semiconductor chip 202B is disposed on the second collector wiring 232 in a posture where the collector terminal electrode 32 faces the heat sink. The collector terminal electrode 32 of the second semiconductor chip 202B is joined to the second collector wiring 232 via a conductive bonding material. The collector terminal electrode 32 of the second semiconductor chip 202B is electrically connected to the second collector wiring 232. The conductive bonding material may include solder or a conductive paste.

[0433] The semiconductor module 201 includes a plurality of terminals 234, 235, 236, 237. The plurality of terminals 234 to 237 include a collector terminal 234, a first emitter terminal 235, a common terminal 236, and a second emitter terminal 237.

[0434] The collector terminal 234 is disposed on the first terminal support portion 215. The collector terminal 234 is electrically connected to the first collector wiring 231. The collector terminal 234 includes a first region 238 and a second region 239. The first region 238 of the collector terminal 234 is located outside the internal space 210. The second region 239 of the collector terminal 234 is located inside the internal space 210.

[0435] The first region 238 of the collector terminal 234 is supported by the support wall 219 of the first terminal support portion 215. The second region 239 of the collector terminal 234 is drawn out from the first region 238 through the side wall 207A into the internal space 210. The second region 239 of the collector terminal 234 is electrically connected to the first collector wiring 231.

[0436] The first emitter terminal 235 is disposed on the second terminal support portion 216. The first emitter terminal 235 is electrically connected to the emitter wiring 233. The first emitter terminal 235 includes a first region 240 and a second region 241. The first region 240 of the first emitter terminal 235 is located outside the internal space 210. The second region 241 of the first emitter terminal 235 is located inside the internal space 210.

[0437] The first region 240 of the first emitter terminal 235 is supported by the support wall 219 of the second terminal support portion 216. The second region 241 of the first emitter terminal 235 is drawn out from the first region 240 through the side wall 207A into the internal space 210. The second region 241 of the first emitter terminal 235 is electrically connected to the emitter wiring 233.

[0438] The common terminal 236 is disposed on the third terminal support portion 217. The common terminal 236 is electrically connected to the second collector wiring 232. The common terminal 236 includes a first region 242 and a second region 243. The first region 242 of the common terminal 236 is located outside the internal space 210. The second region 243 of the common terminal 236 is located inside the internal space 210.

[0439] The first region 242 of the common terminal 236 is supported by the support wall 219 of the second terminal support portion 216. The second region 243 of the common terminal 236 is drawn out from the first region 240 through the side wall 207C into the internal space 210. The second region 243 of the common terminal 236 is electrically connected to the second collector wiring 232.

[0440] The second emitter terminal 237 is disposed on the fourth terminal support portion 218. The second emitter terminal 237 is electrically connected to the emitter wiring 233. The second emitter terminal 237 includes a first region 244 and a second region 245. The first region 244 of the second emitter terminal 237 is located outside the internal space 210. The second region 245 of the second emitter terminal 237 is located inside the internal space 210.

[0441] The first region 244 of the second emitter terminal 237 is supported by the support wall 219 of the fourth terminal support portion 218. The second region 245 of the second emitter terminal 237 is drawn out into the internal space 210 through the side wall 207C from the first region 244. The second region 245 of the second emitter terminal 237 is electrically connected to the emitter wiring 233.

[0442] The semiconductor module 201 includes a plurality (six in this form) of side wall terminals 246A to 246H. The plurality of side wall terminals 246A to 246H are arranged at intervals along the side wall 207D in the internal space 210.

[0443] The plurality of side wall terminals 246A to 246H each include an internal connection portion 247 and an external connection portion 248. The internal connection portion 247 is arranged on the bottom wall 206. The external connection portion 248 extends linearly along the side wall 207D from the internal connection portion 247 and is drawn out of the internal space 210.

[0444] The plurality of side wall terminals 246A to 246H include three side wall terminals 246A to 246D for the first semiconductor chip 202A and three side wall terminals 246E to 246H for the second semiconductor chip 202B.

[0445] The side wall terminals 246A to 246D face the first collector wiring 231 along the short side direction. The side wall terminal 246A is formed as a gate terminal connected to the gate terminal electrode 14 of the first semiconductor chip 202A.

[0446] The side wall terminals 246B to 246D are respectively formed as terminals connected to the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the first semiconductor chip 202A. At least one of the side wall terminals 246B to 246D may be an open terminal.

[0447] The side wall terminals 246E to 246H face the second collector wiring 232 along the short side direction. The side wall terminal 246E is formed as a gate terminal connected to the gate terminal electrode 14 of the second semiconductor chip 202B.

[0448] The side wall terminals 246F to 246H are respectively formed as terminals connected to the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the second semiconductor chip 202B. At least one of the side wall terminals 246F to 246H may be an open terminal.

[0449] The semiconductor module 201 includes a plurality of conductive wires 249A to 249J. The plurality of conductive wires 249A to 249J may each contain at least one of gold, silver, copper, or aluminum. The conductive wires 249A to 249J may each contain a bonding wire. The conductive wires 249A to 249J may each contain a conductive plate.

[0450] The plurality of conductive wires 249A to 249J includes a first conductive wire 249A, a second conductive wire 249B, a third conductive wire 249C, a fourth conductive wire 249D, a fifth conductive wire 249E, a sixth conductive wire 249F, a seventh conductive wire 249G, an eighth conductive wire 249H, a ninth conductive wire 249I, and a tenth conductive wire 249J.

[0451] The first conductive wire 249A connects the collector terminal 234 and the first collector wiring 231. The second conductive wire 249B connects the first emitter terminal 235 and the emitter wiring 233. The third conductive wire 249C connects the common terminal 236 and the second collector wiring 232.

[0452] The fourth conductive wire 249D connects the second emitter terminal 237 and the emitter wiring 233. The fifth conductive wire 249E connects the emitter terminal electrode 13 of the first semiconductor chip 202A and the second collector wiring 232. The sixth conductive wire 249F connects the emitter terminal electrode 13 of the second semiconductor chip 202B and the emitter wiring 233.

[0453] The seventh conductor 249G connects the gate terminal electrode 14 and the sidewall terminal 246A of the first semiconductor chip 202A. The eighth conductor 249H connects the gate terminal electrode 14 and the sidewall terminal 246E of the second semiconductor chip 202B.

[0454] The ninth conductor 249I connects the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the first semiconductor chip 202A to the sidewall terminals 246B to 246D. The tenth conductor 249J connects the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the second semiconductor chip 202B to the sidewall terminals 246F to 246H.

[0455] FIG. 43 is a circuit diagram showing the electrical structure of the semiconductor module 201 shown in FIG. 42.

[0456] Referring to FIG. 43, the semiconductor module 201 includes a half-bridge circuit 250. The half-bridge circuit 250 includes a first semiconductor chip 202A and a second semiconductor chip 202B. The first semiconductor chip 202A constitutes the high-voltage side arm of the half-bridge circuit 250. The second semiconductor chip 202B constitutes the low-voltage side arm of the half-bridge circuit 250.

[0457] A gate terminal (sidewall terminal 246A) is connected to the gate terminal electrode 14 of the first semiconductor chip 202A. A collector terminal 234 is connected to the collector terminal electrode 32 of the first semiconductor chip 202A.

[0458] The collector terminal electrode 32 of the second semiconductor chip 202B is connected to the emitter terminal electrode 13 of the first semiconductor chip 202A. A common terminal 236 is connected to the connection portion of the emitter terminal electrode 13 of the first semiconductor chip 202A and the collector terminal electrode 32 of the second semiconductor chip 202B.

[0459] A gate terminal (side wall terminal 246D) is connected to the gate terminal electrode 14 of the second semiconductor chip 202B. A first emitter terminal 235 (second emitter terminal 237) is connected to the emitter terminal electrode 13 of the second semiconductor chip 202B.

[0460] A gate driver IC or the like may be connected to the gate terminal electrode 14 of the first semiconductor chip 202A via a gate terminal (side wall terminal 246A). A gate driver IC or the like may be connected to the gate terminal electrode 14 of the second semiconductor chip 202B via a gate terminal (side wall terminal 246D).

[0461] The semiconductor module 201 may be an inverter module that drives any one of the U-phase, V-phase, and W-phase in a three-phase motor having the U-phase, V-phase, and W-phase. An inverter device for driving the three-phase motor may be configured by three semiconductor modules 201 corresponding to the U-phase, V-phase, and W-phase of the three-phase motor.

[0462] In this case, a DC power supply is connected to the collector terminal 234 and the first emitter terminal 235 (second emitter terminal 237) of each semiconductor module 201. Also, any one of the U-phase, V-phase, and W-phase of the three-phase motor is connected as a load to the common terminal 236 of each semiconductor module 201. In the inverter device, the first semiconductor chip 202A and the second semiconductor chip 202B are driven and controlled in a predetermined switching pattern. Thereby, the DC voltage is converted into a three-phase AC voltage, and the three-phase motor is driven in a sine wave.

[0463] The present invention can also be implemented in other forms.

[0464] In each of the above-described embodiments, the semiconductor layer 2 may have a stacked structure including a p-type semiconductor substrate and an n - type epitaxial layer formed on the semiconductor substrate, instead of the n-type semiconductor substrate 31. -

[0465] The p-type semiconductor substrate and n - ​The epitaxial layers of any type may all be made of silicon. n - The n-type epitaxial layer is formed by epitaxially growing silicon from the main surface of a p-type semiconductor substrate. In this case, the p-type semiconductor substrate corresponds to the collector region 34. Also, the n - -type epitaxial layer corresponds to the drift region.

[0466] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be formed as an n-type, and the n-type portion may be formed as a p-type.

[0467] Examples of the features extracted from this specification and the drawings are shown below.

[0468] [A1] A semiconductor device including a first-conductivity-type semiconductor layer including a first main surface on one side and a second main surface on the other side, a first-impurity region of a second conductivity type formed in a surface layer portion of the first main surface, and a second-impurity region of a first conductivity type formed in a surface layer portion of the second main surface, a diode region, a body region of a second conductivity type formed on the first main surface, an emitter region of a first conductivity type formed in a surface layer portion of the body region, and a gate electrode facing the body region and the emitter region via a gate insulating layer, and an IGBT region including a collector region of a second conductivity type formed in a surface layer portion of the second main surface and drawn out to the diode region.

[0469] According to this semiconductor device, during the reverse recovery operation of the diode, the carrier density in the vicinity of the boundary between the IGBT region and the diode region can be reduced. As a result, the carrier retention in the vicinity of the boundary between the IGBT region and the diode region can be suppressed, so that the reverse recovery current can be suppressed. Consequently, the reverse recovery loss can be reduced.

[0470] [A2]On the first main surface, a first main surface electrode electrically connected to the emitter region and the first impurity region; and on the second main surface, a second main surface electrode electrically connected to the collector region and the second impurity region. The semiconductor device according to A1, further comprising the above.

[0471] [A3]The extraction region of the collector region faces the first impurity region of the diode region in the normal direction of the first main surface. The semiconductor device according to A1 or A2.

[0472] [A4]The diode region includes a plurality of the first impurity regions, and the extraction region of the collector region faces at least one of the first impurity regions in the normal direction of the first main surface. The semiconductor device according to any one of A1 to A3.

[0473] [A5]The diode region includes trenches formed in the regions between the plurality of the first impurity regions so as to partition the first impurity regions, and the extraction region of the collector region faces the trenches in the normal direction of the first main surface. The semiconductor device according to A4.

[0474] [A6]The diode region includes a plurality of the trenches, and the extraction region of the collector region faces at least one of the trenches in the normal direction of the first main surface. The semiconductor device according to A5.

[0475] [A7]In a plan view, the overlapping width of the extraction region of the collector region with respect to the diode region is 1 μm or more and 200 μm or less. The semiconductor device according to any one of A1 to A6.

[0476] [A8]Further including a boundary region having a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer in the region between the IGBT region and the diode region and electrically connected to the emitter region. The semiconductor device according to any one of A1 to A7.

[0477] According to this semiconductor device, during the reverse recovery operation of the diode, carriers existing in the boundary region can be quickly discharged by the well region. As a result, the retention of carriers in the boundary region can be suppressed, so that the reverse recovery current can be suppressed. Consequently, the reverse recovery loss can be reduced.

[0478] [A9] The extraction region of the collector region is drawn out to the diode region across the boundary region and faces the well region in the normal direction of the first main surface. The semiconductor device according to A8.

[0479] According to this semiconductor device, during the reverse recovery operation of the diode, the density of carriers in the boundary region and in the vicinity of the boundary between the boundary region and the diode region can be reduced. As a result, the retention of carriers in the boundary region and in the vicinity of the boundary between the boundary region and the diode region can be suppressed, so that the reverse recovery current can be suppressed. Consequently, the reverse recovery loss can be reduced.

[0480] [A10] The boundary region includes a boundary body region of a second conductivity type formed in the surface layer portion of the first main surface, a boundary emitter region of a first conductivity type formed in the surface layer portion of the boundary body region, and a boundary gate electrode facing the boundary body region and the boundary emitter region via a boundary gate insulating layer, and includes a boundary FET structure formed in a region adjacent to the well region on the first main surface. The extraction region of the collector region faces the boundary FET structure in the normal direction of the first main surface. The semiconductor device according to A8 or A9.

[0481] [A11] In the boundary region, the well region is partitioned from the boundary FET structure by a well isolation trench formed on the first main surface. The extraction region of the collector region faces the well isolation trench along the normal direction of the first main surface. The semiconductor device according to A10.

[0482] [A12]A semiconductor device according to A8 or A9, wherein a plurality of said well regions are formed in a surface layer portion of said first main surface, and said extraction region of said collector region faces a plurality of said well regions in a direction normal to said first main surface.

[0483] [A13]A semiconductor device according to A12, wherein said boundary region includes a boundary body region of a second conductivity type formed in a surface layer portion of said first main surface, a boundary emitter region of a first conductivity type formed in a surface layer portion of said boundary body region, and a boundary gate electrode facing said boundary body region and said boundary emitter region via a boundary gate insulating layer, and includes a boundary FET structure formed in a region between a plurality of said well regions on said first main surface, and said extraction region of said collector region faces said boundary FET structure in a direction normal to said first main surface.

[0484] [A14]A semiconductor device according to A13, wherein said well region is partitioned from said boundary FET structure by a well isolation trench formed in said first main surface, and said extraction region of said collector region faces said well isolation trench in a direction normal to said first main surface.

[0485] [A15]A semiconductor device according to any one of A8 to A14, wherein said IGBT region, said boundary region, said diode region, said boundary region, and said IGBT region are formed in this order along one direction in a plan view.

[0486] [A16]A semiconductor device according to any one of A7 to A15, wherein said diode region, said boundary region, said IGBT region, said boundary region, and said diode region are formed in this order along one direction in a plan view.

[0487] [A17]A semiconductor device according to any one of A1 to A16, wherein said IGBT region includes a floating region of a second conductivity type formed in a region adjacent to said FET structure in a surface layer portion of said first main surface.

[0488] [A18]The IGBT region includes a plurality of the FET structures and a floating region formed in a region between the plurality of the FET structures in a surface layer portion of the first main surface, the semiconductor device according to A17.

[0489] [A19]The floating region is formed in an electrically floating state, the semiconductor device according to A17 or A18.

[0490] [A20]The floating region is partitioned from the FET structure by a region isolation trench formed in the first main surface, the semiconductor device according to any one of A17 to A19.

[0491] [A21]The gate electrode faces the body region and the emitter region with the gate insulation therebetween in a gate trench formed in the first main surface, the semiconductor device according to any one of A1 to A20.

[0492] [B1]A first-conductivity-type semiconductor layer including a first main surface on one side and a second main surface on the other side, a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a FET structure including a gate electrode facing the body region and the emitter region via a gate insulation layer, and an IGBT region including a second-conductivity-type collector region formed in a surface layer portion of the second main surface, a second-conductivity-type first impurity region formed in a surface layer portion of the first main surface, and a diode region including a first-conductivity-type second impurity region formed in a surface layer portion of the second main surface, and a boundary region including a second-conductivity-type well region formed in a surface layer portion of the first main surface in a region between the IGBT region and the diode region, and a first main surface electrode electrically connected to the emitter region, the first impurity region, and the well region on the first main surface, wherein a trench partitioning the diode region and the boundary region is provided, one end of the trench is in contact with the diode region, and only the second-conductivity-type well region of the boundary region is in contact with the other end of the trench, the semiconductor device.

[0493] [B2] The semiconductor device according to B1, further including a second main surface electrode electrically connected to the collector region and the second impurity region on the second main surface.

[0494] [B3] The semiconductor device according to B1 or B2, wherein the boundary region includes the well region formed in a region overlapping the collector region in a plan view.

[0495] [B4] The semiconductor device according to any one of B1 to B3, wherein the boundary region includes the well region formed in a region not overlapping the second impurity region in a plan view.

[0496] [B5] The semiconductor device according to any one of B1 to B4, wherein the boundary region includes a boundary body region of a second conductivity type formed in a surface layer portion of the first main surface, a boundary emitter region of a first conductivity type formed in a surface layer portion of the boundary body region, and a boundary gate electrode facing the boundary body region and the boundary emitter region via a boundary gate insulating layer, and includes a boundary FET structure formed in a region adjacent to the well region on the first main surface.

[0497] [B6] The semiconductor device according to B5, wherein a plurality of the well regions are formed in a surface layer portion of the first main surface, and the boundary FET structure is formed in a region between the plurality of the well regions in the surface layer portion of the first main surface.

[0498] [B7] The semiconductor device according to B5 or B6, wherein the well region is partitioned from the boundary FET structure by a region isolation trench formed on the first main surface.

[0499] [B8] The semiconductor device according to any one of B5 to B7, wherein the IGBT region includes a floating region of a second conductivity type formed adjacent to the FET structure in a surface layer portion of the first main surface.

[0500] [B9]The semiconductor device according to B8, wherein the IGBT region includes a plurality of the FET structures formed at intervals and the floating region formed in a region between the plurality of the FET structures in a surface layer portion of the first main surface.

[0501] [B10]The semiconductor device according to B8 or B9, wherein the floating region is electrically separated from the first main surface electrode.

[0502] [B11]The semiconductor device according to any one of B8 to B10, wherein the gate electrode faces the body region and the emitter region through the gate insulating layer in a gate trench formed in the first main surface.

[0503] [B12]The semiconductor device according to any one of B8 to B11, wherein the floating region is partitioned from the FET structure by a region isolation trench formed in the first main surface.

[0504] [B13]The semiconductor device according to any one of B1 to B4, wherein the IGBT region includes a floating region of a second conductivity type formed adjacent to the FET structure in a surface layer portion of the first main surface.

[0505] [B14]The semiconductor device according to B13, wherein the IGBT region includes a plurality of the FET structures formed at intervals and the floating region formed in a region between the plurality of the FET structures in a surface layer portion of the first main surface.

[0506] [B15]The semiconductor device according to B13 or B14, wherein the floating region is electrically separated from the first main surface electrode.

[0507] [B16]The semiconductor device according to any one of B13 to B15, wherein the gate electrode faces the body region and the emitter region through the gate insulating layer in a gate trench formed in the first main surface.

[0508] [B17] The semiconductor device according to any one of B13 to B16, wherein the floating region is partitioned from the FET structure by a region isolation trench formed on the first main surface.

[0509] [B18] The semiconductor device according to any one of B1 to B17, wherein the IGBT region, the boundary region, the diode region, the boundary region, and the IGBT region are formed in this order along one direction in a plan view.

[0510] [B19] The semiconductor device according to any one of B1 to B18, wherein the diode region, the boundary region, the IGBT region, the boundary region, and the diode region are formed in this order along one direction in a plan view.

[0511] This application corresponds to Japanese Patent Application No. 2018-103900 filed with the Japan Patent Office on May 30, 2018, and the entire disclosure of this application is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims.

Explanation of Reference Numerals

[0512] 1 Semiconductor device 2 Semiconductor layer 3 First main surface 4 Second main surface 8 IGBT region 9 Diode region 10 Boundary region 34 Collector region 35 FET structure 39 Gate trench 40 Gate insulating layer 41 Gate electrode 45 Body region 46 Emitter region 52 Floating region 54 Region isolation trench 71 Well region 77 Boundary FET structure 161 Semiconductor device 162 Semiconductor device 163 Semiconductor device 164 Semiconductor device 165 Semiconductor device 166 Semiconductor device 167 Semiconductor device 168 Semiconductor device 169 Semiconductor device 170 Semiconductor device 171 Semiconductor device 173 Semiconductor device Z normal direction

Claims

1. A semiconductor layer including a first main surface on one side and a second main surface on the other side, a FET structure including a body region of a first conductivity type formed in a surface layer portion of the first main surface, an emitter region of a second conductivity type formed in a surface layer portion of the body region, and a gate electrode facing the body region and the emitter region via a gate insulating layer, and an IGBT region including a collector region of the first conductivity type formed in a surface layer portion of the second main surface, a diode region including a first impurity region of the first conductivity type formed in a surface layer portion of the first main surface and a second impurity region of the second conductivity type formed in a surface layer portion of the second main surface, a boundary region including a well region of the first conductivity type formed in a surface layer portion of the first main surface in a region between the IGBT region and the diode region, a trench formed on the first main surface in a region between the diode region and the boundary region so as to partition the diode region and the boundary region, having one end on the diode region side and the other end on the well region side, a first main surface electrode electrically connected to the emitter region, the first impurity region, and the well region on the first main surface, the diode region is formed adjacent to the one end side of the trench, the well region is formed adjacent to the other end side of the trench, a side wall of the other end of the trench exposes the well region from an upper end of the trench to a predetermined depth position, A semiconductor device in which the IGBT region, the boundary region, the diode region, the boundary region, and the IGBT region are formed in this order along one direction in a plan view.

2. The semiconductor device according to claim 1, further including a second main surface electrode electrically connected to the collector region and the second impurity region on the second main surface.

3. The semiconductor device according to claim 1 or 2, wherein the well region is formed in a region overlapping the collector region in a thickness direction of the semiconductor layer in a cross-sectional view.

4. The semiconductor device according to any one of claims 1 to 3, wherein the well region is formed in a region not overlapping the second impurity region in a thickness direction of the semiconductor layer in a cross-sectional view.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first impurity region is formed in a region that does not overlap with the collector region in the thickness direction of the semiconductor layer in a cross-sectional view.

6. The boundary region includes a boundary body region of a first conductivity type formed in a surface layer portion of the first main surface, a boundary emitter region of a second conductivity type formed in a surface layer portion of the boundary body region, and a boundary gate electrode facing the boundary body region and the boundary emitter region via a boundary gate insulating layer, and includes a boundary FET structure formed in a region adjacent to the well region on the first main surface. The semiconductor device according to any one of claims 1 to 5.

7. The semiconductor device according to claim 6, further comprising a second well region of a first conductivity type formed in a region on the first main surface opposite to the trench with respect to the well region, with a space therebetween, and the boundary FET structure is formed in a region between the well region and the second well region in a surface layer portion of the first main surface.

8. The semiconductor device according to claim 6 or 7, wherein the well region is partitioned from the boundary FET structure by a region isolation trench formed on the first main surface.

9. The semiconductor device according to any one of claims 6 to 8, wherein the IGBT region includes a floating region of a first conductivity type formed in a surface layer portion of the first main surface adjacent to the FET structure.

10. The semiconductor device according to claim 9, wherein the IGBT region includes a plurality of the FET structures formed with a space therebetween, and the floating region formed in a region between the plurality of the FET structures in a surface layer portion of the first main surface.

11. The semiconductor device according to claim 9 or 10, wherein the floating region is electrically separated from the first main surface electrode.

12. The semiconductor device according to any one of claims 9 to 11, wherein the gate electrode faces the body region and the emitter region via the gate insulating layer in a gate trench formed on the first main surface.

13. The semiconductor device according to any one of claims 9 to 12, wherein the floating region is partitioned from the FET structure by a region isolation trench formed on the first main surface.

14. The semiconductor device according to any one of claims 1 to 5, wherein the IGBT region includes a floating region of a first conductivity type formed adjacent to the FET structure in a surface layer portion of the first main surface.

15. The semiconductor device according to claim 14, wherein the IGBT region includes a plurality of the FET structures formed on the first main surface side with a space therebetween, and the floating region formed in a region between the plurality of the FET structures in a surface layer portion of the first main surface.

16. The semiconductor device according to claim 14 or 15, wherein the floating region is electrically separated from the first main surface electrode.

17. The semiconductor device according to any one of claims 14 to 16, wherein the gate electrode faces the body region and the emitter region through the gate insulating layer in a gate trench formed on the first main surface.

18. The semiconductor device according to any one of claims 14 to 17, wherein the floating region is partitioned from the FET structure by a region isolation trench formed on the first main surface.

19. The semiconductor device according to any one of claims 1 to 18, wherein the diode region, the boundary region, the IGBT region, the boundary region, and the diode region are formed in this order along one direction in a plan view.

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