Memory circuit, dynamic random access memory, and method of operating the same

Abstract

To provide a dynamic random access memory.SOLUTION: A dynamic random access memory includes a storage diode and a controlled field effect transistor. The storage diode consists of a field effect transistor with a floating gate, and the two sources / drains of the field-effect transistor, whose gate is floating, serve as the cathode and anode of the storage diode, respectively. The control field effect transistor is electrically connected to the cathode or the anode of the storage diode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory circuit and an operation method thereof, and particularly to a memory circuit, a dynamic random access memory, and an operation method thereof.

Background Art

[0002] Due to the progress of Moore's law, various embedded memories have come to be mass-produced at a foundry. Semiconductor memories are widely used in various electronic products in many application fields.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, due to the increasing cost and difficulty of high aspect ratio stacked capacitor technology that uses more photomasks in the back end of line (BEOL), the development of dynamic random access memories (eDRAMs) incorporating one transistor and one capacitor (1T1C) has been halted for more advanced processes. Therefore, based on the above reasons, new dynamic random access memories are needed to adapt to the increasingly miniaturized manufacturing processes.

Means for Solving the Problems

[0004] The present invention provides a memory circuit, a dynamic random access memory, and an operation method thereof that improve the problems of the prior art.

[0005] In one embodiment of the present invention, the dynamic random access memory according to the present invention is composed of a field effect transistor with a floating gate, and two source / drains of the field effect transistor with a floating gate are respectively a storage diode serving as a cathode and an anode, and a control field effect transistor electrically connected to the cathode or anode of the storage diode.

[0006] In one embodiment of the present invention, the control field effect transistor includes a first gate, a first source / drain region, a second source / drain region, a first channel region, and a first dielectric layer region. The first source / drain region and the second source / drain region are respectively located on opposite sides of the first gate, the first channel region is located between the first source / drain region and the second source / drain region, and the first dielectric layer region is located between the first gate and the first channel region.

[0007] In one embodiment of the present invention, the control field effect transistor and the storage diode share the second source / drain region, and the storage diode includes a second gate, a second source / drain region, a third source / drain region, a second channel region, and a second dielectric layer region. The second source / drain region and the third source / drain region are respectively located on opposite sides of the second gate. The second channel region is located between the second source / drain region and the third source / drain region, and the second dielectric layer region is located between the second gate and the second channel region.

[0008] In one embodiment of the present invention, the third source / drain region is electrically connected to the selection line, and the second gate is floating.

[0009] In one embodiment of the present invention, the first source / drain region is electrically connected to the bit line, and the first gate is electrically connected to the word line.

[0010] In one embodiment of the present invention, the memory circuit according to the present invention is arranged in an array, each including a dynamic random access memory, and the dynamic random access memory includes a plurality of memory units including a control field effect transistor and a storage diode. The gate of the control field effect transistor is electrically connected to the word line, the storage diode is composed of a field effect transistor with a floating gate, and both opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to the bit line.

[0011] In one embodiment of the present invention, each memory unit includes another dynamic random access memory including another control field effect transistor and another storage diode. The gate of the other control field effect transistor is electrically connected to another word line, the other storage diode is composed of a field effect transistor with a floating gate, and both opposite ends of the other storage diode are electrically connected to another selection line and one end of the other control field effect transistor respectively. The other end of the other control field effect transistor is electrically connected to a bit line, and the bit line is located between the selection line and the other selection line.

[0012] In one embodiment of the present invention, regarding the operation method of the dynamic random access memory according to the present invention, the dynamic random access memory includes a storage diode and a control field effect transistor connected in series with each other. The storage diode is composed of a field effect transistor with a floating gate. The operation method includes the steps of applying a control voltage to the word line, applying a write voltage to the bit line, and applying a zero voltage to the selection line when writing to the dynamic random access memory. The gate of the control field effect transistor is electrically connected to the word line, both opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to the bit line.

[0013] In one embodiment of the present invention, the control voltage turns on the control field effect transistor, generates a Zener tunneling effect in the storage diode by the write voltage, and stores electricity in the storage diode.

[0014] In one embodiment of the present invention, the operation method further includes the steps of applying a control voltage to the word line, applying a write voltage to the bit line, and applying a zero voltage to the selection line when refreshing the dynamic random access memory.

[0015] In one embodiment of the present invention, the operation method further includes the steps of applying a control voltage to a word line, applying a read voltage to a select line, and detecting a read current through a bit line when reading a dynamic random access memory.

[0016] In one embodiment of the present invention, the polarity of the read voltage is opposite to the polarity of the write voltage.

Advantages of the Invention

[0017] As described above, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The dynamic random access memory of the present invention is a dynamic random access memory incorporating one transistor and one diode (1T1D) without a capacitor. Since it can be manufactured entirely using the pure wafer foundry field effect transistor technology in the previous process, it does not require an additional photomask, additional materials, or the layout of a capacitor in the subsequent process, thereby significantly reducing costs and design complexity.

[0018] Hereinafter, the above description will be described in detail using embodiments to further explain the technical solution of the present invention.

Brief Description of the Drawings

[0019] In order to make the above and other objects, features, advantages, and embodiments of the present invention clearer and easier to understand, the accompanying drawings will be described below.

Figure 1

Figure 2

Figure 3

Figure 4

Best Mode for Carrying Out the Invention

[0020] To explain the present invention in more detail and completely, reference is made to the accompanying drawings and the following various embodiments. The same numbers in the drawings represent the same or similar components. On the other hand, well-known components and steps are not described in the embodiments to avoid unnecessary limitations to the present invention.

[0021] Refer to FIG. 1. The technical aspect of the present invention is a dynamic random access memory (DRAM) 100, which may be applied to an embedded dynamic random access memory (eDRAM) or widely applied to the processes of related technologies. The dynamic random access memory 100 of this technical aspect can achieve significant technological progress and has broad industrial utility value. Hereinafter, specific embodiments of the dynamic random access memory 100 will be described with reference to FIG. 1.

[0022] It should be understood that various embodiments of the dynamic random access memory 100 will be described with reference to FIG. 1. In the following description, for the convenience of explanation, many specific details are further set to provide a comprehensive description of one or more embodiments. However, the present technology can be implemented without these specific details. In other examples, known structures and devices are shown in block diagrams to effectively explain these embodiments. The term "for example" used here means "by way of example, instance or illustration". Any embodiment described as "for example" in this specification should not necessarily be construed as being more preferable or superior to other embodiments.

[0023] FIG. 1 is a block diagram of a dynamic random access memory 100 according to an embodiment of the present invention. As shown in FIG. 1, the dynamic random access memory 100 includes a storage diode 110 and a control field effect transistor 120 connected in series with each other. Structurally, the storage diode 110 is composed of a field effect transistor with a floating gate. Thereby, the dynamic random access memory 100 is a 1T1D eDRAM without a capacitor, which can be manufactured using only the pure wafer foundry field effect transistor technology in the previous process, so it does not require an additional photomask in BEOL, nor does it require additional materials or capacitor layout, thereby significantly reducing cost and design complexity.

[0024] In applications, the above eDRAM technology of the present invention reduces the memory-wall and shortens the delay between on-chip static random access memory (on-chip SRAM) / register and on-chip dynamic random access memory (on-DIMM DRAM) to balance cost and performance, thereby enabling a wide range of applications.

[0025] In fact, for example, the field effect transistor with a floating gate may be an N-type field effect transistor with a floating gate or a P-type field effect transistor with a floating gate, and the control field effect transistor 120 may be an N-type control field effect transistor or a P-type control field effect transistor. Hereinafter, for simplicity of explanation, an N-type field effect transistor is taken as an example. Those skilled in the art know the differences in the properties and electrical characteristics between the N-type field effect transistor and the P-type control field effect transistor, so the explanation is omitted here.

[0026] In FIG. 1, the first gate 121 of the control field effect transistor 120 is electrically connected to the word line WL, both opposite ends of the storage diode 110 are electrically connected to the selection line SL and one end of the control field effect transistor 120 respectively, and the other end of the control field effect transistor 120 is electrically connected to the bit line BL.

[0027] Also, in the embodiments and claims, the description "electrically connected" generally refers to that one component is indirectly electrically coupled to another component through other components, or one component is directly electrically coupled to another component without passing through other components.

[0028] Regarding the structure of the storage diode 110, in some embodiments of the present invention, the storage diode 110 is composed of a field effect transistor with a floating gate. The second source / drain region 202 and the third source / drain region 203 of the field effect transistor with a floating gate function as the anode and cathode of the storage diode 110 respectively. The control field effect transistor 120 is electrically connected to the cathode or anode of the storage diode 110. The second channel region 222 is located between the second source / drain region 202 and the third source / drain region 203, and the second dielectric layer region 112 is located between the second gate 111 and the second channel region 222. Actually, for example, the field effect transistor with a floating gate constituting the storage diode 110 may be an N-type field effect transistor with a floating gate. In that case, the second source / drain region 202 functions as the anode of the storage diode 110, and the third source / drain region 203 functions as the cathode of the storage diode 110.

[0029] Regarding the structure of the control field effect transistor 120, in some embodiments of the present invention, the control field effect transistor 120 shares the storage diode 110 and the second source / drain region 202. The first source / drain region 201 of the control field effect transistor 120 is electrically connected to the bit line BL, the second source / drain region 202 of the control field effect transistor 120 is electrically connected to the storage diode 110, the first channel region 221 is located between the first source / drain region 201 and the second source / drain region 202, and the first dielectric layer region 122 is located between the first gate 121 and the first channel region 221. In practice, for example, the control field effect transistor 120 may be an N-type control field effect transistor. The first source / drain region 201 of the N-type control field effect transistor is the drain, and the second source / drain region 202 of the N-type control field effect transistor is the source.

[0030] To further explain the overall structure of the dynamic random access memory 100, please refer to FIGS. 1 and 2 simultaneously. FIG. 2 is a perspective structural view of the dynamic random access memory 100 according to an embodiment of the present invention. As shown in FIG. 2, the first source / drain region 201 and the second source / drain region 202 are respectively located on opposite sides of the first gate 121, and the second source / drain region 202 and the third source / drain region 203 are respectively located on opposite sides of the second gate 111. The control field effect transistor 120 shares the storage diode 110 and the second source / drain region 202. As shown in FIG. 2, in practice, for example, the control field effect transistor 120 may be a control fin field effect transistor, and the storage diode 110 may be composed of a fin field effect transistor with a floating gate, but the present invention is not limited thereto.

[0031] It should be noted that here, various components may be described using terms such as "first", "second", etc., but these components should not be limited to these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the embodiments, the first component may be referred to as the second component, and the second component may be referred to as the first component.

[0032] Regarding the structure of the control field effect transistor 120, in some embodiments of the present invention, the control field effect transistor 120 includes a first gate 121, a first source / drain region 201, a second source / drain region 202, a gap wall 211, and a first channel region 221 (for example, a three-dimensional fin channel). Structurally, the gap walls 211 are respectively located on opposite sides of the first gate 121, and the first channel region 221 physically connects the first source / drain region 201 and the second source / drain region 202.

[0033] Regarding the structure of the storage diode 110, in some embodiments of the present invention, the storage diode 110 includes a second gate 111, a second source / drain region 202, a third source / drain region 203, a gap wall 212, and a second channel region 222 (for example, a three-dimensional fin channel). Structurally, the gap walls 212 are respectively located on opposite sides of the second gate 111, and the second channel region 222 physically connects the second source / drain region 202 and the third source / drain region 203.

[0034] In some embodiments of the present invention, the third source / drain region 203 is electrically connected to the selection line SL, the second gate 111 is floating, the first source / drain region 201 is electrically connected to the bit line BL, and the first gate 121 is electrically connected to the word line WL.

[0035] Regarding the operation method of the dynamic random access memory 100, please refer to FIGS. 1 to 3 simultaneously. FIG. 3 is a schematic diagram of the energy levels of the operation method of the dynamic random access memory 100 according to an embodiment of the present invention.

[0036] In the initial stage 301, the dynamic random access memory 100 is not selected, and zero voltage is applied to the word line WL, the bit line BL, and the selection line SL. At this time, the conduction band E C , the Fermi energy level E F , and the valence band E V are all stable, and by maintaining the control field effect transistor 120 in the off state, the leakage current is effectively prevented.

[0037] In the writing stage 302, that is, when writing to the dynamic random access memory 100, a control voltage is applied to the word line WL, a writing voltage is applied to the bit line BL, and a zero voltage is applied to the selection line SL. The control voltage turns on the control field effect transistor 120, and the writing voltage generates a Zener tunneling effect in the storage diode 110 to store electricity in the storage diode 110.

[0038] In some embodiments of the present invention, the control field effect transistor 120 may be an N-type field effect transistor, the storage diode 110 may be composed of an N-type field effect transistor with a floating gate, the second source / drain region 202 may be an N++ doped region (highly doped region), the second channel region 222 may be a P- doped region (lightly doped region), and the third source / drain region 203 may be an N++ doped region, thereby facilitating the occurrence of the Zener tunneling effect. In the writing stage 302, the control voltage (for example, about +0.8V) turns on the control field effect transistor 120, and when the Zener tunneling effect occurs in the storage diode 110, electrons e -is drawn out by a control voltage (e.g., about +0.8V), whereby excess charge (i.e., holes h + ) is generated and stored in the second channel region 222 (e.g., a three-dimensional fin channel).

[0039] The terms "about," "substantially," or "approximately" as used herein are used to modify quantities that may vary slightly, but it should be understood that such slight variations do not change the essence. Unless otherwise specified in an embodiment, the allowable error range for a numerical value modified by "about," "substantially," or "approximately" is generally within 20%, preferably within 10%, and more preferably within 5%.

[0040] In the holding stage 303, electricity (e.g., holes h + ) is temporarily accumulated in the second channel region 222 (e.g., a three-dimensional fin channel). In some embodiments of the present invention, the dynamic random access memory 100 may be refreshed periodically. The refresh is the same as a predetermined voltage for writing, applying the control voltage to the word line WL, applying the writing voltage to the bit line BL, and applying a zero voltage to the selection line SL. The refresh operation means that, within the dynamic random access memory 100, the stored information is rewritten periodically within a predetermined time as time passes to maintain the electrical characteristics of the original stored information, thereby preventing the information stored in the dynamic random access memory 100 from being lost.

[0041] In the reading stage 304, i.e., in the reading of the dynamic random access memory 100, a control voltage is applied to the word line WL, a reading voltage is applied to the selection line SL, and a reading current I read is detected via the bit line BL.

[0042] In some embodiments of the present invention, the control field effect transistor 120 may be an N-type field effect transistor, the storage diode 110 may be composed of an N-type field effect transistor with a floating gate, the second source / drain region 202 may be an N++ doped region (highly doped region), the second channel region 222 may be a P- doped region (lightly doped region), the third source / drain region 203 may be an N++ doped region. In other words, the doping concentrations of the second and third source / drain regions 202 and 203 are much greater than the doping concentration of the second channel region 222. In the read step 304, a control voltage (e.g., about +0.8V) turns on the control field effect transistor 120, and a read voltage (e.g., about -0.2V) attracts holes h read to form a read current I + .

[0043] In some embodiments of the present invention, the polarity of the read voltage in the read step 304 is opposite to the polarity of the write voltage in the write step 302, thereby enabling the write / read of the dynamic random access memory 100 to operate stably. In practice, for example, the storage diode 110 is composed of an N-type field effect transistor with a floating gate, the read voltage is about -0.2V, and the write voltage is about +0.8V.

[0044] To further illustrate the array formed by the dynamic random access memory 100, refer to FIGS. 1 to 4. FIG. 4 is a circuit diagram of a memory circuit 400 according to an embodiment of the present invention. As shown in FIG. 4, the memory circuit 400 includes a plurality of memory units 410 arranged in an array, and the structure of each memory unit 410 is the same. Taking the corner memory unit 410 as an example, it may include a dynamic random access memory 100 and a dynamic random access memory 100'. In fact, for example, the dynamic random access memory 100 in FIG. 1 and the dynamic random access memory 100 in FIG. 4 are substantially the same, and the dynamic random access memory 100 and the dynamic random access memory 100' are symmetric to each other.

[0045] In FIG. 4, the dynamic random access memory 100 includes a control field effect transistor 120 and a storage diode 110. The gate of the control field effect transistor 120 is electrically connected to the word line WL0, and the storage diode 110 is composed of a field effect transistor with a floating gate. Both opposite ends of the storage diode 110 are electrically connected to the selection line SL 32 and one end of the control field effect transistor 120 respectively, and the other end of the control field effect transistor 120 is electrically connected to the bit line BL 31 electrically.

[0046] Similarly, in FIG. 4, the dynamic random access memory 100' includes a control field effect transistor 120' and a storage diode 110'. The gate of the control field effect transistor 120' is electrically connected to the word line WL1, and the storage diode 110' is composed of a field effect transistor with a floating gate. Both opposite ends of the storage diode 110' are electrically connected to the selection line SL 31 and one end of the control field effect transistor 120' respectively, and the other end of the control field effect transistor 120' is electrically connected to the bit line BL 31 electrically, and the bit line BL 31 is electrically connected to the selection line SL 32 and the selection line SL31 is located between them.

[0047] In FIG. 4, selection lines SL0 to SL 32 are electrically connected to circuit 401, word lines WL0 to WL 63 are electrically connected to circuit 402, and bit lines BL0 to BL 31 are electrically connected to circuit 403. In some embodiments of the present invention, circuit 401 may include a selection line decoder, a selection line driver, and a controller, circuit 402 may include a word line decoder and a controller, and circuit 403 may include a bit line decoder, a controller, and a sense amplifier. In practice, for example, the sense amplifier in circuit 403 can detect a read current via bit line BL 31 . Also, for example, storage diode 110 is composed of an N-type field effect transistor with a floating gate, and the selection line driver of circuit 401 is a negative voltage selection line driver, which provides a read voltage (e.g., about -0.2V).

[0048] In an experimental example, memory circuit 400 is designed with standard fin transistors and has an ultra-small size of 0.0242 μm 2 . Dynamic random access memory 100 achieves a write operation shorter than 7 ns when the write voltage is 0.8V, the single-core operating voltage is at a clock of about 400 MHz, and a read operation shorter than 7 ns when the read voltage is -0.2V. In the holding stage 303, the holding time at 25°C is 116 μs, and the holding time at 75°C is 101 μs. The write power is about 0.4 μW / MHz, and the read power is about 36.5 nW / MHz.

[0049] As described above, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The dynamic random access memories 100, 100' of the present invention have a memory structure of one transistor and one diode (1T1D) without a capacitor. Since it can be manufactured by completely using the pure wafer foundry field effect transistor technology in the previous process, it does not require an additional photomask in the subsequent process, nor does it require additional materials or the layout of a capacitor, thereby significantly reducing the cost and design complexity.

[0050] The present invention has been disclosed as above based on the embodiments, but it does not limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present invention is based on the scope defined in the appended claims.

Explanation of Reference Numerals

[0051] To make the above and other objects, features, advantages and embodiments of the present invention clearer and easier to understand, the reference numerals will be explained below. 100, 100' Dynamic random access memory 110, 110' Storage diode 111 Second gate 112 Second dielectric layer region 120, 120' Control field effect transistor 121 First gate 122 First dielectric layer region 201 First source / drain region 202 Second source / drain region 203 Third source / drain region 221 First channel region 222 Second channel region 301 Initial stage 302 Writing stage 303 Holding stage 304 Reading stage 400 Memory circuit 401, 402, 403 circuits 410 Memory unit BL, BL0~BL 31 Bit line e - Electron E C Conduction band E F Fermi energy level E V Valence band h + Hole I read Read current SL, SL0 - SL 32 Selection line WL, WL0 - WL 63 Word line

Claims

1. Comprising a field effect transistor floated by a gate, wherein two source / drains of the field effect transistor floated by the gate are respectively a cathode and an anode of a storage diode, and a control field effect transistor electrically connected to the cathode or the anode of the storage diode, both opposite ends of the storage diode are respectively electrically connected to a selection line and one end of the control field effect transistor, and the other end of the control field effect transistor is electrically connected to a bit line, When reading a dynamic random access memory, a control voltage is applied to a word line, a read voltage is applied to the selection line, a read current is detected via the bit line, and the polarity of the read voltage is opposite to the polarity of the write voltage. A dynamic random access memory.

2. The control field effect transistor is a first gate, a first source / drain region and a second source / drain region respectively located on both opposite sides of the first gate, a first channel region located between the first source / drain region and the second source / drain region, and a first dielectric layer region located between the first gate and the first channel region. The dynamic random access memory according to claim 1.

3. The control field effect transistor and the storage diode share the second source / drain region, and the storage diode is a second gate, a second source / drain region and a third source / drain region respectively located on both opposite sides of the second gate, a second channel region located between the second source / drain region and the third source / drain region, and a second dielectric layer region located between the second gate and the second channel region. The dynamic random access memory according to claim 2.

4. The third source / drain region is electrically connected to the selection line, and the second gate is floating. The dynamic random access memory according to claim 3.

5. The first source / drain region is electrically connected to the bit line, and the first gate is electrically connected to the word line. The dynamic random access memory according to claim 2, 3 or 4.

6. Comprising a plurality of memory units arranged in an array, each including a dynamic random access memory, The dynamic random access memory, A control field effect transistor having a gate electrically connected to a word line, Composed of a field effect transistor with a floating gate, both opposite ends thereof are electrically connected to a selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to a bit line, and includes a storage diode, When reading the dynamic random access memory, a control voltage is applied to the word line, a read voltage is applied to the selection line, a read current is detected via the bit line, and the polarity of the read voltage is opposite to the polarity of the write voltage. A memory circuit.

7. Each of the memory units includes another dynamic random access memory, and the another dynamic random access memory, Another control field effect transistor having a gate electrically connected to another word line, Composed of a field effect transistor with another floating gate, both opposite ends thereof are electrically connected to another selection line and one end of the another control field effect transistor respectively, and the other end of the another control field effect transistor is electrically connected to the bit line, and includes another storage diode. The memory circuit according to claim 6.

8. A method for operating a dynamic random access memory, The dynamic random access memory includes a storage diode and a control field effect transistor connected in series with each other, the storage diode is composed of a field effect transistor with a floating gate, and the operation method includes, When writing to the dynamic random access memory, applying a control voltage to the word line, applying a write voltage to the bit line, and applying a zero voltage to the selection line. The gate of the control field effect transistor is electrically connected to the word line, both opposite ends of the storage diode are electrically connected to the selection line and one end of the control field effect transistor respectively, and the other end of the control field effect transistor is electrically connected to the bit line, A method of operating a dynamic random access memory, comprising: when reading the dynamic random access memory, applying the control voltage to the word line, applying a read voltage to the select line, detecting a read current through the bit line, wherein the polarity of the read voltage is opposite to the polarity of the write voltage.

9. The method of operation according to claim 8, wherein the control voltage turns on the control field effect transistor, and the write voltage generates a Zener tunneling effect in the storage diode to store electricity in the storage diode.

10. The method of operation according to claim 8, further comprising: when refreshing the dynamic random access memory, applying the control voltage to the word line, applying the write voltage to the bit line, and applying the zero voltage to the select line.

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