Semiconductor device

Abstract

To provide a semiconductor device that can achieve reduction in conduction loss of a Schottky barrier diode.SOLUTION: A semiconductor device 61 includes: a semiconductor layer 22 having a first main surface 3: a unit cell 15 including a diode region 24 of an n type (first conductivity type) formed in a surface layer portion of the first main surface 3, a well region 25 of a p type (second conductivity type) formed in the surface layer portion of the first main surface 3 along a peripheral edge of the diode region 24, and an n type impurity region 26 formed in a surface layer portion of the well region 25; a gate electrode layer 33 that faces the well region 25 and the impurity region 26 across a gate insulating layer 32; and a first main surface electrode 11 covering the diode region 24 and the impurity region 26 on the first main surface 3 and forming a Schottky junction with the diode region 24.SELECTED DRAWING: Figure 18

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] FIG. 14 of Patent Document 1 discloses a semiconductor device including a SiC epitaxial layer in which gate trenches are formed, and Schottky cells and pn diode cells formed in the SiC epitaxial layer so as to be separated from each other by the gate trenches.

[0003] In this semiconductor device, a Schottky barrier diode is formed using the Schottky cell. Also, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed using the pn diode cell.

[0004] In the SiC epitaxial layer, one Schottky cell and a plurality of pn diode cells surrounding the one Schottky cell form one cell group. A plurality of cell groups having such a structure are arranged in a matrix in the SiC epitaxial layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] As a result of intensive studies on the semiconductor device according to Patent Document 1, the inventors of the present application have found that there is room to reduce the conduction loss of the Schottky barrier diode. The conduction loss of the Schottky barrier diode becomes smaller as the increase rate of the forward current with respect to the increase rate of the forward voltage becomes larger.

[0007] The semiconductor device according to Patent Document 1 has a structure in which a Schottky cell and a pn diode cell are separately formed. In such a structure, the current paths for the Schottky cell and the pn diode cell are dispersed in the semiconductor layer.

[0008] Therefore, even if the forward voltage is increased, the forward current does not increase as expected. Such a problem is a drawback in reducing the conduction loss of the Schottky barrier diode.

[0009] Therefore, an embodiment of the present invention provides a semiconductor device capable of reducing the conduction loss of a Schottky barrier diode. Also, an embodiment of the present invention provides a semiconductor device capable of reducing conduction loss.

Means for Solving the Problems

[0010] An embodiment of the present invention includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed along the periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer, and a unit cell including a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region with a gate insulating layer interposed therebetween, and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region, and forming an ohmic junction with the first conductivity type region.

[0011] According to this semiconductor device, the first main surface electrode forms a Schottky junction with the diode region and an ohmic junction with the first conductivity type region of the transistor. Thereby, a Schottky barrier diode and an insulated gate type transistor are formed in one unit cell.

[0012] Therefore, the current path for the Schottky barrier diode and the current path for the transistor are formed in the region directly under the unit cell in the semiconductor layer. As a result, it is possible to suppress the current paths for the Schottky barrier diode and the transistor from being dispersed within the semiconductor layer. Consequently, since the increase rate of the forward current with respect to the increase rate of the forward voltage can be increased, the conduction loss of the Schottky barrier diode can be reduced.

[0013] One embodiment of the present invention includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a well region of a second conductivity type formed in a surface layer portion of the first main surface, and an impurity region of a first conductivity type formed in a surface layer portion of the well region. A unit cell, a gate electrode facing the well region with a gate insulating layer interposed therebetween, and an embedded portion of an insulating material formed between the gate electrode and the impurity region and extending under the gate electrode are provided. The embedded portion may be in contact with the gate insulating layer. The thickness of the embedded portion may be greater than the thickness of the embedded portion. The above-mentioned, or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0015] FIG. 1 is a plan view of a semiconductor device 1 according to the first embodiment of the present invention.

[0016] The semiconductor device 1 includes a chip-shaped semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and four side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

[0017] The first main surface 3 and the second main surface 4 of the semiconductor layer 2 are formed in a rectangular shape in a plan view (hereinafter simply referred to as “plan view”) as viewed from their normal directions. The side surface 5A and the side surface 5C face each other. The side surface 5B and the side surface 5D face each other.

[0018] A device formation region 6 and an outer region 7 are set in the semiconductor layer 2. The device formation region 6 is a region where an SBD (Schottky Barrier Diode) 8 and a MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is an example of an insulated gate type transistor, are formed. The device formation region 6 is also referred to as an active region.

[0019] The device formation region 6 is set in the central region of the semiconductor layer 2 at a distance from the peripheral edge of the semiconductor layer 2 to the inner region of the semiconductor layer 2 in a plan view. In this form, the device formation region 6 is set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

[0020] The outer region 7 is set in a region between the periphery of the semiconductor layer 2 and the periphery of the device formation region 6. The outer region 7 is set in an endless shape (square ring shape) surrounding the device formation region 6 in a plan view.

[0021] The ratio SE / SF of the planar area SF of the device formation region 6 to the planar area SE of the first main surface 3 of the semiconductor layer 2 may be 70% or more and 85% or less. 2 More than 25mm 2 The width WO of the outer region 7 may be 0.1 mm or more and 0.3 mm or less. The width WO of the outer region 7 is defined as the width in a direction perpendicular to the direction in which the outer region 7 extends.

[0022] A gate electrode 10 and a source electrode 11 (first main surface electrode) are formed on the first main surface 3 of the semiconductor layer 2. The gate electrode 10 includes a gate pad 12 and a gate finger 13.

[0023] The gate pad 12 is formed along any one of the side surfaces (side surface 5A in this embodiment) in a plan view. The gate pad 12 is formed in a central region of the side surface 5A in a plan view. In this embodiment, the gate pad 12 is drawn out from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6.

[0024] In this embodiment, the gate pad 12 is formed in a quadrangular shape in a plan view. The gate pad 12 may be formed along one corner that connects two side surfaces 5A to 5D that extend in directions that intersect (are perpendicular to) each other in a plan view.

[0025] The gate fingers 13 are drawn out in a strip shape from the gate pad 12 so as to follow the periphery of the device formation region 6. In this embodiment, the gate fingers 13 are formed in an endless shape (square ring shape) surrounding the device formation region 6 in a plan view. The gate fingers 13 may be formed so as to partition the device formation region 6 from three directions.

[0026] The source electrode 11 is formed in a C-shaped region defined by the inner edge of the gate electrode 10 in a plan view. In this form, the source electrode 11 is formed in a C shape along the inner edge of the gate electrode 10 in a plan view.

[0027] The source electrode 11 covers most of the device formation region 6. The source electrode 11 may have a structure in which it has a plurality of electrode portions divided from each other and the device formation region 6 is covered by the plurality of electrode portions.

[0028] In this form, a first bonding wire for the gate is connected to the gate pad 12. The first bonding wire may be an aluminum wire. In this form, a second bonding wire for the source is connected to the source electrode 11. The second bonding wire may be an aluminum wire.

[0029] FIG. 2 is an enlarged view of the region II shown in FIG. 1, and is a view in which the structure above the first main surface 3 of the semiconductor layer 2 is removed.

[0030] Referring to FIG. 2, unit cells 15 for forming SBDs 8 and MISFETs 9 are formed in the device formation region 6. In FIG. 2, an example in which a plurality of unit cells 15 are arranged in a matrix is shown.

[0031] The plurality of unit cells 15 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. In this form, the first direction X is a direction along any one of the side surfaces 5A to 5D of the semiconductor layer 2 (side surfaces 5B and 5D in this form). The second direction Y is a direction along a side surface orthogonal to the arbitrary side surface (side surfaces 5A and 5C in this form). In this form, the second direction Y is a direction orthogonal to the first direction X.

[0032] The unit cell 15 is formed in a square shape in plan view. The aspect ratio L2 / L1 of the unit cell 15 is "1" here. The aspect ratio L2 / L1 is defined as the ratio of the length L2 of one side along the second direction Y of the unit cell 15 to the length L1 of one side along the first direction X of the unit cell 15.

[0033] That is, in this form, the unit cell 15 is formed in a square shape in plan view. The lengths L1 and L2 of one side of the unit cell 15 may each be 5 μm or more and 15 μm or less (for example, about 10 μm).

[0034] A first line portion 16, a second line portion 17, and an intersection portion 18 are formed on the first main surface 3 of the semiconductor layer 2. The first line portion 16, the second line portion 17, and the intersection portion 18 are all formed by the first main surface 3 of the semiconductor layer 2 exposed from the unit cell 15.

[0035] The first line portion 16 extends along the first direction X in the region between a plurality of unit cells 15 and partitions the region between a plurality of unit cells 15 adjacent in the second direction Y. The second line portion 17 extends along the second direction Y in the region between a plurality of unit cells 15 and partitions the region between a plurality of unit cells 15 adjacent in the first direction X. The intersection portion 18 is a portion where the first line portion 16 and the second line portion 17 intersect.

[0036] The width W1 in the second direction Y of the first line portion 16 may be 0.8 μm or more and 3.0 μm or less. The width W2 in the first direction X of the second line portion 17 may be 0.8 μm or more and 3.0 μm or less.

[0037] An impurity region 19 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 at the intersection portion 18. The impurity region 19 relaxes the electric field generated particularly between adjacent unit cells 15 on the first main surface 3 of the semiconductor layer 2. The impurity region 19 suppresses a decrease in the breakdown voltage of the semiconductor device 1.

[0038] The impurity region 19 is, in this form, a p-type impurity region or p +It includes an impurity region. The impurity region 19 forms a pn junction with the semiconductor layer 2 (n-type epitaxial layer 22 to be described later). -

[0039] Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4 is an enlarged view of the main part of Figure 3. Hereinafter, Figure 2 will also be referred to as necessary.

[0040] Referring to Figure 3, the semiconductor layer 2 has a stacked structure including an n-type semiconductor substrate 21 and an n-type epitaxial layer 22 formed on the n-type semiconductor substrate 21. The first main surface 3 of the semiconductor layer 2 is formed by the n-type epitaxial layer 22. The second main surface 4 of the semiconductor layer 2 is formed by the n-type semiconductor substrate 21. + + - - +

[0041] + In this form, the n-type semiconductor substrate 21 includes a wide-bandgap semiconductor. The n-type semiconductor substrate 21 may include SiC, diamond, or a nitride semiconductor. The off-angle of the n-type semiconductor substrate 21 may be 4°. + +

[0042] - In this form, the n-type epitaxial layer 22 includes a wide-bandgap semiconductor. The n-type epitaxial layer 22 may include SiC, diamond, or a nitride semiconductor. SiC may be 4H-SiC. The nitride semiconductor may be GaN. -

[0043] - + The n-type epitaxial layer 22 may be formed of the same material type as the n-type semiconductor substrate 21. The n-type epitaxial layer 22 may be formed of a material type different from that of the n-type semiconductor substrate 21. - +

[0044] ​​​​​​​​​​​​​​​Hereinafter, n + -type semiconductor substrate 21 and n - -type epitaxial layer 22 both containing SiC (4H-SiC) will be described. That is, n + -type semiconductor substrate 21 has a main surface provided with an off-angle within 10° with respect to the <11-20> direction from the

[0001] plane. More specifically, the off-angle is 2° or 4°.

[0045] n - -type epitaxial layer 22 is formed by epitaxially growing SiC from the main surface of the n + -type semiconductor substrate 21. Therefore, n - -type epitaxial layer 22 has a main surface provided with an off-angle within 10° with respect to the <11-20> direction from the

[0001] plane. More specifically, the off-angle is 2° or 4°.

[0046] In this form, the first direction X is set in a direction orthogonal to the <11-20> direction, and the second direction Y is set in the <11-20> direction. Therefore, the plurality of unit cells 15 are arranged at intervals along the <11-20> direction and the direction orthogonal to the <11-20> direction.

[0047] When a plurality of unit cells 15 are arranged along the <11-20> direction using a 4H-SiC substrate having an off-angle within 10°C, in a plurality of adjacent unit cells 15, the relationship between the electric field and the crystal orientation becomes equal to each other.

[0048] The breakdown voltage strength of the unit cell 15 decreases due to local electric field concentration. Therefore, when the electric field is locally concentrated in a certain unit cell 15 among the plurality of unit cells 15, the breakdown voltage strength of the entire plurality of unit cells 15 is limited by a certain unit cell 15.

[0049] Therefore, by arranging a plurality of unit cells 15 such that the relationship between the electric field and the crystal orientation is equal to each other, it is possible to suppress the local concentration of the electric field in a certain unit cell 15 among the plurality of unit cells 15. As a result, the breakdown voltage strengths of the respective unit cells 15 can be made closer to being equal, so that a decrease in the breakdown voltage of the semiconductor device 1 can be suppressed.

[0050] A drain electrode 23 (second main surface electrode) is connected to the second main surface 4 of the semiconductor layer 2. The drain electrode 23 covers the second main surface 4 of the semiconductor layer 2 and forms an ohmic contact with the n + type semiconductor substrate 21.

[0051] In the semiconductor layer 2, the n + type semiconductor substrate 21 is formed as a low-resistance region (drain region). In the semiconductor layer 2, the n - type epitaxial layer 22 is formed as a high-resistance region (drift region).

[0052] The thickness of the n - type epitaxial layer 22 may be 5 μm or more and 30 μm or less. By increasing the thickness of the n - type epitaxial layer 22, the breakdown voltage of the semiconductor device 1 can be improved.

[0053] For example, by setting the thickness of the n - type epitaxial layer 22 to 5 μm or more, a breakdown voltage of 600 V or more can be obtained. For example, by setting the thickness of the n - type epitaxial layer 22 to 20 μm or more, a breakdown voltage of 3000 V or more can be obtained.

[0054] Referring to FIGS. 2 and 3, a plurality of unit cells 15 are formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. Each unit cell 15 includes an n - type diode region 24, a p-type well region 25, an n + type source region 26 (first conductivity type region), and a p + type contact region 27.

[0055] n - The n-type diode region 24 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. n - The n-type diode region 24 is formed in a rectangular shape in plan view. n - In this form, the n-type diode region 24 is n - formed by directly using a part of the n-type epitaxial layer 22. Therefore, n - the n-type diode region 24 is n - has an n-type impurity concentration substantially equal to the n-type impurity concentration of the n-type epitaxial layer 22.

[0056] n - The n-type diode region 24 may be n - formed by further implanting n-type impurities into the surface layer portion of the n-type epitaxial layer 22. In this case, n - the surface layer portion of the n-type diode region 24 may n - have an n-type impurity concentration higher than the n-type impurity concentration of the n-type epitaxial layer 22.

[0057] The area ratio SD / SC of the planar area SD of the n-type diode region 24 to the planar area SC of the unit cell 15 may be 0.005 or more and 0.015 or less (for example, about 0.01). Hereinafter, the area ratio SD / SC is referred to as "the area ratio SD / SC of the n-type diode region 24 with respect to the unit cell 15". - The area ratio SD / SC of the planar area SD of the n-type diode region 24 to the planar area SC of the unit cell 15 may be 0.005 or more and 0.015 or less (for example, about 0.01). Hereinafter, the area ratio SD / SC is referred to as "the area ratio SD / SC of the n-type diode region 24 with respect to the unit cell 15". - The area ratio SD / SC of the planar area SD of the n-type diode region 24 to the planar area SC of the unit cell 15 may be 0.005 or more and 0.015 or less (for example, about 0.01). Hereinafter, the area ratio SD / SC is referred to as "the area ratio SD / SC of the n-type diode region 24 with respect to the unit cell 15".

[0058] n - The aspect ratio L4 / L3 of the n-type diode region 24 may be "1" or more. The aspect ratio L4 / L3 is n - defined as the ratio of the length L4 of one side along the second direction Y of the n-type diode region 24 to the length L3 of one side along the first direction X of the n-type diode region 24. - The aspect ratio L4 / L3 of the n-type diode region 24 is defined as the ratio of the length L4 of one side along the second direction Y of the n-type diode region 24 to the length L3 of one side along the first direction X of the n-type diode region 24.

[0059] Here, n - an example in which the aspect ratio L4 / L3 of the n-type diode region 24 is "1" is shown. Therefore, n -The p-type diode region 24 is formed in a square shape in plan view here. n - The lengths L3 and L4 of one side of the n-type diode region 24 may each be 1 μm or more and 1.5 μm or less (for example, about 1.2 μm).

[0060] The p-type well region 25 is formed along the peripheral edge of the n-type diode region 24 in the surface layer portion of the first main surface 3 of the semiconductor layer 2. n - The p-type well region 25 is formed more specifically in an endless shape (square ring shape) surrounding the n-type diode region 24 in plan view. n - The p-type well region 25 is formed in an endless shape (square ring shape) surrounding the n-type diode region 24 in plan view.

[0061] The outer peripheral edge of the p-type well region 25 forms the outer peripheral edge of the unit cell 15. The p-type well region 25 forms a first pn junction between the n-type diode region 24 and the n - type diode region 24 and the n - type epitaxial layer 22.

[0062] Referring to FIG. 4, a first diode 28 is formed with the p-type well region 25 as the anode and the n-type diode region 24 (drain electrode 23) as the cathode by the first pn junction. - The n-type source region 26 is formed in the surface layer portion of the p-type well region 25. n

[0063] n + The n-type source region 26 has an n-type impurity concentration higher than the n-type impurity concentration of the n-type diode region 24. n + The n-type source region 26 is formed at a distance from the inner and outer peripheral edges of the p-type well region 25. n - The n-type source region 26 has an n-type impurity concentration higher than the n-type impurity concentration of the n-type diode region 24.

[0064] n + The n-type source region 26 is formed at a distance from the inner and outer peripheral edges of the p-type well region 25. n + In this form, the n-type source region 26 is formed in an endless shape (square ring shape) along the p-type well region 25 in plan view.

[0065] p + The p-type contact region 27 is formed in the surface layer portion of the p-type well region 25. p+ The p-type contact region 27 is formed in the surface layer portion of the p-type well region 25 between the n - -type diode region 24 and the n + -type source region 26. The p + -type contact region 27 has a p-type impurity concentration higher than the p-type impurity concentration of the p-type well region 25.

[0066] p + -type contact region 27 is formed in an endless shape (square ring shape) along the inner peripheral edge of the p-type well region 25 in plan view in this form. The p + -type contact region 27 is exposed from the inner peripheral edge of the p-type well region 25 and forms a second pn junction with the n - -type diode region 24.

[0067] Referring to FIG. 4, the p + -type contact region 27 includes a first region 29 and a second region 30. The first region 29 of the p + -type contact region 27 is formed within the p-type well region 25. The second region 30 of the p + -type contact region 27 is drawn out from the first region 29 into the n - -type diode region 24.

[0068] p + -type contact region 27's second region 30 crosses the boundary region between the p-type well region 25 and the n - -type diode region 24. The second region 30 of the p + -type contact region 27 forms a second pn junction with the n - -type diode region 24. Due to the second pn junction, a second diode 31 is formed with the p + -type contact region 27 as the anode and the n - -type diode region 24 (drain electrode 23) as the cathode.

[0069] Each unit cell 15 has a JBS (Junction Barrier Schottky) structure. The JBS structure is an n- It includes a first pn junction formed between the n-type diode region 24 and the p-type well region 25. Also, the JBS structure is an n - type diode region 24 and a p + type contact region 27 includes a second pn junction formed therebetween.

[0070] Furthermore, on the surface layer portion of the n - type epitaxial layer 22, a JFET (Junction Field Effect Transistor) structure is formed using each unit cell 15.

[0071] The JFET structure includes a first pnp structure and a second pnp structure. The first pnp structure is an n - type epitaxial layer 22 of the first line portion 16, and is formed by the p-type well regions 25 adjacent to each other with the first line portion 16 therebetween. The second pnp structure is an n - type epitaxial layer 22 of the second line portion 17, and is formed by the p-type well regions 25 adjacent to each other with the second line portion 17 therebetween.

[0072] Referring to FIG. 3, on the first main surface 3 of the semiconductor layer 2, a planar gate structure is formed. The planar gate structure has a stacked structure including a gate insulating layer 32 and a gate electrode layer 33. In this form, the planar gate structure is formed in a lattice shape along the first line portion 16 and the second line portion 17 in a plan view.

[0073] The gate electrode layer 33 is electrically connected to the gate electrode 10. The gate electrode layer 33 faces the p-type well region 25, the n + type source region 26 and the n - type epitaxial layer 22 with the gate insulating layer 32 therebetween.

[0074] More specifically, the gate electrode layer 33 extends from the regions above the first line portion 16, the second line portion 17 and the intersection portion 18 to the regions above each unit cell 15, and the p-type well region 25 and the n of each unit cell 15 +Selectively covers the type source region 26.

[0075] An insulating layer 34 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 34 covers the gate electrode layer 33. In the insulating layer 34, n - type diode region 24, n + type source region 26 and p + type contact holes 35 for exposing the contact region 27 are selectively formed.

[0076] The source electrode 11 is formed on the insulating layer 34. The source electrode 11 enters the contact hole 35 from above the insulating layer 34. Inside the contact hole 35, the source electrode 11 is n - type diode region 24, n + type source region 26 and p + type contact region 27 is collectively covered.

[0077] The source electrode 11 is n - type diode region 24 to form a Schottky junction. Thus, referring to FIG. 4, an SBD8 is formed with the source electrode 11 as the anode and the n - type diode region 24 (drain electrode 23) as the cathode.

[0078] The source electrode 11 is n + type source region 26 and p + type contact region 27 to form an ohmic junction. Thereby, a MISFET9 including the semiconductor layer 2, the p-type well region 25, the n + type source region 26, the p + type contact region 27, the gate insulating layer 32, the gate electrode 10 (gate electrode layer 33), the source electrode 11, and the drain electrode 23 is formed.

[0079] FIG. 5 is a circuit diagram showing the electrical structure of the semiconductor device 1 in FIG. 1.

[0080] Referring to FIG. 5, the semiconductor device 1 includes an SBD 8, a MISFET 9, a first diode 28, and a second diode 31. The SBD 8, the first diode 28, and the second diode 31 form a free - wheeling diode of the MISFET 9.

[0081] The SBD 8 is connected in parallel with the MISFET 9. The anode of the SBD 8 is connected to the source electrode 11 of the MISFET 9. The cathode of the SBD 8 is connected to the drain electrode 23 of the MISFET 9.

[0082] The first diode 28 is connected in parallel with the MISFET 9. The anode of the first diode 28 is connected to the source electrode 11 of the MISFET 9. The cathode of the first diode 28 is connected to the drain electrode 23 of the MISFET 9.

[0083] The second diode 31 is connected in parallel with the MISFET 9. The anode of the second diode 31 is connected to the source electrode 11 of the MISFET 9. The cathode of the second diode 31 is connected to the drain electrode 23 of the MISFET 9.

[0084] The source electrode 11 of the MISFET 9 also serves as the anode electrode of the SBD 8, the anode electrode of the first diode 28, and the anode electrode of the second diode 31. The drain electrode 23 of the MISFET 9 also serves as the cathode electrode of the SBD 8, the cathode electrode of the first diode 28, and the cathode electrode of the second diode 31.

[0085] FIG. 6 is a diagram for explaining the structure of the semiconductor device 41 according to the reference example from an electrical point of view. Hereinafter, only the differences from the semiconductor device 1 will be described, and the description of other points will be omitted.

[0086] The semiconductor device 41 according to the reference example has a structure different from that of the semiconductor device 1 in that it does not include the unit cell 15. More specifically, the semiconductor device 41 according to the reference example has a structure in which the SBD cell 42 for the SBD 8 and the MISFET cell 43 for the MISFET 9 are arranged adjacent to each other.

[0087] In the SBD cell 42, an n - -type diode region 24 is formed. In the MISFET cell 43, a p-type well region 25, an n + -type source region 26 and a p + -type contact region 27 are formed.

[0088] FIG. 6 shows the distribution of current density obtained by simulation. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1V.

[0089] In the semiconductor device 41 according to the reference example, current is concentrated in the MISFET cell 43. Therefore, the current paths for the SBD cell 42 and the MISFET cell 43 are dispersed in the semiconductor layer 2. Also, the common portion of the current paths for the SBD cell 42 and the MISFET cell 43 is formed on the bottom side of the semiconductor layer 2 and is relatively small.

[0090] Therefore, in the semiconductor device 41 according to the reference example, even if the forward voltage VF is increased, the forward current IF does not increase as expected. Such a problem is a drawback in reducing the conduction loss of the SBD 8.

[0091] FIG. 7 is a diagram for explaining the structure of the semiconductor device 1 from an electrical point of view.

[0092] FIG. 7 shows the distribution of current density of the semiconductor device 1 obtained by simulation. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1V.

[0093] Referring to FIG. 7, in the semiconductor device 1, the common portion of the current path for the SBD 8 and the current path for the MISFET 9 is larger than the common portion of the semiconductor device 41 according to the reference example.

[0094] The semiconductor device 1 has a structure in which the MISFET 9 and the SBD 8 are formed using one unit cell 15. Therefore, the current path for the SBD 8 and the current path for the MISFET 9 are formed in the region directly below the unit cell 15.

[0095] Thereby, it is possible to suppress the current paths for the SBD 8 and the MISFET 9 from being dispersed in the semiconductor layer 2. Also, it is possible to make the current paths for the SBD 8 and the MISFET 9 common. Thus, since the increase rate of the forward current IF with respect to the increase rate of the forward voltage VF can be increased, the conduction loss of the SBD 8 can be reduced.

[0096] FIG. 8 is a graph showing the measurement results of the current-voltage characteristics of the SBD 8.

[0097] In FIG. 8, the vertical axis represents the drain current ID [A], and the horizontal axis represents the voltage VDS [V] between the drain electrode 23 and the source electrode 11. The drain current ID is also the forward current IF of the SBD 8. The voltage VDS between the drain electrode 23 and the source electrode 11 is also the forward voltage VF of the SBD 8.

[0098] FIG. 8 shows a first characteristic A and a second characteristic B. The first characteristic A shows the current-voltage characteristics of the SBD 8 of the semiconductor device 1. The second characteristic B shows the current-voltage characteristics of the SBD 8 of the semiconductor device 41 according to the reference example.

[0099] Referring to the first characteristic A and the second characteristic B, the increase rate of the drain current ID with respect to the increase rate of the voltage VDS between the drain electrode 23 and the source electrode 11 of the first characteristic A is higher than the increase rate of the drain current ID of the second characteristic B. Thus, according to the semiconductor device 1, a conduction loss smaller than the conduction loss of the semiconductor device 41 according to the reference example could be realized.

[0100] Also, according to the semiconductor device 1, the unit cell 15 has a JBS structure including a first pn junction formed between the p-type well region 25 and the n - type diode region 24. Therefore, the first depletion layer spreading from the first pn junction can suppress current concentration and electric field concentration in the n - type diode region 24.

[0101] Furthermore, in addition to the first pn junction, this JBS structure includes a second pn junction formed between the p + type contact region 27 and the n - type diode region 24. Therefore, the second depletion layer spreading from the second pn junction can also suppress current concentration and electric field concentration in the n - type diode region 24.

[0102] In particular, the second pn junction is formed in the boundary region between the n - type diode region 24 and the second region 30 of the p + type contact region 27. Thereby, the second depletion layer can be surely expanded from the second pn junction. As a result, current concentration and electric field concentration in the n - type diode region 24 can be appropriately suppressed.

[0103] FIG. 9 is a diagram showing the result obtained by simulating the distribution of the current density in the main part of the semiconductor device 1 of FIG. 1. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1V.

[0104] Referring to FIG. 9, in the semiconductor device 1, the concentration of current and electric field by the JBS structure is suppressed. However, even so, the current still concentrates in the n - -type diode region 24. That is, it is understood that in the n - -type diode region 24, the resistance value increases due to the concentration of current.

[0105] Therefore, it is considered that in the n - -type diode region 24, by suppressing the increase in the resistance value caused by the concentration of current and making it easier for current to flow, the conduction loss of the SBD8 can be further reduced.

[0106] Therefore, the aspect ratio L2 / L1, etc. was adjusted based on the unit cell 15 shown in FIG. 2, and the current-voltage characteristics of the SBD8 were examined.

[0107] FIG. 10 is a plan view of a portion corresponding to FIG. 2, showing a structure in which the aspect ratio L2 / L1 of the unit cell 15 is "2". That the aspect ratio L2 / L1 is "2" means that the aspect ratio L2 / L1 is twice the aspect ratio L2 / L1 (= "1") of the unit cell 15 shown in FIG. 2.

[0108] More specifically, referring to FIG. 10, each unit cell 15 is formed in a rectangular shape in plan view. Each unit cell 15 is preferably formed in a rectangular shape extending along the second direction Y, that is, the <11-20> direction. According to such a structure, local electric field concentration with respect to the unit cell 15 can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0109] The length L1 of the short side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 12 μm). The length L2 of the long side of the unit cell 15 may be 10 μm or more and 30 μm or less (for example, about 24 μm).

[0110] n - -type diode region 24 is formed in a rectangular shape in plan view. The n -The area ratio SD / SC of the p-type diode region 24 may be 0.05 or more and 0.06 or less (for example, about 0.055).

[0111] n - The length L3 of the short side of the p-type diode region 24 may be 1 μm or more and 1.5 μm or less (for example, about 1.2 μm). n - The length L4 of the long side of the p-type diode region 24 may be 10 μm or more and 15 μm or less (for example, about 13.2 μm). Considering only the ratio, n - The aspect ratio L4 / L3 of the p-type diode region 24 is larger than the aspect ratio L2 / L1 of the unit cell 15.

[0112] FIG. 11 is a plan view of a portion corresponding to FIG. 2, and shows a structure in which the aspect ratio L2 / L1 of the unit cell 15 is "3". That the aspect ratio L2 / L1 is "3" means that the aspect ratio L2 / L1 is three times the aspect ratio L2 / L1 (= "1") of the unit cell 15 shown in FIG. 2.

[0113] More specifically, referring to FIG. 11, each unit cell 15 is formed in a rectangular shape in plan view. Each unit cell 15 is preferably formed in a rectangular shape extending along the second direction Y, that is, the <11-20> direction. According to such a structure, local electric field concentration with respect to the unit cell 15 can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0114] The length L1 of the short side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 12 μm). The length L2 of the long side of the unit cell 15 may be 15 μm or more and 45 μm or less (for example, about 36 μm).

[0115] n - The p-type diode region 24 is formed in a rectangular shape in plan view. With respect to the unit cell 15 n - The area ratio SD / SC of the p-type diode region 24 may be 0.065 or more and 0.075 or less (for example, about 0.07).

[0116] n - The length L3 of the short side of the n-type diode region 24 may be 1 μm or more and 1.5 μm or less (for example, about 1.2 μm). n - The length L4 of the long side of the n-type diode region 24 may be 20 μm or more and 30 μm or less (for example, about 25.2 μm). Looking only at the ratio, n - The aspect ratio L4 / L3 of the n-type diode region 24 is larger than the aspect ratio L2 / L1 of the unit cell 15.

[0117] FIG. 12 is a graph showing the measurement results of the current-voltage characteristics of SBD8. In FIG. 12, the vertical axis represents the drain current ID [A], and the horizontal axis represents the voltage VDS [V] between the drain electrode 23 and the source electrode 11. The drain current ID is also the forward current IF of SBD8. The voltage VDS between the drain electrode 23 and the source electrode 11 is also the forward voltage VF of SBD8.

[0118] In FIG. 12, in addition to the first characteristic A and the second characteristic B, the third characteristic C and the fourth characteristic D are shown (see also FIG. 8).

[0119] The third characteristic C shows the current-voltage characteristics of SBD8 of the semiconductor device 1 including the unit cell 15 with the aspect ratio L2 / L1 being "2" (see also FIG. 10). The fourth characteristic D shows the current-voltage characteristics of SBD8 of the semiconductor device 1 including the unit cell 15 with the aspect ratio L2 / L1 being "3" (see also FIG. 11).

[0120] Referring to the first characteristic A and the third characteristic C, the increase rate of the drain current ID with respect to the increase rate of the voltage VDS between the drain electrode 23 and the source electrode 11 of the third characteristic C is higher than the increase rate of the drain current ID of the first characteristic A.

[0121] Also, referring to the first characteristic A and the fourth characteristic D, the increase rate of the drain current ID with respect to the increase rate of the voltage VDS between the drain electrode 23 and the source electrode 11 of the fourth characteristic D is higher than the increase rate of the drain current ID of the first characteristic A.

[0122] Also, referring to the third characteristic C and the fourth characteristic D, the increase rate of the drain current ID with respect to the increase rate of the voltage VDS between the drain electrode 23 and the source electrode 11 is not so different between the third characteristic C and the fourth characteristic D.

[0123] It has been found that by increasing the aspect ratio L2 / L1 of the unit cell 15 compared to the first characteristic A, the third characteristic C, and the fourth characteristic D, the increase rate of the drain current ID with respect to the increase rate of the voltage VDS between the drain electrode 23 and the source electrode 11 can be improved. That is, it has been found that by increasing the aspect ratio L2 / L1 of the unit cell 15, the conduction loss of the SBD8 can be reduced.

[0124] On the other hand, the increase rate of the drain current ID of the fourth characteristic D with respect to the third characteristic C is smaller than the increase rate of the drain current ID of the third characteristic C with respect to the first characteristic A. Therefore, it has been found that there is an upper limit to the aspect ratio L2 / L1.

[0125] The aspect ratio L2 / L1 of the unit cell 15 may be adjusted in the range of "1" or more and "4" or less. For the unit cell 15, n - The area ratio SD / SC of the n-type diode region 24 with respect to the unit cell 15 may be adjusted in the range of 0.005 or more and 0.01 or less.

[0126] According to any combination of the aspect ratio L2 / L1 in the above range and the area ratio SD / SC in the above range, the conduction loss of the SBD8 can be reduced, and the degree of freedom in design can be increased.

[0127] FIG. 13 is a plan view showing a part of the device formation region 6, and is a plan view of the semiconductor device 51 according to the second embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0128] As shown in FIG. 13, in this form, the plurality of unit cells 15 includes a plurality of unit cells 15A having a relatively large aspect ratio L2 / L1 and a plurality of unit cells 15B having a relatively small aspect ratio L2 / L1.

[0129] Each of the plurality of unit cells 15A extends in a strip shape along the second direction Y, that is, the <11-20> direction. The aspect ratio L2 / L1 of the plurality of unit cells 15A is "2". That is, the unit cell 15 shown in FIG. 11 is applied as the plurality of unit cells 15A.

[0130] According to such a structure, local electric field concentration on the unit cell 15 can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1. The plurality of unit cells 15A are formed in a staggered arrangement in a plan view instead of a matrix arrangement in a plan view.

[0131] The aspect ratio L2 / L1 of the plurality of unit cells 15B is less than "2". The plurality of unit cells 15B are formed along the periphery of the device formation region 6. The plurality of unit cells 15B may be formed in a region partitioned by the periphery of the device formation region 6 and the plurality of unit cells 15A.

[0132] As described above, the semiconductor device 51 can also achieve the same effects as those described for the semiconductor device 1. Also, a plurality of unit cells 15B are formed in a region partitioned by the periphery of the device formation region 6 and the plurality of unit cells 15A. Thereby, a plurality of unit cells 15A and 15B can be formed in the device formation region 6 without waste, so that the current path can be appropriately increased.

[0133] FIG. 14 is a plan view showing a part of the device formation region 6 and is a plan view of the semiconductor device 52 according to the third embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0134] As shown in FIG. 14, a plurality of unit cells 15 are arranged to be connected to each other along the second direction Y, that is, the <11-20> direction. Thereby, a plurality (two or more) of unit cells 15 form one linear cell 53 extending in a strip shape along the second direction Y. According to such a structure, local electric field concentration on the linear cell 53 can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0135] A plurality of linear cells 53 may be arranged at intervals along the first direction X. FIG. 14 shows a structure in which the unit cell 15 with the aspect ratio L2 / L1 shown in FIG. 11 being "2" is applied.

[0136] Between a plurality of n - type diode regions 24 adjacent to each other along the second direction Y, the p-type well regions 25 of one and / or the other unit cell 15 adjacent to each other along the second direction Y are interposed. Each linear cell 53 has a structure in which a plurality of n - type diode regions 24 are arranged at intervals along the second direction Y.

[0137] As described above, the semiconductor device 52 can also achieve the same effects as those described for the semiconductor device 1.

[0138] The plurality of unit cells 15 may be arranged to be connected to each other along the first direction X instead of the second direction Y. Therefore, the plurality of unit cells 15 may form one linear cell extending along the first direction X. Further, a plurality of such linear cells may be arranged at intervals along the second direction Y.

[0139] FIG. 15 is a plan view of a semiconductor device 61 according to a fourth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be used for description.

[0140] The semiconductor device 61 includes a chip-shaped semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and four side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

[0141] The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal directions. The side surface 5A and the side surface 5C face each other. The side surface 5B and the side surface 5D face each other.

[0142] A device formation region 6 and an outer region 7 are set in the semiconductor layer 2. The device formation region 6 is a region where an SBD 8 and a MISFET 9 are formed. The device formation region 6 is also referred to as an active region.

[0143] The device formation region 6 is set in the central region of the semiconductor layer 2 at an interval from the peripheral edge of the semiconductor layer 2 to the inner region of the semiconductor layer 2 in a plan view. In this form, the device formation region 6 is set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

[0144] The outer region 7 is set in the region between the peripheral edge of the semiconductor layer 2 and the peripheral edge of the device formation region 6. The outer region 7 is set in an endless (square annular) shape surrounding the device formation region 6 in a plan view.

[0145] The ratio SE / SF of the planar area SF of the device formation region 6 to the planar area SE of the first main surface 3 of the semiconductor layer 2 may be 70% or more and 85% or less. The planar area SE of the first main surface 3 of the semiconductor layer 2 may be 16 mm 2 or more and 25 mm 2 or less. The width WO of the outer region 7 may be 0.1 mm or more and 0.3 mm or less. The width WO of the outer region 7 is defined as the width in a direction orthogonal to the direction in which the outer region 7 extends.

[0146] On the first main surface 3 of the semiconductor layer 2, a gate electrode 10 and a source electrode 11 (first main surface electrode) are formed. In FIG. 15, for clarity, the gate electrode 10 and the source electrode 11 are shown by hatching. The gate electrode 10 includes a gate pad 12, a gate finger 13, and a gate line 62.

[0147] The gate pad 12 is formed along any one side surface (side surface 5A in this form) in plan view. The gate pad 12 is formed in the central region of the side surface 5A in plan view. The gate pad 12 is drawn from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6 in this form.

[0148] The gate pad 12 is formed in a rectangular shape in plan view in this form. The gate pad 12 may be formed along one corner connecting two side surfaces 5A to 5D extending along directions intersecting (orthogonal) to each other in plan view.

[0149] The gate finger 13 is drawn out in a strip shape from the gate pad 12 along the periphery of the device formation region 6. The gate finger 13 is formed in an endless shape (square annular shape) surrounding the device formation region 6 in plan view in this form. The gate finger 13 may be formed so as to partition the device formation region 6 from three directions.

[0150] The gate line 62 is drawn out from the leading end of the gate pad 12 toward the central portion of the device formation region 6. The gate line 62 is formed in a strip shape extending linearly from the gate pad 12 toward the side surface 5C of the semiconductor layer 2 in plan view in this form.

[0151] The source electrode 11 is formed in a C-shaped region defined by the inner edge of the gate electrode 10 in plan view. The source electrode 11 is formed in a C-shape along the inner edge of the gate electrode 10 in plan view in this form.

[0152] The source electrode 11 covers most of the device formation region 6. The source electrode 11 may have a plurality of electrode portions divided from each other and may have a structure that covers the device formation region 6 with the plurality of electrode portions.

[0153] In this form, a first bonding wire for the gate is connected to the gate pad 12. The first bonding wire may be an aluminum wire. In this form, a second bonding wire for the source is connected to the source electrode 11. The second bonding wire may be an aluminum wire.

[0154] FIG. 16 is a plan view in which the gate electrode 10 and the source electrode 11 are removed from FIG. 15, and is a diagram for explaining the structure on the first main surface 3 of the semiconductor layer 2.

[0155] On the first main surface 3 of the semiconductor layer 2, a gate pad layer 63, a gate finger layer 64, and a gate line layer 65 are formed. In FIG. 16, for clarity, the gate pad layer 63, the gate finger layer 64, and the gate line layer 65 are shown by hatching.

[0156] The gate pad layer 63 is formed in a region directly below the gate pad 12. The gate pad layer 63 is electrically connected to the gate pad 12. Although not shown, the gate pad 12 is electrically connected to the gate pad layer 63 through a contact hole formed in the insulating layer 34.

[0157] In this form, the gate pad layer 63 is drawn from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6. In this form, the gate pad layer 63 is formed in a rectangular shape in plan view.

[0158] The gate finger layer 64 is formed in the region directly below the gate finger 13. The gate finger layer 64 is electrically connected to the gate finger 13. Although not shown, the gate finger 13 is electrically connected to the gate finger layer 64 through a contact hole formed in the insulating layer 34. The gate finger layer 64 is drawn out in a strip shape from the gate pad layer 63 along the periphery of the device formation region 6.

[0159] In this form, the gate finger layer 64 is formed in an endless (square ring shape) surrounding the device formation region 6 in a plan view. The gate finger layer 64 may be formed so as to partition the device formation region 6 from three directions.

[0160] The gate line layer 65 is formed in the region directly below the gate line 62. The gate line layer 65 is electrically connected to the gate line 62. Although not shown, the gate line 62 is electrically connected to the gate line layer 65 through a contact hole formed in the insulating layer 34.

[0161] The gate line layer 65 is drawn out from the leading end of the drawout of the gate pad layer 63 toward the central portion of the device formation region 6. In this form, the gate line layer 65 is formed in a strip shape extending linearly from the gate pad layer 63 toward the side surface 5C of the semiconductor layer 2 in a plan view.

[0162] A gate electrode layer 33 (planar gate structure) is formed in the C-shaped region partitioned by the gate pad layer 63, the gate finger layer 64, and the gate line layer 65. In this form, the gate electrode layer 33 is formed in a lattice shape in a plan view.

[0163] In FIG. 16, the gate electrode layer 33 is shown by lattice lines. The gate electrode layer 33 is drawn out from the gate pad layer 63, the gate finger layer 64, and the gate line layer 65.

[0164] The gate electrode layer 33 is electrically connected to the gate pad 12, the gate finger 13, and the gate line 62 via the gate pad layer 63, the gate finger layer 64, and the gate line layer 65.

[0165] FIG. 17 is an enlarged view of the region XVII shown in FIG. 16, in which the structure above the first main surface 3 of the semiconductor layer 2 is removed.

[0166] Referring to FIG. 17, unit cells 15 for forming the SBD 8 and the MISFET 9 are formed in the device formation region 6. FIG. 17 shows an example in which a plurality of unit cells 15 are arranged in a matrix.

[0167] The plurality of unit cells 15 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. In this form, the first direction X is a direction along any one of the side surfaces 5A to 5D of the semiconductor layer 2 (side surfaces 5B and 5D in this form). The second direction Y is a direction along the side surface orthogonal to the arbitrary one of the side surfaces (side surfaces 5A and 5C in this form). In this form, the second direction Y is a direction orthogonal to the first direction X.

[0168] The unit cell 15 is formed in a rectangular shape in plan view. The unit cell 15 has corner portions 15a that are convex outward in plan view. Thereby, the concentration of the electric field at the corner portions 15a of the unit cell 15 can be alleviated.

[0169] The aspect ratio L2 / L1 of the unit cell 15 can take a value of “1” or more (for example, “1” or more and “4” or less) as shown in FIGS. 10 and 11 described above. Here, an example in which the aspect ratio L2 / L1 is “1” will be described. The aspect ratio L2 / L1 is defined as the ratio of the length L2 of one side of the unit cell 15 along the second direction Y to the length L1 of one side of the unit cell 15 along the first direction X.

[0170] In this form, the unit cell 15 is formed in a square shape in plan view. The lengths L1 and L2 of one side of the unit cell 15 may each be 5 μm or more and 15 μm or less (for example, about 10 μm).

[0171] On the first main surface 3 of the semiconductor layer 2, a first line portion 16, a second line portion 17, and an intersection portion 18 are formed. The first line portion 16, the second line portion 17, and the intersection portion 18 are all formed by the first main surface 3 of the semiconductor layer 2 exposed from the unit cell 15.

[0172] The first line portion 16 extends along the first direction X in the region between a plurality of unit cells 15 and partitions the region between a plurality of unit cells 15 adjacent in the second direction Y. The second line portion 17 extends along the second direction Y in the region between a plurality of unit cells 15 and partitions the region between a plurality of unit cells 15 adjacent in the first direction X. The intersection portion 18 is a portion where the first line portion 16 and the second line portion 17 intersect.

[0173] The width W1 of the first line portion 16 in the second direction Y may be 0.8 μm or more and 3.0 μm or less (for example, about 1.2 μm). The width W2 of the second line portion 17 in the first direction X may be 0.8 μm or more and 3.0 μm or less (for example, about 1.2 μm).

[0174] In the intersection portion 18, an impurity region 19 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. The impurity region 19 relaxes the electric field generated especially between adjacent unit cells 15 on the first main surface 3 of the semiconductor layer 2. The impurity region 19 suppresses a decrease in the breakdown voltage of the semiconductor device 61.

[0175] In this form, the impurity region 19 is a p-type impurity region or includes a p + type impurity region. The impurity region 19 forms a pn junction with the semiconductor layer 2 (an n - type epitaxial layer 22 to be described later). The impurity region 19 has a corner portion 19a that is convex outward in plan view.

[0176] The impurity region 19 overlaps the unit cell 15 at the intersection 18. More specifically, the corner 19a of the impurity region 19 overlaps the corner 15a of the unit cell 15. Even more specifically, the four corners 19a of one impurity region 19 overlap the corners 15a of four adjacent unit cells 15 at the intersection 18. Thereby, the concentration of the electric field at the corner 15a of each unit cell 15 can be appropriately relaxed.

[0177] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG. 17. FIG. 19 is an enlarged view of the region XIX shown in FIG. 18. Hereinafter, FIG. 17 will also be referred to as necessary.

[0178] Referring to FIG. 18, the semiconductor layer 2 has a stacked structure including an n + -type semiconductor substrate 21 and an n + -type epitaxial layer 22 formed on the n - -type semiconductor substrate 21. The first main surface 3 of the semiconductor layer 2 is formed by the n - -type epitaxial layer 22. The second main surface 4 of the semiconductor layer 2 is formed by the n + -type semiconductor substrate 21.

[0179] n + -type semiconductor substrate 21 includes a wide bandgap semiconductor in this form. The n + -type semiconductor substrate 21 may include SiC, diamond, or a nitride semiconductor. The off-angle of the n + -type semiconductor substrate 21 may be 4°.

[0180] n - -type epitaxial layer 22 includes a wide bandgap semiconductor in this form. The n - -type epitaxial layer 22 may include SiC, diamond, or a nitride semiconductor. The SiC may be 4H-SiC. The nitride semiconductor may be GaN.

[0181] n - -type epitaxial layer 22 is an n +It may be formed of the same material type as the n-type semiconductor substrate 21. - The n-type epitaxial layer 22 may be formed of a material type different from that of the n-type semiconductor substrate 21. In the following, an example in which both the n-type semiconductor substrate 21 and the n-type epitaxial layer 22 contain SiC (4H-SiC) will be described. + The n-type epitaxial layer 22 may be formed of a material type different from that of the n-type semiconductor substrate 21. In the following, an example in which both the n-type semiconductor substrate 21 and the n-type epitaxial layer 22 contain SiC (4H-SiC) will be described. + The n-type semiconductor substrate 21 and - the n-type epitaxial layer 22 will be described for an example in which both contain SiC (4H-SiC).

[0182] That is, + the n-type semiconductor substrate 21 has a main surface provided with an off-angle of 10° or less with respect to the <11-20> direction from the

[0001] plane. More specifically, the off-angle is 2° or 4°.

[0183] The - n-type epitaxial layer 22 is + formed by epitaxially growing SiC from the main surface of the n-type semiconductor substrate 21. Therefore, the n-type epitaxial layer 22 has a main surface provided with an off-angle of 10° or less with respect to the <11-20> direction from the

[0001] plane. More specifically, the off-angle is 2° or 4°. - formed by epitaxially growing SiC from the main surface of the n-type semiconductor substrate 21. Therefore, the n-type epitaxial layer 22 has a main surface provided with an off-angle of 10° or less with respect to the <11-20> direction from the

[0001] plane. More specifically, the off-angle is 2° or 4°.

[0184] In this form, the first direction X is set in a direction orthogonal to the <11-20> direction, and the second direction Y is set in the <11-20> direction. Therefore, the plurality of unit cells 15 are arranged at intervals along the <11-20> direction and the direction orthogonal to the <11-20> direction.

[0185] When a plurality of unit cells 15 are arranged along the <11-20> direction using a 4H-SiC substrate having an off-angle within 10°, in a plurality of adjacent unit cells 15, the relationship between the electric field and the crystal orientation becomes equal to each other.

[0186] The breakdown voltage of the unit cell 15 decreases due to local electric field concentration. Therefore, when the electric field is locally concentrated in a certain unit cell 15 among the plurality of unit cells 15, the breakdown voltage of the entire plurality of unit cells 15 is limited by that certain unit cell 15.

[0187] Therefore, by arranging the plurality of unit cells 15 such that the relationship between the electric field and the crystal orientation is equal to each other, it is possible to suppress the local concentration of the electric field in a certain unit cell 15 among the plurality of unit cells 15. As a result, the breakdown voltages of the respective unit cells 15 can be made closer to being equal, and thus a decrease in the breakdown voltage of the semiconductor device 1 can be suppressed.

[0188] A drain electrode 23 (second main surface electrode) is connected to the second main surface 4 of the semiconductor layer 2. The drain electrode 23 covers the second main surface 4 of the semiconductor layer 2 and forms an ohmic contact with the n + type semiconductor substrate 21.

[0189] In the semiconductor layer 2, the n + type semiconductor substrate 21 is formed as a low-resistance region (drain region). In the semiconductor layer 2, the n - type epitaxial layer 22 is formed as a high-resistance region (drift region).

[0190] The n - type epitaxial layer 22 may have a thickness of 5 μm or more and 70 μm or less. By increasing the thickness of the n - type epitaxial layer 22, the breakdown voltage of the semiconductor device 61 can be improved.

[0191] For example, by setting the thickness of the n - type epitaxial layer 22 to 5 μm or more, a breakdown voltage of 600 V or more can be obtained. For example, by setting the thickness of the n - type epitaxial layer 22 to 20 μm or more, a breakdown voltage of 3000 V or more can be obtained. For example, by setting the thickness of the n - type epitaxial layer 22 to 40 μm or more, a breakdown voltage of 6000 V or more can be obtained.

[0192] Referring to FIGS. 17 to 19, a plurality of unit cells 15 are formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. A recessed portion 71 that is recessed toward the second main surface 4 side of the semiconductor layer 2 is formed on the surface of each unit cell 15.

[0193] That is, a plurality of recessed portions 71 are arranged in a matrix at intervals along the first direction X and the second direction Y on the first main surface 3 of the semiconductor layer 2. And the unit cells 15 are formed along this recessed portion 71. The depth of the recessed portion 71 may be 0.5 μm or more and 5 μm or less.

[0194] The recessed portion 71 has a side wall 72, a bottom wall 73, and an edge portion 74 that connects the side wall 72 and the bottom wall 73. In this form, the recessed portion 71 is set to a rectangular shape having four sides parallel to each side of the unit cell 15 in plan view.

[0195] The bottom wall 73 of the recessed portion 71 has a surface roughness Zr that is equal to or greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 (Zr ≧ Zs). More specifically, the surface roughness Zr of the bottom wall 73 of the recessed portion 71 is greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 (Zr > Zs). The surface roughness Zr and Zs may each be an arithmetic mean roughness.

[0196] An n - -type diode region 24, a p-type well region 25, an n + -type source region 26, and a p + -type contact region 27 are formed.

[0197] n - -type diode region 24 is formed at the center of the bottom wall 73 of the recessed portion 71. The n - -type diode region 24 is formed in a rectangular shape in plan view. The n - -type diode region 24 has a corner portion 24a that is convexly curved outward in plan view.

[0198] n - In this form, the n-type diode region 24 is formed by directly using a partial region of the n-type epitaxial layer 22. Therefore, the n - type diode region 24 has an n-type impurity concentration substantially equal to that of the n-type epitaxial layer 22. - n - type diode region 24 has an n-type impurity concentration substantially equal to that of the n-type epitaxial layer 22.

[0199] n - type diode region 24 may also be formed by further implanting n-type impurities into the surface layer portion of the n-type epitaxial layer 22. In this case, the n - type diode region 24 may have an n-type impurity concentration higher than that of the n-type epitaxial layer 22 in its surface layer portion. - n - type diode region 24 may have an n-type impurity concentration higher than that of the n-type epitaxial layer 22 in its surface layer portion.

[0200] The area ratio SD / SC of the planar area SD of the n - type diode region 24 to the planar area SC of the unit cell 15 may be 0.005 or more and 0.015 or less (for example, about 0.01).

[0201] n - The aspect ratio L4 / L3 of the n-type diode region 24 may be "1". The aspect ratio L4 / L3 is defined as the ratio of the length L4 of one side along the second direction Y of the n - type diode region 24 to the length L3 of one side along the first direction X of the n - type diode region 24.

[0202] Therefore, the n - type diode region 24 is formed in a square shape in plan view in this form. The lengths L3 and L4 of one side of the n - type diode region 24 may be 0.8 μm or more and 3.0 μm or less (for example, about 1.2 μm), respectively.

[0203] The breakdown voltage of the semiconductor layer 2 is n -It is limited by the width (lengths L3, L4) of the narrowest part in the p-type diode region 24, the width W1 of the first line part 16, or the width W2 of the second line part 17. Therefore, n - The width (lengths L3, L4) of the narrowest part in the p-type diode region 24 is preferably substantially equal to the width W1 of the first line part 16 and the width W2 of the second line part 17.

[0204] For example, for the first line part 16 and the second line part 17, when the p - type diode region 24 is small, the breakdown voltage of the semiconductor layer 2 is limited by the p - type diode region 24. Conversely, when the first line part 16 and / or the second line part 17 are small with respect to the p - type diode region 24, the breakdown voltage of the semiconductor layer 2 is limited by the first line part 16 and / or the second line part 17.

[0205] Therefore, n - by forming the width (lengths L3, L4) of the narrowest part in the p-type diode region 24 to be substantially equal to the width W1 of the first line part 16 and the width W2 of the second line part 17, it is possible to suppress the breakdown voltage of the semiconductor layer 2 from being limited by the p - type diode region 24, the first line part 16, or the second line part 17.

[0206] The p-type well region 25 is formed along the periphery of the p - type diode region 24 on the bottom wall 73 of the recess part 71. More specifically, the p-type well region 25 is formed in an endless shape (square annular shape) surrounding the p - type diode region 24 on the bottom wall 73 of the recess part 71.

[0207] The p-type well region 25 covers the side wall 72 from the bottom wall 73 of the recess part 71 via the edge part 74. That is, the bottom wall 73 of the recess part 71 is located closer to the first main surface 3 side of the semiconductor layer 2 than the bottom of the p-type well region 25.

[0208] The outer peripheral edge of the p-type well region 25 forms the outer peripheral edge of the unit cell 15. Therefore, the p-type well region 25 has a corner portion 25a that is convexly curved outward in a plan view. The corner portion 25a of the p-type well region 25 corresponds to the corner portion 15a of the unit cell 15. Thereby, the concentration of the electric field at the corner portion 25a of the p-type well region 25 can be alleviated.

[0209] The bottom of the p-type well region 25 is formed parallel to the first main surface 3 of the semiconductor layer 2. That is, the bottom of the p-type well region 25 is formed parallel to the

[0001] plane of the semiconductor layer 2. According to such a structure, the concentration of the electric field on the p-type well region 25 due to the properties of the crystal can be alleviated.

[0210] p-type well region 25 is an n - -type diode region 24 and an n - -type epitaxial layer 22 to form a pn junction therebetween. By this pn junction, a first diode 28 is formed with the p-type well region 25 as the anode and the n - -type diode region 24 (drain electrode 23) as the cathode.

[0211] n + -type source region 26 is formed in the surface layer portion of the p-type well region 25. The n + -type source region 26 has an n-type impurity concentration higher than the n-type impurity concentration of the n - -type diode region 24.

[0212] n + -type source region 26 is formed at the bottom wall 73 of the recess portion 71 at intervals from the inner peripheral edge and the outer peripheral edge of the p-type well region 25. The n + -type source region 26 covers the side wall 72 from the bottom wall 73 of the recess portion 71 via the edge portion 74.

[0213] n + -type source region 26 is formed in an endless shape (square ring shape) along the p-type well region 25 in a plan view in this form. The n +The p-type source region 26 has a corner portion 26a that is convexly curved outward in a plan view.

[0214] p + The p-type contact region 27 is formed in the surface layer portion of the p-type well region 25. p + The p-type contact region 27 has a p-type impurity concentration higher than the p-type impurity concentration of the p-type well region 25.

[0215] p + The p-type contact region 27 is formed in a region between the inner peripheral edge of the p-type well region 25 and the n-type source region 26 on the bottom wall 73 of the recess portion 71. p + The p-type contact region 27 is formed in a region between the inner peripheral edge of the p-type well region 25 and the n-type source region 26 on the bottom wall 73 of the recess portion 71. p + The boundary region between the p-type contact region 27 and the n-type source region 26 is in contact with the bottom wall 73 of the recess portion 71. + The boundary region between the p-type contact region 27 and the n-type source region 26 is in contact with the bottom wall 73 of the recess portion 71.

[0216] p + In this form, the p-type contact region 27 is formed in an endless shape (square ring shape) along the inner peripheral edge of the p-type well region 25 in a plan view. p + The p-type contact region 27 has a corner portion 27a that is convexly curved outward in a plan view.

[0217] FIG. 20 is a graph showing the impurity concentration profiles of the p-type well region 25, the n-type source region 26, and the p-type contact region 27. In FIG. 20, the vertical axis represents the impurity concentration [cm-3], and the horizontal axis represents the depth [μm] from the first main surface 3 of the semiconductor layer 2. + type source region 26 and p + type contact region 27. In FIG. 20, the vertical axis represents the impurity concentration [cm-3], and the horizontal axis represents the depth [μm] from the first main surface 3 of the semiconductor layer 2.

[0218] FIG. 20 shows a first curve L1, a second curve L2, and a third curve L3. The first curve L1 shows the impurity concentration profile of the p-type well region 25. The second curve L2 shows the impurity concentration profile of the n-type source region 26. The third curve L3 shows the impurity concentration profile of the p-type contact region 27. + type source region 26. The third curve L3 shows the impurity concentration profile of the p-type contact region 27. + type contact region 27.

[0219] Referring to the first curve L1, the p-type impurity concentration in the p-type well region 25 has a peak value (maximum value) in the middle of its depth direction. The p-type impurity concentration in the p-type well region 25 decreases from the peak value toward the first main surface 3 and the second main surface 4 of the semiconductor layer 2.

[0220] Referring to the second curve L2, the n + -type impurity concentration in the n-type source region 26 is higher than the p-type impurity concentration in the p-type well region 25. The n + -type impurity concentration in the n-type source region 26 has a concentration profile that gradually decreases from the first main surface 3 (the bottom wall 73 of the recess portion 71) of the semiconductor layer 2 toward the second main surface 4.

[0221] Referring to the broken line portion of the second curve L2, the n + -type impurity concentration in the n-type source region 26 actually has a peak value (maximum value) in the middle of its depth direction, like the p-type well region 25.

[0222] The recess portion 71 is formed by removing a region of the surface layer portion in the n + -type source region 26 where the n-type impurity concentration is relatively small. In this way, an n + -type source region 26 having a concentration profile in which the n-type impurity concentration gradually decreases from the first main surface 3 to the second main surface 4 of the semiconductor layer 2 is formed.

[0223] Referring to the third curve L3, the p + -type impurity concentration in the p-type contact region 27 is higher than the p-type impurity concentration in the p-type well region 25. The p + -type impurity concentration in the p-type contact region 27 has a concentration profile that gradually decreases from the first main surface 3 (the bottom wall 73 of the recess portion 71) of the semiconductor layer 2 toward the second main surface 4.

[0224] Referring to the broken line portion of the third curve L3, the p + -type impurity concentration in the p-type contact region 27 actually has a peak value (maximum value) in the middle of its depth direction, like the p-type well region 25.

[0225] The recessed portion 71 is p + formed by removing a region of the surface layer portion where the p-type impurity concentration is relatively low in the p-type contact region 27. In this way, a p-type contact region 27 having a concentration profile in which the p-type impurity concentration gradually decreases from the first main surface 3 (the bottom wall 73 of the recessed portion 71) of the semiconductor layer 2 toward the second main surface 4 is formed. +

[0226] Thus, on the bottom wall 73 of the recessed portion 71, portions with relatively high impurity concentrations in the p-type well region 25, n + -type source region 26, and p + -type contact region 27 are exposed. As a result, the electrical connection of the source electrode 11 to each semiconductor region is improved, so that the SBD8 and the MISFET9 can be appropriately formed.

[0227] Each unit cell 15 has a JBS structure. The JBS structure includes a pn junction formed between the n - -type diode region 24 and the p-type well region 25. Further, a JFET structure is formed on the surface layer portion of the n - -type epitaxial layer 22 using each unit cell 15.

[0228] The JFET structure includes a first pnp structure and a second pnp structure. The first pnp structure is formed by the first line portion 16 of the n - -type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the first line portion 16 therebetween. The second pnp structure is formed by the second line portion 17 of the n - -type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the second line portion 17 therebetween.

[0229] Referring to FIG. 18 again, a planar gate structure is formed on the first main surface 3 of the semiconductor layer 2. The planar gate structure has a stacked structure including a gate insulating layer 32 and a gate electrode layer 33. The planar gate structure is formed in a lattice shape along the first line portion 16 and the second line portion 17 in a plan view. ​

[0230] The gate insulating layer 32 may include an oxide film. The oxide film may include silicon oxide. Referring to FIG. 19, a gate through hole 75 communicating with the recess portion 71 is formed in the gate insulating layer 32. The inner wall of the gate through hole 75 is formed flush with the side wall 72 of the recess portion 71.

[0231] The gate electrode layer 33 faces the p-type well region 25, the n + type source region 26, and the n - type epitaxial layer 22 with the gate insulating layer 32 interposed therebetween. The gate electrode layer 33 extends from the regions above the first line portion 16, the second line portion 17, and the intersection portion 18 to the regions above each unit cell 15, and selectively covers the p-type well region 25 and the n + type source region 26 of each unit cell 15.

[0232] More specifically, the gate electrode layer 33 includes a main body portion 76 and an overhanging portion 77. The main body portion 76 of the gate electrode layer 33 is located above the gate insulating layer 32. The overhanging portion 77 of the gate electrode layer 33 extends from the main body portion 76 of the gate electrode layer 33 to the region above the unit cell 15.

[0233] The overhanging portion 77 of the gate electrode layer 33 has an opposing portion 78 that faces the bottom wall 73 of the recess portion 71 with a space therebetween. More specifically, the overhanging portion 77 of the gate electrode layer 33 faces the n + type source region 26 with a space therebetween.

[0234] An upper surface insulating layer 79 is formed on the upper surface of the gate electrode layer 33. The upper surface insulating layer 79 covers substantially the entire upper surface of the gate electrode layer 33. The upper surface insulating layer 79 is formed to enhance the flatness of the region above the gate electrode layer 33. The upper surface insulating layer 79 may include a nitride film. The nitride film may include silicon nitride.

[0235] An insulating layer 34 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 34 covers the gate electrode layer 33. Although not shown in the figure, the insulating layer 34 also covers a gate pad layer 63, a gate finger layer 64, and a gate line layer 65.

[0236] The insulating layer 34 fills the space between the overhanging portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recess portion 71, and covers the outer surface of the gate electrode layer 33. The insulating layer 34 includes an embedded portion 80 embedded in the space. The embedded portion 80 of the insulating layer 34 is in contact with the gate insulating layer 32 in the space.

[0237] The overhanging portion 77 of the gate electrode layer 33 faces the n + type source region 26 with the embedded portion 80 of the insulating layer 34 interposed therebetween. Therefore, the embedded portion 80 of the insulating layer 34 functions as a part of the gate insulating layer 32.

[0238] The thickness of the embedded portion 80 of the insulating layer 34 may be equal to or greater than the thickness of the gate insulating layer 32. That is, the insulating layer 34 can be regarded as having a thin film portion in contact with the inner portion (main body portion 76) of the gate electrode layer 33 and a thick film portion having a thickness greater than that of the thin film portion and in contact with the peripheral portion (overhanging portion 77) of the gate electrode layer 33.

[0239] In this form, the insulating layer 34 has a laminated structure in which a plurality of insulating films are laminated. More specifically, the plurality of insulating films include an insulating film 81 and an insulating film 82 laminated in this order from the side of the first main surface 3 of the semiconductor layer 2. The insulating film 82 includes an insulating material having properties different from those of the insulating material of the insulating film 81.

[0240] The insulating film 81 may include USG (Undoped Silica Glass). The insulating film 82 may include PSG (Phosphosilicate Glass). The insulating film 82 may include BPSG (Borophosphosilicate Glass) instead of PSG.

[0241] The insulating film 81 is formed on the first main surface 3 of the semiconductor layer 2 so as to cover the gate electrode layer 33. The insulating film 81 covers the outer surface of the gate electrode layer 33 from the bottom wall 73 of the recessed portion 71. More specifically, the insulating film 81 includes a first covering portion 83 that covers the bottom wall 73 of the recessed portion 71, and a second covering portion 84 that covers the outer surface of the gate electrode layer 33.

[0242] The first covering portion 83 of the insulating film 81 is formed in a film shape along the bottom wall 73 of the recessed portion 71. The first covering portion 83 of the insulating film 81 is embedded in the space between the protruding portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recessed portion 71. The embedded portion 80 of the insulating layer 34 is formed by the first covering portion 83 of the insulating film 81.

[0243] The second covering portion 84 of the insulating film 81 is formed in a film shape along the outer surface of the gate electrode layer 33. The second covering portion 84 of the insulating film 81 faces the upper surface of the gate electrode layer 33 with the upper surface insulating layer 79 interposed therebetween.

[0244] The insulating film 81 has an n - -type diode region 24, an n + -type source region 26, and a p + -type contact region 27, and a first contact hole 85 is formed to expose them. More specifically, the first contact hole 85 is formed in the first covering portion 83 of the insulating film 81.

[0245] The inner wall of the first contact hole 85 is formed directly above the n + -type source region 26. The opening edge portion of the first contact hole 85 has a convex curved surface that curves convexly outward.

[0246] The insulating film 82 covers the insulating film 81. The insulating film 82 covers the second covering portion 84 of the insulating film 81 from above the first covering portion 83 of the insulating film 81. A second contact hole 86 that communicates with the first contact hole 85 is formed in the insulating film 82.

[0247] In this form, the second contact hole 86 forms one contact hole 35 with the first contact hole 85. The opening edge portion of the second contact hole 86 has a convex curved surface that curves convexly outward.

[0248] The opening width of the second contact hole 86 is equal to or greater than the opening width of the first contact hole 85. The inner wall of the second contact hole 86 surrounds the inner wall of the first contact hole 85. The inner wall of the first contact hole 85 is located in the inner region of the second contact hole 86. A stepped portion 87 including the opening edge portion of the first contact hole 85 is formed in the region between the inner wall of the first contact hole 85 and the inner wall of the second contact hole 86.

[0249] The source electrode 11 is formed on the insulating layer 34. The source electrode 11 enters the contact hole 35 from above the insulating layer 34. The source electrode 11, within the contact hole 35, - type diode region 24, n + type source region 26 and p + type contact region 27 are collectively covered.

[0250] The source electrode 11, n - forms a Schottky junction with the type diode region 24. Thereby, an SBD8 is formed with the source electrode 11 as the anode and the n - type diode region 24 (drain electrode 23) as the cathode.

[0251] The source electrode 11, n + forms an ohmic junction with the type source region 26 and p + type contact region 27. Thereby, a MISFET9 including the semiconductor layer 2, p-type well region 25, n + type source region 26, p + type contact region 27, gate insulating layer 32, gate electrode 10 (gate electrode layer 33), source electrode 11, and drain electrode 23 is formed.

[0252] In this form, the source electrode 11 has a laminated structure including an electrode layer 91 and an electrode layer 92.

[0253] The electrode layer 91 is formed in a film shape and enters the contact hole 35 from above the insulating layer 34. The electrode layer 91 covers a stepped portion 87 including the opening edge portion of the first contact hole 85 within the contact hole 35. The electrode layer 91, within the contact hole 35, collectively covers the n - -type diode region 24, the n + -type source region 26, and the p + -type contact region 27.

[0254] The electrode layer 91 covers the bottom wall 73 of the recess portion 71 having a relatively large surface roughness Zr. Thereby, the adhesion of the electrode layer 91 (source electrode 11) to the bottom wall 73 of the recess portion 71 is enhanced. As a result, an SBD8 can be appropriately formed in the region between the electrode layer 91 (source electrode 11) and the n - -type diode region 24.

[0255] In this form, the electrode layer 91 has a laminated structure including a first barrier electrode film 93 and a second barrier electrode film 94. The first barrier electrode film 93 includes a Ti (titanium) film. The second barrier electrode film 94 includes a TiN (titanium nitride) film. The electrode layer 91 may have a single-layer structure including only one of the Ti (titanium) film and the TiN (titanium nitride) film.

[0256] The electrode layer 92 is formed on the electrode layer 91. The thickness of the electrode layer 92 is equal to or greater than the thickness of the electrode layer 91. The electrode layer 92 is formed in a film shape along the electrode layer 91 and enters the contact hole 35 from above the insulating layer 34.

[0257] Within the contact hole 35, the electrode layer 91 collectively covers the n - -type diode region 24, the n + -type source region 26, and the p + -type contact region 27 with the electrode layer 91 interposed therebetween. The electrode layer 92 may contain aluminum.

[0258] Referring to FIGS. 18 and 19, the source electrode 11 includes a first covering portion 95 covering the insulating layer 34 and a second covering portion 96 covering the bottom wall 73 of the recess portion 71. The first covering portion 95 bulges upward from above the insulating layer 34. The second covering portion 96 has a thickness equal to or less than that of the first covering portion 95.

[0259] The upper surface of the second covering portion 96 is located on the bottom wall 73 side of the recess portion 71 with respect to the upper surface of the first covering portion 95. The upper surface of the second covering portion 96 and the upper surface of the first covering portion 95 are formed by the electrode layer 92.

[0260] In this form, the upper surface of the second covering portion 96 is located at a height position approximately equal to the upper surface of the insulating layer 34. Thereby, a recess is partitioned in the source electrode 11 by the first covering portion 95 and the second covering portion 96.

[0261] A depression 97 is formed at the corner of the upper surface of the second covering portion 96 in the source electrode 11. More specifically, the corner of the second covering portion 96 is a connecting portion connecting the first covering portion 95 and the second covering portion 96.

[0262] The depression 97 is recessed toward the first main surface 3 side of the semiconductor layer 2. The depression 97 may be recessed toward the corner of the insulating layer 34 (insulating film 82). The depression 97 faces the bottom wall 73 of the recess portion 71. The depression 97 faces the n + -type source region 26. The depression 97 faces the p + -type contact region 27.

[0263] Due to this depression 97, a thick film portion 98 having a thickness greater than or equal to that of other regions is formed at the center of the second covering portion 96. The thick film portion 98 is formed in a portion of the second covering portion 96 covering the n - -type diode region 24.

[0264] The width WT of the thick film portion 98 is n -The length L3, L4 of the mesa diode region 24 may be greater than or equal to (WT ≧ L3, L4). By the thick film portion 98, a protruding portion 99 protruding upward from the depression 97 is formed on the upper surface of the second covering portion 96.

[0265] The top of the protruding portion 99 is located above the upper surface of the gate electrode layer 33. The top of the protruding portion 99 may be located in a region between the upper surface of the insulating layer 34 and the upper surface of the first covering portion 95. The top of the protruding portion 99 may be located on the bottom wall 73 side of the recess portion 71 with respect to the upper surface of the insulating layer 34.

[0266] Although not shown, a plurality of contact holes for exposing the gate pad layer 63, the gate finger layer 64, and the gate line layer 65 are selectively formed in the insulating layer 34.

[0267] The gate pad 12, the gate finger 13, and the gate line 62 respectively enter corresponding contact holes (not shown) from above the insulating layer 34. The gate pad 12, the gate finger 13, and the gate line 62 are electrically connected to the gate pad layer 63, the gate finger layer 64, and the gate line layer 65 in the corresponding contact holes, respectively.

[0268] The gate pad 12, the gate finger 13, and the gate line 62 may each have a stacked structure including the electrode layer 91 and the electrode layer 92, like the source electrode 11.

[0269] In the semiconductor device 61, as shown in FIGS. 10 and 11 described above, the aspect ratio L2 / L1 of the plurality of unit cells 15 may be adjusted in the range of "1" or more and "4" or less. For the unit cell 15, the n - The area ratio SD / SC of the n-type diode region 24 may be adjusted in the range of 0.005 or more and 0.01 or less.

[0270] According to any combination of the aspect ratio L2 / L1 within the above range and the area ratio SD / SC within the above range, as described for the semiconductor device 1, it is possible to reduce the conduction loss of the SBD8 and increase the degree of freedom in design.

[0271] Since the specific structures of the plurality of unit cells 15 in which the aspect ratio L2 / L1 is "1" or more and "4" or less are as described in FIGS. 10 and 11 and the like, the description thereof will be omitted.

[0272] As described above, the semiconductor device 61 can also achieve the same effects as those described for the semiconductor device 1.

[0273] FIGS. 21A to 21P are cross-sectional views for explaining an example of the manufacturing method of the semiconductor device 61 shown in FIG. 15. FIGS. 21A to 21P are cross-sectional views of the corresponding portions in FIG. 18.

[0274] Referring to FIG. 21A, a semiconductor layer 2 is prepared. The semiconductor layer 2 is formed through a step of preparing an n + type semiconductor substrate 21 and a step of forming an n + type epitaxial layer 22 on the main surface of the n - type semiconductor substrate 21. The n - type epitaxial layer 22 is formed by epitaxially growing SiC from the main surface of the n + type semiconductor substrate 21.

[0275] Next, referring to FIG. 21B, a p-type well region 25 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. In the step of forming the p-type well region 25, first, an ion implantation mask 101 having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The ion implantation mask 101 has a plurality of openings 102 that expose the region where the p-type well region 25 is to be formed.

[0276] Next, via the ion implantation mask 101, p-type impurities are introduced into the surface layer portion of the first main surface 3 of the semiconductor layer 2. As a result, a p-type well region 25 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. After the formation process of the p-type well region 25, the ion implantation mask 101 is removed.

[0277] Next, referring to FIG. 21C, an n- + type source region 26 is formed in the surface layer portion of the p-type well region 25. In the process of forming the n- + type source region 26, first, an ion implantation mask 103 having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The ion implantation mask 103 has a plurality of openings 104 that expose the region where the n- + type source region 26 is to be formed.

[0278] Next, via the ion implantation mask 103, n-type impurities are introduced into the surface layer portion of the p-type well region 25. As a result, an n- + type source region 26 is formed in the surface layer portion of the p-type well region 25. After the formation process of the n- + type source region 26, the ion implantation mask 103 is removed.

[0279] Next, referring to FIG. 21D, a p- + type contact region 27 is formed in the surface layer portion of the p-type well region 25. In the process of forming the p- + type contact region 27, first, an ion implantation mask 105 having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The ion implantation mask 105 has a plurality of openings 106 that expose the region where the p- + type contact region 27 is to be formed.

[0280] Next, via the ion implantation mask 105, p-type impurities are introduced into the surface layer portion of the p-type well region 25. As a result, a p- + type contact region 27 is formed in the surface layer portion of the p-type well region 25. After the formation process of the p- + type contact region 27, the ion implantation mask 105 is removed.

[0281] The forming process of the p-type well region 25 (see Fig. 21B), n + The forming process of the n-type source region 26 (see Fig. 21C) and p + The forming order of the p-type contact region 27 (see Fig. 21C) is arbitrary and not limited to the above order.

[0282] Next, referring to Fig. 21E, a base insulating layer 107 serving as a base of the gate insulating layer 32 is formed on the first main surface 3 of the semiconductor layer 2. The base insulating layer 107 may be formed by a thermal oxidation treatment method or a CVD (Chemical Vapor Deposition) method. The base insulating layer 107 may contain silicon oxide.

[0283] Next, a base electrode layer 108 serving as a base of the gate electrode layer 33 is formed on the base insulating layer 107. The base electrode layer 108 may be formed by a CVD method. The base electrode layer 108 may contain polysilicon.

[0284] Next, an upper base insulating layer 109 serving as a base of the upper insulating layer 79 is formed on the base electrode layer 108. The upper base insulating layer 109 may be formed by a CVD method. The upper base insulating layer 109 may contain silicon nitride.

[0285] Next, referring to Fig. 21F, a resist mask 110 having a predetermined pattern is formed on the upper base insulating layer 109. The resist mask 110 selectively covers the region where the gate electrode layer 33 is to be formed.

[0286] Next, referring to Fig. 21G, unnecessary portions of the upper base insulating layer 109 and the base electrode layer 108 are removed. The unnecessary portions of the upper base insulating layer 109 and the base electrode layer 108 may be removed by an etching method through the resist mask 110. The etching method may be a dry etching method such as an RIE (Reactive Ion Etching) method. Thereby, the gate electrode layer 33 and the upper insulating layer 79 are formed.

[0287] Next, referring to FIG. 21H, unnecessary portions of the top base insulating layer 109 are removed. The unnecessary portions of the top base insulating layer 109 may be removed by an etching method through the resist mask 110. The etching method may be a dry etching method such as the RIE method. Thereby, the gate insulating layer 32 is formed.

[0288] Next, referring to FIG. 21I, the surface layer portion of the first main surface 3 of the semiconductor layer 2 exposed from the gate insulating layer 32 is selectively removed. The unnecessary portions of the first main surface 3 of the semiconductor layer 2 may be removed by an etching method through the resist mask 110. The etching method may be a dry etching method such as the RIE method.

[0289] The unnecessary portions of the first main surface 3 of the semiconductor layer 2 may be removed until a region where the n-type impurity concentration reaches a peak value (maximum value) in the n + type source region 26 is exposed. The unnecessary portions of the first main surface 3 of the semiconductor layer 2 may be removed until a region where the n-type impurity concentration reaches a peak value (maximum value) in the p + type contact region 27 is exposed.

[0290] In this step, a region located directly under the gate electrode layer 33 in the surface layer portion of the first main surface 3 of the semiconductor layer 2 is removed together with the gate insulating layer 32. Thereby, the recess portion 71 is formed, and at the same time, the gate electrode layer 33 including the main body portion 76 and the protruding portion 77 is formed on the gate insulating layer 32.

[0291] Also, in this step, due to the action of dry etching, the surface roughness Zr of the bottom wall 73 of the recess portion 71 becomes equal to or greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 (Zr ≧ Zs).

[0292] Since the structure of the recess portion 71 and the structure of the gate electrode layer 33 are as described above, specific descriptions are omitted. After the recess portion 71 is formed, the resist mask 110 is removed.

[0293] Next, referring to FIG. 21J, an insulating film 81 is formed on the first main surface 3 of the semiconductor layer 2. The insulating film 81 may be formed by a CVD method. The insulating film 81 may contain USG (Undoped Silica Glass). The insulating film 81 is formed so as to fill the space between the overhanging portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recess portion 71 and cover the gate electrode layer 33.

[0294] Next, referring to FIG. 21K, an insulating film 82 is formed on the insulating film 81. The insulating film 82 may be formed by a CVD method. The insulating film 82 contains an insulating material having properties different from those of the insulating material of the insulating film 81. The insulating film 82 may contain PSG (Phosphosilicate Glass). The insulating film 81 and the insulating film 82 form an insulating layer 34.

[0295] Next, referring to FIG. 21L, a resist mask 111 having a predetermined pattern is formed on the insulating film 82. The resist mask 111 selectively exposes the regions where contact holes (not shown) for the gate electrode 10 and contact holes 35 for the source electrode 11 are to be formed.

[0296] Next, referring to FIG. 21M, unnecessary portions of the insulating film 82 and unnecessary portions of the insulating film 81 are removed. The unnecessary portions of the insulating film 82 and the unnecessary portions of the insulating film 81 are removed by an etching method through the resist mask 111.

[0297] The etching method may be a dry etching method such as the RIE method. Thereby, contact holes (not shown) for the gate electrode 10 and contact holes 35 for the source electrode 11 are formed.

[0298] Next, referring to FIG. 21N, a heat treatment method is performed on the insulating film 81 and the insulating film 82. Thereby, the film forming property and strength of the insulating film 81 and the insulating film 82 are enhanced.

[0299] At the same time, the corners of the insulating film 81 and the corners of the insulating film 82 are rounded. Since the specific shapes of the insulating film 81 and the insulating film 82 are as described above, a specific description thereof will be omitted.

[0300] Next, referring to FIG. 21O, an electrode layer 91 serving as a base for the gate electrode 10 and the source electrode 11 is formed on the first main surface 3 of the semiconductor layer 2. In the step of forming the electrode layer 91, first, a first barrier electrode film 93 containing Ti is formed (see also FIG. 19).

[0301] The first barrier electrode film 93 may be formed by a sputtering method. The first barrier electrode film 93 is formed in a film shape along the first main surface 3 (the bottom wall 73 of the recess portion 71) of the semiconductor layer 2 and the outer surface of the insulating layer 34.

[0302] Next, a second barrier electrode film 94 containing TiN is formed on the first barrier electrode film 93 (see also FIG. 19). The second barrier electrode film 94 may be formed by a sputtering method. The second barrier electrode film 94 is formed in a film shape along the surface of the first barrier electrode film 93.

[0303] Next, referring to FIG. 21P, an electrode layer 92 serving as a base for the gate electrode 10 and the source electrode 11 is formed on the electrode layer 91. The electrode layer 92 may contain aluminum. The electrode layer 92 may be formed by an electroplating method (more specifically, an electro aluminum plating method).

[0304] Next, the electrode layer 91 and the electrode layer 92 are collectively patterned so as to become the gate electrode 10 and the source electrode 11. Thereafter, a drain electrode 23 is formed on the second main surface 4 of the semiconductor layer 2. Through the steps including the above, the semiconductor device 61 is formed.

[0305] FIG. 22 is a cross-sectional view of a portion corresponding to FIG. 19 and is a cross-sectional view of a semiconductor device 121 according to the fifth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 61, the same reference numerals will be given and the description will be omitted.

[0306] Referring to FIG. 22, p + The p-type contact region 27 includes a first region 29 and a second region 30, similar to the semiconductor device 1. p + The first region 29 of the p-type contact region 27 is formed within the p-type well region 25. p + The second region 30 of the p-type contact region 27 extends from the first region 29 into the n - type diode region 24.

[0307] n - In this form, the n-type diode region 24 is partitioned by the second region 30 of the p-type contact region 27. Thus, the n + lengths L3 and L4 of one side of the n-type diode region 24 are the dimensions of the region surrounded by the second region 30 of the p-type contact region 27 in this form. - In this form, the n + lengths L3 and L4 of one side of the n-type diode region 24 are the dimensions of the region surrounded by the second region 30 of the p-type contact region 27.

[0308] p + The second region 30 of the p-type contact region 27 crosses the boundary region between the p-type well region 25 and the n - type diode region 24. p + The second region 30 of the p-type contact region 27 forms a pn junction with the n - type diode region 24. Due to this pn junction, a second diode 31 is formed with the p + type contact region 27 as the anode and the n - type diode region 24 (drain electrode 23) as the cathode.

[0309] In this form, the JBS structure of each unit cell 15 includes, in addition to the first pn junction formed between the n - type diode region 24 and the p-type well region 25, a second pn junction formed between the n - type diode region 24 and the second region 30 of the p + type contact region 27.

[0310] As described above, according to the semiconductor device 121, the unit cell 15 has a JBS structure including a first pn junction and a second pn junction. Therefore, the first depletion layer extending from the first pn junction can suppress the current concentration and electric field concentration in the n - type diode region 24. Also, the second depletion layer extending from the second pn junction can suppress the current concentration and electric field concentration in the n - type diode region 24.

[0311] In particular, the second pn junction is formed in the boundary region between the n - type diode region 24 and the second region 30 of the p + type contact region 27. Thereby, the second depletion layer can be surely expanded from the second pn junction. As a result, the current concentration and electric field concentration in the n - type diode region 24 can be appropriately suppressed.

[0312] FIG. 23 is a plan view showing a part of the device formation region 6 and is a plan view of the semiconductor device 131 according to the sixth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 61, the same reference numerals are given and the description is omitted.

[0313] As shown in FIG. 23, in this embodiment, the plurality of unit cells 15 include a plurality of unit cells 15A having a relatively large aspect ratio L2 / L1 and a plurality of unit cells 15B having a relatively small aspect ratio L2 / L1.

[0314] The plurality of unit cells 15A preferably extend in a strip shape along the second direction Y, that is, the <11-20> direction. The aspect ratio L2 / L1 of the plurality of unit cells 15A is "2". That is, the unit cell 15 shown in FIG. 11 is applied as the plurality of unit cells 15A.

[0315] According to such a structure, local electric field concentration on the unit cell 15A can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1. The plurality of unit cells 15A are formed in a staggered arrangement in plan view instead of a matrix arrangement in plan view.

[0316] The aspect ratio L2 / L1 of the plurality of unit cells 15B is less than "2". The plurality of unit cells 15B are formed along the periphery of the device formation region 6. The plurality of unit cells 15B may be formed in a region partitioned by the periphery of the device formation region 6 and the plurality of unit cells 15A.

[0317] As described above, the semiconductor device 131 can also achieve the same effects as those described for the semiconductor device 61. Also, the plurality of unit cells 15B are formed in a region partitioned by the periphery of the device formation region 6 and the plurality of unit cells 15A. Thereby, a plurality of unit cells 15A and 15B can be formed in the device formation region 6 without waste, so that the current path can be appropriately increased.

[0318] FIG. 24 is a plan view showing a part of the device formation region 6 and is a plan view of the semiconductor device 141 according to the seventh embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 61, the same reference numerals are given and the description is omitted.

[0319] As shown in FIG. 24, the plurality of unit cells 15 are arranged so as to be connected to each other along the second direction Y, that is, the <11-20> direction. Thereby, the plurality (two or more) of unit cells 15 form one linear cell 53 extending in a strip shape along the second direction Y.

[0320] The linear cells 53 may be arranged in a plurality with intervals along the first direction X. In FIG. 14, a structure to which the unit cell 15 with the aspect ratio L2 / L1 shown in FIG. 11 being "2" is applied is shown. According to such a structure, local electric field concentration on the linear cells 53 can be suppressed, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0321] Between a plurality of n-type diode regions 24 adjacent to each other along the second direction Y, the p-type well regions 25 of one and / or the other unit cell 15 adjacent to each other along the second direction Y are interposed. - - Each linear cell 53 has a structure in which a plurality of n-type diode regions 24 are arranged at intervals along the second direction Y.

[0322] As described above, the semiconductor device 141 can also achieve the same effects as those described for the semiconductor device 61.

[0323] FIG. 25 is a plan view of a semiconductor device 151 according to the eighth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 61, the same reference numerals are given and the description is omitted.

[0324] Referring to FIG. 25, in the semiconductor device 151, the gate electrode 10 includes a gate pad 12, a gate finger 13, and a plurality (four in this embodiment) of gate lines 62A, 62B, 62C, 62D.

[0325] The gate pad 12 is formed at the central portion of the first main surface 3 of the semiconductor layer 2 in a plan view. In this embodiment, the gate pad 12 is formed in a square shape having four side surfaces 12A, 12B, 12C, 12D parallel to the side surfaces 5A, 5B, 5C, 5D of the semiconductor layer 2 in a plan view.

[0326] ​The gate fingers 13 are formed in a strip shape extending along the periphery of the device formation region 6 in the outer region 7. In this form, the gate fingers 13 are formed in an endless (square-ring shape) surrounding the device formation region 6 in plan view. The gate fingers 13 may be formed so as to partition the device formation region 6 from three directions.

[0327] The plurality of gate lines 62A to 62D are all drawn from the side surfaces 12A to 12D of the corresponding gate pads 12 toward the side surfaces 5A to 5D of the semiconductor layer 2. The plurality of gate lines 62A to 62D are all formed in a strip shape extending linearly toward the side surfaces 5A to 5D of the semiconductor layer 2.

[0328] More specifically, the plurality of gate lines 62A to 62D include a gate line 62A drawn from the side surface 12A of the gate pad 12, a gate line 62B drawn from the side surface 12B of the gate pad 12, a gate line 62C drawn from the side surface 12C of the gate pad 12, and a gate line 62D drawn from the side surface 12D of the gate pad 12.

[0329] In this form, the gate line 62A among the plurality of gate lines 62A to 62D is connected to the gate fingers 13. Thereby, in plan view, a C-shaped region is partitioned in the device formation region 6 by the inner edge of the gate electrode 10.

[0330] The source electrode 11 is formed in a C-shaped region partitioned by the inner edge of the gate electrode 10. In this form, the source electrode 11 is formed in a C-shape along the inner edge of the gate electrode 10.

[0331] FIG. 26 is a plan view in which the gate electrode 10 and the source electrode 11 are removed from FIG. 25, and is a diagram for explaining the structure on the first main surface 3 of the semiconductor layer 2.

[0332] On the first main surface 3 of the semiconductor layer 2, a gate pad layer 63, a gate finger layer 64, and a plurality (four in this embodiment) of gate line layers 65A, 65B, 65C, 65D are formed.

[0333] The gate pad layer 63 is formed in a region directly below the gate pad 12. The gate pad layer 63 is electrically connected to the gate pad 12. Although not shown, the gate pad 12 is electrically connected to the gate pad layer 63 through a contact hole formed in the insulating layer 34.

[0334] The gate pad layer 63 is formed at the center of the first main surface 3 of the semiconductor layer 2 in a plan view. In this embodiment, the gate pad layer 63 is set to a quadrangular shape having four side surfaces 63A, 63B, 63C, 63D parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

[0335] The gate finger layer 64 is formed in a region directly below the gate finger 13. The gate finger layer 64 is electrically connected to the gate finger 13. Although not shown, the gate finger 13 is electrically connected to the gate finger layer 64 through a contact hole formed in the insulating layer 34.

[0336] The gate finger layer 64 is drawn out from the gate pad layer 63 in a strip shape along the periphery of the device formation region 6. In this embodiment, the gate finger layer 64 is formed in an endless shape (square annular shape) surrounding the device formation region 6 in a plan view. The gate finger layer 64 may be formed so as to partition the device formation region 6 from three directions.

[0337] The plurality of gate line layers 65A to 65D are respectively formed in regions directly below the plurality of gate lines 62A to 62D. The plurality of gate line layers 65A to 65D are electrically connected to the corresponding gate lines 62A to 62D. Although not shown, the gate lines 62A to 62D are electrically connected to the gate line layers 65A to 65D through contact holes formed in the insulating layer 34.

[0338] The plurality of gate line layers 65A to 65D are all drawn from the side surfaces 63A to 63D of the corresponding gate pad layer 63 toward the side surfaces 5A to 5D of the semiconductor layer 2. The plurality of gate line layers 65A to 65D are all formed in a strip shape extending linearly toward the side surfaces 5A to 5D of the semiconductor layer 2.

[0339] More specifically, the plurality of gate line layers 65A to 65D include a gate line layer 65A drawn from the side surface 63A of the gate pad layer 63, a gate line layer 65B drawn from the side surface 63B of the gate pad layer 63, a gate line layer 65C drawn from the side surface 63C of the gate pad layer 63, and a gate line layer 65D drawn from the side surface 63D of the gate pad layer 63.

[0340] Among the plurality of gate line layers 65A to 65D, the gate line layer 65A is connected to the gate finger layer 64 in this form. As a result, in a plan view, a C-shaped region is defined in the device formation region 6 by the inner edge of the gate electrode 10.

[0341] A gate electrode layer 33 (planar gate structure) is formed in the C-shaped region defined by the gate pad layer 63, the gate finger layer 64, and the plurality of gate line layers 65A to 65D.

[0342] The gate electrode layer 33 is formed in a lattice shape in a plan view. In FIG. 26, the gate electrode layer 33 is shown by lattice lines. The gate electrode layer 33 is drawn from the gate pad layer 63, the gate finger layer 64, and the plurality of gate line layers 65A to 65D.

[0343] As a result, the gate electrode layer 33 is electrically connected to the gate pad 12, the gate finger 13, and the plurality of gate lines 62A to 62D via the gate pad layer 63, the gate finger layer 64, and the plurality of gate line layers 65A to 65D.

[0344] As described above, the semiconductor device 151 can also achieve the same effects as those described for the semiconductor device 61.

[0345] FIG. 27 is a cross-sectional view of a portion corresponding to FIG. 18, and is a cross-sectional view of a semiconductor device 161 according to the ninth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 61, the same reference numerals will be given and the description will be omitted.

[0346] Referring to FIG. 27, in this embodiment, the source electrode 11 includes a nickel layer 162, a gold layer 163, and a solder layer 164 laminated in this order on the electrode layer 92. A palladium layer may be interposed in the region between the gold layer 163 and the solder layer 164.

[0347] Although not shown, the gate electrode 10 also includes a nickel layer 162, a gold layer 163, and a solder layer 164 laminated in this order on the electrode layer 92, similar to the source electrode 11. Also, a palladium layer may be interposed in the region between the gold layer 163 and the solder layer 164.

[0348] As described above, the semiconductor device 161 can also achieve the same effects as those described for the semiconductor device 61.

[0349] Further, according to the semiconductor device 161, the gate electrode 10 and the source electrode 11 each include a solder layer 164. Thereby, the semiconductor device 161 can be mounted on the connection target in a posture in which the first main surface 3 of the semiconductor layer 2 faces the connection target.

[0350] FIG. 28 is a plan view showing a part of the device formation region 6, and is a plan view of a semiconductor device 171 according to the tenth embodiment of the present invention. In FIG. 28, the cross-sectional view along line A-A corresponds to the cross-sectional view shown in FIG. 18. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 61, the same reference numerals will be given and the description will be omitted.

[0351] Referring to FIG. 28, in this form, the unit cell 15 is formed in an open-ended strip shape extending along the second direction Y. In this form, a plurality of unit cells 15 are formed at intervals along the first direction X.

[0352] As a result, the plurality of unit cells 15 are formed in a stripe shape in plan view. The region between the plurality of adjacent unit cells 15 is partitioned by a line portion 172 extending along the second direction Y. The line portion 172 corresponds to the second line portion 17 of the semiconductor device 61 (also refer to FIG. 17).

[0353] Each unit cell 15, similar to the semiconductor device 61, includes an n - -type diode region 24, a p-type well region 25, an n + -type source region 26, and a p + -type contact region 27. The n - -type diode region 24, the p-type well region 25, the n + -type source region 26, and the p + -type contact region 27 each extend in an open-ended strip shape along the second direction Y in plan view.

[0354] The p-type well region 25 includes one p-type well region 25A and the other p-type well region 25B in this form. One p-type well region 25A extends in an open-ended strip shape along one end portion on the first direction X side of the n - -type diode region 24.

[0355] The other p-type well region 25B extends in an open-ended strip shape along the other end portion on the first direction X side of the n - -type diode region 24. The n - -type diode region 24 is partitioned by one p-type well region 25A and the other p-type well region 25B in this form.

[0356] n + -type source region 26 is formed in the surface layer portion of each p-type well region 25. The n +The p-type source region 26 is formed at a distance from the inner peripheral edge and the outer peripheral edge of the p-type well region 25. n + The p-type source region 26 extends in a strip shape with an end along the p-type well region 25 in a plan view.

[0357] p + The p-type contact region 27 is formed in the surface layer portion of each p-type well region 25. p + The p-type contact region 27 is formed in the surface layer portion of the p-type well region 25 and is located between the n - type diode region 24 and the n + type source region 26. In this form, the p-type contact region 27 extends in a strip shape with an end along the p-type well region 25 in a plan view. + p

[0358] As described above, the semiconductor device 171 can also achieve the same effects as those described for the semiconductor device 61.

[0359] In the semiconductor device 171, in order to adjust electrical characteristics such as breakdown voltage, the width along the first direction X of the unit cell 15 can be adjusted. On the other hand, in the semiconductor device 61, both the width along the first direction X and the width along the second direction Y of the unit cell 15 can be finely adjusted in order to adjust electrical characteristics. Therefore, it can be said that the degree of freedom in the design of the semiconductor device 61 is higher than that of the semiconductor device 171.

[0360] The structure of the aforementioned semiconductor device 121 (see FIG. 22) may be applied to the semiconductor device 171. That is, the p-type contact region 27 including the first region 29 and the second region 30 may be applied to the semiconductor device 171. + The p-type contact region 27 including the first region 29 and the second region 30 may be applied to the semiconductor device 171.

[0361] As described above, the embodiments of the present invention have been described, but the present invention can also be implemented in other forms.

[0362] In each of the foregoing embodiments, a polygonal unit cell 15 such as a triangular shape, a hexagonal shape, or an octagonal shape may be formed in a plan view. Further, in each of the foregoing embodiments, a circular or elliptical unit cell 15 may be formed in a plan view.

[0363] In each of the foregoing embodiments, an n-type diode region 24 having a polygonal shape such as a triangular shape, a hexagonal shape, or an octagonal shape may be formed in a plan view. - Further, in each of the foregoing embodiments, an n-type diode region 24 having a circular or elliptical shape may be formed in a plan view. -

[0364] In each of the foregoing embodiments, the impurity region 19 may include a crystal defect region including crystal defects (Crystal defects) selectively introduced into the semiconductor layer 2 (n-type epitaxial layer 22). The crystal defects may include lattice defects (Lattice defects) typified by interstitial atoms and atomic vacancies. -

[0365] The crystal defect region may have a crystal defect density N2 higher than the n-type impurity density N1 of the n-type epitaxial layer 22 of the semiconductor layer 2 (n-type impurity density N1 < crystal defect density N2). -

[0366] In each of the foregoing embodiments, the impurity region 19 may include a high-resistance region. The high-resistance region may have a resistivity ρ2 higher than the resistivity ρ1 of the semiconductor layer 2 (n-type epitaxial layer 22) (resistivity ρ1 < resistivity ρ2). The high-resistance region may be formed by a crystal defect region including crystal defects (Crystal defects) selectively introduced into the semiconductor layer 2 (n-type epitaxial layer 22). - -

[0367] In each of the foregoing embodiments, a semiconductor layer 2 having a structure in which the impurity region 19 is not formed at the intersection 18 may be employed.

[0368] ​​​​​In each of the foregoing embodiments, an n-type semiconductor substrate 21 made of silicon (Si) may be applied instead of the wide bandgap semiconductor. + The type semiconductor substrate 21 may be applied.

[0369] In each of the foregoing embodiments, an n-type epitaxial layer 22 made of silicon (Si) may be applied instead of the wide bandgap semiconductor. - The type epitaxial layer 22 may be applied.

[0370] In each of the foregoing embodiments, the semiconductor layer 2 may include an n-type semiconductor substrate manufactured by the FZ method. In this case, a high-resistance region (drift region) corresponding to the foregoing n-type epitaxial layer 22 is formed by the n-type semiconductor substrate. Further, a low-resistance region (drain region) corresponding to the foregoing n-type semiconductor substrate is formed by implanting n-type impurities into the second main surface 4 of the semiconductor layer 2. - The type semiconductor substrate may be included. In this case, - By the type semiconductor substrate, - A high-resistance region (drift region) corresponding to the foregoing n-type epitaxial layer 22 is formed. Also, by implanting n-type impurities into the second main surface 4 of the semiconductor layer 2, + A low-resistance region (drain region) corresponding to the foregoing n-type semiconductor substrate is formed.

[0371] In each of the foregoing embodiments, the first direction X and the second direction Y are not limited to the directions along the side surfaces 5A to 5D of the semiconductor layer 2. For example, in each of the foregoing embodiments, the relationship between the first direction X and the second direction Y may be interchanged. That is, the first direction X may be set in the <11-20> direction, and the second direction Y may be set in a direction perpendicular to the <11-20> direction.

[0372] In this case, the plurality of unit cells 15 are preferably arranged at intervals along the <11-20> direction. Further, when the unit cell 15 is formed in a rectangular shape in plan view, it is preferably formed in a rectangular shape extending along the <11-20> direction.

[0373] In addition, in each of the above-described embodiments, the first direction X and the second direction Y may be directions along the diagonal direction of the semiconductor layer 2. Also in this case, the plurality of unit cells 15 are preferably arranged at intervals along the <11-20> direction. Further, when the unit cell 15 is formed in a rectangular shape in plan view, it is preferably formed in a rectangular shape extending along the <11-20> direction.

[0374] In each of the above-described embodiments, instead of the planar gate structure, a trench gate structure may be employed. The trench gate structure may be formed along the above-described first line portion 16 and second line portion 17 so as to partition the unit cell 15.

[0375] The trench gate structure may include a gate electrode layer 33 embedded in a gate trench formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 with a gate insulating layer 32 interposed therebetween. The side wall of the gate trench may be formed perpendicular to the first main surface 3 of the semiconductor layer 2. The gate trench may be formed in a tapered shape in cross section in which the opening area is larger than the area of the bottom wall.

[0376] The gate insulating layer 32 may be formed along the side wall and the bottom wall of the gate trench so as to partition a concave space in the gate trench. The gate electrode layer 33 may be embedded in the concave space partitioned by the gate insulating layer 32.

[0377] n - A part of the n-type epitaxial layer 22, the p-type well region 25, and n + type source region 26 may be formed so as to face the gate electrode layer 33 with the gate insulating layer 32 interposed therebetween. In this case, in the p-type well region 25, n - a part of the type epitaxial layer 22 and n + the portion sandwiched between the type source regions 26 serves as the channel of the MISFET 9.

[0378] Thus, even with the structure adopting the trench gate structure, the same effects as those described in the foregoing embodiments can be achieved.

[0379] In each of the foregoing embodiments, + instead of the n-type semiconductor substrate 21, a p-type semiconductor substrate may be adopted. That is, in each of the foregoing embodiments, instead of the MISFET 9, an IGBT (Insulated Gate Bipolar Transistor), which is an example of an insulated gate type transistor, may be formed. + In this case, the "source" of the MISFET 9 is read as the "emitter" of the IGBT. Also, the "drain" of the MISFET 9 is read as the "collector" of the IGBT.

[0380] This application corresponds to Japanese Patent Application No. 2017-011609 filed with the Japan Patent Office on January 25, 2017, and the entire disclosure of this application is incorporated herein by reference.

[0381] Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims.

[0382] Hereinafter, characteristic examples extracted from this specification and the drawings are shown.

[0383]

[0384] ​A semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer; a well region of a second conductivity type formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; a unit cell including a region of the first conductivity type formed in a surface layer portion of the well region; a gate electrode layer facing the well region and the region of the first conductivity type with a gate insulating layer interposed therebetween; and a first main surface electrode covering the diode region and the region of the first conductivity type on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region, and forming an ohmic junction with the region of the first conductivity type.

[0385] [A2] The semiconductor device according to A1, wherein the well region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the well region and the diode region.

[0386] [A3] The semiconductor device according to A1 or A2, wherein the well region surrounds the diode region in a plan view.

[0387] [A4] The semiconductor device according to any one of A1 to A3, wherein the unit cell is formed in a region between the diode region and the region of the first conductivity type in the surface layer portion of the well region, and includes a contact region of the second conductivity type having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region.

[0388] [A5] The semiconductor device according to A4, wherein the contact region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the contact region and the diode region.

[0389] [A6] The semiconductor device according to any one of A1 to A5, wherein a plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a part of the well region of each of the unit cells.

[0390] [A7] The semiconductor device according to A6, wherein the plurality of unit cells are arranged at intervals along an arbitrary first direction and a second direction intersecting the first direction.

[0391] [A8] The semiconductor device according to A7, wherein the plurality of unit cells are arranged in a matrix.

[0392] [A9] The semiconductor device according to A7, wherein the plurality of unit cells are arranged in a staggered pattern.

[0393] [A10] The semiconductor device according to A6, wherein the plurality of unit cells are arranged adjacent to each other in an arbitrary one direction to form a single linear cell.

[0394] [A11] The semiconductor device according to A10, wherein a plurality of the linear cells are arranged at intervals along an intersecting direction intersecting the one direction.

[0395] [A12] The semiconductor device according to any one of A1 to A11, wherein the unit cell is formed in a rectangular shape in plan view.

[0396] [A13] The semiconductor device according to any one of A1 to A12, wherein the unit cell is formed in a rectangular shape in plan view.

[0397] [A14] The semiconductor device according to any one of A1 to A13, wherein the unit cell has a first side and a second side extending along directions intersecting each other, and an aspect ratio of the unit cell defined by a ratio of a length of the second side to a length of the first side is 1 or more and 4 or less.

[0398] The semiconductor device according to any one of A1 to A14, wherein a ratio of a planar area of the diode region to a planar area of the unit cell is 0.005 or more and 0.01 or less.

[0399] [A16] The semiconductor layer includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. The first main surface of the semiconductor layer is formed by the epitaxial layer, and the second main surface of the semiconductor layer is formed by the semiconductor substrate. The semiconductor device according to any one of A1 to A15.

[0400] [A17] The semiconductor device according to A16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0401] [A18] The semiconductor device according to A16 or A17, wherein the epitaxial layer has a thickness of 20 μm or more.

[0402] [A19] In the semiconductor layer, a device formation region and an outer region outside the device formation region are set. The unit cell is formed in the device formation region, and a ratio of a planar area of the device formation region to a planar area of the semiconductor layer is 70% or more. The semiconductor device according to any one of A1 to A18.

[0403] [A20] The semiconductor device according to any one of A1 to A19, further including a second main surface electrode that covers the second main surface of the semiconductor layer and forms an ohmic junction with the semiconductor layer.

[0404] A semiconductor device comprising: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer; a well region of a second conductivity type formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a unit cell including a region of the first conductivity type formed in a surface layer portion of the well region; a gate electrode layer having sidewalls facing the well region and the region of the first conductivity type with a gate insulating layer interposed therebetween and located above the region of the first conductivity type; an insulating layer covering the gate electrode layer; and a first main surface electrode electrically connected to the diode region and the region of the first conductivity type on the first main surface of the semiconductor layer, the first main surface electrode forming a Schottky junction with the diode region. The first main surface of the semiconductor layer includes a recess recessed toward the second main surface side so as to expose at least a part of the region of the first conductivity type in a region located laterally of the gate electrode layer. The insulating layer includes a first portion covering the recess so as to extend from the sidewalls of the gate electrode layer along the recess, and a second portion covering the sidewalls of the gate electrode layer so as to extend along the sidewalls of the gate electrode layer. A thickness of the first portion along a parallel direction parallel to the first main surface of the semiconductor layer is larger than a thickness of the second portion along the parallel direction.

[0405] [B2] The well region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the well region and the diode region. The semiconductor device according to B1.

[0406] [B3] The well region surrounds the diode region in a plan view. The semiconductor device according to B1 or B2.

[0407] [B4]The unit cell is formed in a region between the diode region and the first conductivity type region in a surface layer portion of the well region, and includes a second conductivity type contact region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region. The semiconductor device according to any one of B1 to B3.

[0408] [B5]The contact region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the contact region and the diode region. The semiconductor device according to B4.

[0409] [B6]A plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a part of the well region of each unit cell. The semiconductor device according to any one of B1 to B5.

[0410] [B7]The plurality of unit cells are arranged at intervals along an arbitrary first direction and a second direction intersecting the first direction. The semiconductor device according to B6.

[0411] [B8]The plurality of unit cells are arranged in a matrix. The semiconductor device according to B7.

[0412] [B9]The plurality of unit cells are arranged in a staggered pattern. The semiconductor device according to B7.

[0413] [B10]The plurality of unit cells are arranged adjacent to each other in an arbitrary one direction to form a single linear cell. The semiconductor device according to B6.

[0414] [B11]A plurality of the linear cells are arranged at intervals along an intersection direction intersecting the one direction. The semiconductor device according to B10.

[0415] [B12]The semiconductor device according to any one of B1 to B11, wherein the unit cell is formed in a square shape in plan view.

[0416] [B13]The semiconductor device according to any one of B1 to B12, wherein the unit cell is formed in a rectangular shape in plan view.

[0417] [B14]The unit cell has a first side and a second side extending along directions intersecting each other, and the aspect ratio of the unit cell defined by the ratio of the length of the second side to the length of the first side is 1 or more and 4 or less. The semiconductor device according to any one of B1 to B13.

[0418] [B15]The semiconductor device according to any one of B1 to B14, wherein the ratio of the planar area of the diode region to the planar area of the unit cell is 0.005 or more and 0.01 or less.

[0419] [B16]The semiconductor layer includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. The first main surface of the semiconductor layer is formed by the epitaxial layer, and the second main surface of the semiconductor layer is formed by the semiconductor substrate. The semiconductor device according to any one of B1 to B15.

[0420] [B17]The semiconductor device according to B16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0421] [B18]The semiconductor device according to B16 or B17, wherein the epitaxial layer has a thickness of 20 μm or more.

[0422] [B19]In the semiconductor layer, a device formation region and an outer region which is an area outside the device formation region are set. The unit cell is formed in the device formation region, and the ratio of the planar area of the device formation region to the planar area of the semiconductor layer is 70% or more. The semiconductor device according to any one of B1 to B18.

[0423] [B20] The semiconductor device according to any one of B1 to B19, further comprising a second main surface electrode that covers the second main surface of the semiconductor layer and forms an ohmic contact with the semiconductor layer.

[0424] [C1] A semiconductor layer having a first main surface on one side and a second main surface on the other side, a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer, and a unit cell including an impurity region of the first conductivity type formed in a surface layer portion of the well region; a gate electrode layer facing the well region and the impurity region with a gate insulating layer interposed therebetween and having sidewalls positioned above the impurity region; an insulating layer covering the gate electrode layer; and a first main surface electrode electrically connected to the diode region and the impurity region on the first main surface of the semiconductor layer, the first main surface electrode forming a Schottky contact with the diode region. The first main surface of the semiconductor layer includes a recessed portion recessed toward the second main surface side so as to expose at least a part of the impurity region in a region located laterally of the gate electrode layer. The insulating layer includes a first portion extending in a horizontal direction along the first main surface from the sidewall of the gate electrode layer and covering the recessed portion, and a second portion formed above the first portion so as to extend along the sidewall of the gate electrode layer and covering the sidewall of the gate electrode layer. A distance (length) of the first portion in the horizontal direction with reference to the sidewall of the gate electrode layer is larger than a distance (length) of the second portion in the horizontal direction with reference to the sidewall of the gate electrode layer.

[0425] [C2] The semiconductor device according to C1, wherein the first portion is thicker than the gate insulating layer.

[0426] [C3] The semiconductor device according to C1 or C2, wherein the first portion extends in the horizontal direction from the sidewall of the gate electrode layer in a region closer to the first main surface side than an upper end portion of the gate electrode layer.

[0427] [C4]The semiconductor device according to any one of C1 to C3, wherein the well region forms a pn junction with the diode region.

[0428] [C5]The semiconductor device according to any one of C1 to C4, wherein the well region surrounds the diode region in a plan view.

[0429] [C6]The semiconductor device according to any one of C1 to C5, wherein the unit cell is formed in a region between the diode region and the impurity region in a surface layer portion of the well region, and includes a contact region of a second conductivity type having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region.

[0430] [C7]The semiconductor device according to C6, wherein the contact region forms a pn junction with the diode region.

[0431] [C8]The semiconductor device according to any one of C1 to C7, wherein a plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a part of the well region of each unit cell.

[0432] [C9]The semiconductor device according to C8, wherein the plurality of unit cells are arranged at intervals in an arbitrary first direction and a second direction intersecting the first direction.

[0433] [C10]The semiconductor device according to C9, wherein the plurality of unit cells are arranged in a matrix or a staggered pattern.

[0434] [C11]The semiconductor device according to C8, wherein the plurality of unit cells are arranged adjacent to each other in an arbitrary one direction to form a linear cell.

[0435] [C12]The semiconductor device according to C11, wherein a plurality of the linear cells are arranged at intervals in an intersecting direction intersecting the one direction.

[0436] [C13] The semiconductor device according to any one of C1 to C12, wherein the unit cell is formed in a square shape in plan view.

[0437] [C14] The semiconductor device according to any one of C1 to C13, wherein the unit cell has a first side and a second side extending in directions intersecting with each other, and an aspect ratio of the unit cell defined by a ratio of a length of the second side to a length of the first side is 1 or more and 4 or less.

[0438] [C15] The semiconductor device according to any one of C1 to C14, wherein a ratio of a planar area of the diode region to a planar area of the unit cell is 0.005 or more and 0.01 or less.

[0439] [C16] The semiconductor device according to any one of C1 to C15, wherein the semiconductor layer has a stacked structure including a semiconductor substrate and an epitaxial layer, the first main surface is formed by the epitaxial layer, and the second main surface is formed by the semiconductor substrate.

[0440] [C17] The semiconductor device according to C16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0441] [C18] The semiconductor device according to C16 or C17, wherein the epitaxial layer has an impurity concentration lower than an impurity concentration of the semiconductor substrate.

[0442] [C19] The semiconductor device according to any one of C1 to C18, further including a device region set in the semiconductor layer and an outer region set outside the device region in the semiconductor layer, wherein the unit cell is formed in the device region.

[0443] [C20] The semiconductor device according to any one of C1 to C19, further including a second main surface electrode covering the second main surface of the semiconductor layer and forming an ohmic junction with the semiconductor layer.

Description of Reference Numerals

[0444] 1 Semiconductor device 2 Semiconductor layer 3 First main surface of the semiconductor layer 4 Second main surface of the semiconductor layer 6 Device formation region 7 Outer region 8 SBD 9 MISFET 11 Source electrode (main surface electrode) 15 Unit cell 21 n + -type semiconductor substrate 22 n - -type epitaxial layer 24 n - -type diode region 25 p-type well region 26 n + -type source region (first conductivity type region) 27 p + -type contact region 32 Gate insulating layer 33 Gate electrode layer 51 Semiconductor device 52 Semiconductor device 60 Linear cell 61 Semiconductor device 121 Semiconductor device 131 Semiconductor device 141 Semiconductor device 151 Semiconductor device 161 Semiconductor device L1 Length of the unit cell L2 Length of the unit cell SE Planar area of the first main surface of the semiconductor layer SF Planar area of the device formation region SC Planar area of the unit cell SD n - Planar area of the -type diode region

Claims

1. A semiconductor layer having a first main surface on one side and a second main surface on the other side, A unit cell including a well region of a second conductivity type formed in a surface layer portion of the first main surface and an impurity region of a first conductivity type formed in a surface layer portion of the well region, the unit cell having a recess portion recessed toward the second main surface side in the surface layer portion, A gate electrode facing the well region with a gate insulating layer interposed therebetween, An embedded portion of an insulating material formed between the gate electrode and the well region so as to be sandwiched between the gate electrode and a bottom wall of the recess portion and extending to below the gate electrode, The embedded portion is in contact with the gate insulating layer, A semiconductor device in which a thickness of the embedded portion is larger than a thickness of the gate insulating layer.

2. The semiconductor device according to claim 1, wherein the impurity region is formed on a bottom wall of the recess portion.

3. The semiconductor device according to claim 1 or 2, wherein a depth of the recess portion is 0.5 m or more and 5 m or less.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer has a stacked structure including a semiconductor substrate on the second main surface side and an epitaxial layer on the first main surface side.

5. The semiconductor device according to claim 4, wherein the epitaxial layer has a thickness of 5 μm or more.

6. The semiconductor device according to claim 5, wherein the epitaxial layer has a thickness of 20 μm or more.

7. The semiconductor device according to claim 5, wherein the epitaxial layer has a thickness of 5 μm or more and 30 μm or less.

8. The semiconductor device according to any one of claims 1 to 7, wherein the unit cell includes a contact region of a second conductivity type formed in a surface layer portion of the well region and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region.

9. Including a plurality of the unit cells, The semiconductor device according to any one of claims 1 to 8, wherein the plurality of unit cells are arranged in a matrix.

10. Including a plurality of the unit cells, The semiconductor device according to any one of claims 1 to 8, wherein the plurality of unit cells are arranged in a staggered pattern.

11. Further including an insulating layer formed on the first main surface of the semiconductor layer, The semiconductor device according to any one of claims 1 to 10, wherein the embedded portion forms a part of the insulating layer.

12. The semiconductor device according to claim 11, wherein the insulating layer covers the gate electrode.

13. The semiconductor device according to claim 12, further comprising a first main surface electrode formed on the insulating layer and electrically connected to the impurity region.

14. The semiconductor device according to claim 13, further comprising a second main surface electrode covering the second main surface.

15. The first main surface electrode is a source electrode, The semiconductor device according to claim 14, wherein the second main surface electrode is a drain electrode.

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