Scan Chain Testing of Column Redundancy Logic and Memory with Multiplexing

Abstract

A memory is provided in which a scan chain covers redundancy logic for column redundancy as well as a redundancy multiplexer in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexer during a scan mode of operation.

Description

Technical Field

[0001]

[0001] This application relates to a memory having column redundancy, and more particularly, to a scan chain test of its column redundancy logic and a memory with column redundancy multiplexing.

Background Art

[0002]

[0002] A memory having column redundancy includes redundancy logic for determining whether a read operation or a write operation to a column should be shifted to an adjacent column due to a column defect. Each column includes a redundancy multiplexer for shifting a read or write operation to an adjacent column. However, in an existing test facilitation design (DFT: design-for-test) scan chain, errors in the redundancy logic or the redundancy multiplexer are not tested.

Summary of the Invention

[0003]

[0003] A memory is provided, the memory comprising a plurality of columns, each column including a bit line, a complement bit line, a first read multiplexer transistor coupled to the bit line and having a read terminal, a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal, a write driver having a write data output terminal and a complement write data output terminal, a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complement write data output terminal and a second pair of input terminals coupled to the read terminal and the complement read terminal, and a sense amplifier coupled to an output from the scan multiplexer.

[0004] A method for testing columns in a memory is provided, the method comprising routing a shift-in signal to a write driver via a write column redundancy multiplexer in response to a triggering edge of a scan clock signal in accordance with a column redundancy signal of a column being false during a scan mode of operation; processing the shift-in signal via the write driver to form a pair of write driver output signals; routing the pair of write driver output signals to a sense amplifier via a scan multiplexer; sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and routing the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer.

[0005]

[0005] A memory is provided. The memory includes a plurality of columns. Each column includes a bit line, a complementary bit line, a first read multiplexer transistor coupled to the bit line and having a read terminal, a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal, a sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complementary read terminal, a read column redundancy multiplexer having a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to a sense amplifier in an adjacent column, and a data output latch having an input terminal coupled to the output terminal of the read column redundancy multiplexer via a direct electrical connection.

[0006]

[0006] A memory is provided. The memory is a redundancy decoder including a gating logic gate and a fuse decoder having an enable input terminal coupled to the output terminal of the gating logic gate, and further includes a plurality of output terminals for a plurality of decoded address signals. The memory also includes a plurality of column redundancy logic circuits arranged in series. Each column redundancy logic circuit has a set of input terminals for receiving respective sets of redundancy address bits and an output terminal for a column redundancy signal. The memory further includes a scan flip-flop configured to latch the column redundancy signal from the last column redundancy logic circuit among the column redundancy logic circuits.

[0007]

[0007] These and additional advantages may be more fully understood through the following description of the embodiments for carrying out the invention.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

[0009] Diagram of a redundancy logic circuit within the memory of FIG. 1, according to one aspect of the present disclosure.

Figure 3

[0010] Diagram of a conventional column in which a column redundancy multiplexer is bypassed by a DFT scan chain.

Figure 4

[0011] Diagram showing a column in which a column redundancy multiplexer is included within a DFT scan chain, according to a first aspect of the present disclosure.

Figure 5

[0012] Diagram showing a column in which a column redundancy multiplexer is included within a DFT scan chain, according to a second aspect of the present disclosure.

Figure 6

[0013] Diagram showing a redundancy decoder for the memory of FIG. 1, according to one aspect of the present disclosure.

Figure 7

[0014] Timing diagram of signals related to the redundancy decoder of FIG. 6.

Figure 8

[0015] Flowchart of a method for scanning a redundancy multiplexer within a memory column, according to one aspect of the present disclosure.

[0009]

[0016] The implementations of the present disclosure and their advantages are best understood by referring to the following detailed description. It should be understood that like reference numbers are used to identify like elements shown in one or more of the figures.

DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0017] An improved column redundancy scheme is provided to memory to enable a DFT scan chain to scan for errors in redundancy logic and column redundancy multiplexers. An exemplary memory 100 having this improved column redundancy is shown in FIG. 1. Memory 100 includes a plurality of N + 1 columns of bit cells spanning from the Nth column to the 0th column, where N is a positive integer. Memory 100 also includes at least one redundant column. For the sake of brevity, the expression "column" is understood herein to refer to a non-redundant column without any further explanation. During testing of memory 100, there may be no defective columns. In that case, the redundant column(s) are not used. Thus, a read or write operation addressed to a particular column will occur to that column. Since there is no shift due to column redundancy being disabled, all columns can be considered unshifted columns. However, this is not the case when there are defective columns. The array of columns can then be divided into unshifted columns and shifted columns depending on the position of the defective column. For example, assume there is a defect in the ith column. The subsequent columns from the (i + 1)th column to the (N + 1)th column are unshifted, but the preceding columns from the ith column to the 0th column are shifted. For example, when a read or write operation is addressed to the 0th column while column redundancy is enabled, the read or write operation actually occurs to the redundant column.

[0011]

[0018] To implement column redundancy, a fuse decoder (not shown) can function to decode a fuse word to generate a plurality of decoded redundant address signals. For example, the decoding can generate three decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3>. The number of decoded address redundancy signals and their bit widths can be changed in alternative implementations. To process the decoded redundant address signals, each column is associated with a corresponding redundancy logic circuit. Thus, there is an Nth redundancy logic circuit (red logic col (N)) for the Nth column, an (N - 1)th redundancy logic circuit (red logic col (N - 1)) for the (N - 1)th column, and similarly, a 0th redundancy logic circuit (red logic col (0)) for the 0th column. The redundancy logic circuit for each column receives one bit each from the decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3>. Thus, each redundancy logic circuit receives three redundant address bits fa, fb, and fc.

[0012]

[0019] In one implementation, the decoded redundancy address bits fa, fb, and fc are active low. Thus, a defective column is identified by the decoded redundancy address bits fa, fb, and fc all being logic 0 in an implementation where they are all active low. Alternatively, an active high implementation where the decoded redundancy address bits fa, fb, and fc are all logic 1 may be used. As used herein, a binary signal is considered to be asserted when the binary logic signal is true, regardless of whether the true binary state is represented by an active low convention or an active high convention. Each redundancy logic circuit is configured to assert a column redundancy signal (shown as match_next) when its decoded redundancy address bits fa, fb, and fc are logically true (asserted). The terms "column redundancy signal" and "match_next" are used interchangeably herein. Thus, in an active high implementation, each redundancy logic circuit is configured to assert its match_next signal when its bits fa, fb, and fc are all binary 1.

[0013]

[0020] The redundancy logic circuits can be considered to be arranged in series starting from the Nth redundancy logic circuit to the 0th redundancy logic circuit. In this series arrangement, the match_next signal from the preceding redundancy logic circuit is received as the match_prev signal in the subsequent redundancy logic circuit. For example, the match_next signal from the Nth redundancy logic circuit is received as its match_prev signal by the (N - 1)th redundancy logic circuit. Each redundancy logic circuit is configured to assert the match_next signal when the match_prev signal is asserted. In the aforementioned example where the i-th column is the defective column, the i-th redundancy logic circuit will thus assert its match_next signal. Therefore, the subsequent redundancy logic circuits from the (i - 1)th redundancy logic circuit to the 0th redundancy logic circuit will also thus assert their match_next signals because each of the match_prev signals is asserted. In the following description, it is assumed that the match_next signal is a logic high signal that is logic 1 when asserted.

[0014]

[0021] The exemplary redundancy logic circuit 200 is shown in more detail in FIG. 2. Logic gates such as NAND gate 205 process the decoded redundancy address bits of fa, fb, and fc to generate an output signal that is inverted by inverter 210. NOR gate 215 NORs the output signal from inverter 210 with the match_prev signal. Inverter 220 inverts the output signal from NOR gate 215 to generate the match_next signal. If any one of the bits fa, fb, and fc is logic 0, the output of NAND gate 205 is logic 1. This logic 1 is inverted by inverter 210 to generate logic 0 for NOR gate 215. If the match_prev signal is also logic 0, the output of NOR gate 215 will thus be logic 1 which is inverted by inverter 220 to force the match_next signal to logic 0. However, if the fa, fb, and fc bit signals are all logic 1 and / or the match_prev signal is logic 1, the match_next signal is asserted.

[0015]

[0022] Referring back to memory 100, it should be noted that each column receives a match_next signal from its corresponding redundancy logic circuit. As will be further explained herein, each column includes a write column redundancy multiplexer and a read column redundancy multiplexer. In a write operation to a column with an asserted match_next signal, the write column redundancy multiplexer directs the write data bit to the preceding column. For example, if the i-th column has an asserted match_next signal, its write column redundancy multiplexer directs that the write data bit be written to the (i - 1)-th column. However, if the i-th column has a false match_next signal, its write column redundancy multiplexer directs the write data bit to the write driver of the i-th column. The read column redundancy multiplexer is similar in that it selects a bit taken from the current column or the preceding column depending on whether the match_next signal of the current column is true or false.

[0016]

[0023] In a conventional memory having column redundancy, it was typical that neither the write column redundancy multiplexer nor the read column redundancy multiplexer was covered by the DFT scan chain. An exemplary conventional column 300 is shown in FIG. 3. For clarity of explanation, only a single bit cell 305 coupled to bit line bl and complementary bit line blb is shown, but it should be understood that a column such as column 300 includes a plurality of bit cells arranged in rows. During a write operation to column 300, an input data bit din from a core power domain powered by a core power supply is level-shifted by a level shifter (LS) 310 to a din signal in a memory power domain powered by a memory power supply. During a scan operation mode, a shift-in signal is provided by a scan chain flip-flop such as a master-slave flip-flop 315 for the scan chain. During a write operation, a write column redundancy multiplexer (write red mux) 320 routes the level-shifted din signal depending on whether a match_next signal is asserted or de-asserted. When the match_next signal is false, the write column redundancy multiplexer 320 passes the level-shifted din signal to a write driver 325. However, when the match_next signal is true, the write column redundancy multiplexer 320 passes the level-shifted din signal as a din_next signal to the preceding column. If a subsequent column has already asserted its match_next signal, column 300 receives, at the write driver 325, the din_next signal of this subsequent column as a din_prev signal. Based on the input signal to the write driver (either the level-shifted din signal in the case of no redundancy or the din_prev signal when a subsequent column has asserted its match_next signal), the write driver 325 drives a write data signal (wd) and a complementary write data signal (wd_n) accordingly.

[0017]

[0024] During the write operation to column 300, the write multiplexer signal wm is asserted, switching on the n-type metal oxide semiconductor (NMOS) write multiplexer transistor M1 to couple the wd signal to the bit line bl. Similarly, the assertion of the write multiplexer signal wm switches on another NMOS write multiplexer transistor M2 to couple the wd_n signal to the complementary bit line blb. Then, the bit cell 305 can be written accordingly to complete the write operation.

[0018]

[0025] During the read operation with no defect in column 300, the active-low read multiplexer signal rm is discharged, switching on the p-type metal oxide semiconductor (PMOS) read multiplexer transistor P1 to couple the true bit line to the sense amplifier (SAMP) 330. Similarly, the discharge of the read multiplexer signal rm switches on another PMOS read multiplexer transistor P2 to couple the complementary bit line blb to the SAMP 330. Then, the SAMP 330 can make a bit decision. The read column redundancy multiplexer (read red mux) 335 selects the bit decision from the SAMP 330 when the match_next signal of column 300 is false. When the match_next signal is true, the read column redundancy multiplexer 335 selects the bit decision from the previous column (SAMP next). During the read operation for a subsequent column after the match_next signal is asserted, the subsequent column selects the bit decision from the SAMP 330 (SAMP prev).

[0019]

[0026] During the read operation, the scan signal for DFT scan of column 300 is not asserted. The scan signal controls a scan mux 340 that selects a bit decision from the read column redundancy multiplexer 335 during the read operation. Then, a data output latch 345 can latch the output data bits to complete the read operation. During the scan operation mode, the scan mux 340 responds to the assertion of the scan signal by selecting a shift-in signal from the master slave flip flop 315. Thus, such a conventional DFT scan bypasses the operations of the write column redundancy multiplexer 320 and the read column redundancy multiplexer 335.

[0020]

[0027] To provide the ability to include write and read column redundancy multiplexers in DFT scan, as shown in FIG. 4, an improved column 400 is provided. As described for column 300, only a single bit cell 305 coupled to bit line bl and complementary bit line blb is shown within column 400, but it should be understood that column 400 includes a plurality of bit cells arranged in rows. Referring again to memory 100, each of the columns in the range from the Nth column to the 0th column can be implemented as shown for column 400. Similar to the description for column 300, input data bit din from the core power supply domain powered by the core power is level-shifted by level shifter (LS) 310 within column 400 to a din signal in the memory power supply domain powered by the memory power during a write operation to column 400. During the scan operation mode, the shift-in signal is provided by a master latch within master slave flip-flop 315 included in the scan chain. Write red mux 320 multiplexes the level-shifted din signal depending on whether the match_next signal is true or false. When the match_next signal for column 400 is false, write red mux 320 passes the level-shifted din signal through the first output terminal to the input terminal of write driver 325 during a write operation. However, when the match_next signal is true, write red mux 320 passes the level-shifted din signal through the second output terminal to the preceding column as the din_next signal. If a subsequent column has already asserted its match_next signal, column 400 receives the din_next signal of this subsequent column as the din_prev signal at write driver 325. Based on the input signal to the write driver (either the level-shifted din signal without redundancy or the din_prev signal if a subsequent column has asserted its match_next signal), write driver 325 drives the corresponding write data signal (wd) and complementary write data signal (wd_n).

[0021]

[0028] During the write operation to column 400, the active-high write multiplexer signal wm is asserted, switching on the write multiplexer transistor M1 to couple the wd signal to the bit line bl, and switching on the write multiplexer transistor M2 to couple the wd_n signal to the complementary bit line blb. Then, the bit cell 305 can be written accordingly to complete the write operation.

[0022]

[0029] The read operation for column 400 also occurs in the same manner as described for column 300. During the read operation where there is no defect in column 400, the active-low read multiplexer signal rm is discharged, switching on the read multiplexer transistors P1 and P2 to couple the true bit line and the complementary bit line to the scan multiplexer 405. The source of the read multiplexer transistor P1 can be considered to form the read terminal. Similarly, the source of the read multiplexer transistor P2 can be considered to form the complementary read terminal. The scan multiplexer 405 includes a first pair of input terminals coupled to the read terminal and the complementary read terminal. During the read operation, the scan signal is de-asserted to control the scan multiplexer 405, selecting its first pair of input terminals, and thus selecting the bit line signals routed through the read multiplexer transistors P1 and P2. Then, SAMP330 can make a bit decision. The read column redundancy multiplexer (read red mux) 410 includes a first input terminal coupled to the output terminal of SAMP330. The read column redundancy multiplexer 420 selects this first input terminal and thus selects the bit decision from SAMP330 when the match_next signal for column 400 is false. SAMP330 also includes a second input terminal coupled to the sense amplifier in the preceding column. When the match_next signal is true, the read column redundancy multiplexer 410 selects this second input terminal and thus selects the bit decision (SAMP next) from the preceding column. The data output latch (Dout latch) 345 includes an input terminal coupled to the output terminal of the read column redundancy multiplexer 410 so that the data output latch 345 can latch the output data bit to complete the read operation. During the read operation for a subsequent column where the match_next signal is asserted, the subsequent column selects the bit decision (SAMP prev) from SAMP330.

[0023]

[0030] During the scan operation mode, the master slave flip-flop 315 provides a shift-in signal that is routed through the write column redundancy multiplexer 320 and the write driver 325. The write driver 325 has a first output terminal for the write data signal wd (or the shift-in signal during the scan mode) and a second output terminal for the complementary write data signal wd_n (or the complementary shift-in signal during the scan mode). The scan multiplexer 405 includes a second pair of input terminals coupled to the first and second output terminals of the write driver 325. When the scan signal is asserted, the scan multiplexer 405 selects its second pair of input terminals to select a pair of output signals from the write driver 325. Then, the sense amplifier SAMP 330 makes a bit decision based on the shift-in signal. When the match_next signal is false, the shift-in signal bit decision from the SAMP 330 is routed through the read column redundancy multiplexer 410 and latched in the Dout latch 345. Conversely, when the match_next signal is true, the read column redundancy multiplexer 410 selects the shift-in signal bit decision (SAMP next) from the sense amplifier in the preceding column. Advantageously, when the match_next signal is false, the level-shifted shift-in signal is routed through the write column redundancy multiplexer 320 to the write driver 325 (and ultimately to the Dout latch 345), so the operation of the write column redundancy multiplexer 320 can also be tested in the scan mode. When the match_next signal is true, the shift-in signal is routed through the write column redundancy multiplexer 320 to the write driver in the preceding column.

[0024]

[0031] An alternative column implementation form that enables scanning of read and write column redundancy multiplexers is shown in FIG. 5 for column 500. Referring again to memory 100, each of the columns in the range from the Nth column to the 0th column can be implemented as shown for column 500. The read and write operations occur in the same manner as described for column 400. For example, an input data bit din from a core power domain powered by a core power is level-shifted by a level shifter (LS) 310 to a din signal in a memory power domain powered by a memory power during a write operation to column 500. During a scan operation mode, a shift-in signal can be provided by a master-slave flip-flop 315 for a scan chain. During a write operation, a write column redundancy multiplexer (write red mux) 320 multiplexes the level-shifted din signal depending on whether a match_next signal is true or false. If the match_next signal for column 500 is false, the write column redundancy multiplexer 320 passes the level-shifted din signal to a write driver 325. However, if the match_next signal is asserted for column 500, the write column redundancy multiplexer 320 passes the level-shifted din signal to the preceding column as a din_next signal. If a subsequent column has already asserted its match_next signal, column 500 can receive the din_next signal of this subsequent column as a din_prev signal at the write driver 325. Based on an input signal of the write driver during a write operation (either the level-shifted din signal without redundancy or the din_prev signal if the preceding column has asserted its match_next signal), the write driver 325 drives a write data signal (wd) and a complementary write data signal (wd_n) accordingly.

[0025]

[0032] During the write operation to column 500, the active-high write multiplexer signal wm is asserted, switching the write multiplexer transistor M1 on to couple the wd signal to the bit line bl, and switching the write multiplexer transistor M2 on to couple the wd_n signal to the complementary bit line blb. Then, the bit cell 305 can be written accordingly to complete the write operation.

[0026]

[0033] The read operation to column 500 also occurs in the same manner as described for column 400. During the read operation when the match_next signal for column 500 is false, the active-low read multiplexer signal rm is discharged, switching the read multiplexer transistors P1 and P2 on to couple the true bit line and the complementary bit line to the sense amplifier 330. Then, SAMP330 can make a bit decision. The read column redundancy multiplexer (read red mux) 410 selects the bit decision from SAMP330 when the match_next signal for column 500 is false. When the match_next signal is true for column 500, the read column redundancy multiplexer 410 selects the bit decision (SAMP next) from the previous column. Then, the data output latch (Dout latch) 345 can latch the output data bit to complete the read operation. During the read operation for subsequent columns where the match_next signal is asserted, the subsequent columns select the bit decision (SAMP prev) from SAMP330.

[0027]

[0034] In the scan operation mode, a memory controller (not shown) switches on read multiplexer transistors M1 and M2 simultaneously with write multiplexer transistors P1 and P2. The master slave flip flop 315 provides a shift-in signal. When the match_next signal in column 500 is false, the shift-in signal passes through the write column redundancy multiplexer 320 and is driven in true and complementary forms as wd and wd_n signals, respectively. The wd signal during the scan operation mode is coupled to the bit line bl via the write multiplexer transistor M1 and also drives the sense amplifier 330 via the read multiplexer transistor P1. Similarly, the wd_n signal is coupled via the write multiplexer transistor M2 and the read multiplexer transistor P2 to drive the sense amplifier 330 during the scan operation mode. When the match_next signal is true during the scan operation mode, the write column redundancy multiplexer 320 passes the shift-in signal to the write driver in the preceding column. As described for column 500, in this preceding column, both the write multiplexer transistor and the read multiplexer transistor are on.

[0028]

[0035] In the scan operation mode of column 500, the sense amplifier 330 restores the shift-in signal from the wd and wd_n signals. When the match_next signal of column 500 is false, the read column redundancy multiplexer 410 selects the restored shift-in signal so that it can be latched into the Dout latch 345. The direct electrical connection 505 extends from the output terminal of the read column redundancy multiplexer 410 to the input terminal of the Dout latch 345. As used herein, the term "direct electrical connection" refers to an electrical path or lead that does not include any switching elements such as transistors within the multiplexer. When the match_next signal is false, the shift-in signal passes through the write column redundancy multiplexer 320, the read column redundancy multiplexer 410, and the direct electrical path 505 and is latched into the Dout latch 345. Thus, the scan operation mode can test the operation of both the write column redundancy multiplexer 320 and the read column redundancy multiplexer 410 during the scan operation mode when the match_next signal is false. When the match_next signal is true during the scan operation mode, the operation of the write column redundancy multiplexer 320 in column 500 and the read column redundancy multiplexer 410 in the preceding column is similarly tested. Here, the scan mode of the redundancy logic circuit and the redundancy decoder will be described.

[0029] Redundancy Logic and Decoding

[0036] Redundancy decoders typically respond to a redundancy enable signal. During a scan operation mode using such a conventional redundancy decoder, assertion of the redundancy enable signal can occur well before assertion of the trigger edge of the scan clock signal for the DFT scan chain. Referring again to memory 100, the decoded redundancy address signal is thus presented to the redundancy logic circuit relatively early before the scan clock signal edge is asserted. Next, the match_next signals from the various redundancy logic circuits have sufficient time to settle. This is a problem because there may be resistive path faults that would otherwise go undetected. For example, a resistive path fault may exist in one of the NAND gate 205, inverters 210 and 220, or NOR gate 215 within the redundancy logic circuit 200. Such a resistive path fault may cause the redundancy logic circuit 200 to take too long to assert its match_next signal, which can lead to a read error or a write error. However, such a resistive path fault may not be detectable if the redundancy decoder is triggered solely by the redundancy enable signal.

[0030]

[0037] The redundancy decoder 600 shown in FIG. 6 advantageously enables the redundancy logic circuit as described with respect to FIGS. 1 and 2 to be tested by a scan operation mode that includes detection of resistive path faults. When enabled during the scan operation mode, the redundancy decoder 600 decodes the fuse word fuse<0:5> to generate three decoded redundancy address signals fa<0:3>, fb<0:3>, and fc<0:3>. The bit width of the fuse word, as well as the number and bit width of the decoded redundancy address signals, can be changed in alternative implementations. A gating logic gate such as NAND gate 605 controls the enabling of the redundancy decoder 600. The NAND gate 605 gates the active-low redundancy enable signal fc_en using an active-low gating signal (shift_n) signal that is asserted at a known time prior to the assertion of the trigger edge of the scan clock signal for the DFT scan chain. In the following description, it is assumed that the trigger edge of the scan clock signal is a rising edge without loss of generality. If the shift_n signal discharges just prior to the assertion of the scan clock signal and the redundancy enable signal fc_en has already discharged, the output signal from the NAND gate 605 is asserted. The asserted NAND gate output can then be level-shifted from the core (CX) power domain to the memory (MX) power domain by the level shifter 610 to form a gated enable signal received at the enable input terminal of the fuse decoder 615. The fuse decoder 615 is configured to decode the fuse word fuse<0:5> into the decoded redundancy address signals fa<0:3>, fb<0:3>, and fc<0:3> when enabled by the assertion of the gated enable signal.

[0031]

[0038] Referring again to memory 100, when scan chain flip-flop 105 is clocked by a scan clock signal, it registers the match_next signal from the 0th redundancy logic circuit. Flip-flop 105 shifts out the sampled match_next signal as a redundancy scan out signal (red_scan_out). Then, a timer (not shown) can determine the delay between the discharge of the gating signal (shift_n) and the assertion of the redundancy scan out signal. If this delay is greater than a threshold delay, a resistive path fault within the redundancy logic circuit is detected. For example, the scan can be started by testing the 0th redundancy logic circuit. If the 0th redundancy logic circuit asserts its match_next signal and as a result does not reach the threshold delay, the scan can continue to test the first redundancy logic circuit, and so on until the Nth redundancy logic circuit is finally tested.

[0032]

[0039] Timing diagrams of the redundancy decoder signals fc_en, shift_n, fuse word, scan clock signal, and redundancy scan out signal are shown in FIG. 7. Prior to time t0, the fuse word fuse<5:0> is received by the redundancy decoder, and the redundancy enable signal fc_en is asserted by being discharged in an active-low implementation. The fuse word is encoded such that the addressed redundancy logic asserts its match_next signal. To test whether this assertion of the match_next signal undergoes a resistive path delay, the active-low gating signal shift_n is not asserted by being discharged until time t0. The rising edge of the scan clock is not asserted until time t1, approximately 20 ns later. Generally, the delay between the shift_n edge and the scan clock edge may be greater than or less than 20 ns depending on the distinction between the normal processing delay and the resistive path delay. If the delay between the shift_n falling edge and the rising edge of the redundancy scan out signal (Red_scan_out) is excessive, the resistive path delay is considered to be detected in the target redundancy logic. Then, the redundancy enable signal is de-asserted by being charged to the power supply voltage at time t2. This time is also controlled to be prior to a known time (e.g., 20 ns) of the next rising edge of the scan clock signal at time t3, so as to determine whether the redundancy scan out signal is taking too long to discharge.

[0033]

[0040] Here, an exemplary method for scanning a redundancy multiplexer within a column will be described with reference to the flowchart of FIG. 8. The operations in this flowchart respond to the trigger edge of the scan clock signal during a scan operation mode in which the column redundancy signal of the column is false. The method includes an operation 800 of routing a shift-in signal to a write driver via a write column redundancy multiplexer. Routing the shift-in signal via the write column redundancy multiplexer 320 within column 400 is an example of operation 800. The method also includes an operation 805 of processing the shift-in signal via the write driver to form a pair of write driver output signals. Processing the shift-in signal at the write driver 325 within column 400 is an example of operation 805. The method further includes an operation 810 of routing a pair of write driver output signals to a sense amplifier via a scan multiplexer. Routing via the scan multiplexer 405 in column 400 is an example of operation 810. Additionally, the method includes an operation 815 of sensing a pair of write driver output signals at the sense amplifier to form a sensed version of the shift-in signal. Sensing at the sense amplifier 330 within column 400 is an example of operation 815. Finally, the method includes an operation 820 of routing the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer. Routing via the read column redundancy multiplexer 410 in column 400 is an example of operation 820.

[0034]

[0041] Here, the present disclosure is summarized in the following exemplary clauses. Clause 1. A memory, comprising a plurality of columns, each column having, bit lines, complementary bit lines, a first read multiplexer transistor coupled to the bit line and having a read terminal, a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal, A write driver having a write data output terminal and a complementary write data output terminal, A scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal, A sense amplifier coupled to the output from the scan multiplexer, a memory.

[0035] Clause 2. The memory according to clause 1, wherein the scan multiplexer is configured to select the first pair of input terminals during the scan mode and the second pair of input terminals during the read operation.

[0036] Clause 3. Each column further includes a read column redundancy multiplexer having a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to the output terminal of the sense amplifier in an adjacent column, the memory according to clause 1 or 2.

[0037] Clause 4. The memory according to clause 3, wherein each column further includes a data output latch having an input terminal coupled to the output terminal of the read column redundancy multiplexer.

[0038] Clause 5. The memory according to clause 3 or 4, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to the column redundancy signal of the column being false and its second input terminal in response to the column redundancy signal being true.

[0039] Clause 6. The memory according to any one of clauses 1 to 5, wherein each column further includes a write column redundancy multiplexer having a first output terminal coupled to the input terminal of the write driver and a second output terminal coupled to the write driver in an adjacent column.

[0040] Clause 7. The memory according to clause 6, wherein each column further includes a scan flip-flop, and the write column redundancy multiplexer includes an input terminal coupled to the output of the scan flip-flop.

[0041] Clause 8. The memory according to Clause 7, wherein the scan flip-flop includes a master latch and a slave latch.

[0042] Clause 9. The memory according to any one of Clauses 1 to 8, wherein the first read multiplexer transistor and the second read multiplexer transistor each include a p-type metal oxide semiconductor (PMOS) transistor.

[0043] Clause 10. The memory according to Clause 5, further comprising a plurality of redundancy logic circuits corresponding to a plurality of columns, wherein each redundancy logic circuit is configured to process a plurality of decoded redundancy address bits to generate a column redundancy signal for a corresponding column.

[0044] Clause 11. The memory according to Clause 10, wherein each redundancy logic circuit includes a first logic gate configured to process a column redundancy signal from a preceding one of the redundancy logic circuits.

[0045] Clause 12. The memory according to Clause 11, wherein each first logic gate is a NOR gate.

[0046] Clause 13. The memory according to Clause 11, wherein each redundancy logic circuit further includes a second logic gate configured to process a plurality of decoded redundancy address bits.

[0047] Clause 14. The memory according to Clause 13, wherein each second logic gate includes a NAND gate.

[0048] Clause 15. A first write multiplexer transistor coupled between the bit line and the write data output terminal, A memory according to any one of clauses 1 to 14, further comprising a second write multiplexer transistor coupled between a complementary bit line and a complementary write data output terminal.

[0049] Clause 16. A redundancy decoder, comprising a gating logic gate configured to process a column redundancy enable signal using a gating signal, and further comprising a redundancy decoder configured to decode a fuse word in response to an assertion of an output signal from the gating logic gate, the memory according to any one of clauses 10 to 13.

[0050] Clause 17. The memory according to clause 16, wherein the gating logic gate includes a NAND gate.

[0051] Clause 18. A method for testing columns in a memory, in response to a column redundancy signal of a column being false during a scan operation mode, routing a shift-in signal to a write driver via a write column redundancy multiplexer in response to a trigger edge of a scan clock signal; processing the shift-in signal via the write driver to form a pair of write driver output signals; routing the pair of write driver output signals to a sense amplifier via a scan multiplexer; sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; routing the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer.

[0052] Clause 19. In response to a column redundancy signal of a column being true during a scan operation mode, routing a shift-in signal through a write column redundancy multiplexer to a first adjacent column; and routing a sensed version of the shift-in signal from a second adjacent column through a read column redundancy multiplexer to a data output latch, the method of claim 18 further comprising.

[0053] Claim 20. asserting a gating signal at a gating delay prior to a trigger edge of a scan clock signal; decoding a fuse word in response to the assertion of the gating signal to form a plurality of decoded redundancy bits; and processing the plurality of decoded redundancy bits to form a column redundancy signal, the method of claim 18 or 19 further comprising.

[0054] Claim 21. A memory, comprising a plurality of columns, each column comprising a bit line; a complementary bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; a sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complementary read terminal; a read column redundancy multiplexer having a first input terminal coupled to an output terminal of the sense amplifier and a second input terminal coupled to a sense amplifier in an adjacent column; A memory including a data output latch having an input terminal coupled to an output terminal of a read column redundancy multiplexer via a direct electrical connection.

[0055] Clause 22. The memory according to clause 21, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to a column redundancy signal of a column being false and to select its second input terminal in response to the column redundancy signal being true.

[0056] Clause 23. Each column further includes a write driver, and a write column redundancy multiplexer having a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column, the memory according to clause 21 or 22.

[0057] Clause 24. Each column further includes a scan flip-flop, and the write column redundancy multiplexer includes an input terminal coupled to an output terminal of the scan flip-flop, the memory according to clause 23.

[0058] Clause 25. A memory comprising a redundancy decoder including a gating logic gate and a fuse decoder having an enable input terminal coupled to an output terminal of the gating logic gate, the redundancy decoder further including a plurality of output terminals for a plurality of decoded address signals, and a plurality of column redundancy logic circuits arranged in series, each column redundancy logic circuit having a set of input terminals for receiving each set of redundancy address bits and having an output terminal for a column redundancy signal, and a scan flip-flop configured to latch a column redundancy signal from a last column redundancy logic circuit among the column redundancy logic circuits.

[0059] Clause 26. The memory according to clause 25, wherein the gating logic gate includes a NAND gate.

[0060] Clause 27. The memory according to clause 25 or 26, wherein each redundancy logic circuit is configured to assert the column redundancy signal of the redundancy logic circuit in response to the assertion of the column redundancy signal from the preceding one of the redundancy logic circuits.

[0061] Clause 28. The memory according to clause 26, wherein each redundancy logic circuit further includes a first logic gate configured to process the column redundancy signal from the preceding one of the redundancy logic circuits.

[0062] Clause 29. The memory according to clause 28, wherein each redundancy logic circuit further includes a second logic gate configured to process each set of decoded redundancy address bits.

[0063] Clause 30. The memory according to clause 29, wherein each first logic gate includes a NOR gate, and each second logic gate includes a NAND gate.

[0064]

[0042] As will now be understood by those skilled in the art, and depending on the immediate specific application, many modifications, substitutions, and variations can be made in and to the materials, apparatus, configurations, and methods of use of the devices of the present disclosure without departing from the spirit and scope of the present disclosure. In light of this, the specific embodiments illustrated and described herein are only for some examples thereof, and the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be exactly the same as the scope of the following appended claims and their functional equivalents. The invention described in the claims of the present application at the time of filing is appended below. [C1] A memory, comprising: a plurality of columns, each column comprising: a bit line; a complementary bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; a write driver having a write data output terminal and a complementary write data output terminal; a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal; a sense amplifier coupled to an output from the scan multiplexer. [C2] The memory according to C1, wherein the scan multiplexer is configured to select the first pair of input terminals during a scan mode and the second pair of input terminals during a read operation. [C3] The memory according to C1, wherein each column further comprises a read column redundancy multiplexer having a first input terminal coupled to an output terminal of the sense amplifier and a second input terminal coupled to an output terminal of a sense amplifier in an adjacent column. [C4] The memory according to C3, wherein each column further comprises a data output latch having an input terminal coupled to an output terminal of the read column redundancy multiplexer. [C5] The memory according to C4, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to the column redundancy signal of the column being false and to select its second input terminal in response to the column redundancy signal of the column being true. [C6] The memory according to C1, wherein each column further comprises a write column redundancy multiplexer having a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column. [C7] The memory according to C6, wherein each column further comprises a scan flip-flop, and the write column redundancy multiplexer includes an input terminal coupled to an output terminal of the scan flip-flop. ​ ​ ​ [C8] The memory according to C7, wherein the scan flip-flop includes a master latch and a slave latch. [C9] The memory according to C1, wherein each of the first read multiplexer transistor and the second read multiplexer transistor includes a p-type metal oxide semiconductor (PMOS) transistor. [C10] The memory according to C5, further comprising a plurality of redundancy logic circuits corresponding to the plurality of columns, each redundancy logic circuit being configured to process a plurality of decoded redundancy address bits to generate the column redundancy signal for the corresponding column. [C11] The memory according to C10, wherein each redundancy logic circuit includes a first logic gate configured to process the column redundancy signal from a preceding one of the redundancy logic circuits. [C12] The memory according to C11, wherein each first logic gate is a NOR gate. [C13] The memory according to C11, wherein each redundancy logic circuit further includes a second logic gate configured to process the plurality of decoded redundancy address bits. [C14] The memory according to C13, wherein each second logic gate includes a NAND gate. [C15] A first write multiplexer transistor coupled between the bit line and the write data output terminal, and [C16] A second write multiplexer transistor coupled between the complementary bit line and the complementary write data output terminal, the memory according to C1. [C17] The memory according to C10, further comprising a redundancy decoder including a gating logic gate configured to process a column redundancy enable signal using a gating signal, the redundancy decoder being configured to decode a fuse word in response to an assertion of an output signal from the gating logic gate. [C18] The memory according to C16, wherein the gating logic gate includes a NAND gate. [C19] A method of testing columns in a memory, comprising: [C20] In response to the column redundancy signal of the column being false during a scan operation mode, [C21] Routing a shift-in signal to a write driver via a write column redundancy multiplexer in response to a trigger edge of a scan clock signal. Processing the shift-in signal through the write driver to form a pair of write driver output signals; Routing the pair of write driver output signals to a sense amplifier through a scan multiplexer; Sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; Routing the sensed version of the shift-in signal to a data output latch through a read column redundancy multiplexer. A method comprising the steps above. [C19] Responsive to the column redundancy signal of the column being true during the scan operation mode, Routing the shift-in signal to a first adjacent column through the write column redundancy multiplexer; Routing a sensed version of the shift-in signal from a second adjacent column to the data output latch through the read column redundancy multiplexer. The method according to C18, further comprising the steps above. [C20] Asserting a gating signal at a gating delay prior to the trigger edge of the scan clock signal; Decoding a fuse word to form a plurality of decoded redundancy bits responsive to the assertion of the gating signal; Processing the plurality of decoded redundancy bits to form the column redundancy signal. The method according to C18, further comprising the steps above. [C21] A memory, Comprising a plurality of columns, each column comprising: Bit lines; Complementary bit lines; A first read multiplexer transistor coupled to the bit line and having a read terminal; A second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; A sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complementary read terminal; A read column redundancy multiplexer having a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to a sense amplifier in an adjacent column; A data output latch having an input terminal coupled to the output terminal of the read column redundancy multiplexer through a direct electrical connection. A memory including the components above. [C22] The memory according to C21, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to the column redundancy signal of the column being false and to select its second input terminal in response to the column redundancy signal being true. [C23] Each column further includes a write driver and a write column redundancy multiplexer having a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column, the memory according to C21. [C24] Each column further includes a scan flip-flop, and the write column redundancy multiplexer includes an input terminal coupled to an output terminal of the scan flip-flop, the memory according to C23. [C25] A memory comprising a redundancy decoder including a gating logic gate and a fuse decoder having an enable input terminal coupled to an output terminal of the gating logic gate, the redundancy decoder further including a plurality of output terminals for a plurality of decoded address signals, a plurality of column redundancy logic circuits arranged in series, each column redundancy logic circuit having a set of input terminals for receiving each set of redundancy address bits and having an output terminal for a column redundancy signal, a scan flip-flop configured to latch the column redundancy signal from the last column redundancy logic circuit among the column redundancy logic circuits, the memory. [C26] The memory according to C25, wherein the gating logic gate includes a NAND gate. [C27] The memory according to C25, wherein each redundancy logic circuit is configured to assert the column redundancy signal of the redundancy logic circuit in response to an assertion of the column redundancy signal from a preceding one of the redundancy logic circuits. [C28] The memory according to C26, wherein each redundancy logic circuit further includes a first logic gate configured to process the column redundancy signal from a preceding one of the redundancy logic circuits. [C29] The memory according to C28, wherein each redundancy logic circuit further includes a second logic gate configured to process each set of the decoded redundancy address bits. [C30] The memory according to C29, wherein each first logic gate includes a NOR gate and each second logic gate includes a NAND gate.

Claims

1. A memory, comprising: a plurality of columns, each column including: a bit line; a complementary bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; a write driver having a write data output terminal and a complementary write data output terminal; a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal; a sense amplifier coupled to an output of the scan multiplexer; wherein the memory is further configured to route a shift-in signal to the write driver via a write column redundancy multiplexer in response to a trigger edge of a scan clock signal in response to a column redundancy signal of a column among the plurality of columns being false during a scan operation mode; process the shift-in signal via the write driver to form a pair of write driver output signals; route the pair of write driver output signals to the sense amplifier via the scan multiplexer; sense the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; route the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer.

2. The memory according to claim 1, wherein the scan multiplexer is configured to select the first pair of input terminals during the scan mode and the second pair of input terminals during a read operation.

3. Each column further includes: the read column redundancy multiplexer having a first input terminal coupled to an output terminal of the sense amplifier and a second input terminal coupled to an output terminal of a sense amplifier in an adjacent column; the data output latch having an input terminal coupled to an output terminal of the read column redundancy multiplexer. ​ The read column redundancy multiplexer is configured to select its first input terminal in response to the column redundancy signal of the column being false, and to select its second input terminal in response to the column redundancy signal being true. The memory according to claim 1.

4. Each column Further includes the write column redundancy multiplexer having a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column. The memory according to claim 1.

5. Each column Further includes a scan flip-flop, and the write column redundancy multiplexer includes an input terminal coupled to an output terminal of the scan flip-flop. The scan flip-flop includes a master latch and a slave latch. The memory according to claim 4.

6. Each of the first read multiplexer transistor and the second read multiplexer transistor includes a p-type metal oxide semiconductor (PMOS) transistor. The memory according to claim 1.

7. Further includes a plurality of redundancy logic circuits corresponding to the plurality of columns, and each redundancy logic circuit is configured to process a plurality of decoded redundancy address bits to generate the column redundancy signal for the corresponding column. The memory according to claim 3.

8. Each redundancy logic circuit includes a first logic gate configured to process the column redundancy signal from a preceding one of the redundancy logic circuits. The memory according to claim 7.

9. Each of the first logic gates is a NOR gate. The memory according to claim 8.

10. Each redundancy logic circuit further includes a second logic gate configured to process the plurality of decoded redundancy address bits. Each of the second logic gates includes a NAND gate. The memory according to claim 8.

11. A first write multiplexer transistor coupled between the bit line and the write data output terminal. And a second write multiplexer transistor coupled between the complementary bit line and the complementary write data output terminal. The memory according to claim 1.

12. A redundancy decoder further comprising a gating logic gate configured to process a column redundancy enable signal using a gating signal, wherein the redundancy decoder is configured to decode a fuse word in response to an assertion of an output signal from the gating logic gate. The memory according to claim 10, wherein the gating logic gate comprises a NAND gate. **Claim 13** A method for testing a column in a memory according to any one of claims 1 to 12, comprising: In response to the column redundancy signal of the column being false during the scan operation mode, Routing a shift-in signal to a write driver via a write column redundancy multiplexer in response to a trigger edge of a scan clock signal; Processing the shift-in signal via the write driver to form a pair of write driver output signals; Routing the pair of write driver output signals to a sense amplifier via a scan multiplexer; Sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; Routing the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer. **Claim 14** In response to the column redundancy signal of the column being true during the scan operation mode, Routing the shift-in signal to a first adjacent column via the write column redundancy multiplexer; The method according to claim 13, further comprising routing a sensed version of a shift-in signal from a second adjacent column to the data output latch via the read column redundancy multiplexer. **Claim 15** Asserting a gating signal at a gating delay prior to the trigger edge of the scan clock signal; Decoding a fuse word to form a plurality of decoded redundancy bits in response to the assertion of the gating signal; The method according to claim 13, further comprising processing the plurality of decoded redundancy bits to form the column redundancy signal.

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