Switching circuit

Abstract

To surely detects a dead time to perform an adjustment.SOLUTION: A switching circuit includes: a first gate control circuit (25) connected to a gate of a first switching element; and a second gate control circuit (26) connected to a gate of a second switching element. A reflux side gate control circuit that controls a reflux side element of the first gate control circuit and the second gate control circuit executes detection of the length of a dead time on the basis of a main voltage (Vds22) as a voltage between a high-potential main terminal and a low-potential main terminal of the reflux side element and a gate voltage (Vgs22) of the reflux side element, and executes an adjustment of the length of the dead time after the detection on the basis of the length of the detected dead time.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to a switching circuit.

[0002] Patent Document 1 discloses a switching circuit having a first switching element and a second switching element connected in series between a high-potential wiring and a low-potential wiring. An output wiring is connected to the connection point between the first switching element and the second switching element. Also, a reflux diode is connected in parallel to each of the first switching element and the second switching element. The first switching element and the second switching element are configured to turn on alternately. Also, a dead time during which both the first switching element and the second switching element are off is provided between the period during which the first switching element is on and the period during which the second switching element is on. By providing the dead time, it is possible to prevent both the first switching element and the second switching element from turning on and short-circuiting between the high-potential wiring and the low-potential wiring.

[0003] The switching circuit of Patent Document 1 has a dead time adjustment circuit. The dead time adjustment circuit detects the on / off state of the first switching element based on the gate signal of the first switching element and detects the on / off state of the second switching element based on the gate signal of the second switching element, thereby detecting the dead time. The dead time adjustment circuit adjusts the dead time based on the detected dead time.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The dead time adjustment circuit of Patent Document 1 detects the gate signal of the first switching element and the gate signal of the second switching element. Since the reference voltages of the gate signal of the first switching element and the gate signal of the second switching element are significantly different, in this dead time adjustment circuit, it is necessary to transmit and receive signals between the circuit on the first switching element side and the circuit on the second switching element side via an insulating element. Since a delay occurs in the transmission and reception of signals via the insulating element, the dead time cannot be accurately detected and the dead time cannot be accurately adjusted. Therefore, in this specification, a technique capable of accurately detecting and adjusting the dead time is proposed.

Means for Solving the Problems

[0006] The switching circuit disclosed in this specification includes a high-potential wiring, an intermediate wiring, a low-potential wiring, a first switching element, a second switching element, a first diode, a second diode, a first gate control circuit, a second gate control circuit, and a determination circuit. The first switching element has a high-potential main terminal connected to the high-potential wiring, a low-potential main terminal connected to the intermediate wiring, and a gate. The second switching element has a high-potential main terminal connected to the intermediate wiring, a low-potential main terminal connected to the low-potential wiring, and a gate. The first diode has a cathode connected to the high-potential main terminal of the first switching element and an anode connected to the low-potential main terminal of the first switching element. The second diode has a cathode connected to the high-potential main terminal of the second switching element and an anode connected to the low-potential main terminal of the second switching element. The first gate control circuit is connected to the gate of the first switching element. The second gate control circuit is connected to the gate of the second switching element. The determination circuit determines which of the first switching element and the second switching element is the reflux-side element. The determination circuit determines that the first switching element is the reflux-side element when a reflux current flows through the first diode, and determines that the second switching element is the reflux-side element when a reflux current flows through the second diode. The first gate control circuit and the second gate control circuit control the first switching element and the second switching element so that a first period in which the first switching element is on and the second switching element is off and a second period in which the first switching element is off and the second switching element is on are alternately repeated with a dead time in between. The reflux-side gate control circuit that controls the reflux-side element among the first gate control circuit and the second gate control circuit detects the length of the dead time based on the main voltage, which is the voltage between the high-potential main terminal and the low-potential main terminal of the reflux-side element, and the gate voltage of the reflux-side element, and adjusts the length of the dead time after the detection based on the detected length of the dead time.

[0007] Note that the above dead time may be the pre-turn-on dead time before the return-side element turns on, the post-turn-off dead time after the return-side element turns off, or both of them.

[0008] In this switching circuit, the return-side gate control circuit detects the length of the dead time based on the main voltage and the gate voltage of the return-side element. The main voltage of the return-side element can be used to detect whether the driving-side element (i.e., the switching element other than the return-side element among the first switching element and the second switching element) is on or off. Also, the gate voltage of the return-side element can be used to detect whether the return-side element is on or off. Therefore, the return-side gate control circuit can detect the length of the dead time. That is, the return-side gate control circuit can detect the length of the dead time based on the main voltage and the gate voltage of the return-side element. For this reason, the return-side gate control circuit can detect the length of the dead time without transmitting and receiving signals between the circuits of the driving-side element and the return-side element having different reference voltages. For this reason, the return-side gate control circuit does not need to transmit and receive signals for detecting the dead time via an insulating element and can accurately detect the length of the dead time. When the return-side gate control circuit detects the length of the dead time, it adjusts the length of the dead time after the detection. Since the return-side gate control circuit can accurately detect the dead time, it can accurately adjust the length of the dead time after the detection. Therefore, it is possible to prevent the dead time from becoming longer than necessary and reduce the power consumption of the switching circuit.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

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Figure 5

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Figure 22

Figure 23

Embodiment for Carrying Out the Invention

[0010] In the above switching circuit, the first gate control circuit may charge and discharge the gate of the first switching element with a constant current, and the second gate control circuit may charge and discharge the gate of the second switching element with a constant current.

[0011] According to this configuration, fluctuations in dead time due to the operating state of the switching circuit can be suppressed, and the dead time can be adjusted more accurately.

[0012] In the above switching circuit, the reflux-side gate control circuit may be configured to adjust the pre-turn-on dead time before the reflux-side element turns on. The longer the specific period from the first specific timing when the main voltage of the reflux-side element starts to fall to the second specific timing when the gate voltage of the reflux-side element starts to rise thereafter by the reflux-side gate control circuit, the shorter the pre-turn-on dead time after the detection may be.

[0013] According to this configuration, the specific period corresponds to the pre-turn-on dead time, and the pre-turn-on dead time can be accurately detected. Therefore, the pre-turn-on dead time can be accurately adjusted after detection.

[0014] In the above switching circuit, the reflux-side gate control circuit may include a specific voltage output circuit that outputs a specific voltage having a magnitude corresponding to the length of the specific period, and a specific timing adjustment circuit that adjusts the timing at which the gate voltage of the reflux-side element rises after the detection according to the magnitude of the specific voltage.

[0015] In the above switching circuit, the specific voltage output circuit may include a specific voltage output capacitor, a first Wilson-type current mirror circuit that charges the specific voltage output capacitor when the specific period is shorter than a reference value, and a second Wilson-type current mirror circuit that discharges the specific voltage output capacitor when the specific period is longer than the reference value. The specific voltage may be the voltage across both ends of the specific voltage output capacitor.

[0016] According to this configuration, a specific voltage can be output so as to linearly change with respect to the length of the specific period.

[0017] In the above switching circuit, the specific timing adjustment circuit may be configured to receive an input of a command signal that changes between an on voltage and an off voltage. The specific timing adjustment circuit may include an adjustment voltage output capacitor, a first Wilson-type current mirror circuit for the adjustment voltage that charges the adjustment voltage output capacitor from the timing when the command signal switches from the off voltage to the on voltage, and a second Wilson-type current mirror circuit for the adjustment voltage that discharges the adjustment voltage output capacitor from the timing when the command signal switches from the on voltage to the off voltage. The specific timing adjustment circuit may output a signal that raises the gate voltage of the reflux-side element when the voltage across both ends of the adjustment voltage output capacitor becomes higher than the specific voltage.

[0018] Note that the on voltage is a voltage that commands turning on the reflux-side element, and the off voltage is a voltage that commands turning off the reflux-side element. According to this configuration, the waveform of the adjustment voltage can be made into a trapezoidal waveform with a substantially constant slope angle, and the timing for outputting a signal that raises the gate voltage of the reflux-side element can be accurately controlled.

[0019] In the above switching circuit, the reflux-side gate control circuit may include a first specific delay circuit that inputs a first specific delay signal obtained by delaying a signal indicating the main voltage of the reflux-side element to the specific voltage output circuit, and a second specific delay circuit that inputs a second specific delay signal obtained by delaying a signal indicating the gate voltage of the reflux-side element to the specific voltage output circuit. The specific voltage output circuit may adjust the magnitude of the specific voltage based on the first specific delay signal and the second specific delay signal.

[0020] According to this configuration, the specific voltage output circuit is less likely to be affected by noise.

[0021] In the above switching circuit, when the gate voltage of the reflux-side element rises while the main voltage of the reflux-side element has not decreased, the reflux-side gate control circuit may stop the adjustment of the dead time length.

[0022] In the above switching circuit, the reflux-side gate control circuit may be configured to adjust the post-turn-off dead time after the reflux-side element turns off. The longer the predetermined period from the first predetermined timing at which the gate voltage of the reflux-side element falls to the second predetermined timing at which the main voltage of the reflux-side element rises thereafter, the shorter the post-turn-off dead time after the detection may be.

[0023] According to this configuration, the predetermined period corresponds to the post-turn-off dead time, and the post-turn-off dead time can be accurately detected. Therefore, the post-turn-off dead time can be accurately adjusted after the detection.

[0024] In the above switching circuit, the reflux-side gate control circuit may include a predetermined voltage output circuit that outputs a predetermined voltage having a magnitude corresponding to the length of the predetermined period, and a predetermined timing adjustment circuit that adjusts the timing at which the gate voltage of the reflux-side element falls after the detection according to the magnitude of the predetermined voltage.

[0025] In the above switching circuit, the predetermined voltage output circuit may include a predetermined voltage output capacitor, a first Wilson type current mirror circuit that charges the predetermined voltage output capacitor when the predetermined period is shorter than the level value, and a second Wilson type current mirror circuit that discharges the predetermined voltage output capacitor when the predetermined period is longer than the level value. The predetermined voltage may be the voltage across both ends of the predetermined voltage output capacitor.

[0026] According to this configuration, a predetermined voltage can be output so as to linearly change with respect to the length of the predetermined period.

[0027] In the above switching circuit, the predetermined timing adjustment circuit may be configured to receive an input of a command signal that changes between an on voltage and an off voltage. The predetermined timing adjustment circuit may include an adjustment voltage output capacitor, a first adjustment voltage Wilson type current mirror circuit that charges the adjustment voltage output capacitor from the timing when the command signal switches from the off voltage to the on voltage, and a second adjustment voltage Wilson type current mirror circuit that discharges the adjustment voltage output capacitor from the timing when the command signal switches from the on voltage to the off voltage. The predetermined timing adjustment circuit may output a signal that reduces the gate voltage of the reflux side element when the voltage across both ends of the adjustment voltage output capacitor becomes lower than the predetermined voltage.

[0028] Note that the on voltage is a voltage that commands the reflux side element to turn on, and the off voltage is a voltage that commands the reflux side element to turn off. According to this configuration, the waveform of the adjustment voltage can be made into a trapezoidal waveform with a substantially constant slope angle, and the timing for outputting a signal that reduces the gate voltage of the reflux side element can be accurately controlled.

[0029] In the above switching circuit, the reflux-side gate control circuit may include a first predetermined delay circuit that inputs a first predetermined delay signal obtained by delaying a signal indicating the main voltage of the reflux-side element to the predetermined voltage output circuit, and a second predetermined delay circuit that inputs a second predetermined delay signal obtained by delaying a signal indicating the gate voltage of the reflux-side element to the predetermined voltage output circuit. The predetermined voltage output circuit may adjust the magnitude of the predetermined voltage based on the first predetermined delay signal and the second predetermined delay signal.

[0030] According to this configuration, the predetermined voltage output circuit is less likely to be affected by noise.

[0031] In the above switching circuit, when the main voltage of the reflux-side element rises while the gate voltage of the reflux-side element has not decreased, the adjustment of the dead time length may be stopped.

[0032] In the above switching circuit, the one that is not the reflux-side gate control circuit among the first gate control circuit and the second gate control circuit may be the drive-side gate control circuit. When the first gate control circuit is the reflux-side gate control circuit, it may increase the gate current of the first switching element more than when it is the drive-side gate control circuit. When the second gate control circuit is the reflux-side gate control circuit, it may increase the gate current of the second switching element more than when it is the drive-side gate control circuit.

[0033] According to this configuration, the reflux-side element can be switched at high speed, and the dead time can be adjusted more appropriately.

[0034] In the above switching circuit, the reflux-side gate control circuit may include a main voltage detection circuit that detects the main voltage of the reflux-side element. The main voltage detection circuit may include a series circuit of two capacitors to which the main voltage is applied, and an output wiring that outputs the voltage at the connection point of the two capacitors.

Example

[0035] The inverter 10 shown in FIG. 1 is mounted on a vehicle. The vehicle is also equipped with a battery 80 and a motor 82. The motor 82 is a three-phase motor. The motor 82 drives the drive wheels of the vehicle to make the vehicle run. The inverter 10 has a high-potential wiring 12, a low-potential wiring 14, and three intermediate wirings 16a to 16c. The high-potential wiring 12 is connected to the positive electrode of the battery 80. The low-potential wiring 14 is connected to the negative electrode of the battery 80. Therefore, the output voltage (i.e., DC voltage) of the battery 80 is applied between the high-potential wiring 12 and the low-potential wiring 14. The intermediate wirings 16a to 16c are connected to the motor 82. The inverter 10 converts the DC power supplied between the high-potential wiring 12 and the low-potential wiring 14 by the battery 80 into three-phase AC power and outputs the three-phase AC power to the intermediate wirings 16a to 16c. The three-phase AC power output by the inverter 10 is supplied to the motor 82 via the intermediate wirings 16a to 16c.

[0036] The inverter 10 has three switching circuits 20. Each switching circuit 20 is connected to the high potential wiring 12 and the low potential wiring 14. Also, each switching circuit 20 is connected to the corresponding intermediate wiring 16. That is, the switching circuit 20a is connected to the intermediate wiring 16a, the switching circuit 20b is connected to the intermediate wiring 16b, and the switching circuit 20c is connected to the intermediate wiring 16c. Each switching circuit 20 has a switching element 21 and a switching element 22. The switching elements 21 and 22 are FETs (i.e., field effect transistors). However, the switching elements 21 and 22 may be IGBTs (i.e., insulated gate bipolar transistors). The drain of the switching element 21 is connected to the high potential wiring 12. The source of the switching element 21 is connected to the corresponding intermediate wiring 16. The drain of the switching element 22 is connected to the corresponding intermediate wiring 16. The source of the switching element 22 is connected to the low potential wiring 14. Each switching circuit 20 has diodes 23 and 24. The diodes 23 and 24 may be the body diodes of the switching elements 21 and 22, or may be diodes provided separately from the diodes 23 and 24. The diode 23 is connected in parallel to the switching element 21. The anode of the diode 23 is connected to the source of the switching element 21. The cathode of the diode 23 is connected to the drain of the switching element 21. The diode 24 is connected in parallel to the switching element 22. The anode of the diode 24 is connected to the source of the switching element 22. The cathode of the diode 24 is connected to the drain of the switching element 22. Each switching circuit 20 has gate control circuits 25 and 26. The gate control circuit 25 is connected to the gate G21 of the switching element 21. The gate control circuit 25 switches the switching element 21 by controlling the gate voltage Vgs21 of the switching element 21. The gate control circuit 26 is connected to the gate G22 of the switching element 22.The gate control circuit 26 controls the gate voltage Vgs22 of the switching element 22 to switch the switching element 22. The inverter 10 has an inverter controller 84. The inverter controller 84 inputs a command signal for the switching timing of the switching elements 21 and 22 to each switching circuit 20. The gate control circuits 25 and 26 of each switching circuit 20 switch the switching elements 21 and 22 based on the command signal input from the inverter controller 84. When each switching element 21, 22 of each switching circuit 20 switches, the direction and magnitude of the output currents Iout1 to Iout3 flowing through the intermediate wirings 16a to 16c change. As a result, three-phase AC power is output to the intermediate wirings 16a to 16c. Since the structures and operations of the switching circuits 20a to 20c are equal to each other, the structure and operation of the switching circuit 20a will be described below.

[0037] FIG. 2 shows the gate voltages Vgs21 and Vgs22 of the switching elements 21 and 22 of the switching circuit 20a. Note that the gate voltage Vgs21 is the potential of the gate G21 of the switching element 21 with respect to the source, and the gate voltage Vgs22 is the potential of the gate G22 of the switching element 22 with respect to the source. As shown in FIG. 2, the gate voltages Vgs21 and Vgs22 change between a high voltage and a low voltage. When the gate voltage Vgs21 is high, the switching element 21 is turned on, and when the gate voltage Vgs21 is low, the switching element 21 is turned off. Also, when the gate voltage Vgs22 is high, the switching element 22 is turned on, and when the gate voltage Vgs22 is low, the switching element 22 is turned off. As shown in FIG. 2, the gate control circuits 25 and 26 control the gate voltages Vgs21 and Vgs22 so that the period T1 in which the switching element 21 is on and the switching element 22 is off, the dead time Td1 in which the switching elements 21 and 22 are both off, the period T2 in which the switching element 22 is on and the switching element 21 is off, and the dead time Td2 in which the switching elements 21 and 22 are both off are repeated in this order. That is, the gate control circuits 25 and 26 control the switching elements 21 and 22 so that the periods T1 and T2 are alternately repeated with a dead time in between.

[0038] Next, the current path flowing in the switching circuit 20a will be described. The current path in the switching circuit 20a differs depending on the direction of the output current Iout1 (i.e., the current flowing through the intermediate wiring 16a) shown in FIG. 1.

[0039] FIG. 3 shows a current path when the direction of the output current Iout1 is the outflow direction (i.e., the direction from the switching circuit 20a to the motor 82). FIG. 3(a) shows the period T1, FIG. 3(b) shows the dead time Td1, FIG. 3(c) shows the period T2, and FIG. 3(d) shows the dead time Td2. Further, the graph A in FIG. 2 shows the drain voltages Vds21 and Vds22 of the switching elements 21 and 22 when the direction of the output current Iout1 is the outflow direction. Note that the drain voltage Vds21 is the potential of the drain of the switching element 21 with respect to the source, and the drain voltage Vds22 is the potential of the drain of the switching element 22 with respect to the source.

[0040] As shown in FIG. 3(a), during period T1, the switching element 21 is on and the switching element 22 is off, so the current I flows from the high-potential wiring 12 to the intermediate wiring 16a through the switching element 21. In this state, the potential of the intermediate wiring 16a is substantially equal to the potential of the high-potential wiring 12. Therefore, as shown in graph A of FIG. 2, during period T1, the drain voltage Vds21 becomes a low voltage, and the drain voltage Vds21 becomes a high voltage. Next, at dead time Td1 (i.e., FIG. 3(b)), the switching element 21 turns off. Then, the current stops flowing through the switching element 21. Then, due to the induced voltage generated by the inductance L of the motor 82, the potential of the intermediate wiring 16a decreases, and the diode 24 turns on. For this reason, the current I (i.e., the reflux current) flows from the low-potential wiring 14 to the intermediate wiring 16a through the diode 24. In this state, the potential of the intermediate wiring 16a is substantially equal to the potential of the low-potential wiring 14. Therefore, as shown in graph A of FIG. 2, at dead time Td1, the drain voltage Vds21 becomes a high voltage, and the drain voltage Vds22 becomes a low voltage. Next, during period T2 (i.e., FIG. 3(c)), the switching element 22 turns on. Then, the current I flows from the low-potential wiring 14 to the intermediate wiring 16a through the parallel circuit of the diode 24 and the switching element 22. That is, when the switching element 22 turns on, the path through which the current I flows branches into the diode 24 and the switching element 22. In other words, even when the switching element 22 turns on, the state in which the current I flows from the low-potential wiring 14 to the intermediate wiring 16a does not change, and the potential of the intermediate wiring 16a hardly changes. Therefore, as shown in graph A of FIG. 2, during period T2, the drain voltage Vds21 becomes a high voltage, and the drain voltage Vds22 becomes a low voltage. Next, at dead time Td2 (i.e., FIG. 3(d)), the switching element 22 turns off. Then, the current stops flowing through the switching element 22. In this state, the current I flows from the low-potential wiring 14 to the intermediate wiring 16a through the diode 24. In other words, even when the switching element 22 turns off, the state in which the current I flows from the low-potential wiring 14 to the intermediate wiring 16a does not change, and the potential of the intermediate wiring 16a hardly changes.Therefore, as shown in graph A of FIG. 2, during dead time Td2, the drain voltage Vds21 becomes a high voltage and the drain voltage Vds22 becomes a low voltage. Next, switching element 21 turns on and period T1 (i.e., FIG. 3(a)) is reached again. Thus, when the direction of output current Iout1 is the outflow direction, the current path changes as shown in FIGS. 3(a) to (d), and the drain voltages Vds21 and Vds22 change as shown in graph A of FIG. 2.

[0041] FIG. 4 shows a change pattern of the current path when the direction of output current Iout1 is the inflow direction (i.e., the direction from motor 82 to switching circuit 20a). FIG. 4(a) shows period T1, FIG. 4(b) shows dead time Td1, FIG. 4(c) shows period T2, and FIG. 4(d) shows dead time Td2. Also, graph B of FIG. 2 shows the drain voltages Vds21 and Vds22 when the direction of output current Iout1 is the inflow direction.

[0042] As shown in Fig. 4(c), during period T2, the switching element 22 is on and the switching element 21 is off, so the current I flows from the intermediate wiring 16a to the low-potential wiring 14 through the switching element 22. In this state, the potential of the intermediate wiring 16a is substantially equal to the potential of the low-potential wiring 14. Therefore, as shown in graph B of Fig. 2, during period T2, the drain voltage Vds21 becomes a high voltage and the drain voltage Vds22 becomes a low voltage. Next, at dead time Td2 (i.e., Fig. 4(d)), the switching element 22 turns off. Then, the current stops flowing through the switching element 22. Then, due to the induced voltage generated by the inductance L of the motor 82, the potential of the intermediate wiring 16a rises and the diode 23 turns on. For this reason, the current I (i.e., the reflux current) flows from the intermediate wiring 16a to the high-potential wiring 12 through the diode 23. In this state, the potential of the intermediate wiring 16a is substantially equal to the potential of the high-potential wiring 12. Therefore, as shown in graph B of Fig. 2, at dead time Td2, the drain voltage Vds21 becomes a low voltage and the drain voltage Vds22 becomes a high voltage. Next, during period T1 (i.e., Fig. 4(a)), the switching element 21 turns on. Then, the current I starts to flow from the intermediate wiring 16a to the high-potential wiring 12 through the parallel circuit of the diode 23 and the switching element 21. That is, when the switching element 21 turns on, the path through which the current I flows branches into the diode 23 and the switching element 21. In other words, even when the switching element 21 turns on, the state in which the current I flows from the intermediate wiring 16a to the high-potential wiring 12 does not change, and the potential of the intermediate wiring 16a hardly changes. Therefore, as shown in graph B of Fig. 2, during period T1, the drain voltage Vds21 becomes a low voltage and the drain voltage Vds22 becomes a high voltage. Next, at dead time Td1 (i.e., Fig. 4(b)), the switching element 21 turns off. Then, the current stops flowing through the switching element 21. In this state, the current I flows from the intermediate wiring 16a to the high-potential wiring 12 through the diode 23. In other words, even when the switching element 21 turns off, the state in which the current I flows from the intermediate wiring 16a to the high-potential wiring 12 does not change, and the potential of the intermediate wiring 16a hardly changes.Therefore, as shown in graph B of FIG. 2, during dead time Td1, the drain voltage Vds21 becomes a low voltage and the drain voltage Vds22 becomes a high voltage. Next, switching element 22 turns on and period T2 (i.e., FIG. 4(c)) occurs again. Thus, when the direction of output current Iout1 is the inflow direction, the current path changes as shown in FIGS. 4(a) to (d), and the drain voltages Vds21 and Vds22 change as shown in graph B of FIG. 2.

[0043] As described above, during dead times Td1 and Td2, a reverse current flows through the diode. When the direction of output current Iout1 is the outflow direction (i.e., the case of FIG. 3), when switching element 22 turns on, the reverse current branches and flows through diode 24 and switching element 22. Also, when the direction of output current Iout1 is the inflow direction (i.e., the case of FIG. 4), when switching element 21 turns on, the reverse current branches and flows through diode 23 and switching element 21. Thus, when turning on the switching element connected in parallel to the diode through which the reverse current is flowing, the reverse current branches and flows through the diode and the switching element, and the loss caused by the reverse current is reduced compared to when the reverse current only flows through the diode (i.e., during dead time). Therefore, by shortening the dead time, the loss generated in switching circuit 20a can be reduced.

[0044] Hereinafter, the entire period consisting of period T1, dead time Td1, period T2, and dead time Td2 is referred to as a control unit period. Also, hereinafter, the switching element connected in parallel to the diode through which the reflux current flows during the control unit period is referred to as a reflux-side element. Further, hereinafter, the switching element that is not the reflux-side element among the switching element 21 and the switching element 22 is referred to as a drive-side element. When the direction of the output current Iout1 is the outflow direction (i.e., the case of FIG. 3), the switching element 21 is the drive-side element, and the switching element 22 is the reflux-side element. Also, when the direction of the output current Iout1 is the inflow direction (i.e., the case of FIG. 4), the switching element 22 is the drive-side element, and the switching element 21 is the reflux-side element. Further, hereinafter, the gate control circuit that controls the reflux-side element is referred to as a reflux-side gate control circuit, and the gate control circuit that controls the drive-side element is referred to as a drive-side gate control circuit.

[0045] FIG. 5 shows the details of the switching circuit 20a. In FIG. 5, the ground potential in the gate control circuit 25 is the source potential of the switching element 21, and the ground potential in the gate control circuit 26 is the source potential of the switching element 22.

[0046] As shown in FIG. 5, the switching circuit 20a includes a current sensor 30 and a determination circuit 32. The current sensor 30 detects the output current Iout1 flowing through the intermediate wiring 16a. The determination circuit 32 outputs a signal Sk indicating which of the switching elements 21 and 22 is the reflux-side element and which is the drive-side element based on the direction of the output current Iout1 detected by the current sensor 30. The determination circuit 32 determines that the switching element 22 is the reflux-side element when the direction of the output current Iout1 is the outflow direction, and determines that the switching element 21 is the reflux-side element when the direction of the output current Iout1 is the inflow direction. The signal Sk output by the determination circuit 32 is input to the gate control circuits 25 and 26 via the insulating element 86.

[0047] As shown in FIG. 5, the switching circuit 20a has main voltage detection circuits 41 and 42. The main voltage detection circuit 41 detects the drain voltage Vds21 of the switching element 21. The main voltage detection circuit 41 inputs a signal Sds21 indicating the drain voltage Vds21 to the gate control circuit 25. The main voltage detection circuit 42 detects the drain voltage Vds22 of the switching element 22. The main voltage detection circuit 42 inputs a signal Sds22 indicating the drain voltage Vds22 to the gate control circuit 26.

[0048] The main voltage detection circuits 41 and 42 may be any circuit as long as they can detect the drain voltage of the switching element. FIGS. 6 and 7 show an example of the main voltage detection circuits 41 and 42.

[0049] The main voltage detection circuit in FIG. 6 has a diode 43, a resistor 44, and a Zener diode 45. The cathode of the diode 43 is connected to the drain of the switching element 21 (or 22). The anode of the diode 43 is connected to one end of the resistor 44. The other end of the resistor 44 is connected to the cathode of the Zener diode 45. The anode of the Zener diode 45 is connected to the ground. A signal output wiring 46 is connected to the connection portion of the resistor 44 and the Zener diode 45. A signal Sds, which is proportional to the drain voltage Vds and is much smaller than the drain voltage Vds, is output to the signal output wiring 46.

[0050] The main voltage detection circuit in FIG. 7 has capacitors 47 and 48. One end of the capacitor 47 is connected to the drain of the switching element 21 (or 22). The other end of the capacitor 47 is connected to one end of the capacitor 48. The other end of the capacitor 48 is connected to the ground. A signal output wiring 46 is connected to the connection portion of the capacitor 47 and the capacitor 48. A signal Sds, which is proportional to the drain voltage Vds and is much smaller than the drain voltage Vds, is output to the signal output wiring 46.

[0051] In any of the main voltage detection circuits of FIGS. 6 and 7, a signal Sds proportional to the drain voltage Vds can be preferably output. However, in the main voltage detection circuit of FIG. 6, due to the influence of the series circuit composed of the parasitic capacitance of the Zener diode 45 and the resistor 44, the change in the signal Sds may be slightly delayed with respect to the change in the drain voltage Vds. On the other hand, in the main voltage detection circuit of FIG. 7, the signal Sds is less likely to be delayed with respect to the drain voltage Vds than in the main voltage detection circuit of FIG. 6.

[0052] As shown in FIG. 5, a command signal Ss1 for commanding the switching timing of the switching element 21 is input from the inverter controller 84 to the gate control circuit 25 via the insulating element 86. As shown in FIG. 18, the command signal Ss1 is a pulse signal that changes between a high voltage and a low voltage. The high voltage of the command signal Ss1 is a voltage for commanding to turn on the switching element 21 (i.e., the on voltage), and the low voltage of the command signal Ss1 is a voltage for commanding to turn off the switching element 21 (i.e., the off voltage). Also, a command signal Ss2 for commanding the switching timing of the switching element 22 is input from the inverter controller 84 to the gate control circuit 26 via the insulating element 86. As shown in FIG. 18, the command signal Ss2 is a pulse signal that changes between a high voltage and a low voltage. The high voltage of the command signal Ss2 is a voltage for commanding to turn on the switching element 22 (i.e., the on voltage), and the low voltage of the command signal Ss2 is a voltage for commanding to turn off the switching element 22 (i.e., the off voltage). The inverter controller 84 generates the command signals Ss1 and Ss2 so that the switching elements 21 and 22 are alternately turned on with a dead time in between.

[0053] As described above, the signals Sds21, Ss1, and Sk are input to the gate control circuit 25. The gate control circuit 25 controls the gate voltage Vgs21 based on the signals Sds21, Ss1, and Sk. Also, the signals Sds22, Ss2, and Sk are input to the gate control circuit 26. The gate control circuit 26 controls the gate voltage Vgs22 based on the signals Sds22, Ss2, and Sk.

[0054] As shown in FIG. 5, the gate control circuit 26 includes a gate drive signal output circuit 50, a gate drive circuit 52, a gate voltage determination circuit 54, a drain voltage determination circuit 56, delay circuits 58a to 58d, phase comparators 60a and 60b, comparison voltage output circuits 62a and 62b, comparison voltage holding circuits 64a and 64b, and a selector circuit 66.

[0055] A command signal Ss2 is input to the gate drive signal output circuit 50. The gate drive signal output circuit 50 outputs a gate drive signal Sa based on the command signal Ss2. As shown in FIG. 17, the gate drive signal Sa is a pulse signal that varies between a high voltage and a low voltage, similar to the command signal Ss2. When the switching element 22 is a drive-side element, the gate drive signal output circuit 50 outputs a signal having the same waveform as the command signal Ss2 as the gate drive signal Sa. When the switching element 22 is a reflux-side element, the gate drive signal output circuit 50 outputs a pulse signal obtained by changing the rising timing and the falling timing from the command signal Ss2 as the gate drive signal Sa.

[0056] A gate drive signal Sa is input to the gate drive circuit 52. The gate drive circuit 52 controls the gate voltage Vgs22 according to the gate drive signal Sa. FIG. 8 shows an example of the gate drive circuit 52. As shown in FIG. 8, the gate drive circuit 52 includes a wiring 52v, a constant current source 52a, a switching element 52b, a switching element 52c, and a constant current source 52d. A voltage Vin1 is applied to the wiring 52v. The voltage Vin1 is higher than the gate threshold of the switching element 22. The constant current source 52a and the switching element 52b are connected in series between the wiring 52v and the gate G22. The switching element 52c and the constant current source 52d are connected in series between the gate G22 and the ground. A gate drive signal Sa (more specifically, a signal obtained by inverting the gate drive signal Sa) is input to the gates of the switching element 52b and the switching element 52c. When the gate drive signal Sa is at a high potential, the switching element 52b turns on and the switching element 52c turns off. In this state, a gate current flows from the wiring 52v to the gate G22 through the constant current source 52a and the switching element 52b, and the gate G22 is charged. For example, graph A in FIG. 9 shows the gate voltage Vgs22 controlled by the gate drive circuit 52 in FIG. 8. When the gate drive signal Sa rises from a low potential to a high potential at timing tx1, the switching element 52b turns on. Then, after timing tx1, the gate G22 is charged and the gate voltage Vgs22 rises. At this time, since the gate current is controlled to a constant current by the constant current source 52a, the gate voltage Vgs22 rises with a constant slope. The gate voltage Vgs22 transitions at a constant value at the mirror voltage Vmr when it reaches the mirror voltage Vmr, and then rises to the voltage Vin1. The switching element 22 turns on at timing tx2 when the gate voltage Vgs22 rises from the mirror voltage Vmr. Also, when the gate drive signal Sa is at a low potential, the switching element 52b turns off and the switching element 52c turns on. In this state, a gate current flows from the gate G22 to the ground through the switching element 52c and the constant current source 52d, and the gate G22 is discharged.For example, when the gate drive signal Sa drops from a high potential to a low potential at the timing tx3 in FIG. 9, the switching element 52c turns on. Then, after the timing tx3, the gate G22 is discharged and the gate voltage Vgs22 decreases. At this time, since the gate current is controlled to a constant current by the constant current source 52d, the gate voltage Vgs22 decreases at a constant slope. When the gate voltage Vgs22 decreases to the mirror voltage Vmr, it remains at a constant value at the mirror voltage Vmr and then decreases to 0V. The switching element 22 turns off at the timing tx4 when the gate voltage Vgs22 decreases from the mirror voltage Vmr.

[0057] Also, the mirror voltage Vmr changes according to the current flowing through the switching element 22 (i.e., the current flowing from the drain to the source). For example, graph B in FIG. 9 shows the change in the gate voltage Vgs22 when the current flowing through the switching element 22 is small. When the current flowing through the switching element 22 is small, as shown in graph B, the mirror voltage Vmr becomes low. According to the change in the mirror voltage Vmr, the timings tx2 and tx4 at which the switching element turns on and off also change.

[0058] Note that instead of the circuit in FIG. 8, the circuit in FIG. 10 can also be used as the gate drive circuit 52. The circuit in FIG. 10 is not provided with a constant current source. Also, in the circuit of FIG. 10, a resistor 52e is provided in the wiring connected to the gate G22. When the switching element 52b turns on, a gate current flows from the wiring 52v to the gate G22 through the switching element 52b and the resistor 52e, and the gate G22 is charged. When the switching element 52c turns on, a gate current flows from the gate G22 to the ground through the resistor 52e and the switching element 52c, and the gate G22 is discharged. In this circuit, the gate current does not become a constant current and changes according to the gate voltage Vg22.

[0059] FIG. 11 shows the gate voltage Vgs22 controlled by the gate drive circuit of FIG. 10. Graph A in FIG. 11 shows the high current state, and graph B shows the low current state. Since the gate drive circuit of FIG. 10 does not have a constant current source, in FIG. 11, the gate voltage Vgs22 rises and falls in a curved shape. Therefore, in FIG. 11, the deviation of the timing tx2 at which the switching element 22 turns on between the high current state (i.e., graph A) and the low current state (i.e., graph B) becomes larger than that in FIG. 9. Also, in FIG. 11, the deviation of the timing tx4 at which the switching element 22 turns off between the high current state (i.e., graph A) and the low current state (i.e., graph B) becomes larger than that in FIG. 9. Thus, when the gate current is not controlled by a constant current, variations in the on and off timings of the switching element 22 are likely to occur due to changes in the mirror voltage Vmr. When a circuit capable of constant current control of the gate current as shown in FIG. 8 is used as the gate drive circuit 52, the switching timings of the switching elements 21 and 22 can be controlled more accurately, and the dead time can be adjusted more accurately.

[0060] Note that in figures other than FIGS. 9 and 11, the illustration of the mirror voltage is omitted.

[0061] The gate voltage determination circuit 54 compares the gate voltage Vgs22 with the reference voltage Vref1 and outputs a signal Sr1, which is a pulse signal indicating which of these is larger. That is, the signal Sr1 is a pulse signal that rises when the gate voltage Vgs22 rises and falls when the gate voltage Vgs22 falls.

[0062] The drain voltage determination circuit 56 compares the signal Sds22 (i.e., a voltage proportional to the drain voltage Vds22) with the reference voltage Vref2 and outputs a signal Sr2, which is a pulse signal indicating which of these is larger. That is, the signal Sr2 is a pulse signal that rises when the drain voltage Vds22 rises and falls when the drain voltage Vds22 falls.

[0063] The delay circuits 58a to 58d are circuits that delay an input signal and output it. The signal Sr1 is input to the delay circuits 58a and 58d, and the signal Sr2 is input to the delay circuits 58b and 58c. FIG. 12 shows an example of the delay circuits 58a to 58d. In the delay circuit of FIG. 12, the signal Sr1 (or Sr2) is applied to the series circuit of the resistor 59a and the capacitor 59b, and the capacitor 59b is charged. Therefore, the waveform of the voltage Vc across both ends of the capacitor 59b becomes a waveform in which the signal Sr1 (or Sr2) is smoothed. The voltage Vc is input to the non-inverting input terminal of the comparator 59e. Also, a reference voltage Vref3 generated by dividing the voltage Vin2 with the resistors 59c and 59d is input to the inverting input terminal of the comparator 59. The comparator 59e outputs a signal indicating which of the voltage Vc and the reference voltage Vref3 is larger. The output signal of the comparator 59e becomes a pulse signal obtained by delaying the signal Sr1 (or Sr2) by a predetermined time. Note that the circuit constants of the delay circuits 58a to 58d are different from each other, and for this reason, the delay times for which the delay circuits 58a to 58d delay the signal are different from each other.

[0064] The delay circuit 58a outputs a signal Sr1d1 obtained by delaying the signal Sr1. The delay circuit 58b outputs a signal Sr2d1 obtained by delaying the signal Sr2. The delay time for which the delay circuit 58b delays the signal Sr2 is longer than the delay time for which the delay circuit 58a delays the signal Sr1. The signals Sr1d1 and Sr2d1 are input to the phase comparator 60a. The delay circuit 58c outputs a signal Sr2d2 obtained by delaying the signal Sr2. The delay circuit 58d outputs a signal Sr1d2 obtained by delaying the signal Sr1. The delay time for which the delay circuit 58d delays the signal Sr1 is longer than the delay time for which the delay circuit 58c delays the signal Sr2. The signals Sr2d2 and Sr1d2 are input to the phase comparator 60b.

[0065] The phase comparator 60a outputs a signal Sdd indicating the falling timing of the signal Sr2d1 (i.e., the timing obtained by delaying the falling timing of the drain voltage Vds22), and a signal Sgi indicating the rising timing of the signal Sr1d1 (i.e., the timing obtained by delaying the rising timing of the gate voltage Vgs22). As is clear from graph A in FIG. 2, when the switching element 22 is a reflux-side element, the falling timing of the drain voltage Vds22 is the start timing of the dead time Td1, and the rising timing of the gate voltage Vgs22 is the end timing of the dead time Td1. Therefore, the signal Sdd and the signal Sgi are signals indicating the length of the dead time Td1.

[0066] The phase comparator 60a outputs a signal Sgd indicating the falling timing of the signal Sr1d2 (i.e., the timing obtained by delaying the falling timing of the gate voltage Vgs22), and a signal Sdi indicating the rising timing of the signal Sr2d2 (i.e., the timing obtained by delaying the rising timing of the drain voltage Vds22). As is clear from graph A in FIG. 2, when the switching element 22 is a reflux-side element, the falling timing of the gate voltage Vgs22 is the start timing of the dead time Td2, and the rising timing of the drain voltage Vds22 is the end timing of the dead time Td2. Therefore, the signal Sgd and the signal Sdi are signals indicating the length of the dead time Td2.

[0067] The comparison voltage output circuits 62a and 62b are circuits that output a voltage with a magnitude corresponding to the timing deviation between two input signals. The comparison voltage output circuit 62a outputs a comparison voltage Vth1 with a magnitude corresponding to the timing deviation between the signal Sdd and the signal Sgi. Since the timing deviation between receiving the signal Sdd and the signal Sgi is a deviation corresponding to the length of the dead time Td1, the comparison voltage output circuit 62a outputs a comparison voltage Vth1 with a magnitude corresponding to the length of the dead time Td1. The comparison voltage output circuit 62b outputs a comparison voltage Vth2 with a magnitude corresponding to the timing deviation between the signal Sgd and the signal Sdi. Since the timing deviation between receiving the signal Sgd and the signal Sdi is a deviation corresponding to the length of the dead time Td2, the comparison voltage output circuit 62b outputs a comparison voltage Vth2 with a magnitude corresponding to the length of the dead time Td2.

[0068] FIG. 13 shows an example of the comparison voltage output circuits 62a and 62b. The comparison voltage output circuit in FIG. 13 includes a current mirror circuit 63a, a current mirror circuit 63b, a switching element 63c, a switching element 63d, and a capacitor 63e. The current mirror circuits 63a and 63b are Wilson-type current mirror circuits. The current mirror circuit 63a is a constant current circuit for charging the capacitor 63e, and the current mirror circuit 63b is a constant current circuit for discharging the capacitor 63e. A signal Sgi (or Sdi) is input to the gate of the switching element 63c, and a signal Sdd (or Sgd) is input to the gate of the switching element 63d.

[0069] When the circuit in Fig. 13 is the comparison voltage output circuit 62a, if the signal Sdd is input to the comparison voltage output circuit 62a before the signal Sgi, the current mirror circuit 63b operates and the capacitor 63e is discharged. Then, when the signal Sgi is input to the comparison voltage output circuit 62a, the current mirror circuit 63a operates and the discharge of the capacitor 63e stops. Also, if the signal Sgi is input to the comparison voltage output circuit 62a before the signal Sdd, the current mirror circuit 63a operates and the capacitor 63e is charged. Then, when the signal Sdd is input to the comparison voltage output circuit 62a, the current mirror circuit 63b operates and the charging of the capacitor 63e stops. Therefore, the comparison voltage output circuit 62a outputs a lower comparison voltage Vth1 as the dead time Td1 is longer. Fig. 14 shows the relationship between the dead time Td1 and the comparison voltage Vth1. As shown in Fig. 14, according to the circuit in Fig. 13, the comparison voltage Vth1 can be output such that the dead time Td1 and the comparison voltage Vth1 have a linear relationship. This is because the current mirror circuits 63a and 63b perform accurate constant current control. Even when the circuit in Fig. 13 is the comparison voltage output circuit 62b, as shown in Fig. 14, the comparison voltage Vth2 can be output such that the dead time Td2 and the comparison voltage Vth2 have a linear relationship. That is, the comparison voltage output circuit 62b outputs a lower comparison voltage Vth2 as the dead time Td2 is longer.

[0070] Note that the comparison voltage output circuits 62a and 62b may be configured by the circuit shown in Fig. 15 instead of the circuit in Fig. 13. Also in the circuit shown in Fig. 15, lower comparison voltages Vth1 and Vth2 can be output as the dead times Td1 and Td2 are longer.

[0071] A comparison voltage holding circuit 64a receives a comparison voltage Vth1 from a comparison voltage output circuit 62a. When the comparison voltage Vth1 output by the comparison voltage output circuit 62a is fixed, the comparison voltage holding circuit 64a holds the comparison voltage Vth1 as an output voltage. The comparison voltage holding circuit 64a holds the comparison voltage Vth1. A comparison voltage holding circuit 64b receives a comparison voltage Vth2 from a comparison voltage output circuit 62b. When the comparison voltage Vth2 output by the comparison voltage output circuit 62b is fixed, the comparison voltage holding circuit 64b holds the comparison voltage Vth2 as an output voltage.

[0072] A selector circuit 66 receives comparison voltages Vth1 and Vth2 from the comparison voltage holding circuits 64a and 64b. Also, a signal Sk is input to the selector circuit 66 from a determination circuit 32. The selector circuit 66 changes its operation according to the signal Sk. When the signal Sk indicates that the switching element 22 is a reflux-side element, the selector circuit 66 inputs the comparison voltages Vth1 and Vth2 to a gate drive signal output circuit 50. When the signal Sk indicates that the switching element 22 is a drive-side element, the selector circuit 66 does not input the comparison voltages Vth1 and Vth2 to the gate drive signal output circuit 50.

[0073] As described above, the gate drive signal output circuit 50 outputs a gate drive signal Sa according to a command signal Ss2 and a signal input from the selector circuit 66. When the gate drive signal output circuit 50 does not receive the input of the comparison voltages Vth1 and Vth2 from the selector circuit 66 (that is, when the switching element 22 is a drive-side element), the gate drive signal output circuit 50 outputs a signal having the same waveform as the command signal Ss2 as the gate drive signal Sa.

[0074] The gate drive signal output circuit 50 has an adjustment voltage output circuit 51. When the gate drive signal output circuit 50 receives the input of the comparison voltages Vth1 and Vth2 from the selector circuit 66 (that is, when the switching element 22 is a reflux side element), it compares the output voltage of the adjustment voltage output circuit 51 with the comparison voltages Vth1 and Vth2 to generate the gate drive signal Sa. The gate drive signal output circuit 50 outputs the gate drive signal Sa such that the dead time Td1 becomes longer as the comparison voltage Vth1 is higher, and the dead time Td2 becomes longer as the comparison voltage Vth2 is higher.

[0075] FIG. 16 shows an example of the adjustment voltage output circuit 51. The adjustment voltage output circuit 51 in FIG. 15 has a current mirror circuit 51a, a current mirror circuit 51b, a switching element 51c, a switching element 51d, and a capacitor 51e. The current mirror circuits 51a and 51b are Wilson type current mirror circuits. The current mirror circuit 51a is a constant current circuit for charging the capacitor 51e, and the current mirror circuit 51b is a constant current circuit for discharging the capacitor 51e. A command signal Ss2 is applied to the gates of the switching element 51c and the switching element 51d. FIG. 17 shows the adjustment voltage Vtc output by the adjustment voltage output circuit 51. When the command signal Ss2 switches from a low voltage to a high voltage at the timing ty1, the switching element 51c turns off and the switching element 51d turns on. Therefore, after the timing ty1, the capacitor 51e is charged by the current mirror circuit 51a, and the adjustment voltage Vtc rises with a constant slope. The adjustment voltage Vtc rises to the voltage Vin1. Thereafter, when the command signal Ss2 switches from a high voltage to a low voltage at the timing ty2, the switching element 51c turns on and the switching element 51d turns off. Therefore, after the timing ty2, the capacitor 51e is discharged by the current mirror circuit 51b, and the adjustment voltage Vtc decreases with a constant slope. The adjustment voltage Vtc decreases to 0V. In this way, the adjustment voltage output circuit 51 converts the square-wave command signal Ss2 into the trapezoidal-wave adjustment voltage Vtc.

[0076] The gate drive signal output circuit 50 compares the adjusted voltage Vtc of the adjusted voltage output circuit 51 with the comparison voltages Vth1 and Vth2. As shown in FIG. 17, the gate drive signal output circuit 50 switches the gate drive signal Sa from a low potential to a high potential at the timing tz1 when the adjusted voltage Vtc rises from a value lower than the comparison voltage Vth1 to a value higher than the comparison voltage Vth1. Further, the gate drive signal output circuit 50 switches the gate drive signal Sa from a high potential to a low potential at the timing tz2 when the adjusted voltage Vtc drops from a value higher than the comparison voltage Vth2 to a value lower than the comparison voltage Vth2. Therefore, the gate drive signal Sa becomes a pulse signal whose rising timing and falling timing of the command signal Ss2 are changed.

[0077] Similar to the gate control circuit 26, the gate control circuit 25 includes a gate drive signal output circuit 50, a gate drive circuit 52, a gate voltage determination circuit 54, a drain voltage determination circuit 56, delay circuits 58a to 58d, phase comparators 60a and 60b, comparison voltage output circuits 62a and 62b, comparison voltage holding circuits 64a and 64b, and a selector circuit 66. The gate drive signal output circuit 50 of the gate control circuit 25 outputs a gate drive signal Sa based on the command signal Ss1. When the switching element 21 is a driving-side element, the gate drive signal output circuit 50 of the gate control circuit 25 outputs a gate drive signal Sa having the same waveform as the command signal Ss1. When the switching element 21 is a reflux-side element, the gate drive signal output circuit 50 outputs, as the gate drive signal Sa, a signal with the rising and falling timings of the command signal Ss1 changed. The gate drive circuit 52 of the gate control circuit 25 controls the gate voltage Vgs21 based on the gate drive signal Sa. The gate voltage determination circuit 54 of the gate control circuit 25 compares the gate voltage Vgs21 with the reference voltage Vref1. The drain voltage determination circuit 56 of the gate control circuit 25 compares the signal Sds21 with the reference voltage Vref2. The delay circuits 58a to 58d of the gate control circuit 25 output signals Sr1d1, Sr2d1, Sr1d2, and Sr2d2 obtained by delaying the signal Sr1 output from the gate voltage determination circuit 54 and the signal Sr2 output from the drain voltage determination circuit 56. The phase comparator 60a and the comparison voltage output circuit 62a of the gate control circuit 25 output a comparison voltage Vth1 based on the signals Sr1d1 and Sr2d1. The phase comparator 60b and the comparison voltage output circuit 62b of the gate control circuit 25 output a comparison voltage Vth2 based on the signals Sr1d2 and Sr2d2. The comparison voltage holding circuits 64a and 64b of the gate control circuit 25 hold the comparison voltages Vth1 and Vth2. When the switching element 21 is a reflux-side element, the selector circuit 66 of the gate control circuit 25 inputs the comparison voltages Vth1 and Vth2 to the gate control circuit 26. When the switching element 21 is a driving-side element, the selector circuit 66 does not input the comparison voltages Vth1 and Vth2 to the gate control circuit 26.When the switching element 21 is a reflux-side element, the gate drive signal output circuit 50 of the gate control circuit 25 compares the output voltage of the adjustment voltage output circuit 51 (i.e., the output voltage of the trapezoidal waveform) with the comparison voltages Vth1 and Vth2, and outputs a pulse signal with the rising timing and falling timing of the command signal Ss1 changed as the gate drive signal Sa.

[0078] Next, the process of the gate control circuits 25 and 26 adjusting the dead time will be described. Note that the operation of the gate control circuit 25 when the switching element 21 is a reflux-side element is the same as the operation of the gate control circuit 26 when the switching element 22 is a reflux-side element, and the operation of the gate control circuit 26 when the switching element 21 is a reflux-side element is the same as the operation of the gate control circuit 25 when the switching element 22 is a reflux-side element. Therefore, below, the operations of the gate control circuits 25 and 26 when the switching element 22 is a reflux-side element will be described. That is, the operation when the gate control circuit 25 is a drive-side gate control circuit and the gate control circuit 26 is a reflux-side gate control circuit will be described below.

[0079] The gate control circuit 25, which is a drive-side control circuit, outputs a gate drive signal Sa having the same waveform as the command signal Ss1 to control the gate voltage Vgs21. Therefore, the gate voltage Vgs21 rises substantially simultaneously with the rising of the command signal Ss1 and falls substantially simultaneously with the falling of the command signal Ss1. The gate control circuit 26, which is a reflux-side control circuit, detects the lengths of the dead times Td1 and Td2, and adjusts the subsequent lengths of the dead times Td1 and Td2 according to the detected lengths of the dead times Td1 and Td2. Below, the operation of the gate control circuit 26 (i.e., the reflux-side gate control circuit) will be described.

[0080] Figure 18 shows the changes in each value when the switching element 22 is a reflux-side element. In the following, the start timing of the dead time Td1 is referred to as timing ta2, the end timing of the dead time Td1 is referred to as timing ta3, the start timing of the dead time Td2 is referred to as timing ta3, and the end timing of the dead time Td2 is referred to as timing ta4. Timing ta2 is equal to the falling timing of the drain voltage Vds22, timing ta3 is equal to the rising timing of the gate voltage Vgs22, timing ta4 is equal to the falling timing of the gate voltage Vgs22, and timing ta1 is equal to the rising timing of the drain voltage Vds22. The inverter controller 84 outputs the command signal Ss1 and the command signal Ss2 so that the period T1 during which the command signal Ss1 is at a high potential and the period T2 during which the command signal Ss2 is at a high potential visit alternately with a period during which both the command signals Ss1 and Ss2 are at a low potential in between. As described above, the gate voltage Vgs21 rises substantially simultaneously with the rising of the command signal Ss1 and falls substantially simultaneously with the falling of the command signal Ss1. The rising timing and the falling timing of the gate voltage Vgs22 are adjusted by the gate control circuit 26.

[0081] When the switching element 21 (i.e., the driving-side element) is turned on at timing ta1, the drain voltage Vds21 decreases and the drain voltage Vds22 increases. When the switching element 21 (i.e., the driving-side element) is turned off at timing ta2, the drain voltage Vds21 increases and the drain voltage Vds22 decreases. When the switching element 22 (i.e., the reflux-side element) is turned on at timing ta3, the drain voltages Vds21 and Vds22 hardly change. When the switching element 22 (i.e., the reflux-side element) is turned off at timing ta4, the drain voltages Vds21 and Vds22 hardly change. The gate control circuit 26 detects the lengths of the dead times Td1 and Td2 in the control unit period Tc1, and adjusts the lengths of the dead times Td1 and Td2 in the next control unit period Tc2 according to the detected lengths of the dead times Td1 and Td2. The operation of the gate control circuit 26 in the case of Figure 18 will be described in detail below.

[0082] FIG. 19 shows each signal in the gate control circuit 26 during the control unit period Tc1. As shown in FIG. 19, the signal Sr1 output from the gate voltage determination circuit 54 rises when the gate voltage Vgs22 rises and falls when the gate voltage Vgs22 falls. That is, the signal Sr1 has substantially the same waveform as the gate voltage Vgs22. Also, the signal Sr2 output from the drain voltage determination circuit 56 rises when the drain voltage Vds22 rises and falls when the drain voltage Vds22 falls. That is, the signal Sr2 has substantially the same waveform as the drain voltage Vds22. Further, the signals Sr1d1, Sr2d1, Sr1d2, and Sr2d2 output from the delay circuits 58a to 58d are signals obtained by delaying the signals Sr1 and Sr2. The delay time d1 of the signal Sr1d1 is shorter than the delay time d2 of the signal Sr2d1. The dead time Tdx1 shown in FIG. 19 is a pseudo dead time between the fall of the signal Sr2d1 and the rise of the signal Sr1d1. The pseudo dead time Tdx1 is a value obtained by subtracting the delay time d2 from the actual dead time Td1 and adding the delay time d1 (that is, Tdx1 = Td1 - d2 + d1). The pseudo dead time Tdx1 is shorter than the actual dead time Td1. In FIG. 19, the rise of the signal Sr1d1 occurs after the fall of the signal Sr2d1, and the length of the pseudo dead time Tdx1 is a positive value. However, there may be a case where these orders are reversed and the length of the pseudo dead time Tdx1 becomes a negative value. Also, the delay time d4 of the signal Sr2d2 is shorter than the delay time d3 of the signal Sr1d2. The dead time Tdx2 shown in FIG. 19 is a pseudo dead time between the fall of the signal Sr1d2 and the rise of the signal Sr2d2. The pseudo dead time Tdx2 is a value obtained by subtracting the delay time d3 from the actual dead time Td2 and adding the delay time d4 (that is, Tdx2 = Td2 - d3 + d4). The pseudo dead time Tdx2 is shorter than the actual dead time Td2. In FIG. 19, the rise of the signal Sr2d2 occurs after the fall of the signal Sr1d2, and the length of the pseudo dead time Tdx2 is a positive value. However, there may be a case where these orders are reversed and the length of the pseudo dead time Tdx2 becomes a negative value.When the pseudo dead time Tdx1 has a positive value, the phase comparator 60a and the comparison voltage output circuit 62a lower the comparison voltage Vth1 during the dead time Tdx1. Also, when the pseudo dead time Tdx2 has a positive value, the phase comparator 60b and the comparison voltage output circuit 62b lower the comparison voltage Vth2 during the dead time Tdx2.

[0083] Also, FIG. 20 shows the case where the pseudo dead times Tdx1 and Tdx2 are negative. When the pseudo dead time Tdx1 has a negative value, the phase comparator 60a and the comparison voltage output circuit 62a raise the comparison voltage Vth1 during the dead time Tdx1. Also, when the pseudo dead time Tdx2 has a negative value, the phase comparator 60b and the comparison voltage output circuit 62b raise the comparison voltage Vth2 during the dead time Tdx2.

[0084] As described above, when the pseudo dead time Tdx1 is less than 0 (i.e., when Td1 < d2 - d1), the comparison voltage output circuit 62a charges the capacitor 63e with the current mirror circuit 63a to increase the comparison voltage Vth1. When the pseudo dead time Tdx1 is greater than 0 (i.e., when Td1 > d2 - d1), the current mirror circuit 63a discharges the capacitor 63e to decrease the comparison voltage Vth1. Similarly, when the pseudo dead time Tdx2 is less than 0 (i.e., when Td2 < d3 - d4), the comparison voltage output circuit 62b charges the capacitor 63e with the current mirror circuit 63a to increase the comparison voltage Vth2. When the pseudo dead time Tdx2 is greater than 0 (i.e., when Td2 > d3 - d4), the current mirror circuit 63b discharges the capacitor 63e to decrease the comparison voltage Vth2. That is, when the pseudo dead times Tdx1 and Tdx2 are positive, Vth1 and Vth2 are adjusted to increase. When the pseudo dead times Tdx1 and Tdx2 are negative, Vth1 and Vth2 are adjusted to decrease. Therefore, the comparison voltages Vth1 and Vth2 decrease as the dead times Td1 and Td2 become longer, and increase as the dead times Td1 and Td2 become shorter. Note that one of the pseudo dead time Tdx1 and the pseudo dead time Tdx2 may be a positive value and the other may be a negative value. Even in this case, the comparison voltage Vth1 and the comparison voltage Vth2 are adjusted independently.

[0085] When the comparison voltages Vth1 and Vth2 output by the comparison voltage output circuit are fixed, at the timing th immediately after that, the comparison voltage holding circuits 64a and 64b hold the comparison voltages Vth1 and Vth2. Then, even if the comparison voltages Vth1 and Vth2 output by the comparison voltage output circuits 62a and 62b fluctuate thereafter, the comparison voltages Vth1 and Vth2 output by the comparison voltage holding circuits 64a and 64b do not fluctuate. Therefore, after the timing th, the comparison voltage output circuits 62a and 62b can output new comparison voltages Vth1 and Vth2 based on the dead times Td1 and Td2 in the next control unit period Tc2. Further, the comparison voltage holding circuits 64a and 64b hold the output voltage from the timing th to the next timing th, and update the output voltage at the next timing th.

[0086] When the comparison voltage holding circuits 64a and 64b output comparison voltages Vth1 and Vth2, the selector circuit 66 inputs the comparison voltages Vth1 and Vth2 to the gate drive signal output circuit 50. Then, the gate drive signal output circuit 50 generates a gate drive signal Sa based on the command signal Ss2 and the comparison voltages Vth1 and Vth2. FIG. 21 shows the process of adjusting the dead times Td1 and Td2 in the next control unit period Tc2 when the dead times Td1 and Td2 in the control unit period Tc1 are short (i.e., when the comparison voltages Vth1 and Vth2 are high). As described above, since the gate control circuit 25 that controls the driving-side element (i.e., the switching element 21) outputs the command signal Ss1 as the gate drive signal as it is, the gate voltage Vgs21 has substantially the same waveform as the command signal Ss1. On the other hand, in the gate control circuit 26 that controls the reflux-side element (i.e., the switching element 22), as described above, the adjustment voltage output circuit 51 generates a trapezoidal adjustment voltage Vtc based on the command signal Ss2 input from the inverter controller 84. The gate drive signal output circuit 50 outputs the gate drive signal Sa such that the gate drive signal Sa rises at the timing to1 when the adjustment voltage Vtc exceeds the comparison voltage Vth1 and the gate drive signal Sa falls at the timing to2 when the adjustment voltage Vtc falls below the comparison voltage Vth2. Therefore, the gate voltage Vgs22 rises at a timing substantially coinciding with to1 and falls at a timing substantially coinciding with to2. For this reason, the gate voltage Vgs22 rises with a delay of the delay time dd1 with respect to the rising timing of the command signal Ss2 and falls with a delay of the delay time dd2 with respect to the falling timing of the command signal Ss2. Thereby, the lengths of the dead times Td1 and Td2 are adjusted. Also, FIG. 22 shows the process of adjusting the dead times Td1 and Td2 in the next control unit period Tc2 when the dead times Td1 and Td2 in the previous control unit period Tc1 are long (i.e., when the comparison voltages Vth1 and Vth2 are low). Also in this case, the gate voltage Vgs22 rises with a delay of the delay time dd1 with respect to the rising timing of the command signal Ss2 and falls with a delay of the delay time dd2 with respect to the falling timing of the command signal Ss2.As a result, the lengths of the dead times Td1 and Td2 are adjusted. As shown in FIGS. 21 and 22, when the comparison voltage Vth1 is high, the delay time dd1 becomes longer and the dead time Td1 becomes longer than when the comparison voltage Vth1 is low. Therefore, when the dead time Td1 in the previous control unit period Tc1 is short, the dead time Td1 in the control unit period Tc2 is adjusted to be longer than when the dead time Td1 in the previous control unit period Tc1 is long. Also, as shown in FIGS. 21 and 22, when the comparison voltage Vth2 is high, the delay time dd2 becomes shorter and the dead time Td2 becomes longer than when the comparison voltage Vth2 is low. Therefore, when the dead time Td2 in the previous control unit period Tc1 is short, the dead time Td2 in the control unit period Tc2 is adjusted to be longer than when the dead time Td2 in the previous control unit period Tc1 is long.

[0087] As described above, when the previous dead times Td1 and Td2 are long, the gate control circuit 26 adjusts so that the next dead times Td1 and Td2 become short, and when the previous dead times Td1 and Td2 are short, the gate control circuit 26 adjusts so that the next dead times Td1 and Td2 become long. The gate control circuit 26 repeats this process for each control unit period to adjust each dead time Td1 and Td2 to an optimal length. As a result, it is possible to suppress the dead times Td1 and Td2 from becoming longer than necessary, and to suppress the losses generated in the switching circuit 20a.

[0088] Also, the gate control circuit 26 detects the dead times Td1 and Td2 based on the drain voltage Vds22 and the gate voltage Vgs22 of the switching element 22. Since the dead times Td1 and Td2 can be detected inside a circuit where the reference voltages are equal (that is, the switching element 22, the gate control circuit 26, and the main voltage detection circuit 42), it is possible to transmit and receive signals for detecting the dead time without passing through an insulating element. Therefore, the dead times Td1 and Td2 can be accurately detected with almost no influence of signal delay.

[0089] Also, the gate control circuit 26 does not use the characteristic values of the switching element 21 for detecting the dead times Td1 and Td2. Further, the gate control circuit 26 adjusts the dead times Td1 and Td2 by changing the switching timing of the switching element 22. In this way, the adjustment process of the dead time can be completed inside the circuits (i.e., the switching element 22, the gate control circuit 26, and the main voltage detection circuit 42) where the reference voltages are equal. Therefore, it is not necessary to communicate between the gate control circuit 26 and the gate control circuit 25 having different reference voltages for adjusting the dead time. Thereby, an increase in the insulating elements can be suppressed, and the switching circuit 20a can be miniaturized.

[0090] Also, the comparison voltage output circuits 62a and 62b output the comparison voltages Vth1 and Vth2 such that the comparison voltages Vth1 and Vth2 have a linear relationship with the lengths of the dead times Td1 and Td2 by a Wilson type current mirror circuit. Further, the adjustment voltage output circuit 51 outputs a trapezoidal waveform with a linear slope portion as the adjustment voltage Vtc by a Wilson type current mirror circuit. By outputting the comparison voltages Vth1 and Vth2 and the adjustment voltage Vtc in a linear shape in this way, the dead time can be adjusted more accurately.

[0091] Also, noise may be superimposed on the signal Sr1 output by the gate voltage determination circuit 54 and the signal Sr2 output by the drain voltage determination circuit 56. However, when the signals Sr1 and Sr2 pass through the delay circuits 58a to 58d, the noise is removed. By inputting the signals after passing through the delay circuits 58a to 58d to the phase comparators 60a and 60b, false detection due to noise can be prevented.

[0092] Further, when either of the pseudo dead times Tdx1 and Tdx2 is a negative value and its absolute value exceeds the upper limit value, the gate control circuit 26 stops the dead time adjustment process. When the pseudo dead time Tdx1 is a negative value and its absolute value exceeds the upper limit value, it means that the switching element 22 is on before the switching element 21 turns off, which means that the dead time Td1 does not exist. Also, when the pseudo dead time Tdx2 is a negative value and its absolute value exceeds the upper limit value, it means that the switching element 21 is on before the switching element 22 turns off, which means that the dead time Td2 does not exist. In these cases, the dead time adjustment process is not properly performed for some reason, and a short circuit occurs between the high potential wiring 12 and the low potential wiring 14. Therefore, in this case, the gate control circuit 26 stops the dead time adjustment process to prevent a short circuit.

[0093] In the above description, the case where the switching element 22 is the reflux side element and the switching element 21 is the drive side element has been described. When the switching element 21 is the reflux side element and the switching element 22 is the drive side element, the gate control circuit 25 detects the dead time and adjusts the dead time in the same manner as described above. In this case, the gate control circuit 26 outputs the command signal Ss2 as the gate drive signal Sa as it is.

Embodiment

[0094] The switching circuit of Example 2 has a different configuration of the gate drive circuits 52 of each gate control circuit 25, 26 from that of Example 1. As shown in FIG. 23, in Example 2, the gate drive circuit 52 of the gate control circuit 26 has a configuration in which a constant current source 152a, a switching element 152b, a switching element 152c, a constant current source 152d, and a selector circuit 152f are added to the gate drive circuit 52 of FIG. 8. The constant current source 152a and the switching element 152b are connected in series between the wiring 52v and the gate G22. The switching element 152c and the constant current source 152d are connected in series between the gate G22 and the ground. The set value of the current of the constant current source 152a is higher than the set value of the current of the constant current source 52a. Also, the set value of the current of the constant current source 152d is higher than the set value of the current of the constant current source 52d. The signal Sk and the gate drive signal Sa (more specifically, the signal obtained by inverting the gate drive signal Sa) are input to the selector circuit 152f. The selector circuit 152f switches the input destination of the gate drive signal Sa based on the signal Sk (that is, the signal indicating which of the switching elements 21 and 22 is the reflux-side element). When the switching element 22 is the reflux-side element, the selector circuit 152f inputs the gate drive signal Sa to the gates of the switching element 152b and the switching element 152c, and when the switching element 22 is the drive-side element, the selector circuit 152f inputs the gate drive signal Sa to the gates of the switching element 52b and the switching element 52c. Therefore, when the switching element 22 is the reflux-side element, the gate drive circuit 52 charges and discharges the gate of the switching element 22 with a high gate current, and when the switching element 22 is the drive-side element, the gate drive circuit 52 charges and discharges the gate of the switching element 22 with a low gate current. Although not shown, the gate drive circuit 52 of the gate control circuit 25 also has the same configuration as that of FIG. 23. When the switching element 21 is the reflux-side element, the gate drive circuit 52 of the gate control circuit 25 charges and discharges the gate of the switching element 21 with a high gate current, and when the switching element 21 is the drive-side element, the gate drive circuit 52 of the gate control circuit 25 charges and discharges the gate of the switching element 21 with a low gate current.

[0095] According to this configuration, it becomes possible to change the gate voltage of the reflux-side element at a higher speed, and it becomes possible to more accurately control the dead times Td1 and Td2. Also, as described above, when changing the gate voltage of the reflux-side element, the drain voltages Vds21 and Vds22 hardly change. Therefore, even if the gate voltage of the reflux-side element is changed at high speed, almost no noise is generated. Also, when changing the gate voltage of the drive-side element, the gate voltage can be changed at a low speed, and the generation of noise can be suppressed. Thus, according to the configuration of the second embodiment, it becomes possible to more accurately control the dead times Td1 and Td2 while suppressing the generation of noise.

[0096] In the above-described first and second embodiments, the determination circuit 32 determines which of the switching elements 21 and 22 is the reflux-side element based on the direction of the output current Iout1 flowing through the intermediate wiring 16a. However, the determination circuit 32 may have any configuration as long as it can determine that the switching element 21 is the reflux-side element when a reflux current is flowing through the diode 23, and can determine that the switching element 22 is the reflux-side element when a reflux current is flowing through the diode 24. For example, the determination circuit 32 may detect the currents flowing through the diodes 23 and 24, and determine which of the switching elements 21 and 22 is the reflux-side element based on the detection result.

[0097] The gate drive circuit 52 is an example of a circuit that charges and discharges the gate of the first switching element with a constant current, and a circuit that charges and discharges the gate of the second switching element with a constant current. The dead time Td1 is an example of the pre-turn-on dead time. The timing ta2 in FIG. 18 is an example of the first specific timing. The timing ta3 in FIG. 18 is an example of the second specific timing. The comparison voltage Vth1 is an example of the specific voltage. The comparison voltage output circuit 62a is an example of the specific voltage output circuit. The capacitor 63e is an example of the specific voltage output capacitor. The current mirror circuit 63a is an example of the first Wilson type current mirror circuit. The current mirror circuit 63b is an example of the second Wilson type current mirror circuit. The gate drive signal output circuit 50 is an example of the specific timing adjustment circuit. The capacitor 51e is an example of the adjustment voltage output capacitor. The current mirror circuit 51a is an example of the first Wilson type current mirror circuit for the adjustment voltage. The current mirror circuit 51b is an example of the second Wilson type current mirror circuit for the adjustment voltage. The delay circuit 58b is an example of the first specific delay circuit. The delay circuit 58a is an example of the second specific delay circuit. The timing ta4 in FIG. 18 is an example of the first predetermined timing. The timing ta1 in FIG. 18 is an example of the second predetermined timing. The comparison voltage Vth2 is an example of the predetermined voltage. The comparison voltage output circuit 62b is an example of the predetermined voltage output circuit. The capacitor 63e is an example of the predetermined voltage output capacitor. The gate drive signal output circuit 50 is an example of the predetermined timing adjustment circuit. The delay circuit 58c is an example of the first predetermined delay circuit. The delay circuit 58d is an example of the second predetermined delay circuit.

[0098] The following lists the configurations of the technology disclosed in the present specification. (Configuration 1) A switching circuit, A high potential wiring (12), An intermediate wiring (16a), A low potential wiring (14), A high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the intermediate wiring, and a first switching element (21) having a gate, A high-potential main terminal connected to the intermediate wiring, a low-potential main terminal connected to the low-potential wiring, a second switching element (22) having a gate, A first diode (23) having a cathode connected to the high-potential main terminal of the first switching element and an anode connected to the low-potential main terminal of the first switching element, A second diode (24) having a cathode connected to the high-potential main terminal of the second switching element and an anode connected to the low-potential main terminal of the second switching element, A first gate control circuit (25) connected to the gate of the first switching element, A second gate control circuit (26) connected to the gate of the second switching element, A determination circuit (32) for determining which of the first switching element and the second switching element is the reflux-side element, which determines that the first switching element is the reflux-side element when a reflux current flows through the first diode, and determines that the second switching element is the reflux-side element when a reflux current flows through the second diode, having The first gate control circuit and the second gate control circuit control the first switching element and the second switching element so that a first period (T1) in which the first switching element is on and the second switching element is off and a second period (T2) in which the first switching element is off and the second switching element is on are alternately repeated with a dead time (Td) in between, A reflux-side gate control circuit that controls the reflux-side element among the first gate control circuit and the second gate control circuit performs detection of the length of the dead time based on the main voltage (Vds22), which is the voltage between the high-potential main terminal and the low-potential main terminal of the reflux-side element, and the gate voltage (Vgs22) of the reflux-side element, and performs adjustment of the length of the dead time after the detection based on the detected length of the dead time. A switching circuit. (Configuration 2) The first gate control circuit charges and discharges the gate of the first switching element with a constant current, The second gate control circuit charges and discharges the gate of the second switching element with a constant current. The switching circuit according to Configuration 1. (Configuration 3) The reflux-side gate control circuit is configured to adjust an on-time dead time (Td1) before the reflux-side element turns on, The switching circuit according to Configuration 1 or 2, wherein the reflux-side gate control circuit shortens the on-time dead time after the detection as the specific period from a first specific timing (ta2) at which the main voltage of the reflux-side element rises to a second specific timing (ta3) at which the gate voltage of the reflux-side element rises thereafter becomes longer. (Configuration 4) The reflux-side gate control circuit A specific voltage output circuit (62a) that outputs a specific voltage (Vth1) having a magnitude corresponding to the length of the specific period, A specific timing adjustment circuit (50) that adjusts the timing at which the gate voltage of the reflux-side element rises after the detection according to the magnitude of the specific voltage, The switching circuit according to Configuration 3, which includes (Configuration 5) The specific voltage output circuit A specific voltage output capacitor (63e), A first Wilson-type current mirror circuit (63a) that charges the specific voltage output capacitor when the specific period is shorter than a reference value, A second Wilson-type current mirror circuit (63b) that discharges the specific voltage output capacitor when the specific period is longer than the reference value, and includes wherein the specific voltage is the voltage between both ends of the specific voltage output capacitor. The switching circuit according to Configuration 4. (Configuration 6) The specific timing adjustment circuit is configured to receive an input of a command signal (Ss2) that changes between an on voltage and an off voltage. the specific timing adjustment circuit a regulated voltage output capacitor (51e); a first regulated voltage Wilson-type current mirror circuit (51a) that charges the regulated voltage output capacitor from the timing when the command signal switches from the off voltage to the on voltage; a second regulated voltage Wilson-type current mirror circuit (51b) that discharges the regulated voltage output capacitor from the timing when the command signal switches from the on voltage to the off voltage; and has the specific timing adjustment circuit outputs a signal that raises the gate voltage of the reflux side element when the voltage (Vtc) between both ends of the regulated voltage output capacitor becomes higher than the specific voltage. The switching circuit according to Configuration 4 or 5. (Configuration 7) The reflux side gate control circuit a first specific delay circuit (58b) that inputs a first specific delay signal obtained by delaying a signal indicating the main voltage of the reflux side element to the specific voltage output circuit; a second specific delay circuit (58a) that inputs a second specific delay signal obtained by delaying a signal indicating the gate voltage of the reflux side element to the specific voltage output circuit; and has the specific voltage output circuit adjusts the magnitude of the specific voltage based on the first specific delay signal and the second specific delay signal. The switching circuit according to any one of Configurations 4 to 6. (Configuration 8) The reflux side gate control circuit stops the adjustment of the dead time length when the gate voltage of the reflux side element rises while the main voltage of the reflux side element has not decreased, according to any one of Configurations 3 to 7. (Configuration 9) The reflux side gate control circuit is configured to adjust the post-turn-off dead time (Td2) after the reflux side element turns off. The switching circuit according to any one of Configurations 1 to 8, wherein the reflux-side gate control circuit shortens the off dead time after the detection as the predetermined period from the first predetermined timing (ta4) at which the gate voltage of the reflux-side element falls to the second predetermined timing (ta1) at which the main voltage of the reflux-side element rises thereafter is longer. (Configuration 10) The reflux-side gate control circuit includes a predetermined voltage output circuit (62b) that outputs a predetermined voltage (Vth2) having a magnitude corresponding to the length of the predetermined period, and a predetermined timing adjustment circuit (50) that adjusts the timing at which the gate voltage of the reflux-side element falls after the detection according to the magnitude of the predetermined voltage. The switching circuit according to Configuration 9, having the above components. (Configuration 11) The predetermined voltage output circuit includes a predetermined voltage output capacitor (63e), a first Wilson-type current mirror circuit (63a) that charges the predetermined voltage output capacitor when the predetermined period is shorter than a level value, and a second Wilson-type current mirror circuit (63b) that discharges the predetermined voltage output capacitor when the predetermined period is longer than the level value. The switching circuit according to Configuration 10, having the above components, wherein the predetermined voltage is the voltage between both ends of the predetermined voltage output capacitor. The switching circuit according to Configuration 10. (Configuration 12) The predetermined timing adjustment circuit is configured to receive an input of a command signal (Ss2) that changes between an on voltage and an off voltage. The predetermined timing adjustment circuit includes an adjustment voltage output capacitor (51e), a first adjustment voltage Wilson-type current mirror circuit (51a) that charges the adjustment voltage output capacitor from the timing at which the command signal switches from the off voltage to the on voltage, and A second regulated voltage Wilson-type current mirror circuit (51b) that discharges the regulated voltage output capacitor from the timing when the command signal switches from the on voltage to the off voltage. having When the voltage (Vtc) between both ends of the regulated voltage output capacitor becomes lower than the predetermined voltage, the predetermined timing adjustment circuit outputs a signal that reduces the gate voltage of the return side element. The switching circuit according to Configuration 10 or 11. (Configuration 13) The return side gate control circuit A first predetermined delay circuit (58c) that inputs a first predetermined delay signal obtained by delaying a signal indicating the main voltage of the return side element to the predetermined voltage output circuit; A second predetermined delay circuit (58d) that inputs a second predetermined delay signal obtained by delaying a signal indicating the gate voltage of the return side element to the predetermined voltage output circuit. having The predetermined voltage output circuit adjusts the magnitude of the predetermined voltage based on the first predetermined delay signal and the second predetermined delay signal. The switching circuit according to any one of Configurations 10 to 12. (Configuration 14) When the main voltage of the return side element rises while the gate voltage of the return side element has not decreased, the return side gate control circuit stops the adjustment of the dead time length. The switching circuit according to any one of Configurations 9 to 13. (Configuration 15) The one that is not the return side gate control circuit among the first gate control circuit and the second gate control circuit is the drive side gate control circuit. When the first gate control circuit is the return side gate control circuit, it increases the gate current of the first switching element more than when it is the drive side gate control circuit. When the second gate control circuit is the return side gate control circuit, it increases the gate current of the second switching element more than when it is the drive side gate control circuit. The switching circuit according to any one of Configurations 1 to 14. (Configuration 16) The reflux-side gate control circuit has a main voltage detection circuit (42) that detects the main voltage of the reflux-side element. The main voltage detection circuit is a series circuit of two capacitors (47, 48) to which the main voltage is applied, and an output wiring (46) that outputs the voltage at the connection point of the two capacitors. It has The switching circuit according to any one of Configurations 1 to 15.

[0099] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Numerals

[0100] 21, 22: Switching elements, 23, 24: Diodes, 25, 26: Gate control circuits, 32: Determination circuit

Claims

1. A switching circuit comprising: a high potential wiring (12); an intermediate wiring (16a); a low potential wiring (14); a high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the intermediate wiring, and a first switching element (21) having a gate; a high potential main terminal connected to the intermediate wiring, a low potential main terminal connected to the low potential wiring, and a second switching element (22) having a gate; a first diode (23) having a cathode connected to the high potential main terminal of the first switching element and an anode connected to the low potential main terminal of the first switching element; a second diode (24) having a cathode connected to the high potential main terminal of the second switching element and an anode connected to the low potential main terminal of the second switching element; a first gate control circuit (25) connected to the gate of the first switching element; a second gate control circuit (26) connected to the gate of the second switching element; a determination circuit (32) for determining which of the first switching element and the second switching element is a reflux side element, the determination circuit determining that the first switching element is the reflux side element when a reflux current flows through the first diode, and determining that the second switching element is the reflux side element when a reflux current flows through the second diode; wherein: the first gate control circuit and the second gate control circuit control the first switching element and the second switching element such that a first period (T1) in which the first switching element is on and the second switching element is off and a second period (T2) in which the first switching element is off and the second switching element is on are alternately repeated with a dead time (Td) therebetween; a reflux side gate control circuit that controls the reflux side element among the first gate control circuit and the second gate control circuit performs detection of the length of the dead time based on a main voltage (Vds22) that is a voltage between the high potential main terminal and the low potential main terminal of the reflux side element and a gate voltage (Vgs22) of the reflux side element, and performs adjustment of the length of the dead time after the detection based on the detected length of the dead time; The reflux-side gate control circuit is configured to adjust an on-time dead time (Td1) before the reflux-side element turns on. The longer the specific period from a first specific timing (ta2) at which the main voltage of the reflux-side element falls to a second specific timing (ta3) at which the gate voltage of the reflux-side element then rises, the shorter the on-time dead time after the detection, with the reflux-side gate control circuit. Switching circuit.

2. The reflux-side gate control circuit, A specific voltage output circuit (62a) that outputs a specific voltage (Vth1) having a magnitude corresponding to the length of the specific period, A specific timing adjustment circuit (50) that adjusts the timing at which the gate voltage of the reflux-side element rises after the detection according to the magnitude of the specific voltage, The switching circuit according to claim 1, comprising:

3. The specific voltage output circuit, A specific voltage output capacitor (63e), A first Wilson-type current mirror circuit (63a) that charges the specific voltage output capacitor when the specific period is shorter than a reference value, A second Wilson-type current mirror circuit (63b) that discharges the specific voltage output capacitor when the specific period is longer than the reference value, Comprising: The specific voltage is the voltage across both ends of the specific voltage output capacitor. The switching circuit according to claim 2.

4. The specific timing adjustment circuit is configured to receive an input of a command signal (Ss2) that changes between an on-voltage and an off-voltage, The specific timing adjustment circuit, An adjustment voltage output capacitor (51e), A first adjustment voltage Wilson-type current mirror circuit (51a) that charges the adjustment voltage output capacitor from the timing when the command signal switches from the off-voltage to the on-voltage, A second adjustment voltage Wilson-type current mirror circuit (51b) that discharges the adjustment voltage output capacitor from the timing when the command signal switches from the on-voltage to the off-voltage, Comprising: The specific timing adjustment circuit outputs a signal to raise the gate voltage of the reflux-side element when the voltage (Vtc) across both ends of the adjustment voltage output capacitor becomes higher than the specific voltage. The switching circuit according to claim 2.

5. The reflux-side gate control circuit, A first specific delay circuit (58b) that inputs a first specific delay signal obtained by delaying a signal indicating the main voltage of the reflux-side element to the specific voltage output circuit; A second specific delay circuit (58a) that inputs a second specific delay signal obtained by delaying a signal indicating the gate voltage of the reflux-side element to the specific voltage output circuit; having the specific voltage output circuit adjusts the magnitude of the specific voltage based on the first specific delay signal and the second specific delay signal; The switching circuit according to claim 2.

6. The switching circuit according to claim 1, wherein the reflux-side gate control circuit stops the adjustment of the dead time length when the gate voltage of the reflux-side element rises while the main voltage of the reflux-side element has not decreased.

7. A switching circuit, a high-potential wiring (12); an intermediate wiring (16a); a low-potential wiring (14); a high-potential main terminal connected to the high-potential wiring, a low-potential main terminal connected to the intermediate wiring, and a first switching element (21) having a gate; a high-potential main terminal connected to the intermediate wiring, a low-potential main terminal connected to the low-potential wiring, and a second switching element (22) having a gate; a first diode (23) having a cathode connected to the high-potential main terminal of the first switching element and an anode connected to the low-potential main terminal of the first switching element; a second diode (24) having a cathode connected to the high-potential main terminal of the second switching element and an anode connected to the low-potential main terminal of the second switching element; a first gate control circuit (25) connected to the gate of the first switching element; a second gate control circuit (26) connected to the gate of the second switching element; a determination circuit (32) for determining which of the first switching element and the second switching element is the reflux-side element, the determination circuit determining that the first switching element is the reflux-side element when a reflux current flows through the first diode, and determining that the second switching element is the reflux-side element when a reflux current flows through the second diode; having The first gate control circuit and the second gate control circuit control the first switching element and the second switching element such that a first period (T1) in which the first switching element is on and the second switching element is off and a second period (T2) in which the first switching element is off and the second switching element is on are alternately repeated with a dead time (Td) therebetween. A freewheeling side gate control circuit that controls the freewheeling side element among the first gate control circuit and the second gate control circuit performs detection of the length of the dead time based on a main voltage (Vds22) that is the voltage between the high potential main terminal and the low potential main terminal of the freewheeling side element and a gate voltage (Vgs22) of the freewheeling side element, and performs adjustment of the length of the dead time after the detection based on the detected length of the dead time. The freewheeling side gate control circuit is configured to adjust an off dead time (Td2) after the freewheeling side element turns off. The freewheeling side gate control circuit shortens the off dead time after the detection as the predetermined period from a first predetermined timing (ta4) at which the gate voltage of the freewheeling side element falls to a second predetermined timing (ta1) at which the main voltage of the freewheeling side element rises thereafter is longer. Switching circuit.

8. The freewheeling side gate control circuit A predetermined voltage output circuit (62b) that outputs a predetermined voltage (Vth2) having a magnitude corresponding to the length of the predetermined period, A predetermined timing adjustment circuit (50) that adjusts the timing at which the gate voltage of the freewheeling side element falls after the detection according to the magnitude of the predetermined voltage. The switching circuit according to claim 7, comprising:

9. The predetermined voltage output circuit A predetermined voltage output capacitor (63e), A first Wilson type current mirror circuit (63a) that charges the predetermined voltage output capacitor when the predetermined period is shorter than a level value, A second Wilson type current mirror circuit (63b) that discharges the predetermined voltage output capacitor when the predetermined period is longer than the level value. comprising: The predetermined voltage is the voltage between both ends of the predetermined voltage output capacitor. The switching circuit according to claim 8.

10. The predetermined timing adjustment circuit is configured to receive an input of a command signal (Ss2) that changes between an on voltage and an off voltage. the predetermined timing adjustment circuit a regulated voltage output capacitor (51e); a first regulated voltage Wilson type current mirror circuit (51a) for charging the regulated voltage output capacitor from the timing when the command signal switches from the off voltage to the on voltage; a second regulated voltage Wilson type current mirror circuit (51b) for discharging the regulated voltage output capacitor from the timing when the command signal switches from the on voltage to the off voltage; and having the predetermined timing adjustment circuit outputs a signal for reducing the gate voltage of the current return element when the voltage (Vtc) across both ends of the regulated voltage output capacitor becomes lower than the predetermined voltage; The switching circuit according to claim 8.

11. The current return side gate control circuit a first predetermined delay circuit (58c) that inputs a first predetermined delay signal obtained by delaying a signal indicating the main voltage of the current return element to the predetermined voltage output circuit; a second predetermined delay circuit (58d) that inputs a second predetermined delay signal obtained by delaying a signal indicating the gate voltage of the current return element to the predetermined voltage output circuit; and having the predetermined voltage output circuit adjusts the magnitude of the predetermined voltage based on the first predetermined delay signal and the second predetermined delay signal; The switching circuit according to claim 8.

12. The current return side gate control circuit stops the adjustment of the dead time length when the main voltage of the current return element rises while the gate voltage of the current return element has not decreased, according to the switching circuit of claim 7.

13. A switching circuit, comprising a high potential wiring (12); an intermediate wiring (16a); a low potential wiring (14); a high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the intermediate wiring, and a first switching element (21) having a gate; a high potential main terminal connected to the intermediate wiring, a low potential main terminal connected to the low potential wiring, and a second switching element (22) having a gate; a first diode (23) having a cathode connected to the high potential main terminal of the first switching element and an anode connected to the low potential main terminal of the first switching element; a second diode (24) having a cathode connected to the high potential main terminal of the second switching element and an anode connected to the low potential main terminal of the second switching element; a first gate control circuit (25) connected to the gate of the first switching element; a second gate control circuit (26) connected to the gate of the second switching element; a determination circuit (32) for determining which of the first switching element and the second switching element is the reflux-side element, the determination circuit determining that the first switching element is the reflux-side element when a reflux current flows through the first diode, and determining that the second switching element is the reflux-side element when a reflux current flows through the second diode; comprising the first gate control circuit and the second gate control circuit control the first switching element and the second switching element such that a first period (T1) in which the first switching element is on and the second switching element is off and a second period (T2) in which the first switching element is off and the second switching element is on are alternately repeated with a dead time (Td) therebetween; a reflux-side gate control circuit that controls the reflux-side element among the first gate control circuit and the second gate control circuit detects the length of the dead time based on a main voltage (Vds22) that is a voltage between the high-potential main terminal and the low-potential main terminal of the reflux-side element and a gate voltage (Vgs22) of the reflux-side element, and adjusts the length of the dead time after the detection based on the detected length of the dead time; the non-reflux-side gate control circuit among the first gate control circuit and the second gate control circuit is a drive-side gate control circuit; when the first gate control circuit is the reflux-side gate control circuit, the first gate control circuit increases the gate current of the first switching element more than when it is the drive-side gate control circuit; when the second gate control circuit is the reflux-side gate control circuit, the second gate control circuit increases the gate current of the second switching element more than when it is the drive-side gate control circuit; a switching circuit.

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