Semiconductor device

Abstract

To provide a programmable logic device (PLD) with a smaller number of switches and high reliability.SOLUTION: A PLD 100 includes wirings 103-109, and columns 102-1 to 102-3 having a plurality of logic elements (LE) 101. Each of first output terminals of LEs 101 of the first column 102-1 is connected to respective one of the plurality of wirings 103. Each of second output terminals of LEs 101 of the first column 102-1 is connected to respective one of the plurality of wirings 104, and the same applies to other columns. A switch circuit 110 for controlling connections between the plurality of wirings 104 to wirings 106 and the input terminals of the LEs 101 of the second column 102-2 includes a plurality of switch circuits 120-1 to 120-3. The number of switch circuits 120 of the switch circuit 110 can be defined according to the number of the input terminals of the LE 101.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a programmable logic device capable of changing the configuration of hardware, and a semiconductor device using the programmable logic de vice, etc.

Background Art

[0002] A programmable logic device (PLD) is characterized in that a logic circuit is composed of logic elements (basic blocks) of an appropriate scale, and the functions of each logic element and the connection structure between the logic elements can be changed after manufacturing. Specifically, the PLD has a plurality of logic elements , wiring resources for controlling the connections between the logic elements, and registers. The above registers store data (configuration data) for defining the functions of each logic element and the connection structure between the logic elements constituted by the wiring resources. The register for storing the configuration data is called a configuration memory. Storing the configuration data in the configuration memory is called configuration. In particular, the co nfiguration of the configuration data into the configuration memory is called configuration.

[0003] The register for storing the configuration data is called a configuration memory. Storing the configuration data in the configuration memory is called configuration. In particular, the co nfiguration of the configuration data into the configuration memory to the configuration memory New storage of configuration data is called reconfiguration (reconstruction). is called.

[0004] By the way, a PLD that can reconfigure a logic circuit during operation, called dynamic reconfiguration, has the advantage of higher area efficiency compared to a normal PLD. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. has the advantage of being more area-efficient than a normal PLD. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method is a technique for realizing dynamic reconfiguration by storing the configuration data read from a memory element in a configuration memory corresponding to each of the logic elements or wiring resources respectively. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. The multi-context method can perform reconfiguration of a logic circuit at a higher speed compared to a configuration information distribution method that realizes dynamic reconfiguration by sending the configuration data read from a memory element in order to the configuration memory corresponding to the logic element or wiring resource. can be done.

[0005] Patent Document 1 below describes a programmable LSI that performs reconfiguration in a short time by storing the configuration data sent from a DRAM (Dynamic Random Access Memory) in a configuration memory composed of an SRAM (Static Random Access Memory). Patent Document 1 below describes a programmable LSI that performs reconfiguration in a short time by storing the configuration data sent from a DRAM (Dynamic Random Access Memory) in a configuration memory composed of an SRAM (Static Random Access Memory). Patent Document 1 below describes a programmable LSI that performs reconfiguration in a short time by storing the configuration data sent from a DRAM (Dynamic Random Access Memory) in a configuration memory composed of an SRAM (Static Random Access Memory). Patent Document 1 below describes a programmable LSI that performs reconfiguration in a short time by storing the configuration data sent from a DRAM (Dynamic Random Access Memory) in a configuration memory composed of an SRAM (Static Random Access Memory). is described.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, the PLD using the multi-context method mentioned above has a memory element and a Since a configuration memory is required, dynamic reconfiguration such as configuration information delivery method is not possible. Compared to other methods of achieving this, the memory elements and configuration memory The advantage of dynamic reconfiguration is that it occupies a large area on the PLD of memory devices such as In particular, SRAM has a large number of elements per memory cell, so It is difficult to reduce the area of ​​the device. Also, the number of elements per memory cell is Since the number of bits is smaller than that of SRAM, it is advantageous for keeping the area of ​​the memory device small. It is difficult to reduce power consumption because of the need for a resh.

[0008] In addition, increasing the degree of freedom in designing programmable logic devices reduces wiring resources. The number of switches in a routing resource tends to increase. The selection of the non-conducting state (switching) is determined by the configuration data. Therefore, when the number of switches increases, the circuit scale of the programmable logic device increases. In proportion to this, the capacity of the configuration data corresponding to one circuit configuration becomes large. This reduces the time it takes to transfer configuration data to the configuration memory. In addition, as the number of switches increases, memory elements with large storage capacities or Configuration memory is required, making it difficult to keep the area of ​​the storage device small. In addition, the increase in the number of switches increases the number of internal Then, the delay of the signal passing through the switch becomes significant, impeding the high-speed operation of the programmable logic device.

[0009] In addition, various wirings connected to the switch of the wiring resources may have an indeterminate potential after the power supply of the programmable logic device is turned off. Furthermore, depending on the configuration of the memory element used for the configuration memory, the configuration data that determines the switching of the switch included in the wiring resources may be lost when the power supply of the programmable logic device is turned off. For example, in the programmable LSI described in Patent Document 1 above, since the configuration memory is composed of SRAM, when the power supply of the programmable logic device is turned off, the configuration data is lost. And when the potential of the wiring becomes indeterminate, and furthermore, when the configuration data is lost, wirings that are electrically separated during normal operation may become conductive through the above switch after the power supply of the programmable logic device is turned on. In this case, if the potentials between the above wirings are different, a large amount of current may flow through these wirings, possibly causing damage to the programmable logic device.

[0010] Under the technical background as described above, one aspect of the present invention is to provide a programmable logic device that can increase the degree of design freedom while suppressing the number of switches that control the connection between logic elements. Another aspect of the present invention is to provide a highly reliable programmable logic device.

[0011] Also, one of the problems of the present invention is to provide a semiconductor device that can achieve high-speed operation or high reliability by using the programmable logic device.

[0012] In addition, as the circuit scale of the programmable logic device increases, a configuration memory with a larger storage capacity is required, making it difficult to reduce the area of the programmable logic device.

[0013] Therefore, one aspect of the present invention is to provide a programmable logic device that can suppress the layout area from increasing even when the circuit scale increases.

[0014] Also, one aspect of the present invention is to provide a programmable logic device that can suppress the area of the storage device. Also, one aspect of the present invention is to provide a programmable logic device that can perform the reconstruction of the logic circuit at high speed and suppress the area of the storage device. Also, one aspect of the present invention is to provide a programmable logic device that can perform the reconstruction of the logic circuit at high speed, suppress the area of the storage device, and achieve high-speed operation.

[0015] Also, one aspect of the present invention is to provide a semiconductor device that can achieve miniaturization or high functionality by using the programmable logic device.

[0016] Alternatively, one aspect of the present invention is to provide a novel semiconductor device or the like. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention ​​​​​​​​​​​ It is assumed that it is not necessary to solve all of these problems. Other problems will be obvious from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0017] In a first aspect of the present invention, a storage device function for holding its conduction state is added to a switch circuit included in wiring resources. Specifically, the switch circuit includes a first transistor that functions as a first switch for controlling electrical connections between wirings or terminals, and a second transistor that functions as a second switch for supplying, holding, and discharging an amount of charge determined by configuration data at the gate of the first transistor. A plurality of sets each having such a combination are provided. Then, according to the configuration data, when the first transistor in one of the plurality of sets becomes conductive, the connection structure via the switch circuit between the plurality of wirings and the input terminals of the logic elements is determined.

[0018] A transistor having a channel formation region in a semiconductor film with a wider bandgap and a lower intrinsic carrier density than silicon can make the off-current extremely small compared to a transistor having a channel formation region in a semiconductor such as ordinary silicon or germanium. Examples of semiconductors having a wider bandgap and a lower intrinsic carrier density than silicon include oxide semiconductors, silicon carbide, gallium nitride, etc., which have a bandgap more than twice that of silicon.

[0019] In order to prevent the charge held in the gate of the first transistor from leaking, it is desirable that the off-current be extremely small. Therefore, a semiconductor film having a wider bandgap and a lower intrinsic carrier density than silicon, such as the one described above, a transistor having a channel formation region is suitable for use as the second transistor. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. Also, since the off-current of the second transistor is smaller than that of a transistor having a channel formation region in a silicon film, the data holding time in the switch circuit can be made longer than that of a DRAM. Therefore, the frequency of rewriting the data can be reduced, thereby suppressing the power consumption. Furthermore, the programmable logic device according to the first aspect of the present invention includes a plurality of first logic .

[0020] In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element.

[0021] In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element. In the switch circuit having the above configuration, the conduction state of the first transistor that controls the electrical connection between the wirings or the terminals is determined by the configuration data, and the conduction state is maintained by the second transistor having an extremely small off-current. Therefore, in the programmable logic device according to one aspect of the present invention, the switch circuit has both a function as a configuration memory and a function as a memory element, and since the number of elements in each set is smaller than that of SRAM, the area of the storage device for storing the configuration data can be kept smaller than that of a conventional programmable logic device having both a configuration memory and a memory element.

[0022] Furthermore, the programmable logic device according to the first aspect of the present invention includes a plurality of first logic A column having first logic elements, a column having a plurality of second logic elements, and a plurality of third logic elements at least. Further, a programmable logic device according to an aspect of the present invention has a plurality of first wirings electrically connected to output terminals respectively had by the plurality of first logic elements, a plurality of second wirings electrically connected to output terminals respectively had by the plurality of second logic elements, and a plurality of third wirings electrically connected to output terminals respectively had by the plurality of third logic elements. Further, the first wiring and the second wiring are provided between the plurality of first logic elements and the plurality of second logic elements, the third wiring is provided between the plurality of first logic elements and the plurality of second logic elements, and is also provided between the plurality of second logic elements and the plurality of third logic elements.

[0023] Also, in the first aspect of the present invention, the electrical connection between the first wiring, the second wiring, and the third wiring and the input terminals respectively had by the plurality of second logic elements is controlled by a plurality of the switch circuits. Specifically, in each switch circuit, according to the configuration data, when the first transistor in one of the plurality of sets becomes conductive, the electrical connection structure between the first wiring, the second wiring, and the third wiring and the input terminals respectively had by the plurality of second logic elements is determined.

[0024] In the first aspect of the present invention, with the above configuration, the electrical connection between one second logic element and one second logic element can be controlled by one switch circuit. Further , the electrical connection between one first logic element and one second logic element can be controlled by one switch circuit. Also, the electrical connection between one second logic element and one third logic element can be controlled by one switch circuit. Therefore, in one aspect of the present invention, while increasing the degree of freedom in design in a programmable logic device, the number of switch circuits included in the wiring resources can be suppressed.

[0025] In a second aspect of the present invention, the switch circuit included in the wiring resources includes a first switch and a second switch that controls the electrical connection between wirings according to the potential of a node to which a signal including configuration data is applied via the first switch described above. And there are a plurality of sets each having at least the above. Then, according to the configuration data, in one of the above plurality of sets, when the second switch is turned on, a connection structure via a switch circuit is defined between one of the plurality of wirings respectively connected to the output terminals of the plurality of logic elements and one of the wirings electrically connected to the input terminal of one logic element.

[0026] Furthermore, the programmable logic device according to the second aspect of the present invention has at least a column having a plurality of first logic elements, a column having a plurality of second logic elements, and a column having a plurality of third logic elements. And a plurality of wirings respectively electrically connected to the output terminals of the plurality of first logic elements are defined as first wirings, and a plurality of wirings respectively electrically connected to the output terminals of the plurality of second logic elements are defined as second wirings, and a plurality of wirings respectively electrically connected to the output terminals of the plurality of third logic elements are connected to the second wirings, and a plurality of wirings respectively electrically connected to the output terminals of the plurality of third logic elements are defined as third wirings. When a plurality of continuous wirings are used as the third wiring, in one aspect of the present invention, the plurality of first wirings and the plurality of second wirings are provided between a column having a plurality of first logic elements and a column having a plurality of second logic elements, and the plurality of third wirings are provided between a column having a plurality of first logic elements and a column having a plurality of second logic elements, and are also provided between a column having a plurality of second logic elements and a column having a plurality of third logic elements. And it is assumed that they are provided. And when a plurality of wirings each electrically connected to the input terminals of the plurality of second logic elements are used as the fourth wiring, in one aspect of the present invention, the electrical connection between the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings and the plurality of fourth wirings is controlled by the plurality of switch circuits. Specifically, according to the configuration data, when the second switch in one of the plurality of sets of each switch

[0027] circuit becomes conductive, an electrical connection structure between any one of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings and any one of the plurality of fourth wirings is determined. In a second aspect of the present invention, with the above configuration, the electrical connection between one second logic element and another second logic element can be controlled by one switch circuit. Also, the electrical connection between one first logic element and one second logic element can be controlled by one switch circuit. Also, the electrical connection between one second logic element and one third logic element can be controlled by one switch circuit. Therefore, in one aspect of the present invention, the design freedom in the programmable logic device is increased. Specifically, the electrical connection between any one of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings and any one of the plurality of fourth wirings is determined by the second switch in one of the plurality of sets of each switch circuit becoming conductive according to the configuration data. That is, the electrical connection structure between any one of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings and any one of the plurality of fourth wirings is determined.

[0028] In a second aspect of the present invention, with the above configuration, the electrical connection between one second logic element and another second logic element can be controlled by one switch circuit. Also, the electrical connection between one first logic element and one second logic element can be controlled by one switch circuit. Also, the electrical connection between one second logic element and one third logic element can be controlled by one switch circuit. Therefore, in one aspect of the present invention, the design freedom in the programmable logic device is increased. Specifically, the electrical connection between any one of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings and any one of the plurality of fourth wirings is determined by the second switch in one of the plurality of sets of each switch circuit becoming conductive according to the configuration data. While increasing the degree of freedom, the number of switch circuits included in the wiring resources can be suppressed.

[0029] Furthermore, the programmable logic device according to the second aspect of the present invention includes a wiring electrically connected to an input terminal of any one of the first to third logic elements, and a switch for controlling an electrical connection with a wiring to which a predetermined potential is applied is provided. In one aspect of the present invention, with the above configuration, the potential of the wiring electrically connected to the input terminal can be initialized to a predetermined level. Therefore, after the power supply of the programmable logic device is turned off, the potential of the wiring electrically connected to the input terminal becomes an indeterminate state, and further, due to the disappearance of the configuration data, after the power supply is turned on, even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. Also, immediately after the power supply of the programmable logic device is turned on, the input terminal of the logic element may become an intermediate potential between the high level and the low level. When the intermediate potential is applied to the input terminal of the logic element, a through current is likely to occur in the CMOS circuit of the logic element. However, in one aspect of the present invention, with the above configuration, it is possible to prevent the input terminal from becoming an intermediate potential after the power supply is turned on, so that the occurrence of the above through current can be prevented. A wiring electrically connected to an input terminal of any one of the first to third logic elements, and a switch for controlling an electrical connection with a wiring to which a predetermined potential is applied is provided. A switch for controlling an electrical connection between a wiring electrically connected to an input terminal of any one of the first to third logic elements and a wiring to which a predetermined potential is applied is provided. In one aspect of the present invention, with the above configuration, the potential of the wiring electrically connected to the input terminal can be initialized to a predetermined level. Therefore, after the power supply of the programmable logic device is turned off, the potential of the wiring electrically connected to the input terminal becomes an indeterminate state, and further, due to the disappearance of the configuration data, after the power supply is turned on, even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. After the power supply of the programmable logic device is turned off, the potential of the wiring electrically connected to the input terminal becomes an indeterminate state, and further, due to the disappearance of the configuration data, after the power supply is turned on, even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. Furthermore, due to the disappearance of the configuration data, after the power supply is turned on, even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. After the power supply is turned on, even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. Even if the wiring electrically connected to the input terminal and the plurality of wirings electrically connected to the output terminals are in a conductive state, the current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. The current flowing between the wirings can be prevented from flowing into the logic element from the input terminal, thereby preventing damage to the programmable logic device. Thereby, it is possible to prevent damage to the programmable logic device. Immediately after the power supply of the programmable logic device is turned on, the input terminal of the logic element may become an intermediate potential between the high level and the low level. When the intermediate potential is applied to the input terminal of the logic element, a through current is likely to occur in the CMOS circuit of the logic element. When the intermediate potential is applied to the input terminal of the logic element, a through current is likely to occur in the CMOS circuit of the logic element. However, in one aspect of the present invention, with the above configuration, it is possible to prevent the input terminal from becoming an intermediate potential after the power supply is turned on, so that the occurrence of the above through current can be prevented. However, in one aspect of the present invention, with the above configuration, it is possible to prevent the input terminal from becoming an intermediate potential after the power supply is turned on, so that the occurrence of the above through current can be prevented.

[0030] In addition to the above switch for performing initialization, the programmer according to the second aspect of the present invention The Boolean logic device may be provided with a latch having a function of maintaining the potential of the wiring electrically connected to the input terminal at either a high level or a low level. In one aspect of the present invention, with the above configuration, after the power is turned on, the potential of the input terminal can be maintained at either a high level or a low level, so that the occurrence of the above-mentioned through current can be prevented.

[0031] Also, in a third aspect of the present invention, a configuration memory included in a logic element includes a first switch, and a first wiring to which a first potential is applied according to the potential of a first node to which a first signal including configuration data is applied via the first switch, a second switch that controls electrical connection between the first wiring and a second wiring, a third switch, and a second node to which a second signal having a polarity inverted with respect to the first signal is applied via the third switch, a fourth switch that controls electrical connection between a third wiring to which a second potential lower than the first potential is applied and the second wiring according to the potential of the second node, and a fifth switch that controls output of the potential of the second wiring to a fourth wiring. And, it is assumed that a logical operation performed by the logic element is defined according to the configuration data. In a third aspect of the present invention, with the above configuration, according to the configuration data, the first potential or the second potential can be applied to the fourth wiring. Therefore, before reading the configuration data from the configuration memory, the configuration data can be accurately read without pre-charging the fourth wiring.

[0032] In a third aspect of the present invention, with the above configuration, according to the configuration data, the first potential or the second potential can be applied to the fourth wiring. Thus, before reading the configuration data from the configuration memory, the configuration data can be accurately read without pre-charging the fourth wiring. ging the fourth wiring. Therefore, the configuration data can be accurately read without pre-charging the fourth wiring. ​​​​​​Then, a circuit for performing precharge is provided in the drive circuit of the configuration memory There is no need, and the area of the programmable logic device can be reduced.

[0033] And, in the fourth aspect of the present invention, a plurality of logic elements each having the configuration memory as described above form a column, and the configuration memories respectively included in the plurality of logic elements are arranged in a matrix It is assumed that they are arranged. Further, in the fourth aspect of the present invention, a plurality of switch circuits included in the wiring resources are also arranged in a matrix It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced

[0034] In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced

Effects of the Invention

[0035] According to one aspect of the present invention, a programmable logic device capable of reducing the area of the memory device can be provided. Also, according to one aspect of the present invention, the logical circuit can be reconfigured at high speed It is assumed that they are arranged. In the configuration memory of the third aspect, the portion composed of the first switch and the second switch and the portion composed of the third switch and the fourth switch are the same as the portion composed of the first switch and the second switch in the switch circuit of the second aspect, and the connection configuration of each switch is the same. Therefore, in the fourth aspect of the present invention, by arranging the configuration memory and the switch circuit in a matrix, the operation of the configuration memory and the operation of the switch circuit can be controlled by the same drive circuit. Therefore, compared with the case where the drive circuit of the switch circuit and the drive circuit of the configuration memory are provided separately, the area of the programmable logic device can be reduced This allows the area of ​​the memory device to be kept small. According to one embodiment of the present invention, a logic circuit can be reconfigured at high speed. This allows the area of ​​the memory device to be kept small, and allows high-speed operation. In accordance with another aspect of the present invention, there is provided a programmable logic device. By using a block logic device, miniaturization and high functionality can be achieved. A semiconductor device can be provided.

[0036] According to one aspect of the present invention, a method for controlling connections between logic elements while increasing design freedom is provided. It is therefore possible to provide a programmable logic device that can reduce the number of switches required. According to another aspect of the present invention, a highly reliable programmable logic device is provided. Moreover, according to one embodiment of the present invention, high-speed operation or high reliability can be realized. It is possible to provide a semiconductor device.

[0037] In addition, according to one embodiment of the present invention, even if the circuit scale increases, the layout area can be kept small. In addition, according to one aspect of the present invention, a programmable logic device can be provided. This makes it possible to provide a miniaturized semiconductor device. [Brief description of the drawings]

[0038]

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Mode for Carrying Out the Invention

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0040] Note that the programmable logic device of the present invention includes various semiconductor integrated circuits using semiconductor elements such as microprocessors, image processing circuits , controllers for semiconductor display devices, DSPs (Digital Signal Proc essors), and microcontrollers. Further, the semiconductor device of the present invention includes various devices such as RF tags using the above semiconductor integrated circuits, semiconductor display devices, etc. The semiconductor display devices include liquid crystal display devices , light-emitting devices having light-emitting elements typified by organic light-emitting elements (OLEDs) in each pixel, electronic paper pars, DMDs (Digital Micromirror Device), PDPs (P lasma Display Panel), FEDs (Field Emission Display), etc., and other semiconductor display devices having semiconductor elements in the drive circuit are included in that category.

[0041] ​<Configuration Example of PLD> In the PLD according to one aspect of the present invention, columns having a plurality of LEs (logic elements) are arranged in multiple numbers, and a plurality of wirings and a plurality of switch circuits are arranged between the columns. FIG. 1(A) exemplifies a part of the PLD 100 according to one aspect of the present invention.

[0042] In FIG. 1(A), a first column 102-1 having a plurality of LEs 101, a second column 102-2 having a plurality of LEs 101, and a third column 102-3 having a plurality of LEs 101 are provided in the PL D100. In FIG. 1(A), the first column 1 02-1, the second column 102-2, and the third column 102-3 are arranged in parallel in the order from the left side towards the drawing. This is an example.

[0043] Also, in FIG. 1(A), a plurality of wirings 103, a plurality of wirings 104, a plurality of wirings 105, a plurality of wirings 106, a plurality of wirings 107, a plurality of wirings 108, and a plurality of wirings 109 are provided in the PLD 100.

[0044] The first output terminal of each LE 101 included in the first column 102-1 is connected to any one of the plurality of wirings 103 respectively. The second output terminal of each LE 101 included in the first column 102-1 is connected to any one of the plurality of wirings 104 respectively.

[0045] Also, the first output terminal of each LE 101 included in the second column 102-2 is connected to any one of the plurality of wirings 106 respectively. The second output terminal of each LE 101 included in the second column 102-2 is connected to any one of the plurality of wirings 107 respectively.

[0046] Also, the first output terminal of each LE101 in the third column 102-3 is connected to any one of the plurality of wirings 105. The second output terminal of each LE101 in the third column 102-3 is connected to any one of the plurality of wirings 109. Note that the number of first output terminals and the number of second output terminals of each LE101 are not necessarily one,

[0047] either one of them may be plural, or both may be plural. However, even if the number of first output terminals is plural or the number of second output terminals is plural, only one output terminal must be connected to one wiring. That is, if the number of LE101s in column 102 is Y (Y is a natural number), the PLD100 has at least Y wirings connected to the first output terminals and Y wirings connected to the second output terminals. (Y is a natural number), the PLD100 has at least Y wirings connected to the first output terminals and Y wirings connected to the second output terminals.

[0048] In this specification, "connection" means electrical connection, corresponding to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily mean a directly continuous state, but also includes a state where current, voltage, or potential is indirectly connected through circuit elements such as wirings, resistors, diodes, and transistors so that they can be supplied or transmitted. And the first column 102-1 is arranged between the plurality of wirings 103 and the plurality of wirings 104. The second column 102-2 is arranged between the plurality of wirings 106 and the plurality of wirings 107. The third column 102-3 is arranged between the plurality of wirings 105 and the plurality of wirings 109.

[0049] And the first column 102-1 is arranged between the plurality of wirings 103 and the plurality of wirings 104. The second column 102-2 is arranged between the plurality of wirings 106 and the plurality of wirings 107. The third column 102-3 is arranged between the plurality of wirings 105 and the plurality of wirings 109.

[0050] Further, a plurality of wirings 106 connected to the first output terminals of the respective LEs 101 included in the second column 102-2 are arranged to straddle between the first column 102-1 and the second column 102-2, between the first column 102-1, and a column of LEs 101 (not shown) arranged on the left side of the first column 102-1 toward the drawing of FIG. 1(A). A plurality of wirings 105 connected to the first output terminals of the respective LEs 101 included in the third column 102-3 are arranged to straddle between the first column 102-1 and the second column 102-2, and between the second column 102-2 and the third column 102-3. Further, a plurality of wirings 108 connected to the first output terminals of the respective LEs 101 (not shown) arranged on the right side of the third column 102-3 toward the drawing of FIG. 1(A) are arranged to straddle between the second column 102-2 and the third column 102-3, and between the third column 102-3 and a column of LEs 101 (not shown) arranged on the right side of the third column 102-3. That is, focusing on the Nth column (N is a natural number of 3 or more), a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the above column are arranged to straddle between the Nth column and the (N-1)th column, and between the (N-1)th column and the (N-2)th column. When N is 2, a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the second column are arranged to straddle between the second column and the first column, and between the first column and the I / O element (IO). The above IO has a function as an interface that controls the input of signals from outside the PLD to the LE101 or the output of signals from the LE101 to outside the PLD. Note that the positional relationship between the column 102 having the LE101 shown in FIG. 1(A) and the plurality of various wirings is

[0051] That is, focusing on the Nth column (N is a natural number of 3 or more), a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the above column are arranged to straddle between the Nth column and the (N-1)th column, and between the (N-1)th column and the (N-2)th column. When N is 2, a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the second column are arranged to straddle between the second column and the first column, and between the first column and the I / O element (IO). The above IO has a function as an interface that controls the input of signals from outside the PLD to the LE101 or the output of signals from the LE101 to outside the PLD. That is, when focusing on the Nth column (N is a natural number of 3 or more), a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the above column are arranged to straddle between the Nth column and the (N-1)th column, and between the (N-1)th column and the (N-2)th column. When N is 2, a plurality of wirings connected to the first output terminals of the respective LEs 101 included in the second column are arranged to straddle between the second column and the first column, and between the first column and the I / O element (IO). The above IO has a function as an interface that controls the input of signals from outside the PLD to the LE101 or the output of signals from the LE101 to outside the PLD. Note that the positional relationship between the column 102 having the LE101 shown in FIG. 1(A) and the plurality of various wirings

[0052] Note that the positional relationship between the column 102 having the LE101 shown in FIG. 1(A) and the plurality of various wirings , in one aspect of the present invention, it corresponds to an example. In one aspect of the present invention, as long as the column 102 having LE101 and a plurality of various wirings are arranged in parallel. That's all that is required.

[0053] Also, in one aspect of the present invention, focusing on the (N - 1)-th column (N is a natural number of 3 or more), a plurality of wirings connected to the first output terminals of each LE101 included in the above-described column, a plurality of wirings connected to the first output terminals of each LE101 included in the N-th column, and a plurality of wirings connected to the second output terminals of each LE101 included in the (N - 2)-th column are connected to the plurality of input terminals of each LE101 included in the (N - 1)-th column via the switch circuit 110.

[0054] Specifically, in the case of FIG. 1(A), for example, a plurality of wirings 106 connected to the first output terminals of each LE101 included in the second column 102-2, a plurality of wirings 105 connected to the first output terminals of each LE101 included in the third column 102-3, and a plurality of wirings 104 connected to the second output terminals of each LE101 included in the first column 102-1 are connected to the plurality of input terminals of each LE101 included in the second column 102-2 via the switch circuit 110.

[0055] In FIG. 1(B), the circuit diagram of the switch circuit 110 that controls the connection between the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 1(A) and the plurality of input terminals of each LE101 included in the second column 102-2 is extracted and shown. In FIG. 1(B), the plurality of wirings 111 are respectively connected to the plurality of input terminals of one LE101 included in the second column 102-2. And the switch circuit 110 has a plurality of switch circuits 120. FIG. 1(C) shows a more specific configuration example of the switch circuit 110 shown in FIG. 1(B). ​​​​​​​​​​​​​ 。As shown in FIG. 1(B), the switch circuit 110, as shown in FIG. 1(C), is composed of three switch circuits 120, namely, switch circuit 1 20-1, switch circuit 120-2, and switch circuit 120-3. It has three switch circuits 120.

[0056] Note that in FIG. 1(C), the switch circuit 110 corresponding to the three wirings 111 is exemplified, so the case where the switch circuit 110 has three switch circuits 120, namely, switch circuit 120-1, switch circuit 120-2, and switch circuit 120-3, is illustrated. The number of switch circuits 120 in the switch circuit 110 can be determined according to the number of a plurality of input terminals of the LE101.

[0057] Also, in FIGS. 1(B) and 1(C), the switch circuit 110 that controls the connection between the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 and the plurality of wirings 111 is illustrated. However, the switch circuit 1 10 that controls the connection between the plurality of wirings in FIG. 1(A) shall have a similar configuration.

[0058] Next, a more specific configuration example of the switch circuit 110 shown in FIG. 1(C) is shown in FIG. 2. In FIG. 2, the connection relationship between the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 and the switch circuit 110 is shown more clearly. As shown in FIG. 2, each switch circuit 120 controls the connection between all of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 and one of the plurality of wirings 111. Specifically, in FIG. 2, the plurality of wirings 104 includes wiring 104-1, wiring 104-2, wiring 10

[0059] 4-3, etc. ​It has 4 - 3, and a plurality of wirings 105 include wiring 105 - 1, wiring 105 - 2, and wiring 105 - 3 It has, and a plurality of wirings 106 include wiring 106 - 1, wiring 106 - 2, and wiring 106 - 3 is illustrated. Also, in FIG. 2, a case where a plurality of wirings 111 include wiring 111 - 1, wiring 1 11 - 2, and wiring 111 - 3 is illustrated.

[0060] And, in FIG. 2, the switch circuit 120 - 1 controls the connection between all of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106, and wiring 111 - 1. Specifically, the switch circuit 120 - 1 selects one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 according to configuration data, and has a function of connecting the selected one of the wirings and wiring 111 - 1.

[0061] Also, the switch circuit 120 - 2 controls the connection between all of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 and wiring 111 - 2. Specifically, the switch circuit 120 - 2 selects one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 according to configuration data, and has a function of connecting the selected one of the wirings and wiring 111 - 2.

[0062] Also, the switch circuit 120 - 3 controls the connection between all of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 and wiring 111 - 3. Specifically, the switch circuit 120 - 3 selects one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 according to configuration data, and has a function of connecting the selected one of the wirings and wiring 111 - 3. ​​​​​

[0063] <Example of switch circuit configuration> Next, a configuration example of the switch circuit 120 will be described. The configuration of the switch circuit 120 is illustrated. The switch circuit 120 includes a switch 131 and a In FIG. 3, each of the above-mentioned groups is represented by a cell 14. 3, the switch circuit 120 is illustrated as cell 140-1 through cell 140- 1 illustrates a case in which there are a plurality of cells 140, indicated by n (n is a natural number).

[0064] The switch 131 transmits a packet including configuration data to the node FD in the cell 140. Specifically, when the switch 131 is in a conducting state, When the signal is ON, a signal including configuration data is applied to the wiring 121. The potential of the switch 131 is supplied to the node FD. When this occurs, the potential of the node FD is maintained.

[0065] The selection of the conductive or non-conductive state of the switch 131 is determined by a signal provided to the wiring 122. In FIG. 3, the switching is performed in the cells 140-1 to 140-n. The selection of the conductive state or non-conductive state of the switch 131 is performed by the wiring 122-1 to the wiring 122-n The case where the signal is applied to each of the wirings 122 is represented by the potential of the signal Illustrated here.

[0066] The switch 130 electrically connects the wiring 123 and the wiring 111 in accordance with the potential of the node FD. Specifically, when the switch 130 is in a conductive state, the wiring 12 3 is electrically connected to the wiring 111. Also, when the switch 130 is in a non-conductive state , the wiring 123 and the wiring 111 are in an electrically separated state. In FIG. 3, in the cells 140-1 to 140-n, the case where the switch 130 controls the electrical connection between the plurality of wirings 123 shown by the wirings 123-1 to 123-n and the wiring 111 respectively is illustrated.

[0067] Note that the wiring 123 is electrically connected to the output terminals of the LE or IO, and the wiring 111 is electrically connected to the input terminals of the LE or IO. Therefore, according to the configuration data , in at least one of the cells 140-1 to 140-n, when the switch 13 0 becomes conductive, at least one of the plurality of wirings 1 23 shown by the wirings 123-1 to 123-n, that is, at least one of the output terminals of the LE or IO is selected by the switch circuit 120, and the selected output terminal is electrically connected to the wiring 111, that is, the input terminal of the LE or IO.

[0068] Note that in this specification, the input terminal means a node such as a wiring to which an input signal is applied, and the potential, voltage, current, etc. of the input signal are applied to the circuit through the node. Therefore, the wiring electrically connected to the input terminal can also be regarded as a part of the input terminal. Also , in this specification, the output terminal means a node such as a wiring to which an output signal is applied, and the potential, voltage, current, etc. of the output signal are output from the circuit through the node. Therefore, the wiring electrically connected to the output terminal can also be regarded as a part of the output terminal.

[0069] Furthermore, in the PLD100 according to one aspect of the present invention, a switch 126 for controlling the electrical connection between the wiring 111 and the wiring 125 to which a predetermined potential is applied is provided. The switch 126 performs switching according to the signal INIT. Specifically, when the switch 126 is in the conductive state, the potential of the wiring 125 is applied to the wiring 111, and when the switch 126 is in the non-conductive state , the potential of the wiring 125 is not applied to the wiring 111. When the switch 126 is in the conductive state, the potential of the wiring 125 is applied to the wiring 111, and when the switch 126 is in the non-conductive state , the potential of the wiring 125 is not applied to the wiring 111.

[0070] In one aspect of the present invention, by setting the switch 126 to the conductive state, the potential of the wiring 111 can be initialized to a predetermined height. Note that the potentials of the wiring 111 and the wiring 123 are likely to become indeterminate after the power supply of the PLD100 is turned off. Also, after the power supply of the PLD is turned off, depending on the configuration of the storage element included in the configuration memory, the configuration data may be lost. In this case, when the power is turned on to the PLD, the wiring 111 and the plurality of wirings 123 become conductive through the switch circuit 120, and when the potential of the wiring 11 1 and the plurality of wirings 123 are different, a large amount of current may flow through these wirings. However, in one aspect of the present invention, as described above, the potential of the wiring 111 can be initialized, so that it is possible to prevent a large amount of current from flowing between the wiring 111 and the plurality of wirings 123. Thereby, it is possible to prevent the PLD from being damaged. When the potential of the wiring 111 and the plurality of wirings 123 are different, a large amount of current may flow through these wirings. However, in one aspect of the present invention, as described above, the potential of the wiring 111 can be initialized, so that it is possible to prevent a large amount of current from flowing between the wiring 111 and the plurality of wirings 123. Thereby, it is possible to prevent the PLD from being damaged. Thereby, it is possible to prevent the PLD from being damaged.

[0071] Also, immediately after the power is turned on to the PLD100, the input terminal of the LE101 may become an intermediate potential between the high level and the low level. When the intermediate potential is applied to the input terminal of the LE101, a through current is likely to occur in the CMOS circuit included in the LE101. However, when the intermediate potential is applied to the input terminal of the LE101, a through current is likely to occur in the CMOS circuit included in the LE101. However, In one embodiment of the present invention, the potential of the wiring 111 can be initialized as described above. Therefore, it is necessary to prevent the input terminal of LE101 from becoming an intermediate potential immediately after the power is turned on. Therefore, the occurrence of the shoot-through current can be prevented.

[0072] Furthermore, in the PLD 100 according to one embodiment of the present invention, when the power is applied to the PLD 100 and the wiring After initializing the potential of 111, all the cells 140 in the switch circuit 120 are switched The configuration data that causes the switch 130 to be in a non-conducting state is With the above configuration, the wiring 111 and the plurality of wirings Since the wiring 111 and the multiple wirings 123 can be electrically separated, When the potentials are different, a large amount of current flows through these wirings via the switch circuit 120. This can prevent damage to the PLD100. can.

[0073] The switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-1 shown in FIG. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 corresponds to the wiring 123-1 to wiring 123-n shown in FIG. This corresponds to the wiring 111 shown in FIG.

[0074] In addition, the switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-2 shown in FIG. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 corresponds to the wiring 123-1 to wiring 123-n shown in FIG. This corresponds to the wiring 111 shown in FIG.

[0075] Also, the switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-3 shown in FIG. 2. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 correspond to the wirings 123-1 to 123-n shown in FIG. 3, and the wiring 111-3 shown in FIG. 2 corresponds to the wiring 111 shown in FIG. 3. corresponds to the wiring 111 shown in FIG. 3.

[0076] As described above, in one aspect of the present invention, among a plurality of wirings such as the wiring 104, the wiring 105, and the wiring 106 electrically connected to the output terminal of the LE101, one wiring is selected according to the configuration data, and the selected one wiring and one wiring such as the wiring 111 electrically connected to the input terminal of the LE101 are electrically connected by the switch circuit 120. And, in one aspect of the present invention, the switch circuit 110 including the switch circuit 120 having the above configuration and the various wirings whose electrical connection is controlled by the switch circuit 110 are provided between columns including the LE101 such as the first column 102-1, the second column 102-2, and the third column 102-3. Thus, in the PLD100 shown in FIG. 1(A), the electrical connection between one LE101 included in the second column 102-2 and another LE101 included in the second column 102-2 can be controlled by one switch circuit 120. Also, the electrical connection between one LE101 included in the first column 102-1 and one LE101 included in the second column 102-2 can be controlled by one switch circuit 120. Also, the electrical connection between one LE101 included in the second column 102-2 and one LE101 included in the third column 102-3 can be controlled by one switch circuit 120. Therefore, in one aspect of the present invention ​​​​​​​​​​​​​​, while increasing the design freedom in the PLD100, the number of switch circuits included in the wiring resources can be suppressed.

[0077] 〈Specific Configuration Example 1 of Switch Circuit〉 Next, a specific configuration example of the switch circuit 120 shown in FIG. 3 will be described. In FIG. 4, a circuit configuration of the switch circuit 120 is shown as an example. The switch circuit 120 includes a transistor 130t that controls the electrical connection between wirings or terminals and a plurality of sets of transistors 131t with extremely small off - currents for supplying, holding, and discharging a determined amount of charge at the gate of the transistor 130t. In FIG. 4, each of the above - mentioned sets is illustrated as a cell 140. The switch circuit 120 shown in FIG. 4

[0078] is provided with cells 140 corresponding to a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106, respectively. In FIG. 2, since the total number of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is exemplified as 9, in FIG. 4, in accordance with the configuration of FIG. 2, the switch circuit 120 has 9 cells 140 consisting of cells 140 - 1 to 140 - 9, and a case where there are 9 wirings 123 (wirings 123 - 1 to 123 - 9) corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is exemplified.

[0079] And each cell 140 has, in addition to the transistor 130t and the transistor 131t, a capacitive element 132 connected to the gate of the transistor 130t. Note that the capacitive element 132

[0079] has a function of holding the charge accumulated at the gate of the transistor 130t, and in addition to that, the transistor ​​While keeping the gate of the transistor 130t in a floating state, the change in the potential of the wiring 127 is It has the function of adding to the potential of the gate of 130t.

[0080] Specifically, one of the source and drain of the transistor 130t is connected to the wiring 111. The other is connected to one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106. The transistor 131t is connected to a wiring 123 corresponding to the wiring 123. One of the source and drain is connected to the gate of the transistor 130t, and the other is connected to the wiring 1 21. The gate of the transistor 131t is connected to a plurality of wirings 122 (wirings 12 The pair of electrodes of the capacitor 132 are connected to one of the wirings 122-1 to 122-9. One of the electrodes is connected to one of the wirings 127 (127-1 to 127-9). and the other end is connected to the gate of transistor 130t.

[0081] The source of a transistor is a source region that is a part of a semiconductor film that functions as an active layer. The term "transistor" refers to a transistor region, or a source electrode electrically connected to the semiconductor film. The drain of a transistor is a drain region that is a part of a semiconductor film that functions as an active layer, or The term "gate" refers to a gate electrode electrically connected to the semiconductor film. means.

[0082] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics of each terminal. The name is changed depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. It is called a drain. Also, in a p-channel transistor, the terminal to which a low potential is applied is called a drain, and the terminal to which a high potential is applied is called a source. In this specification, for convenience, assuming that the source and the drain are fixed, the connection relationship of the transistor may be described. However, in reality, the names of the source and the drain are interchanged according to the above potential relationship.

[0083] Cell 140 may further have other circuit elements such as transistors, diodes, resistive elements, capacitive elements, and inductors, as necessary.

[0084] Next, an example of the operation of the switch circuit 120 shown in FIG. 4 will be described using the timing chart shown in FIG. 5. However, in the timing chart shown in FIG. 5, the case where the transistors 130t and 131t are n-channel type is illustrated.

[0085] First, the first writing of the configuration data performed at times T1 to T6 will be described. At times T1 to T6, it is assumed that the ground potential GND is applied to the wiring 127.

[0086] At times T1 to T2, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-1, and a low-level potential VSS lower than the ground potential GND is applied to the other wirings 122. Also, the potential VSS is applied to the wiring 121. By the above operation, the potential VSS is applied to the gate (FD1) of the transistor 130t included in the cell 140-1. Therefore, the cell 140-1 corresponds to a digital value of "0". ​The configured data is stored.

[0087] At time T3 to time T4, among the plurality of wirings 122, a high level potential VDD is applied to the wiring 122-2, and a low level potential VSS is applied to the other wirings 122. Also, a high level potential VDD is applied to the wiring 121. By the above operation, a potential VDD is applied to the gate (FD2) of the transistor 130t included in the cell 140-2. Therefore, in the cell 1 40-2, the configured data corresponding to the digital value of "1" is stored .

[0088] At time T5 to time T6, among the plurality of wirings 122, a high level potential VDD is applied to the wiring 122-3, and a low level potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, a potential VSS is applied to the gate (FD3) of the transistor 1 30t included in the cell 140-3. Therefore, in the cell 140-3 , the configured data corresponding to the digital value of "0" is stored.

[0089] Note that in the timing chart shown in FIG. 5, only the first writing of the configured data to the cells 140-1 to 140-3 is shown, but the first writing of the configured data to the cells 140-4 to 140-9 is also performed in the same manner . However, among the cells 140-1 to 140-9, only one cell 140 in which the configured data corresponding to the digital value of "1" is stored by the first writing . is.

[0090] Next, the configuration data stored in the cell 140 by the first write is The switching of the first logic circuit that is performed in accordance with this will now be described.

[0091] At times T7 and T8, a high-level potential VDD is applied to the wiring 127. Between time T7 and time T8, in cell 140-1, transistor 130t is in a non-conducting state. In cell 140-2, transistor 130t is in a conducting state, and in cell 140-3, transistor Therefore, the wiring 123-2 and the wiring 111 are in a conductive state. Thus, the potential of the wiring 123-2 is applied to the wiring 111. Specifically, in the timing shown in FIG. In the chart, the case where the potential VDD is applied to the wiring 111 is illustrated.

[0092] Next, the first processing of the configuration data is performed from time T8 to time T13. The writing of 2 will be described. Between time T8 and time T13, the wiring 127 is connected to the ground. It is assumed that the potential GND is applied.

[0093] Between time T8 and time T9, a high level is applied to the wiring 122-1 of the multiple wirings 122. A potential VDD is applied to the line 121, and a low-level potential VSS is applied to the other line 122. A high-level potential VDD is applied to the cell 121. By the above operation, the transistor of the cell 140-1 The gate (FD1) of the transistor 130t is supplied with a potential VDD. 40-1 stores the configuration data corresponding to the digital value of "1". do.

[0094] Between time T10 and time T11, a high level is applied to the wiring 122-2 among the multiple wirings 122. Apply the potential VDD of the bell to one wire 122, and apply the low-level potential VSS to the other wires 122. Also, Apply the potential VSS to the wire 121. By the above operation, the transistor 130t of the cell 140-2 has its gate (FD2) supplied with the potential VSS. Therefore, the cell 140-2 stores the configuration data corresponding to the digital value "0".

[0095] At times T12 to T13, among the plurality of wires 122, the wire 122-3 is supplied with the high-level potential VDD of the bell, and the other wires 122 are supplied with the low-level potential VSS. Also, Apply the potential VSS to the wire 121. By the above operation, the transistor 130t of the cell 140-3 has its gate (FD3) supplied with the potential VSS. Therefore, the cell 140-3 stores the configuration data corresponding to the digital value "0".

[0096] Note that in the timing chart shown in FIG. 5, only the second writing of the configuration data to the cells 140-1 to 140-3 is shown, but the second writing of the configuration data to the cells 140-4 to 140-9 is also performed in the same manner. However, among the cells 140-1 to 140-9, only one cell 140 stores the configuration data corresponding to the digital value "1" by the second writing.

[0097] Next, the switching of the second logic circuit, which is accordingly performed based on the configuration data stored in the cell 140 by the second writing, will be described.

[0098] At times T14 to T15, the high-level potential VDD is applied to the wire 127.​​​​ At time T14 to time T15, in cell 140-1, transistor 130t is conducting state, in cell 140-2, transistor 130t is non-conducting state, in cell 140-3, the transistor 130t is in a non-conducting state. Therefore, wiring 123-1 and wiring 111 become conducting state, and the potential of wiring 123-1 is applied to wiring 111. Specifically, in the timing chart shown in FIG. 5, the case where the ground potential GND is applied to wiring 111 is exemplified.

[0099] Note that when writing the configuration data, it is desirable to keep the potentials of wiring 123-1 to wiring 123 -9 and the potential of wiring 111 at the same height. With the above configuration , even if transistor 130t becomes conducting during the writing of the configuration data, it is possible to prevent an excessive current from flowing between any one of wiring 123-1 to wiring 123-9 and wiring 111 through transistor 130t.

[0100] Also, the potential of wiring 111 is preferably held at a predetermined height by a latch circuit or the like. With the above configuration, it is possible to prevent the potential of wiring 111 from becoming a floating state, and it is possible to prevent an excessive current from occurring in LE where the potential of wiring 111 is applied to the input terminal.

[0101] As described above, according to the configuration data, when any one of the plurality of cells 140 included in the switch circuit 120 becomes conducting, the connection structure between one of the plurality of wirings 123 and wiring 111 is determined through the switch circuit 120.

[0102] ​​In one aspect of the present invention, with the above configuration, in the PLD 100 shown in FIG. 1(A), a first LE 101 included in the second column 102-2 and another LE 1 01 can be controlled by a single switch circuit 120 for electrical connection. Also, a first LE 101 included in the first column 102-1 and a LE 101 included in the second column 102-2 can be controlled by a single switch circuit 120 for electrical connection. Further, the electrical connection between a LE 101 included in the second column 102-2 and a LE 101 included in the third column 102-3 can be controlled by a single switch circuit 120. Therefore, in one aspect of the present invention, while increasing the design freedom in the PLD 100, the number of switch circuits included in the wiring resources can be suppressed.

[0103] Note that the transistor 131t with extremely low off-current has a channel formation region formed in a semiconductor film having a wider bandgap than silicon and a lower intrinsic carrier density than silicon. Such a semiconductor includes, for example, an oxide semiconductor, silicon carbide, gallium nitride, etc., having a bandgap more than twice that of silicon. The transistor having such a semiconductor can make the off-current extremely small compared to a transistor formed of a semiconductor such as ordinary silicon or germanium. Therefore, by using the transistor 131t having the above configuration, the charge held at the gate of the transistor 130t that controls the electrical connection between wirings or terminals can be prevented from leaking.

[0104] In the switch circuit 120 having the above configuration, according to the configuration data, the distribution The conduction state of the transistor 130t that controls the electrical connection between the lines or terminals is determined and the conduction state is maintained by the transistor 131t with a significantly small off-current. Therefore, in one aspect of the present invention, the switch circuit 110 has both a function as a configuration memory and a function as a memory element, and the number of elements in each cell 140 is smaller than that of SRAM. Therefore, the area of the storage device for storing the configuration data can be suppressed to be smaller than that of the conventional PLD having both a configuration memory and a memory element. 0 is smaller than that of SRAM. Therefore, the area of the storage device for storing the configuration data can be suppressed to be smaller than that of the conventional PLD having both a configuration memory and a memory element. memory element, and the area of the storage device for storing the configuration data can be suppressed to be smaller than that of the conventional PLD having both a configuration memory and a memory element. can be suppressed to be small.

[0105] In addition, since the off-current of the transistor 131t is smaller than that of a transistor having a channel formation region in a silicon film, the data holding time in the switch circuit 110 can be made longer than that of DRAM. Therefore, the frequency of rewriting data can be reduced, and thus the power consumption can be suppressed to be small. In addition, since the off-current of the transistor 131t is smaller than that of a transistor having a channel formation region in a silicon film, the data holding time in the switch circuit 110 can be made longer than that of DRAM. Therefore, the frequency of rewriting data can be reduced, and thus the power consumption can be suppressed to be small. can be made longer than that of DRAM. Therefore, the frequency of rewriting data can be reduced, and thus the power consumption can be suppressed to be small. can be suppressed to be small.

[0106] <Specific Configuration Example 2 of Switch Circuit> Next, a specific configuration example of the switch circuit 120 shown in FIG. 3 will be described. The switch circuit 120 shown in FIG. 6 has a plurality of cells 140 each having a transistor 131t that functions as a switch 131, a transistor 130t that functions as a switch 130, and a capacitive element 132 electrically connected to the gate of the transistor 130t. Specifically, in FIG. 6 the case where the switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n is illustrated. has a plurality of cells 140 each having a transistor 131t that functions as a switch 131, a transistor 130t that functions as a switch 130, and a capacitive element 132 electrically connected to the gate of the transistor 130t. Specifically, in FIG. 6 illustrates the case where the switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n. illustrates the case where the switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n.

[0107] Specifically, for transistor 131t, its gate is electrically connected to wiring 122. . Also, one of the source and drain of transistor 131t is electrically connected to wiring 121 and the other is electrically connected to the gate of transistor 130t. One of the source and drain of transistor 130t is electrically connected to wiring 123 and the other is electrically connected to wiring 1 11.

[0108] One of the pair of electrodes of capacitor element 132 is electrically connected to the gate of transistor 130t and the other is electrically connected to one of the plurality of wirings 127 indicated by wirings 127-1 to 127-n 7. In addition to the function of holding the charge stored in node FD, capacitor element 132 has a function of adding the change in the potential of wiring 127 to the potential of node FD while keeping node FD in a floating state.

[0109] Cell 140 may further include other circuit elements such as transistors, diodes, resistive elements, capacitor elements, and inductors, if necessary.

[0110] <Example of operation of the switch circuit> Next, an example of the operation of switch circuit 120 shown in FIG. 6 will be described with reference to the timing chart shown in FIG. 7. However, in the timing chart shown in FIG. 7, the case where transistors 131t and 130t are n-channel type is illustrated. However, it is assumed that a low-level potential VSS lower than the ground potential GND is applied to wiring 125.

[0111] First, after power is applied to the PLD, at times T1 to T8, wiring 111 The initialization of the potential and the initialization of the potential of node FD will be described.

[0112] Before time T1, since the power has just been turned on for the PLD, among the plurality of wirings 123 and the wiring 111 is in an indeterminate state, and the potential of node FD of each cell 140 is also assumed to be in an indeterminate state. Note that in FIG. 7, the period during which the potential is in an indeterminate state is indicated by hatching.

[0113] At times T1 to T8, the potential of the signal INIT input to the gate of transistor 126t T becomes high level, and transistor 126t becomes conductive. Therefore, through transistor 126t, potential VSS is applied to wiring 111. Note that by setting the potential of signal INIT to high level simultaneously with turning on the power of the PLD, the period during which the potential of wiring 111 becomes indeterminate can be further shortened. In one aspect of the present invention, by applying potential VSS to wiring 111, the potential of wiring 111 can be initialized, so that the input terminals of the LEs do not become indeterminate, and in the CMOS circuits of the LEs, through-current can be prevented . Thereby, it is possible to prevent the PLD from being damaged. Also, at times T1 to T8, by applying ground potential GND to wiring 127, conduction between wiring 123 and wiring 111 can be prevented, and even if the potentials of wiring 123 and wiring 111 are different, a large amount of current flowing between wiring 1 23 and wiring 111 can be suppressed. And at times T1 to T8, while potential VSS is applied to wiring 111, the potential of node FD of all cells 140 is initialized. Specifically, in FIG. 7, first, at times T2

[0114] to T3, among the plurality of wirings 122, ground potential G is applied to wiring 122-1. And at times T1 to T8, while potential VSS is applied to wiring 111, the potential of node FD of all cells 140 is initialized. Specifically, in FIG. 7, first, at times T2 to T3, among the plurality of wirings 122, ground potential G is applied to wiring 122-1. A high-level potential VDD higher than ND is applied, and a potential VSS is applied to the other wiring 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140 -1, since a potential VSS is applied to the node FD1, the transistor 130t is non-conductive and becomes the off state.

[0115] Next, at times T4 to T5, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-2, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-2, since a potential VSS is applied to the node FD2, the transistor 130 t is non-conductive and becomes the off state. Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130 t is non-conductive and becomes the off state. Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130

[0116] Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130 t is non-conductive and becomes the off state. Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130 t is non-conductive and becomes the off state. Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130

[0117] Note that in the timing chart shown in FIG. 7, only the initialization of the potential of the node FD in the cells 140-1 to 140-3 is shown, but the initialization of the potential of the node FD in the cells 140-4 to 140- n is also performed in the same manner. By the above series of operations, in all the cells 140, the potential of the node FD is initialized, and the transistor 130t becomes non-conductive and becomes the off state. Next, at times T6 to T7, among the plurality of wirings 122, a high-level potential VDD higher than the ground potential GND is applied to the wiring 122-3, and a potential VSS is applied to the other wirings 122. Also, a potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, since a potential VSS is applied to the node FD3, the transistor 130

[0118] Next, at time T8, the potential of signal INIT becomes low level, and transistor 12 6t becomes non-conductive.

[0119] Next, the writing of configuration data performed at times T9 to T15 will be described. At times T9 to T15, it is assumed that ground potential GND is applied to wiring 127. Also, at times T9 to T15, the potential of signal INIT remains at a low level, and transistor 126t remains non-conductive. T First, at times T9 to T10, among the plurality of wirings 122, a high-level potential VDD is applied to wiring 122-1, and a low-level potential VSS is applied to the other wirings 122. Also, a high-level potential VDD is applied to wiring 121. By the above operation, in cell

[0120] 140-1, potential VDD is applied to node FD1. That is, it can be said that cell 140-1 is in a state where configuration data corresponding to the digital value "1" is stored.

[0121] Next, at times T11 to T12, among the plurality of wirings 122, a high-level potential VDD is applied to wiring 122-2

[0121] Next, at times T11 to T12, among the plurality of wirings 122, a high-level potential VDD is applied to wiring 122-2 and a low-level potential VSS is applied to the other wirings 122. Also, a low-level potential VSS is applied to wiring 121. By the above operation, in cell 140-2, potential VSS is applied to node FD2. That is, it can be said that cell 140- 2 is in a state where configuration data corresponding to the digital value "0" is stored.

[0122]

[0122] Next, at times T13 to T14, among the plurality of wirings 122, wiring 122-3 A high-level potential VDD is applied to it, and a low-level potential VSS is applied to the other wiring 122. Also, a low-level potential VSS is applied to the wiring 121. By the above operation, in the cell 140-3, a potential VSS is applied to the node FD3. That is, the cell 140- 3 can be said to be in a state where configuration data corresponding to a digital value of "0" is stored. It can be said so.

[0123] Note that in the timing chart shown in FIG. 7, only the writing of the configuration data to the cells 140-1 to 140-3 is shown, but the writing of the configuration data to the cells 140-4 to 140- n is also performed in the same manner. However, among the cells 140-1 to 140-n, only one cell 140 stores configuration data corresponding to a digital value of "1" by writing.

[0124] Next, the switching of the logic circuit performed according to the configuration data stored in the cell 140 by writing will be described.

[0125] At times T15 to T16, a high-level potential VDD is applied to the wiring 127, and the potential difference between the ground potential GND and the potential VDD is added to the node FD of each cell 140. Thus, at times T9 to T15, only in the cell 140 in which configuration data corresponding to a digital value of "1" is stored, the potential of the node FD becomes high enough, and the transistor 130t becomes conductive. Specifically, in the case of the timing chart shown in FIG. 7, at times T9 to T15, in the cell 140-1, corresponding to a digital value of "1". ​​​​​Since the configuration data is stored, the transistor 130t that controls the electrical connection between the wiring 123-1 and the wiring 111 becomes conductive, and the potential of the wiring 123-1 is applied to the wiring 111 via the transistor 130t. As described above, according to the configuration data, when any one of the plurality of cells 140 included in the switch circuit 120 becomes conductive, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined via the switch circuit 120.

[0126] As described above, according to the configuration data, when any one of the plurality of cells 140 included in the switch circuit 120 becomes conductive, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined via the switch circuit 120. As described above, according to the configuration data, when any one of the plurality of cells 140 included in the switch circuit 120 becomes conductive, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined via the switch circuit 120. As described above, according to the configuration data, when any one of the plurality of cells 140 included in the switch circuit 120 becomes conductive, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined via the switch circuit 120.

[0127] In FIG. 7, the case where the potential of the node FD is initialized in order for each cell 140 is illustrated, but the potential of the node FD may be initialized all at once in all the cells 140. In FIG. 7, the case where the potential of the node FD is initialized in order for each cell 140 is illustrated, but the potential of the node FD may be initialized all at once in all the cells 140.

[0128] <Specific Configuration Example 3 of Switch Circuit> Next, another specific configuration example different from FIG. 4 of the switch circuit 120 shown in FIG. 3 will be described. Next, another specific configuration example different from FIG. 4 of the switch circuit 120 shown in FIG. 3 will be described.

[0129] FIG. 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 includes a plurality of sets of a transistor 130t that controls the electrical connection between wirings or terminals, a transistor 131t with an extremely small off-current for supplying, holding, and discharging an amount of electric charge determined by configuration data at the gate of the transistor 130t, and a transistor 133t connected in series to the transistor 130t. FIG. 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 includes a plurality of sets of a transistor 130t that controls the electrical connection between wirings or terminals, a transistor 131t with an extremely small off-current for supplying, holding, and discharging an amount of electric charge determined by configuration data at the gate of the transistor 130t, and a transistor 133t connected in series to the transistor 130t. FIG. 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 includes a plurality of sets of a transistor 130t that controls the electrical connection between wirings or terminals, a transistor 131t with an extremely small off-current for supplying, holding, and discharging an amount of electric charge determined by configuration data at the gate of the transistor 130t, and a transistor 133t connected in series to the transistor 130t. FIG. 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 includes a plurality of sets of a transistor 130t that controls the electrical connection between wirings or terminals, a transistor 131t with an extremely small off-current for supplying, holding, and discharging an amount of electric charge determined by configuration data at the gate of the transistor 130t, and a transistor 133t connected in series to the transistor 130t. FIG. 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 includes a plurality of sets of a transistor 130t that controls the electrical connection between wirings or terminals, a transistor 131t with an extremely small off-current for supplying, holding, and discharging an amount of electric charge determined by configuration data at the gate of the transistor 130t, and a transistor 133t connected in series to the transistor 130t.

[0130] In this specification, the state where transistors are connected in series means that, for example, only one of the source or drain of the first transistor is connected to the source or drain of the second transistor. In this specification, the state where transistors are connected in series means that, for example, only one of the source or drain of the first transistor is connected to the source or drain of the second transistor. ​means a state where it is connected to only one of the drains. Also, the state where the transistors are connected in parallel means that one of the source or drain of the first transistor is connected to one of the source or drain of the second transistor, and the other of the source or drain of the first transistor is connected to the other of the source or drain of the second transistor. In FIG. 8, each of the above groups is illustrated as cell 140. The switch circuit 120 shown in FIG. 8 is provided with cells 140 corresponding to a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106, respectively. Note that in FIG. 2, since the case where the total number of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is 9 is illustrated, in FIG. 8, in accordance with the configuration of FIG. 2, the switch circuit 120 has 9 cells 140 composed of cells 140-1 to 140-9, and the case where there are 9 wirings 123 corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is illustrated. Specifically, one of the source and drain of transistor 133t is connected to wiring 111, and the other is connected to one of the source and drain of transistor 130t. The other of the source and drain of transistor 130t is connected to one of the plurality of wirings 123 (wirings 123-1 to 123-9). One of the source and drain of transistor 131t is connected to the gate of transistor 130t, and the other is connected to wiring 121. The gate of transistor 131t is connected to one of the plurality of wirings 122 (wirings 122-1 to wirings 122-9).

[0131]

[0132] ​​​​​​​​​​​​​​​​The gate is connected to one of the plurality of wirings 128 (wirings 128-1 to 128-9). It is.

[0133] Cell 140 may further have other circuit elements such as transistors, diodes, resistive elements, capacitive elements, and inductors as necessary. It may further have.

[0134] The operation of the switch circuit 120 shown in FIG. 8 can be referred to the timing chart shown in FIG. 5. However, in the timing chart shown in FIG. 5, it corresponds to the case where the transistors 130t, 131t, and 133t are n-channel type. However, in the timing chart shown in FIG. 5, it corresponds to the case where the transistors 130t, 131t, and 133t are n-channel type. It corresponds to the case where the transistors 130t, 131t, and 133t are n-channel type.

[0135] 〈Specific configuration example 4 of the switch circuit〉 Next, a configuration example different from FIG. 6 of the switch circuit 120 shown in FIG. 3 will be described. The switch circuit 120 shown in FIG. 9 has a plurality of cells 140 having a transistor 131t, a transistor 130t, and a transistor 133t. Specifically, in FIG. 9, the case where the switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n is illustrated. The switch circuit 120 has a plurality of cells 140 having a transistor 131t, a transistor 130t, and a transistor 133t. Specifically, in FIG. 9, the case where the switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n is illustrated. The switch circuit 120 has n cells 140 indicated by cells 140-1 to 140-n. The case is illustrated.

[0136] The transistor 131t has a function of controlling the supply of the potential of the signal including the configuration data to the node FD. The transistor 130t has its conduction state or non-conduction state selected according to the potential of the node FD. The transistor 133t has its conduction state or non-conduction state selected according to the potential of the wiring 128. And the transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111. The transistor 131t has a function of controlling the supply of the potential of the signal including the configuration data to the node FD. The transistor 130t has its conduction state or non-conduction state selected according to the potential of the node FD. The transistor 133t has its conduction state or non-conduction state selected according to the potential of the wiring 128. And the transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111. The transistor 131t has a function of controlling the supply of the potential of the signal including the configuration data to the node FD. The transistor 130t has its conduction state or non-conduction state selected according to the potential of the node FD. The transistor 133t has its conduction state or non-conduction state selected according to the potential of the wiring 128. And the transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111. The transistor 131t has a function of controlling the supply of the potential of the signal including the configuration data to the node FD. The transistor 130t has its conduction state or non-conduction state selected according to the potential of the node FD. The transistor 133t has its conduction state or non-conduction state selected according to the potential of the wiring 128. And the transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111. The transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111. The transistor 130t and the transistor 133t are connected in series and both have a function of controlling the electrical connection between the wiring 123 and the wiring 111.

[0137] Specifically, for transistor 131t, its gate is electrically connected to wiring 122. . Also, one of the source and drain of transistor 131t is electrically connected to wiring 121, and the other is electrically connected to the gate of transistor 130t. One of the source and drain of transistor 130t is electrically connected to wiring 123, and the other is electrically connected to one of the source and drain of transistor 133t. The other of the source and drain of transistor 133t is electrically connected to wiring 111. The gate of transistor 133t is electrically connected to wiring 128.

[0138] Cell 140 may further include other circuit elements such as transistors, diodes, resistive elements, capacitive elements, inductors, etc., as required.

[0139] <Specific Configuration Example 5 of Switch Circuit> Next, taking the circuit configuration of switch circuit 120 shown in FIG. 2 as an example, another specific configuration example of switch circuit 120 different from FIG. 4 will be described.

[0140] FIG. 10 shows an example of the circuit configuration of switch circuit 120. The switch circuit 120 shown in FIG. 10, similar to the switch circuit 120 shown in FIG. 8, has a plurality of sets of transistor 130t for controlling the electrical connection between wirings or terminals, transistor 131t with an extremely small offset current for supplying, holding, and discharging a predetermined amount of charge at the gate of transistor 130t, and transistor 133t connected in series with transistor 130t. However, in FIG. 10, a plurality of wirings 104, Two sets are respectively provided for the plurality of wirings 105 and the plurality of wirings 106. This is an example of the situation.

[0141] In FIG. 10, each of the above sets is illustrated as a cell 140. In the switch circuit 120 shown in FIG. 10, two cells 140 corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 are respectively provided. Note that in FIG. 2, since the total number of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is nine, in FIG. 10, in accordance with the configuration of FIG. 2, the switch circuit 120 has 18 cells 140 composed of cells 140-1 to cells 140-18, and an example where there are nine wirings 123 corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is illustrated.

[0142] Note that the number of cells 140 corresponding to each of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 is not limited to two. A plurality of three or more cells 140 may correspond to each of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106.

[0143] Specifically, in FIG. 10, two of the plurality of cells 140 are connected to one of the plurality of wirings 123. For example, in the case of cells 140-1 and cells 140-2, the other of the source and drain of the two transistors 130t are both connected to the wiring 123-1.

[0144] The cell 140 may further have other circuit elements such as transistors, diodes, resistive elements, capacitive elements, and inductors as required.

[0145] ​​​​​​​​​​In FIGS. 8 and 10, the case where the transistor 133t is electrically connected between one of the source and drain of the transistor 130t and the wiring 111 is illustrated. The transistor 133t may be electrically connected between the other of the source and drain of the transistor 130t and one of the plurality of wirings 123.

[0146] Next, an example of the operation of the switch circuit 120 shown in FIG. 10 will be described with reference to the timing chart shown in FIG. 11. However, in the timing chart shown in FIG. 11, the case where the transistors 130t, 131t, and 133t are n-channel type is illustrated.

[0147] First, the writing of the configuration data performed at times T1 to T8 will be described. At times T1 to T8, a ground potential GND is applied to the plurality of wirings 128, and the transistors 133t included in all the cells 140 are assumed to be in a non-conductive state.

[0148] At times T1 to T2, a high-level potential VDD is applied to the wiring 122-1 among the plurality of wirings 122, and a low-level potential VSS is applied to the other wirings 122. Also, a potential VDD is applied to the wiring 121. By the above operation, a potential VDD is applied to the gate (FD1) of the transistor 130t included in the cell 140-1. Therefore, the first configuration data corresponding to the digital value "1" is stored in the cell 140-1.

[0149] At times T3 to T4, a high-level potential VDD is applied to the wiring 122-2 among the plurality of wirings 122. ​​​​​​​​​​​​Apply the potential VDD to it, and apply the low-level potential VSS to the other wiring 122. Also, apply the potential VSS to the wiring 121. By the above operation, the transistor 1 30t of the cell 140-2 has its gate (FD2) supplied with the potential VSS. Therefore, the cell 140-2 stores the second configuration data corresponding to the digital value "0".

[0150] At time T5 to time T6, among the plurality of wirings 122, apply the high-level potential VDD to the wiring 122-3, and apply the low-level potential VSS to the other wirings 122. Also, apply the potential VSS to the wiring 121. By the above operation, the transistor 1 30t of the cell 140-3 has its gate (FD3) supplied with the potential VSS. Therefore, the cell 140-3 stores the first configuration data corresponding to the digital value "0".

[0151] At time T7 to time T8, among the plurality of wirings 122, apply the high-level potential VDD to the wiring 122-4, and apply the low-level potential VSS to the other wirings 122. Also, apply the potential VDD to the wiring 121. By the above operation, the transistor 1 30t of the cell 140-4 has its gate (FD4) supplied with the potential VDD. Therefore, the cell 140-4 stores the second configuration data corresponding to the digital value "1".

[0152] Note that in the timing chart shown in FIG. 11, only the writing of the first configuration data or the second configuration data to the cells 140-1 to 140-4 is shown, but for the first configuration to the cells 140-5 to 140-18 Writing of the first configuration data or the second configuration data is performed in the same manner. However, among the plurality of cells 140 represented by cell 140-M (M is a natural number and an odd number not exceeding 18), only one cell 140 stores the configuration data corresponding to the digital value "1" due to the writing of the first configuration data. Among the plurality of cells 140 represented by cell 140-L (L is a natural number and an even number not exceeding 18), only one cell 140 stores the configuration data corresponding to the digital value "1" due to the writing of the second configuration data.

[0153] Next, switching of the first logic circuit performed according to the first configuration data will be described.

[0154] At times T9 to T10, a high-level potential VDD is applied to the plurality of wirings 128 represented by wiring 128-M. A ground potential GND continues to be applied to the plurality of wirings 128 represented by wiring 128-L. Then, at times T9 to T10, among the plurality of cells 140 represented by cell 140-M, cell 140-1 is in a conductive state, and the other cells 140 are in a non-conductive state. Therefore, wiring 123-1 and wiring 111 become conductive, and the potential of wiring 123-1 is applied to wiring 111. Specifically, the timing chart shown in FIG. 11 exemplifies the case where the ground potential GND is applied to wiring 111.

[0155] Next, switching of the second logic circuit performed according to the second configuration data will be described.

[0156] ​​​​​​ At times T11 to T12, a high-level potential VDD is applied to a plurality of wirings 128 represented by wiring 128-L. A ground potential GND is applied to a plurality of wirings 128 represented by wiring 128-M. And at times T11 to T12, among a plurality of cells 140 represented by cell 140-L, cell 140-4 is in a conductive state, and the other cells 1 40 are in a non-conductive state. Accordingly, wiring 123-2 and wiring 111 become conductive, and the potential of wiring 123-2 is applied to wiring 111. Specifically, in the timing chart shown in FIG. 11, the case where the potential VDD is applied to wiring 111 is illustrated. When writing the first configuration data or the second configuration data, it is desirable to keep the potentials of wirings 123-1 to 123-18 and the potential of wiring 111 at the same height. With the above configuration, even if transistor 130t becomes conductive during the writing of the first configuration data or the second configuration data, it is possible to prevent an excessive current from flowing between any of wirings 123-1 to 123-18 and wiring 111 through transistor 130t. -L. In addition, the potential of wiring 111 is preferably held at a predetermined height by a latch circuit or the like. With the above configuration, it is possible to prevent the potential of wiring 111 from becoming a floating state and to prevent an excessive current from occurring in LE where the potential of wiring 111 is applied to the input terminal. In the case of the switch circuit 120 shown in FIG. 10, a plurality of configuration data

[0157]

[0158]

[0159] ​​​​​​​​​​​​is stored, and the configuration data used for the configuration can be freely selected. Therefore, while operating the PLD in which the logic circuit is defined by one configuration data, other configuration data can be rewritten.

[0160] <Specific Configuration Example 6 of Switch Circuit> Next, a configuration example different from that in FIG. 6 of the switch circuit 120 shown in FIG. 3 will be described. The switch circuit 120 shown in FIG. 12 has a plurality of cells 140 having a transistor 131t, a transistor 130t, and a transistor 133t, similarly to the switch circuit 120 shown in FIG. 9. However, in FIG. 12, the configuration of the switch circuit 120 in which a plurality of wirings 123 are shared by two cells 140 is illustrated.

[0161] Specifically, in FIG. 12, the case where the switch circuit 120 has 2n cells 140 indicated by cells 140-1 to 140-2n is illustrated. And among the 2n cells 140, the cell 140-i and the cell 140-i + 1 (i is a natural number equal to or less than 2n-1) share one of the wirings 123-1 to 123-n.

[0162] Note that the number of cells 140 sharing a plurality of wirings 123 is not limited to two. A plurality of three or more cells 140 may share a plurality of wirings 123.

[0163] Specifically, in FIG. 12, one of the source and drain of the transistor 130t of the cell 140-1 and one of the source and drain of the transistor 130t of the cell 140-2 ​​​​​​​​​​​The figure illustrates the case where the squares are electrically connected to the wiring 123-1 together.

[0164] The cell 140 may further include other circuit elements such as transistors, diodes, resistive elements, capacitive elements, inductors, etc., if necessary.

[0165] Note that in FIGS. 9 and 12, the case where the transistor 133t is electrically connected between the other of the source and drain of the transistor 130t and the wiring 111 is illustrated. The transistor 133t may be electrically connected between one of the source and drain of the transistor 130t and one of the plurality of wirings 123.

[0166] In the switch circuit 120 shown in FIG. 12, configuration data corresponding to a plurality of circuit configurations can be stored in each of the plurality of cells 140 electrically connected to one wiring 123. And the switching of the logic circuit performed according to the configuration data can be executed by turning on the transistor 133t in the cell 140 in which the configuration data corresponding to one circuit configuration is stored, and turning off the transistor 133t in the cell 140 in which the configuration data corresponding to another circuit configuration is stored.

[0167] Therefore, in the case of the switch circuit 120 shown in FIG. 12, a plurality of configuration data are stored, and the selection of the configuration data used for the configuration can be freely performed. Therefore, one configuration data ​​​​​​​​​While operating a PLD defined by a logic circuit, other configurations The data can be rewritten.

[0168] In the case of Patent Document 1 described above, in the multi-context method, to switch the configuration data, it is necessary to read the configuration data from the DRAM, and it is necessary to use a sense amplifier to read the configuration data. In one aspect of the present invention shown in FIG. 10 or FIG. 12, in the multi-context method, to switch the configuration data, it is not necessary to read the configuration data from a DRAM or the like. Therefore, it is not necessary to use a sense amplifier. Therefore, the time required for switching the configuration data can be shortened, and thus the logical circuit in the programmable logic device can be reconfigured at high speed.

[0169] In the switch circuit 120, since the transistor 131t has a function of holding the potential of the node FD, it is desirable that the transistor has an extremely small off-current. A transistor characterized in that a channel formation region is formed in a semiconductor film having a wider bandgap than silicon and a lower intrinsic carrier density than silicon has an extremely small off-current and is thus suitable for use as the transistor 131t. Examples of such a semiconductor include an oxide semiconductor having a bandgap more than twice that of silicon, gallium nitride, and the like. A transistor having the above semiconductor has an extremely small off-current compared to a transistor formed of a semiconductor such as ordinary silicon or germanium. This can be achieved. Therefore, by using the transistor 131t having the above configuration, the charge held in the node FD can be prevented from leaking.

[0170] In the switch circuit 120 having the above configuration, according to the configuration data, the conductive state or non-conductive state of the transistor 130t that controls the electrical connection between the wirings is selected, and by setting the transistor 131t to the non-conductive state, the potential of the signal including the configuration data is held at the node FD. Therefore, in one aspect of the present invention, the switch circuit 120 included in the wiring resources is provided with a function as a configuration memory that holds information on the selection of its conductive state or non-conductive state. And since the number of elements in each cell 140 is smaller than that of SRAM, the area of the configuration memory can be reduced as compared with a conventional PLD having both a configuration memory and a switch.

[0171] In particular, a multi-context type PLD realizes dynamic reconfiguration by storing configuration data corresponding to a plurality of circuit configurations in the configuration memory. Therefore, compared with other methods for realizing dynamic reconfiguration such as the configuration information delivery method, the area occupied by the configuration memory in the PLD is extremely large. However, in the case of the PLD according to one aspect of the present invention using the switch circuit 120 having the configuration shown in FIG. 10 or FIG. 12, even in the multi-context type, as described above, the area of the configuration memory

[0172] In addition, an oxide semiconductor (purified OS) that has been purified by reducing impurities such as moisture or hydrogen that act as electron donors and also reducing oxygen vacancies is of the i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, a transistor having a channel formation region in the purified oxide semiconductor film has an extremely small off-current and high reliability. Thus, by using the above transistor as the transistor 131t of the switch circuit 120, it is possible to ensure a long data retention period. oxide semiconductor (purified OS) purified by reducing impurities such as moisture or hydrogen that act as electron donors and also reducing oxygen vacancies is of the i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, a transistor having a channel formation region in the purified oxide semiconductor film has an extremely small off-current and high reliability. Thus, by using the above transistor as the transistor 131t of the switch circuit 120, it is possible to ensure a long data retention period. Specifically, the fact that the off-current of a transistor having a channel formation region in the purified oxide semiconductor film is small can be proven by various experiments. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be made below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less.

[0173] Specifically, the fact that the off-current of a transistor having a channel formation region in the purified oxide semiconductor film is small can be proven by various experiments. For example, even in an element with a channel width of 1×1 0 6 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be made below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 A or less. It can be seen that in this case, the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current. -13 In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens of yA / μm can be obtained. Therefore, It can be seen that in this case, the off-current normalized by the channel width of the transistor is 100 zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens of yA / μm can be obtained. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off-current of several tens of yA / μm can be obtained. Therefore, And a transistor using a highly purified oxide semiconductor film in the channel formation region has an extremely small off-current compared to a transistor using crystalline silicon.

[0174] Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, etc. are different from silicon carbide, gallium nitride, or gallium oxide, and transistors with excellent electrical characteristics can be fabricated by sputtering or the wet method, and have the advantage of excellent mass productivity. Also, different from silicon carbide, gallium nitride, or gallium oxide, the above oxide semiconductor (In-Ga-Zn-based oxide) can be used to fabricate a transistor with excellent electrical characteristics on a glass substrate or on an integrated circuit using silicon. Further, it is possible to fabricate a transistor with excellent electrical characteristics on a glass substrate or on an integrated circuit using silicon. Also, it can cope with the enlargement of the substrate size.

[0175] Note that as the oxide semiconductor, it is preferably to contain at least indium (In) or zinc (Zn). Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferably to have gallium (Ga) in addition to them as a stabilizer. Also, it is preferably to have tin (Sn) as a stabilizer. Also, it is preferably to have hafnium (Hf) as a stabilizer. Also, it is preferably to have aluminum (Al) as a stabilizer. Also, it is preferably to contain zirconium (Zr) as a stabilizer.

[0176] Also, as other stabilizers, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium, which are lanthanoids. (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu), or any one or more of them may be included.

[0177] For example, as the oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, S n-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxid e (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, I n-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, In -Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In- Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-H o-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb -Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In- Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn -based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used.

[0178] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn ​It may contain. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high mobility. The off-current can be made sufficiently small, and the mobility is also high.

[0179] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) or oxides in the vicinity of their compositions can be used. Alternatively, In-Sn-Zn-based oxides with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) or oxides in the vicinity of their compositions may be used. The off-current can be made sufficiently small, and the mobility is also high. For example, In-Sn-Zn-based oxides with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) or oxides in the vicinity of their compositions may be used. :1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) of atomic ratio of In-Sn-Zn-based oxides or oxides in the vicinity of their compositions may be used.

[0180] For example, relatively high mobility can be obtained more easily in In-Sn-Zn-based oxides. However, in In-Ga-Zn-based oxides as well, the mobility can be increased by reducing the defect density in the bulk. However, in In-Ga-Zn-based oxides as well, the mobility can be increased by reducing the defect density in the bulk. The off-current can be made sufficiently small, and the mobility is also high.

[0181] Hereinafter, the structure of the oxide semiconductor film will be described.

[0182] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. The off-current can be made sufficiently small, and the mobility is also high.

[0183] Also, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. .

[0184] Oxide semiconductor films are roughly classified into single-crystalline oxide semiconductor films and non-single-crystalline oxide semiconductor films. Non Single-crystalline oxide semiconductor films refer to amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, polycrystalline oxide semiconductor films, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) films, and the like.

[0185] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor film that has no crystal part even in a minute region and the whole film has a perfect amorphous structure. Even in a minute region, it has no crystal part, and the whole film has a perfect amorphous structure. An oxide semiconductor film is typical.

[0186] A microcrystalline oxide semiconductor film contains, for example, microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the atomic arrangement regularity of a microcrystalline oxide semiconductor film is higher than that of an amorphous oxide semiconductor film. For this reason, a microcrystalline oxide semiconductor film is characterized by having a lower defect level density than an amorphous oxide semiconductor film. (Also called nanocrystals.) is included. Therefore, the atomic arrangement regularity of a microcrystalline oxide semiconductor film is higher than that of an amorphous oxide semiconductor film. For this reason, a microcrystalline oxide semiconductor film is characterized by having a lower defect level density than an amorphous oxide semiconductor film. For this reason, a microcrystalline oxide semiconductor film is characterized by having a lower defect level density than an amorphous oxide semiconductor film. than an amorphous oxide semiconductor film.

[0187] A CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated within a cube having a side length of less than 100 nm. Therefore, the crystal parts included in a CAAC-OS film also include cases where the size can be accommodated within a cube having a side length of less than 10 nm, less than 5 nm, or less than 3 nm. A CAAC-OS film is characterized by having a lower defect level density than a microcrystalline oxide semiconductor film. Hereinafter, a detailed description will be given of the CAAC-OS film. than an amorphous oxide semiconductor film. than a microcrystalline oxide semiconductor film. Hereinafter, a detailed description will be given of the CAAC-OS film. Hereinafter, a detailed description will be given of the CAAC-OS film. .

[0188] When a CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Elect ron Microscope), a clear boundary between crystal parts, that is, a crystal Grain boundaries (also referred to as grain boundaries) cannot be confirmed. Therefore, CA It can be said that in the AC-OS film, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0189] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation ), it can be confirmed that in the crystal part, metal atoms are arranged in layers. Metal atoms Each layer has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0190] On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is found in the arrangement of metal atoms between different crystal parts.

[0191] From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0192] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the out-of-plane method analysis of the CAAC-OS film having crystals of InGaZnO4 , peaks may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal , it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0193] ​​​​​On the other hand, in the in-plane method in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear at around 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor film of InGaZnO4, when the analysis (φ scan) is performed while fixing 2θ at around 56° and rotating the sample with the normal vector of the sample surface as the axis (φ axis), six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when the φ scan is performed with 2θ fixed at around 56°.

[0194] From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0195] Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film.

[0196] Also, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface ​​​​​​​​​​​The nearby region may have a higher crystallinity than the region near the surface to be formed. Also, CAA When impurities are added to the C-OS film, the crystallinity of the region where the impurities are added changes, and regions with different degrees of crystallinity may be formed partially .

[0197] In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method , in addition to the peak with 2θ near 31°, a peak may also appear with 2θ near 36° . The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation . It is preferable that the CAAC-OS film shows a peak with 2θ near 31° and does not show a peak with 2θ near 36° .

[0198] A transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light . Therefore, the transistor has high reliability

[0199] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CA AC-OS film

[0200] The CAAC-OS film is formed, for example, by a sputtering method using a target for sputtering an oxide semiconductor that is polycrystalline . When ions collide with the sputtering target, the crystal regions contained in the sputtering target split from the a-b plane and peel off as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a -b plane . In this case, the flat plate-shaped sputtering particles reach the substrate while maintaining the crystal state, and thus a CAAC-OS film can be formed . ​

[0201] In addition, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0202] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0203] In addition, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when flat sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0204] In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30% by volume or higher, preferably 100% by volume.

[0205] As an example of the sputtering target, an In-Ga-Zn based oxide target is shown below.

[0206] InO X powder, GaO Y powder, and ZnO Z powder are mixed in a predetermined number of moles, and after pressure treatment, heat treatment is performed at a temperature of 1000°C or higher and 1500°C or lower to obtain polycrystalline In-Ga ​​​​​​- Use a -Zn - based oxide target. Here, X, Y, and Z are arbitrary positive numbers. The specified molar ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powder being 2: 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Also, the type of powder and the molar ratio for mixing can be appropriately changed according to the sputtering target to be produced.

[0207] In addition, the semiconductor film may have a structure in which a plurality of oxide semiconductor films formed using targets of metal oxides with different atomic ratios of metals are laminated. For example, the atomic ratio of the target may be such that the first - layer oxide semiconductor film has In:Ga:Zn = 1:1:1 and the second - layer oxide semiconductor film has In:Ga:Zn = 3:1:2. Also, the atomic ratio of the target may be such that the first - layer oxide semiconductor film has In:Ga:Zn = 1:3:2, the second layer oxide semiconductor film has In:Ga:Zn = 3:1:2, and the third - layer oxide semiconductor film has In: Ga:Zn = 1:1:1. Or, the semiconductor film may have a structure in which a plurality of oxide semiconductor films formed using targets of metal oxides containing different metals are laminated.

[0208] Alternatively, the semiconductor film may have a structure in which a plurality of oxide semiconductor films formed using targets of metal oxides containing different metals are laminated. Note that transistor 130t or transistor 133t may use a transistor having a channel - forming region in a semiconductor film such as amorphous, microcrystalline, polycrystalline, or

[0209] single - crystal silicon or germanium. Or, similar to transistor 131t, a semiconductor film made of silicon or germanium may be used. from silicon The band gap is wider than that of silicon, and the intrinsic carrier density is lower than that of silicon. A transistor having a silicon-based CVD process may be used. Amorphous silicon, amorphous silicon produced by vapor phase growth methods such as the D method or sputtering method Polycrystalline silicon, which is made by crystallizing silicon through processes such as laser annealing, and single-crystal silicon It is possible to use single crystal silicon, which has been peeled off by injecting hydrogen ions into a silicon wafer. can.

[0210] Example of cell configuration Next, another configuration example of the switch circuit 120 shown in FIG. 13A shows an example of a cell 140 included in the switch circuit 120. 40 includes a transistor 13, similar to the cell 140 included in the switch circuit 120 shown in FIG. 1t, transistor 130t, and transistor 133t. The cell 140 shown in A) includes an inverter 180 for holding the potential of the node FD and an inverter The configuration differs from that of the cell 140 shown in FIG.

[0211] Specifically, in FIG. 13A, the input terminal of an inverter 180 and the output terminal of an inverter 181 The terminal is electrically connected to the node FD, and the output terminal of the inverter 180 and the inverter The input terminal of the cell 140 shown in FIG. With the above configuration, the potential of the node FD is maintained by the inverter 180 and the inverter 181. It can be held.

[0212] In addition, the cell 140 shown in FIG. 13A has a configuration in which the wiring 123 is shared by two cells. An example is shown in FIG. 13B. In FIG. 13B, two cells 140 are connected to the wiring 123. Although the example shows a case where the wiring 123 is shared, in one embodiment of the present invention, the wiring 123 is divided into three or more Several cells 140 may be shared.

[0213] The cell 140 shown in FIG. 13(A) and FIG. 13(B) may include transistors, diodes, etc., as necessary. It may further include other circuit elements such as diodes, resistors, capacitors, and inductors. That's fine.

[0214] In addition, in FIG. 13(A) and FIG. 13(B), the transistor 133t is a transistor 13 The other of the source and drain of the 0t is electrically connected to the wiring 111. The transistor 133t has a source and a drain of the transistor 130t. The drain may be electrically connected to the wiring 123 .

[0215] <Preventing shoot-through current by latching> In the PLD according to one aspect of the present invention, the wiring 11 electrically connected to the input terminal of the LE A latch may be electrically connected to the switch 126 for initialization. In addition, the latch 182 is electrically connected to the wiring 111 as shown in FIG. The latch 182 shown in FIG. 14A has a wiring 111 electrically connected to the input terminal of the LE. The transistor has a function of keeping the potential of the transistor at either a high level or a low level.

[0216] FIG. 14B shows an example of the configuration of the latch 182. The inverter 2 includes an inverter 183 and a p-channel transistor 184. The input terminal of 183 is electrically connected to wiring 111, and the output terminal of inverter 183 is electrically connected to the gate of transistor 184. One of the source and drain of transistor 184 is electrically connected to wiring 185 to which a potential higher than that of wiring 125 is applied, and the other is electrically connected to wiring 111. One of the source and drain of transistor 184 is electrically connected to wiring 185 to which a potential higher than that of wiring 125 is applied, and the other is electrically connected to wiring 111. One of the source and drain of transistor 184 is electrically connected to wiring 185 to which a potential higher than that of wiring 125 is applied, and the other is electrically connected to wiring 111.

[0217] In one aspect of the present invention, by electrically connecting the latch 182 having the above configuration to the wiring 111, after the PLD is powered on, the potential of the wiring 111 can be maintained at either a high level or a low level, so that an intermediate potential is applied to the wiring 111, preventing a through current from occurring in the LE whose input terminal is connected to the wiring 111. In one aspect of the present invention, by electrically connecting the latch 182 having the above configuration to the wiring 111, after the PLD is powered on, the potential of the wiring 111 can be maintained at either a high level or a low level, so that an intermediate potential is applied to the wiring 111, preventing a through current from occurring in the LE whose input terminal is connected to the wiring 111. In one aspect of the present invention, by electrically connecting the latch 182 having the above configuration to the wiring 111, after the PLD is powered on, the potential of the wiring 111 can be maintained at either a high level or a low level, so that an intermediate potential is applied to the wiring 111, preventing a through current from occurring in the LE whose input terminal is connected to the wiring 111. In one aspect of the present invention, by electrically connecting the latch 182 having the above configuration to the wiring 111, after the PLD is powered on, the potential of the wiring 111 can be maintained at either a high level or a low level, so that an intermediate potential is applied to the wiring 111, preventing a through current from occurring in the LE whose input terminal is connected to the wiring 111. In one aspect of the present invention, by electrically connecting the latch 182 having the above configuration to the wiring 111, after the PLD is powered on, the potential of the wiring 111 can be maintained at either a high level or a low level, so that an intermediate potential is applied to the wiring 111, preventing a through current from occurring in the LE whose input terminal is connected to the wiring 111.

[0218] <Connection structure between IO and logic elements> Next, the connection structure between the IO and the logic elements in the PLD 100 will be described. FIG. 15 illustrates a part of the PLD 100 according to one aspect of the present invention.

[0219] In FIG. 15, a column 102 having a plurality of LEs 101 and a column 151 having a plurality of IOs 150 are provided in the PLD 100. In FIG. 15, a case where the column 151 and the column 102 are arranged in parallel in order from the left side toward the drawing is illustrated. In FIG. 15, a case where the column 151 and the column 102 are arranged in parallel in order from the left side toward the drawing is illustrated. In FIG. 15, a case where the column 151 and the column 102 are arranged in parallel in order from the left side toward the drawing is illustrated.

[0220] Also, in FIG. 15, a plurality of wirings 152, a plurality of wirings 153, a plurality of wirings 154, a plurality of wirings 155, and a plurality of wirings 156 are provided in the PLD 100. Also, in FIG. 15, a plurality of wirings 152, a plurality of wirings 153, a plurality of wirings 154, a plurality of wirings 155, and a plurality of wirings 156 are provided in the PLD 100.

[0221] And the first output terminal of each LE 101 included in the column 102 is connected to a plurality of wirings 152 and a plurality of They are respectively connected to the wiring 156. The second output terminals of each LE101 included in the column 102 are connected to a plurality of wirings 153 respectively. The output terminals of each IO150 included in the column 151 are connected to a plurality of wirings 155 respectively. The plurality of wirings 154 are the first outputs of a plurality of each LE101 (not shown) arranged on the right side of the column 102 toward the drawing of FIG. 15 terminals, and are respectively connected thereto.

[0222] Note that the number of output terminals of each IO150 is not necessarily one, and may be plural. However, even if there are a plurality of the above output terminals, one output terminal must be connected to one wiring. That is, if the number of IO150s included in the column 151 is Y (Y is a natural number), the PLD 100 has at least Y wirings 155 that are electrically connected to the above output terminals.

[0223] And the plurality of wirings 152, the plurality of wirings 154, the plurality of wirings 155, and the plurality of wirings 1 56 are arranged between the column 151 and the column 102. Further, the column 102 is provided between the plurality of wirings 1 52 and the plurality of wirings 153.

[0224] Also, in FIG. 15, the plurality of wirings 152, the plurality of wirings 154, and the plurality of wirings 155 are electrically connected to a plurality of input terminals of each LE101 included in the column 102 via the switch circuit 110. Also, in FIG. 15, the plurality of wirings 156 are electrically connected to the input terminals of each IO150 included in the column 151 via the switch 157.

[0225] And the switch 157 has one switch circuit 120 having the above-described configuration. The switch ​The switch circuit 120 of the ichi 157 selects one of the plurality of wirings 156 according to the configuration data and has a function of connecting the selected one wiring to the input power terminals of each IO150.

[0226] In FIGS. 1(A) and 15, the case where the LE101s belonging to the same column are connected through a plurality of wirings provided between the columns having the LE101 is illustrated. However, a wiring for directly connecting the LE101s belonging to the same column may be provided in the PLD100.

[0227] <Example configuration of LE> FIG. 16(A) illustrates one form of the LE101. The LE101 shown in FIG. 16(A) includes a LUT (look-up table) 160, a flip-flop 161, and a configuration memory 162. The configuration memory 162 has a function of storing the configuration data sent from the memory element. The LUT 160 has different logic circuits determined by the content of the configuration data sent from the configuration memory 162. When the configuration data is determined, the LUT160 determines one output value for the input values of the plurality of input signals given to the input terminal 163. Then, a signal including the above output value is output from the LUT160. The flip-flop 161 holds the signal output from the LUT160 and outputs an output signal corresponding to the signal in synchronization with the clock signal CLK from the first output terminal 164 and the second output terminal 165.

[0228] Note that LE101 further has a multiplexer circuit, and the multiplexer circuit can select whether the output signal from LUT160 passes through flip-flop 161 or not. This may be done.

[0229] Also, the type of flip-flop 161 may be defined by configuration data. Specifically, the configuration may be such that the type of flip-flop 161 is defined by configuration data, and flip-flop 161 may have the function of any one of a D-type flip-flop, a T-type flip-flop, a JK-type flip-flop, or an RS-type flip-flop.

[0230] Also, another form of LE101 is illustrated in FIG. 16(B). LE101 shown in FIG. 16(B) has a configuration in which an AND circuit 166 is added to LE101 shown in FIG. 16(A). A signal from flip-flop 161 is given as a positive logic input to AND circuit 166, and a signal INIT for initializing the potential of wiring 111 shown in FIG. 3 is given as a negative logic input. With the above configuration, when the potential of wiring 111 is initialized according to signal INIT, the output signal from LE101 can be set to the same potential as that of wiring 125. Therefore, it is possible to prevent a large amount of current from flowing through a plurality of wirings 123 to which the output signal from LE101 shown in FIG. 3 is applied and wiring 111, thereby preventing damage to the PLD.

[0231] Also, another form of LE101 is illustrated in FIG. 16(C). LE101 shown in FIG. 16(C) has a multiplexer 168 and a configuration for LE101 shown in FIG. 16(A). - It has a configuration with an additional cache memory 169. In FIG. 16(C), the multiplexer 168 receives the output signal from the LUT 160 and the output signal from the flip-flop 161. And the multiplexer 168 has a function of selecting and outputting one of the above two output signals according to the configuration data stored in the configuration memory 169. The output signal from the multiplexer 168 is output from the first output terminal 164 and the second output terminal 165.

[0232] <Top view of the PLD> FIG. 17 shows, as an example, the top view of the PLD 100.

[0233] In FIG. 17, the PLD 100 has a logic array 170, an IO 150, a PLL (phase lock loop) 172, a RAM 173, and a multiplier 174.

[0234] The logic array 170 includes a plurality of LEs 101 and a wiring resource 175 including wirings and switches for controlling the connections between the LEs 101. The PLL 172 has a function of generating a clock signal CLK. The RAM 173 has a function of storing data used for logical operations. The multiplier 174 corresponds to a dedicated logic circuit for multiplication. If the logic array 170 includes a multiplication function, the multiplier 174 is not necessarily provided.

[0235] Note that in FIG. 17, an example is shown in which the configuration data for defining the logic circuit of each LE 101 is stored in a memory element provided outside the PLD 100. However, the memory element may be provided in the PLD 100. ​

[0236] <Configuration example of LUT> In this embodiment, a configuration example of the LUT 160 included in the LE 101 will be described. The LUT 160 can be configured using a plurality of multiplexers. Then, configuration data is input to either the input terminals or the control terminals of the plurality of multiplexers. It can be configured as such.

[0237] FIG. 18(A) shows one aspect of the LUT 160 included in the LE 101.

[0238] In FIG. 18(A), the LUT 160 is configured using seven 2-input multiplexers (multiplexer 31, multiplexer 32, multiplexer 33, multiplexer 34, multiplexer 35, multiplexer 36, multiplexer 37). The input terminals of multiplexers 31 to 34 correspond to the input terminals M1 to M8 of the LUT 160. respectively.

[0239] The control terminals of multiplexers 31 to 34 are electrically connected, and the above control terminal corresponds to the input terminal IN3 of the LUT 160. The output terminal of multiplexer 31 and the output terminal of multiplexer 32 are electrically connected to the two input terminals of multiplexer 35, and the output terminal of multiplexer 33 and the output terminal of multiplexer 34 are electrically connected to the two input terminals of multiplexer 36. The control terminals of multiplexers 35 and 36 are electrically connected, and the above control terminal corresponds to the input The output terminal of SA36 is electrically connected to two input terminals of multiplexer 37. The control terminal of multiplexer 37 corresponds to input terminal IN1 of LUT160. The output terminal of multiplexer 37 corresponds to output terminal OUT of LUT160.

[0240] By applying output signals corresponding to the configuration data stored in the configuration memory from input terminals M1 to input terminal M8, the type of logical operation performed by LUT160 can be determined.

[0241] For example, in the LUT160 of FIG. 18(A), when output signals corresponding to the configuration data stored in the configuration memory with digital values of "0", "1", "0", "1", "0", "1", "1", "1" are respectively input from the configuration memory to input terminals M1 to input terminal M8, the function of the equivalent circuit shown in FIG. 18(C) can be realized.

[0242] FIG. 18(B) shows another aspect of the LUT160 included in LE101.

[0243] In FIG. 18(B), LUT160 is composed of three 2-input multiplexers (multiplexer 41, multiplexer 42, multiplexer 43) and a 2-input OR circuit 44.

[0244] The output terminal of multiplexer 41 and the output terminal of multiplexer 42 are electrically connected to two input terminals of multiplexer 43. The output terminal of OR circuit 44 is ​​​It is electrically connected to the control terminal of MUX 43. The output terminal of MUX 43 corresponds to the output terminal OUT of LUT 160.

[0245] Then, to any one of the control terminal A1, input terminals A2 and A3 of MUX 41, the control terminal A6, input terminals A4 and A5 of MUX 42, and the input terminals A 7 and A8 of OR circuit 44, an output signal corresponding to the configuration data stored in the configuration memory is input from the configuration memory so that the type of logical operation performed by LUT 160 can be determined. For example, in the LUT 160 of FIG. 18(B), when output signals corresponding to the configuration data stored in the configuration memory with digital values of "0", "1", "0", "0", "0" are respectively input to the input terminal A2, input terminal A4, input terminal A5, control terminal A6, and input terminal A8, the function of the equivalent circuit shown in FIG. 18(C) can be realized. In the case of the above configuration, the control terminal A1, input terminals A3, and A7 respectively correspond to the input terminal IN1, input terminal IN2,

[0246] For example, in the LUT 160 of FIG. 18(B), when output signals corresponding to the configuration data stored in the configuration memory with digital values of "0", "1", "0", "0", "0" are respectively input to the input terminal A2, input terminal A4, input terminal A5, control terminal A6, and input terminal A8, the function of the equivalent circuit shown in FIG. 18(C) can be realized. In the case of the above configuration, the control terminal A1, input terminals A3, and A7 respectively correspond to the input terminal IN1, input terminal IN2, are "0", "1", "0", "0", "0", the function of the equivalent circuit shown in FIG. 18(C) can be realized. In the case of the above configuration, the control terminal A1, input terminals A3, and A7 respectively correspond to the input terminal IN1, input terminal IN2, Inputting the output signals corresponding to the configuration data stored in the configuration memory respectively, The function of the equivalent circuit shown in FIG. 18(C) can be realized. In the case of the above configuration, the control terminals A1, input terminals A3, and A7 respectively correspond to the input terminal IN1, input terminal IN2, Input terminal IN3. correspond.

[0247] In FIGS. 18(A) and 18(B), an example of LUT 160 configured using 2-input multiplexers is shown, but LUT 1 60 configured using more-input multiplexers may also be used. 60 may also be used.

[0248] Also, in addition to the multiplexer, LUT 160 includes diodes, resistive elements, logic circuits (or may further have any one or all of a logic element and a switch. The logic circuit (or as the logic element, a buffer, an inverter, a NAND circuit, a NOR circuit, a three-state buffer, a clocked inverter, etc. can be used. As the switch, for example, an analog switch, a transistor, etc. can be used.

[0249] Also, when performing a 3-input 1-output logic operation as shown in FIG. 18(C) using the LUT160 shown in FIGS. 18(A) and 18(B), this is shown as an example, but it is not limited thereto. By appropriately determining the LUT160 and the configuration data to be input, a logic operation with more inputs and more outputs can be realized.

[0250] <Example of the cross-sectional structure of the cell> FIG. 19 shows, as an example, the cross-sectional structures of the transistor 130t, the transistor 13 1t, and the capacitive element 132 included in the cell 140 shown in FIG. 6.

[0251] In this embodiment, an example is illustrated in which the transistor 13 1t having a channel formation region in the oxide semiconductor film and the capacitive element 132 are formed on the transistor 13 0t having a channel formation region in a single-crystalline silicon substrate.

[0252] Note that the transistor 130t may use a semiconductor film such as amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium as an active layer. Alternatively, the transistor 130t may use an oxide semiconductor as an active layer. When all the transistors use an oxide semiconductor as an active layer, the transistor 131t is stacked on the transistor 130t. It is not necessary, and the transistor 131t and the transistor 130t may be formed in the same layer. They may be formed.

[0253] When forming the transistor 130t using thin-film silicon, amorphous silicon produced by a vapor growth method such as plasma CVD or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, and the like can be used.

[0254] The semiconductor substrate 400 on which the transistor 130t is formed may be, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP substrate, GaInAs P substrate, ZnSe substrate, etc.) having an n-type or p-type conductivity type. In FIG. 19, the case of using a single-crystalline silicon substrate having n-type conductivity is illustrated.

[0255] Further, the transistor 130t is electrically separated from other transistors by the element isolation insulating film 401. For forming the element isolation insulating film 401, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method) or a trench isolation method etc. can be used.

[0256] Specifically, the transistor 130t includes impurity regions 402 and 403 formed in the semiconductor substrate 400 and functioning as a source region or a drain region, a gate electrode 40 4, and a gate insulating film 405 provided between the semiconductor substrate 400 and the gate electrode 404. The gate electrode 404 is connected to the impurity region 402 with a gate insulating film 405 interposed therebetween. The channel forming region is formed between the solid regions 403 .

[0257] An insulating film 409 is provided over the transistor 130t. The insulating film 409 has an opening. In the opening, impurity regions 402 and 403 are formed. The wiring 410 and the wiring 411 are electrically connected to the gate electrode 404. A line 412 is formed.

[0258] The wiring 410 is electrically connected to a wiring 415 formed on the insulating film 409. The wiring 411 is electrically connected to a wiring 416 formed on the insulating film 409. The wiring 412 is electrically connected to a wiring 417 formed on the insulating film 409 .

[0259] An insulating film 420 and an insulating film 440 are stacked in this order over the wirings 415 to 417. An opening is formed in the insulating film 420 and the insulating film 440. In the portion, a wiring 421 electrically connected to the wiring 417 is formed.

[0260] In FIG. 19, the transistor 131t and the capacitor 132 are formed over the insulating film 440. It has been done.

[0261] The transistor 131t has a semiconductor film 430 including an oxide semiconductor over an insulating film 440. A conductive film 432 functioning as a source electrode or a drain electrode and a conductive a semiconductor film 430, a conductive film 432, and a gate insulating film 431 on the conductive film 433; , which is located on the gate insulating film 431 and between the conductive film 432 and the conductive film 433, It has a gate electrode 434 overlapping with 30. Note that the conductive film 433 is electrically connected to the wiring 421. is electrically connected.

[0262] Also, a conductive film 435 is provided at a position overlapping with the conductive film 433 on the gate insulating film 431. The portion where the conductive film 433 and the conductive film 435 overlap with the gate insulating film 431 interposed therebetween functions as the capacitor element 132. Note that in FIG. 19, the case where the capacitor element 132 is provided on the insulating film 440 together with the transistor 131t is illustrated, but the capacitor element 132 may be provided under the insulating film 440 together with the transistor 130t.

[0263] And, an insulating film 441 and an insulating film 442 are provided so as to be laminated in sequence on the transistor 131t and the capacitor element 132. Openings are provided in the insulating film 441 and the insulating film 442, and a conductive film 443 in contact with the gate electrode 434 is provided on the insulating film 441 at the above openings. Note that in FIG. 19, the transistor 131t only needs to have at least the gate electrode 434 on one side of the semiconductor film 430, but may have a pair of gate electrodes sandwiching the semiconductor film 430. If the transistor 131t has a pair of gate electrodes sandwiching the semiconductor film 430, a signal for controlling the conductive state or non-conductive state is applied to one of the gate electrodes, and the other gate electrode may be in a state where a potential is applied from elsewhere. In this case

[0264] And, an insulating film 441 and an insulating film 442 are provided so as to be laminated in sequence on the transistor 131t and the capacitor element 132. Openings are provided in the insulating film 441 and the insulating film 442, and a conductive film 443 in contact with the gate electrode 434 is provided on the insulating film 441 at the above openings. Note that in FIG. 19, the transistor 131t only needs to have at least the gate electrode 434 on one side of the semiconductor film 430, but may have a pair of gate electrodes sandwiching the semiconductor film 430. is provided on the insulating film 441.

[0265] Note that in FIG. 19, the transistor 131t only needs to have at least the gate electrode 434 on one side of the semiconductor film 430, but may have a pair of gate electrodes sandwiching the semiconductor film 430. If the transistor 131t has a pair of gate electrodes sandwiching the semiconductor film 430, a signal for controlling the conductive state or non-conductive state is applied to one of the gate electrodes, and the other gate electrode may be in a state where a potential is applied from elsewhere. In this case has a pair of gate electrodes sandwiching the semiconductor film 430, a signal for controlling the conductive state or non-conductive state is applied to one of the gate electrodes, and the other gate electrode may be in a state where a potential is applied from elsewhere.

[0266] When the transistor 131t has a pair of gate electrodes sandwiching the semiconductor film 430 a signal for controlling the conductive state or non-conductive state is applied to one of the gate electrodes, and the other gate electrode may be in a state where a potential is applied from elsewhere. is applied, and the other gate electrode may be in a state where a potential is applied from elsewhere. In this case The same potential may be applied to a pair of gate electrodes, or a fixed potential such as a ground potential may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled. Also, in FIG. 19, the case where the transistor 131t has a single gate structure having a channel formation region corresponding to one gate electrode 434 is illustrated. However, the transistor 131t may have a multi-gate structure having a plurality of channel formation regions in one active layer by having a plurality of electrically connected gate electrodes.

[0267]

[0268] <Example Configuration of Transistor> Next, an example of the structure of a transistor having a channel formation region in an oxide semiconductor film will be described.

[0269] The transistor 601 shown in FIG. 20 has a conductive film 602, a conductive film 603, and a gate electrode 604 on an insulating surface. The gate electrode 604 is positioned between the conductive film 602 and the conductive film 603. Also, the transistor 601 has an insulating film 605 positioned between the conductive film 602, the conductive film 603, and the gate electrode 604 provided on the insulating surface.

[0270] Also, the transistor 601 has an island-shaped insulating film 606 on the gate electrode 604 and the insulating film 605, and an island-shaped oxide semiconductor film 607 positioned on the insulating film 606. And the transistor 601 has a source electrode 608 on the conductive film 602 and the oxide semiconductor film 607 and a drain electrode 609 on the conductive film 603 and the oxide semiconductor film 607.

[0271] Further, the transistor 601 has an insulating film 610 provided on an oxide semiconductor film 607, a source electrode 608, and a drain electrode 609. The source electrode 608 and the drain electrode 609 have the insulating film 610 provided thereon.

[0272] Note that the source electrode 608 and the drain electrode 609 have a stepwise reduced film thickness at their ends. Alternatively, the source electrode 608 and the drain electrode 609 may have a continuously reduced film thickness at their ends. With the above configuration, the coverage of the insulating film 610 provided on the source electrode 608 and the drain electrode 609 at the ends of the source electrode 608 and the drain electrode 609 can be improved. Further, the transistor 601 has a gate electrode 611 provided on the insulating film 610. The gate electrode 611 overlaps with the oxide semiconductor film 607 with the insulating film 610 interposed therebetween. Note that in FIG. 20, a case is illustrated in which the transistor 601 has an insulating film 612 provided so as to cover the gate electrode 611 and the insulating film 610. In FIG. 21, a cross-sectional view shows a state in which the transistor 601 shown in FIG. 20 is stacked on a transistor 630 having a channel formation region on a single-crystalline silicon substrate. As shown in FIG. 21, the transistor 630 is formed on a semiconductor substrate 631. The semiconductor substrate 631 can be, for example, a single-crystalline silicon substrate having an n-type or p-type conductivity type, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP substrate, GaInAsP substrate, ZnSe substrate, etc.). In FIG. 21, an n-type conductivity is shown.

[0273] Further, the transistor 601 has a gate electrode 611 provided on the insulating film 610. The gate electrode 611 overlaps with the oxide semiconductor film 607 with the insulating film 610 interposed therebetween.

[0274] Note that in FIG. 20, a case is illustrated in which the transistor 601 has an insulating film 612 provided so as to cover the gate electrode 611 and the insulating film 610.

[0275] In FIG. 21, a cross-sectional view shows a state in which the transistor 601 shown in FIG. 20 is stacked on a transistor 630 having a channel formation region on a single-crystalline silicon substrate.

[0276] As shown in FIG. 21, the transistor 630 is formed on a semiconductor substrate 631. The semiconductor substrate 631 can be, for example, a single-crystalline silicon substrate having an n-type or p-type conductivity type, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP substrate, GaInAsP substrate, ZnSe substrate, etc.). In FIG. 21, an n-type conductivity is shown. ​​​​An example is given in the case of using a single-crystalline silicon substrate to be processed.

[0277] Further, the transistor 630 is electrically separated from other semiconductor elements such as transistors by the element isolation insulating film 632. For the formation of the element isolation insulating film 632, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method) or a trench isolation method or the like can be used. An impurity element imparting p-type conductivity is selectively introduced into a region where the transistor 630 of the n-channel type is formed, thereby forming a p-well 633. When forming a p-channel type transistor using a semiconductor substrate having p-type conductivity, an impurity element imparting n-type conductivity is selectively introduced into a region where the p-channel type transistor is formed, thereby forming a region called an n-well. a trench isolation method or the like can be used.

[0278] When forming a p-channel type transistor using a semiconductor substrate having p-type conductivity, an impurity element imparting n-type conductivity is selectively introduced into a region where the p-channel type transistor is formed, thereby forming a region called an n-well.

[0279] Specifically, the transistor 630 has impurity regions 634 and 635 that function as a source region or a drain region formed in the semiconductor substrate 631, and a gate insulating film 637 provided between the semiconductor substrate 631 and the gate electrode 636. The gate electrode 636 overlaps a channel formation region formed between the impurity region 634 and the impurity region 635 with the gate insulating film 637 interposed therebetween.

[0280] An insulating film 638 is provided on the transistor 630. An opening is formed in the insulating film 638, and wirings 639 and 640 that are in contact with the impurity region 634, the impurity region 635, and the gate electrode 636 are respectively formed in the opening.

[0281] ​​​​​​​​​​​ And wiring 639 is connected to wiring 641 formed on insulating film 638, and wiring 640 is connected to wiring 642 formed on insulating film 638.

[0282] An insulating film 643 is formed on wiring 641 and wiring 642.

[0283] And in FIG. 21, a transistor 601 is formed on insulating film 643. Conductive film 6 03 is connected to the gate electrode of transistor 630.

[0284] FIG. 22 shows, in cross-section, the state in which another wiring layer is formed between the layer in which transistor 630 is formed and the layer in which transistor 601 is stacked.

[0285] In FIG. 22, a wiring 645 is formed on insulating film 643. Also, an insulating film 643 and a wiring 645, an insulating film 646 is formed. An opening is formed in insulating film 646 and in the opening, a wiring 647 connected to wiring 645 is formed. On insulating film 646, a wiring 648 connected to wiring 647 is formed. Also, on insulating film 64 6 and wiring 648, an insulating film 649 is formed. An opening is formed in insulating film 649 and in the opening, a wiring 650 connected to wiring 648 is formed. On insulating film 649, a transistor 601 is formed, and wiring 650 is connected to conductive film 603 continuously.

[0286] FIG. 23 shows, in cross-section, the state in which another wiring layer is formed on the layer in which transistor 601 is formed.

[0287] In FIG. 23, an insulating film 651 is formed on the transistor 601. Also, a wiring 652 is formed on the insulating film 651, and the wiring 652 is connected to the drain electrode 609 at the opening formed in the insulating film 651, the insulating film 610, and the insulating film 612. An insulating film 653 is formed on the insulating film 651 and the wiring 652. Also, a wiring 654 is formed on the insulating film 653, and the wiring 654 is connected to the wiring 652 at the opening formed in the insulating film 653. An insulating film 655 is formed on the insulating film 653 and the wiring 654. Also, a wiring 656 is formed on the insulating film 655, and the wiring 656 is connected to the wiring 654 at the opening formed in the insulating film 655. A wiring 652 is formed on the insulating film 651, and the wiring 652 is connected to the drain electrode 609 at the opening formed in the insulating film 651, the insulating film 610, and the insulating film 612. An insulating film 653 is formed on the insulating film 651 and the wiring 652. Also, a wiring 654 is formed on the insulating film 653, and the wiring 654 is connected to the wiring 652 at the opening formed in the insulating film 653. An insulating film 655 is formed on the insulating film 653 and the wiring 654. Also, a wiring 656 is formed on the insulating film 655, and the wiring 656 is connected to the wiring 654 at the opening formed in the insulating film 655. A wiring 654 is formed on the insulating film 653, and the wiring 654 is connected to the wiring 652 at the opening formed in the insulating film 653. An insulating film 655 is formed on the insulating film 653 and the wiring 654. Also, a wiring 656 is formed on the insulating film 655, and the wiring 656 is connected to the wiring 654 at the opening formed in the insulating film 655. A wiring 656 is formed on the insulating film 655, and the wiring 656 is connected to the wiring 654 at the opening formed in the insulating film 655. A wiring 656 is formed on the insulating film 655, and the wiring 656 is connected to the wiring 654 at the opening formed in the insulating film 655.

[0288] <Configuration Example of Configuration Memory> Next, FIG. 24 shows, as an example, the circuit configuration of the memory cell included in the configuration memory. As an example, the circuit configuration of the memory cell included in the configuration memory is shown in FIG. 24.

[0289] In one aspect of the present invention, the memory cell 200 has at least switches 201 to 205. Also, the memory cell 200 may have a capacitor element 206 and a capacitor element 207 as shown in FIG. 24. In one aspect of the present invention, the memory cell 200 has at least switches 201 to 205. Also, the memory cell 200 may have a capacitor element 206 and a capacitor element 207 as shown in FIG. 24. In one aspect of the present invention, the memory cell 200 has at least switches 201 to 205. Also, the memory cell 200 may have a capacitor element 206 and a capacitor element 207 as shown in FIG. 24.

[0290] Note that in FIG. 24, the case where one transistor is used as the switch is illustrated, but a plurality of transistors may be used as the switch. Note that in FIG. 24, the case where one transistor is used as the switch is illustrated, but a plurality of transistors may be used as the switch.

[0291] The switch 201 has a function of controlling the supply of the potential of the first signal including the configuration data to the node FD1 in the memory cell 200. Specifically, the switch 20 The switch 201 has a function of controlling the supply of the potential of the first signal including the configuration data to the node FD1 in the memory cell 200. Specifically, the switch 20 When 1 is in the conductive state (on), the potential of the first signal including the configuration data given to the wiring 210 is supplied to the node FD1. Also, when the switch 201 is in the non-conductive state (off), the potential of the node FD1 is held. The capacitive element 206 is electrically connected to the node F D1 and has a function of holding the potential of the node FD1.

[0292] The selection of the conductive state or the non-conductive state in the switch 201 is performed according to the potential of the signal given to the wiring 212.

[0293] The switch 202 has a function of controlling the electrical connection between the wiring 208 and the wiring 209 according to the potential of the node FD1. Specifically, when the switch 202 is in the conductive state, the wiring 2 08 and the wiring 209 are electrically connected. Also, when the switch 202 is in the non-conductive state, the wiring 208 and the wiring 209 are in an electrically separated state.

[0294] Also, the switch 203 has a function of controlling the supply of the potential of the second signal including the configuration data to the node FD2 in the memory cell 200. Specifically, when the switch 203 is in the conductive state (on), the potential of the second signal including the configuration data given to the wiring 211 is supplied to the node FD2. Also, when the switch 203 is in the non-conductive state (off), the potential of the node FD2 is held. The capacitive element 207 is electrically connected to the node FD2 and has a function of holding the potential of the node FD2. The selection of the conductive state or the non-conductive state in the switch 203 is performed according to the potential of the signal given to the wiring 212.

[0295]

[0296] Switch 204 has a function of controlling the electrical connection between wiring 214 and wiring 209 according to the potential of node FD2. Specifically, when switch 204 is in the conducting state, wiring 214 and wiring 209 are electrically connected. Also, when switch 204 is in the non-conducting state, wiring 214 and wiring 209 are in an electrically separated state. Note that a high-level potential VDD is applied to wiring 208, and a low-level potential VSS is applied to wiring 214. And when writing configuration data to memory cell 200, the potential of the first signal and the potential of the second signal are of opposite polarities, that is, the logic levels are inverted. Therefore, when one of switch 202 and switch 204 is in the conducting state, the other is in the non-conducting state. Also, which of switch 202 and switch 204 is in the conducting state and which is in the non-conducting state is determined by the potentials of the first signal and the second signal, that is, the configuration data. Thus, it is determined by the configuration data whether the potential applied to wiring 209 is the high-level potential VDD or the low-level potential VSS. And switch 205 has a function of controlling the electrical connection between wiring 209 and wiring 215. Specifically, when switch 205 is in the conducting state, wiring 209 and wiring 215 are electrically connected, and the potential of wiring 209 is applied to wiring 215. Also, when switch 205 is in the non-conducting state, wiring 209 and wiring 215 are in an electrically separated state.

[0297]

[0298]

[0299] ​​​​​​​​​​​​​​In the configuration memory shown in FIG. 24, the transistors used for switch 201 and switch 203 have the function of holding the potentials of node FD1 and node FD2, and thus it is desirable that they are transistors with extremely low off-current. A transistor characterized in that a channel formation region is formed in a semiconductor film having a wider bandgap and a lower intrinsic carrier density than silicon has an extremely small off-current, and thus is suitable for use in switch 201 and switch 203. Examples of such semiconductors include oxide semiconductors having a bandgap more than twice that of silicon, gallium nitride, and the like. A transistor having the above semiconductor can make the off-current extremely smaller than that of a transistor formed of a semiconductor such as ordinary silicon or germanium. Therefore, by using the transistor having the above configuration in switch 201 and switch 203, it is possible to prevent the

[0300] charges held in node FD1 and node FD2 from leaking. In the configuration memory according to one aspect of the present invention, either the low-level potential VSS or the high-level potential VDD can be given to wiring 215 according to the configuration data. Therefore, unlike a configuration memory that reads configuration data by determining whether to give one potential to the wiring 215 through which the configuration data is output, accurate reading of the configuration data can be performed without There is no need to provide a circuit for precharging in the circuit, and the area of the programmable logic de vice can be kept small.

[0301] Note that after the PLD is powered on, even if the configuration data is lost and nodes F D1 and node FD2 are in an indeterminate state, by setting the potential of the first signal and the potential of the second signal both to a low-level potential, it is possible to prevent the wiring 208 and the wiring 214 from being electrically connected.

[0302] Also, in FIG. 24, by making the switch 20 5 conductive in only one of the two memory cells 200, either one of the configuration data stored in the two memory cells 200 is read from one wiring 215, and the configuration of a multi-context configuration memory is illustrated. However, in the configuration memory according to an aspect of the present invention, the configuration data stored in the plurality of memory cells 200 may be read from different wirings 215.

[0303] In addition to the above configuration, a latch 182 having a function of keeping the potential of the wiring 215 at either a high level or a low level may be provided so as to be electrically connected to the wiring 215. In one aspect of the present invention, with the above configuration, after the power is turned on, the potential of the wiring 21 5 can be kept at either a high level or a low level, so that it is possible to prevent a through current from occurring in a circuit such as a LUT or a multiplexer connected to the wiring 215 after the power is turned on.

[0304] ​​​​​​​​​​ When the potential VDD of the wiring 210 is applied to the node FD1 via the switch 201 , actually, the node FD1 has a potential lower than the potential VDD by the threshold voltage of the transistor used for the switch 201 . Therefore, even when the switch 205 is turned on, it is difficult to raise the potential of the wiring 21 5 to the same potential VDD as the wiring 208. However, by providing the latch 1 82, the potential of the wiring 215 can be raised to the potential VDD, and it is possible to prevent the wiring 2 15 from becoming an intermediate potential between the potential VSS and the potential VDD. Also, when the potential VSS of the wiring 210 is applied to the node FD1 via the switch 201, the potential of the node F D1 does not drop by the threshold voltage of the transistor used for the switch 201 . Similarly, when the potential VSS of the wiring 211 is applied to the node FD2 via the switch 203 , the potential of the node FD2 does not drop by the threshold voltage of the transistor used for the switch 203 . Therefore, since the switch 202 or the switch 204 can be surely made into a non-conductive state, no through current flows through the switch 202 or the switch 204 .

[0305] Note that, as described above, when an n-channel type transistor is used for the switch 201 , it is easy to set the node FD1 to the potential VSS, but it is difficult to set the node FD1 to the potential VDD considering the threshold voltage of the above transistor. Therefore, if a p-channel type transistor is used for the switch 202 , it becomes difficult to completely turn off the switch 202, and a through current easily flows through the switch 202 . Therefore, ​When an n-channel transistor is used for switch 201, for switch 202, it is desirable to use an n-channel transistor to prevent through-current. The same applies to switches 203 and 204. That is, when an n-channel transistor is used for switch 203, for switch 204, it is desirable to use an n-channel transistor to prevent through-current.

[0306] Also, when a p-channel transistor is used for switch 201, it is easy to set node FD1 to potential VDD, but it is difficult to set node FD1 to potential VSS considering the threshold voltage of the transistor. Therefore, when an n-channel transistor is used for switch 202, it becomes difficult to completely turn off switch 202, and through-current easily flows through switch 202. Thus, when a p-channel transistor is used for switch 201, for switch 202, it is desirable to use a p-channel transistor to prevent through-current. The same applies to switches 203 and 204. That is, when a p-channel transistor is used for switch 203, for switch 204, it is desirable to use a p-channel transistor to prevent through-current.

[0307] In addition to the above configuration, a wiring 216 to which a predetermined potential is applied and a switch 217 for controlling the electrical connection between the wiring 216 and the wiring 215 may be provided. In one aspect of the This is possible. Therefore, even if the potential of the wiring 215 becomes indeterminate after the programmable logic device is powered off, and further, even if the configuration data is lost it is possible to prevent the LUT and multiplexer in the LE from malfunctioning after the power is turned on. This is possible.

[0308] Also, in the configuration memory, when the wiring 210 and the wiring 211 are arranged along the direction in which the columns of cells of the LE and the switch circuit are arranged, and the wiring 212 and the wiring 213 are arranged in a direction intersecting the above direction, even if the number of memory cells 200 corresponding to one wiring 215 increases in the multi-context method, the distance between the wiring 210 or the wiring 211 and the wiring 21 5, that is, the distance between the switch circuit and the LE, can be prevented from becoming long. Therefore, in the multi-context method, it is possible to suppress an increase in the load such as parasitic resistance and parasitic capacitance of the wiring that electrically connects between a plurality of switch circuits and the LE, and to prevent an increase in the size of the switch circuit. This is possible. Next, taking a configuration memory having a plurality of sets 220 including two memory cells 200, a latch 182, a switch 217, and a wiring 216 shown in FIG. 24 as an example, the connection configuration of the sets 220 in the logic element is shown as an example in FIG. 25. The LE 221 shown in FIG. 25 includes a configuration memory 162 composed of a plurality of sets 220, a configuration memory 169 composed of a plurality of sets 220, a logic cell 225, and a latch 224.

[0309]

[0310]

[0311] ​​​​​​The logic cell 225 has a LUT, a multiplexer, a flip-flop, etc. The con The configuration memory 162 stores the configuration data input to the LUT of the logic cell 225. The configuration memory 169 stores the configuration data input to the multiplexer of the logic cell 225.

[0312] Also, a signal including the data given to the wiring 223 is input to the LUT of the logic cell 225. A latch 224 for holding data is connected to the wiring 223.

[0313] Also, a signal INIT for controlling the switching of the switch 217 is input to the wiring 222.

[0314] In one aspect of the present invention, by arranging the LEs 221 in a column, the configuration memories 162 and 169 are also arranged in a matrix, for example, like the matrix ( Mem) shown in FIG. 28. Thus, the configuration memories 162 and 169 can be arranged densely, and the layout area of the PLD can be reduced.

[0315] Next, a configuration example of the IO in which a plurality of the above-described sets 220 are provided will be described with reference to FIG. 26. The IO 230 shown in FIG. 26 includes sets 220a to 220d, a latch 224, Ex OR circuits 231a and 231b, a tri-state buffer 232, an in verter 233, a buffer 234, and a terminal 236.

[0316] The output signal of the set 220a, specifically, the signal having the potential given to the wiring 215 in FIG. 24 is and input to the ExOR circuit 231a. Also, a signal containing data is input to the ExOR circuit 231a from the wiring 213a . The output signal of the ExOR circuit 231a is input to the tri-state buffer 232 as a signal A containing data.

[0317] Also, the output signal of the set 220b, specifically, the signal having the potential given to the wiring 215 in FIG. 24, is input to the ExOR circuit 231b. Also, a signal containing data is input to the ExOR circuit 231b from the wiring 2 13b. The output signal of the ExOR circuit 231b is input to the tri-state buffer 232 as a signal EN that determines whether to put the tri-state buffer 232 in a high-impedance state.

[0318] The ExOR circuit 231a and the ExOR circuit 231b have a function of inverting the polarities of the signals on the wiring 213a and the wiring 213b according to the configuration data stored in the set 220a and the set 220b. In this way, by providing the ExOR circuit 231a and the ExOR circuit 231b that invert the polarity of the input signal according to the configuration data at the IO, a desired arithmetic circuit can be realized with a small number of LEs, and thereby, a large-scale circuit can be configured in the entire PLD. Also, since a desired arithmetic circuit can be realized with a small number of LEs, the power supply to the LEs not used in the arithmetic circuit can be stopped, and the operation of the LEs can be stopped, so that the power consumption of the PLD can also be reduced. Also , similarly, the ExOR circuit 231a and the ExOR circuit 231b that invert the polarity of the input signal may be provided on the input side of the LEs.

[0319] Also, the output signal of the set 220d, specifically the potential given to the wiring 215 in FIG. 24, is inverted in polarity in the inverter 233 and then input as the signal OD to the tri- state buffer 232. And the output signal of the set 220d has a function of controlling whether to open-drain the output of the tri-state buffer 232. That is, when the potential of the output signal of the set 220d is at the low level, the tri-state buffer 232 operates as a normal tri-state buffer. Also, when the potential of the output signal of the set 220d is at the high level, the potential of the signal A is at the low level, and the potential of the signal EN is at the high level, the output terminal of the tri-state buffer 232 becomes a low-level potential. Also, when the potential of the output signal of the set 220d is at the high level but the potentials of the signal A and the signal EN are different from the above combination, that is, when the potential of the signal A is at the low level and the potential of the signal EN is at the high level except, the tri-state buffer 232 becomes a high

[0320] impedance. Note that if a pull-up resistor is added outside the tri-state buffer 232, even when the tri- state buffer 232 is at a high impedance, the potential of the output signal from the tri-state buffer 232 can be set to the high level. By using the IO230 having a configuration in which a pull-up resistor is added outside the tri-state buffer 232, semiconductor devices with different

[0321] power supplies can be electrically connected via the IO230. FIG. 27 shows an example of the circuit configuration of the tri-state buffer 232. The tri-The line-state buffer 232 is a NAND gate to which the signals OD, EN, and A are input. A circuit 501, an inverter 502 to which an output signal of the NAND circuit 501 is input, and an inverter An inverter 503 to which the output signal of the inverter 502 is input, and an output signal of the inverter 503 is The tri-state buffer 504 also has a p-channel transistor 508. 232 includes an inverter 504 to which a signal EN is input, an output signal of the inverter 504, and A NOR circuit 505 to which the signal A is input and an output signal of the NOR circuit 505 is input. an inverter 506; an inverter 507 to which the output signal of the inverter 506 is input; and an n-channel transistor 509 to which an output signal of the inverter 507 is input.

[0322] The p-channel transistor 508 and the n-channel transistor 509 are connected to each other's drains. The potential of the drain is output as the output signal Y to the tri-state buffer 2. It is output from 32.

[0323] In addition, the drains of the p-channel transistor 508 and the n-channel transistor 509 are An output terminal of an inverter 510 and an input terminal of an inverter 511 are connected to each other. The input terminal of the inverter 510 is connected to the output terminal of the inverter 511. .

[0324] The inverters 502 and 503 function as buffers and are not necessarily It is not necessary to provide the inverter 506 and the inverter 507 in the state buffer 232. No. 07 functions as a buffer and does not necessarily need to be provided in the tri-state buffer 232. There is no need.

[0325] The output signal of the tri-state buffer 232 is applied to terminal 236.

[0326] Also, the signal input from terminal 236 to IO230 is input to the switch circuit via buffer 234.

[0327] Note that in FIG. 26, the case where the set 220c is provided in IO230 as a dummy is exemplified here. By providing the set 220c, in addition to being able to add functions to the set 220 with a slight mask correction, compared to the case where the set 220c is not provided, the periodicity in the layout of the mask of the set 220 can be increased. When the periodicity of the mask is low, in the photolithography process using the above mask, due to the interference of light emitted from the exposure apparatus, defects in the shape such as the width of the conductive film, insulating film, semiconductor film, etc. formed by photolithography are likely to occur, such as being partially narrowed. However, in FIG. 26, by providing the set 220c, the periodicity in the layout of the mask of the set 220 can be increased, thereby preventing defects in the shape of the conductive film, insulating film, and semiconductor film from occurring after the photolithography process. This can be achieved.

[0328] 〈Description of the mask drawing of the PLD〉 Next, the mask drawing of the PLD according to one aspect of the present invention is shown in FIG. 28. In FIG. 28, a column of logic elements (indicated by LE) is provided between columns of switch circuits (indicated by sw). Also, a column of switch circuits is provided between the column of IO elements (indicated by I / O) and the column of logic elements. is provided.

[0329] Also, in FIG. 28, as exemplified in FIG. 16(C), a plurality of configuration memories A logic element having a Li is used. And the plurality of configuration memory is also provided so as to form a matrix (denoted by Mem). In one aspect of the present invention a logic element, an IO element, and a switch circuit are each provided in a column Since they are provided, the configuration memory included in the logic element can also be densely arranged in a matrix shape. Therefore, in the PLD according to one aspect of the present invention, as shown in FIG. 28, a drive circuit (denoted by bd and wd) for controlling the operation of the switch circuit and the configuration memory can be collectively arranged around the region where the logic element, the IO element, and the switch circuit are provided When the configuration memory and the switch circuit are regarded as a memory cell array, the region where the memory cell array is arranged can be regarded as overlapping with the region where the LE is arranged. Therefore, in one aspect of the present invention the layout area of the PLD can be reduced by the above configuration. In the mask layout of the PLD shown in FIG. 28 Pad corresponds to a terminal, and cc corresponds to a controller for controlling the operation of the drive circuit bd, the drive circuit wd, etc. In the mask layout of the PLD shown in FIG. 28, Pad corresponds to a terminal, and cc corresponds to a controller for controlling the operation of the drive circuit bd, the drive circuit wd, etc. of the drive circuit bd, the drive circuit wd, etc.

[0330] In addition, when the configuration memory is not arranged in a matrix as shown in FIG. 28 the layout of the wiring for electrically connecting the drive circuit and the configuration memory becomes complicated. Also, a plurality of drive circuits may be provided for each small region of the configuration memory, but in this case, the layout of the wiring for supplying a control signal to each drive circuit becomes complicated. In addition, when the configuration memory is not arranged in a matrix as shown in FIG. 28, the layout of the wiring for electrically connecting the drive circuit and the configuration memory becomes complicated. Also, a plurality of drive

[0331] Also, in FIG. 29, the connection of LE101 and switch circuits 120a to 120c An example of the structure is shown. In FIG. 29, a switch circuit 120 that controls the electrical connection between the output terminal of LE101 and the input terminal of LE101 is shown as switch circuit 120a. Also, a switch circuit 120 that controls the electrical connection between the output terminal of IO (not shown) and the input terminal of LE101 is shown as switch circuit 120b. Further, a switch circuit 120 that controls the electrical connection between the output terminal of LE101 and the input terminal of IO (not shown) is shown as switch circuit 120c. (not shown) and the input terminal of LE101 is shown as switch circuit 120 is shown as switch circuit 120b. Also, the output terminal of LE101 and the input terminal of IO (not shown) The switch circuit 120 that controls the electrical connection is shown as switch circuit 120 c.

[0332] Also, as shown in FIG. 29, in one aspect of the present invention, the wiring 195 and wiring 196 to which the output signal of each LE101 is applied are arranged between adjacent LE101s. With the above configuration, the wiring length from each LE101 to the switch circuit 120 can be kept short. Therefore, even if the current supply capacity of the buffer on the output side of LE101 is small, the size of the above buffer can be kept small. Thus, it becomes possible to reduce the current supply capacity of the buffer on the output side of LE101, and the size of the above buffer can be kept small.

[0333] Also, wiring for supplying an output signal to an adjacent LE without passing through a switch circuit is provided. These wirings are effective when configuring a shift register, an adder circuit, a subtractor circuit, etc. with a plurality of LEs. Further, by adding a half adder circuit and a full adder circuit for one bit to an LE, an adder circuit and a subtractor circuit composed of a plurality of LEs can be configured with one LE, and a desired arithmetic circuit can be realized with a small number of LEs. For example, an adder circuit and a subtractor circuit composed of a plurality of LEs can be configured with one LE, and a desired arithmetic circuit can be realized with a small number of LEs.

[0334] Also, when the LEs are arranged in a column and adjacent LEs are connected without passing through a switch circuit, as in the case of the PLD disclosed in U.S. Patent No. 4,870,302 ​​​​​​​Is different and can shorten the wiring between LEs.

[0335] 〈Cell Comparison〉 Next, the difference in operation between a cell having a transistor using an OS film and a cell having a transistor using a silicon (Si) film and a pair of inverters will be described. And a pair of inverters will be described.

[0336] Fig. 30 shows a circuit diagram of a cell 140a having a transistor using an OS film and a cell 140b having a transistor using a silicon (Si) film and a pair of inverters. Also In Fig. 30, a timing chart of the potential of node FD in cells 140a and 140b and a timing chart of the potential of signal IN including configuration data applied to wiring 121 are shown. And a timing chart of the potential of the signal IN including the configuration data applied to the wiring 121 are shown. In cells 140a and 140b, the conduction state or non-conduction state of transistor 131t is controlled by the potential of wiring 122, and the potential corresponding to the configuration data supplied from wiring 121 is held at node FD, and the conduction state or non-conduction state of transistor 130t is controlled. Note that the timing chart shown in Fig. 30 illustrates the case where transistor 130t is an n-channel type. Is controlled. Note that the timing chart shown in Fig. 30 illustrates the case where the transistor 130t is an n-channel type.

[0337] In cells 140a and 140b, the conduction state or non-conduction state of transistor 131t is controlled by the potential of wiring 122, and the potential corresponding to the configuration data supplied from wiring 121 is held at node FD, and the conduction state or non-conduction state of transistor 130t is controlled. Is controlled by the potential of the wiring 122, and the potential corresponding to the configuration data supplied from the wiring 121 is held at the node FD, and the conduction state or non-conduction state of the transistor 130t is controlled. Is held at node FD, and the conduction state or non-conduction state of transistor 130t is controlled. In cells 140a and 140b, the conduction state or non-conduction state of transistor 131t is controlled by the potential of wiring 122, and the potential corresponding to the configuration data supplied from wiring 121 is held at node FD, and the conduction state or non-conduction state of transistor 130t is controlled. Note that the timing chart shown in Fig. 30 illustrates the case where transistor 130t is an n-channel type. Is illustrated as an example.

[0338] In cell 140b, the potential of node FD is held by inverters 180 and 181. On the other hand, in cell 140a, since the off-current of transistor 131t using an OS film is extremely small, the potential of node FD is held. Therefore, in cell 140a, when transistor 131t is in the non-conduction state, node FD becomes a floating electrode with extremely high insulation between it and other electrodes and wirings. Therefore, cell 1 is more than cell 140b. Is held by the inverters 180 and 181. On the other hand, in the cell 140a, since the off-current of the transistor 131t using the OS film is extremely small, the potential of the node FD is held. Therefore, in the cell 140a, when the transistor 131t is in the non-conduction state, the node FD becomes a floating electrode with extremely high insulation between it and other electrodes and wirings. Therefore, the cell 1 is more than the cell 140b. Since the off-current of the transistor 131t using the OS film is extremely small, the potential of the node FD is held. Therefore, in the cell 140a, when the transistor 131t is in the non-conduction state, the node FD becomes a floating electrode with extremely high insulation between it and other electrodes and wirings. Therefore, the cell 1 is more than the cell 140b. In cell 140a, when transistor 131t is in the non-conduction state, node FD becomes a floating electrode with extremely high insulation between it and other electrodes and wirings. Therefore, cell 1 is more than cell 140b. Among them, the insulation between it and other electrodes and wirings is extremely high. Therefore, cell 1 is more than cell 140b. 40a can hold the potential of node FD with a smaller number of transistors.

[0339] Also, in cell 140a, when transistor 131t is in the non-conducting state, node FD becomes floating, so the boosting effect described below can be expected. That is, in cell 140a, when node FD is floating, as the potential of signal IN changes from low level to high level, the potential of node FD rises due to the capacitance Cgs formed between the source and gate of transistor 130t. And the rising amplitude of the potential of node FD varies according to the logic level of the configuration data input to the gate of transistor 130t. Specifically, when the configuration data written in cell 140a is "0", since transistor 130t is in the weak inversion mode, the capacitance Cgs that contributes to the rising of the potential of node FD includes a capacitance Cos that does not depend on the potential of the gate electrode, that is, the potential of node FD. Specifically, the capacitance Cos includes an overlap capacitance formed in the region where the gate electrode and the source region overlap, and a parasitic capacitance formed between the gate electrode and the source electrode, etc. On the other hand, when the configuration data written in cell 140a is "1", since transistor 130t is in the strong inversion mode, the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD includes, in addition to the above-mentioned capacitance Cos, a capacitance Cod formed between the gate electrode and the drain electrode, and a part of the capacitance Cox formed between the channel formation region and the gate electrode. Therefore, when the configuration data is "1" the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD is dependent on the potential of node FD. Specifically, the capacitance Cos includes an overlap capacitance formed in the region where the gate electrode and the source region overlap, and a parasitic capacitance formed between the gate electrode and the source electrode, etc. On the other hand, when the configuration data written in cell 140a is "1", since transistor 130t is in the strong inversion mode, the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD includes, in addition to the above-mentioned capacitance Cos, a capacitance Cod formed between the gate electrode and the drain electrode, and a part of the capacitance Cox formed between the channel formation region and the gate electrode. Therefore, when the configuration data is "1" the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD is the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD includes, in addition to the above-mentioned capacitance Cos, a capacitance Cod formed between the gate electrode and the drain electrode, and a part of the capacitance Cox formed between the channel formation region and the gate electrode. Therefore, when the configuration data is "1" the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD is dependent on the potential of node FD. Specifically, the capacitance Cos includes an overlap capacitance formed in the region where the gate electrode and the source region overlap, and a parasitic capacitance formed between the gate electrode and the source electrode, etc. On the other hand, when the configuration data written in cell 140a is "1", since transistor 130t is in the strong inversion mode, the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD includes, in addition to the above-mentioned capacitance Cos, a capacitance Cod formed between the gate electrode and the drain electrode, and a part of the capacitance Cox formed between the channel formation region and the gate electrode. Therefore, when the configuration data is "1" the capacitance Cgs of transistor 130t that contributes to the rising of the potential of node FD is​​​ The configuration data will be greater than when it is "0". Therefore, cell 14 In 0a, when the configuration data is "1", the potential of node FD changes more as the potential of signal IN changes than when the configuration data is "0". This is because the potential of node FD changes more as the potential of signal IN changes than when the configuration data is "0". A boosting effect can be obtained, that is, the potential of node FD can be raised higher as the potential of signal IN changes. Due to the above-described boosting effect, the switching speed of cell 140a is improved when the configuration data is "1". When the configuration data is "0", transistor 130t is in a non-conducting state. When the configuration data is "0", transistor 130t is in a non-conducting state. t is in a non-conducting state.

[0340] In general, n-channel transistors are used in switches included in the wiring resources of PLDs to improve the integration density. However, in the above switches, there is a problem of a decrease in the switching speed caused by the potential of the signal passing through the gate of the n-channel transistor dropping due to the threshold voltage. In general, n-channel transistors are used in switches included in the wiring resources of PLDs to improve the integration density. However, in the above switches, there is a problem of a decrease in the switching speed caused by the potential of the signal passing through the gate of the n-channel transistor dropping due to the threshold voltage. In general, n-channel transistors are used in switches included in the wiring resources of PLDs to improve the integration density. However, in the above switches, there is a problem of a decrease in the switching speed caused by the potential of the signal passing through the gate of the n-channel transistor dropping due to the threshold voltage. A method using overdrive driving to apply a high potential to the gate of the n-channel transistor has also been proposed for the purpose of improving the switching speed. However, in this case, the reliability of the n-channel transistor used in the switch may be reduced. A method using overdrive driving to apply a high potential to the gate of the n-channel transistor has also been proposed for the purpose of improving the switching speed. However, in this case, the reliability of the n-channel transistor used in the switch may be reduced. A method using overdrive driving to apply a high potential to the gate of the n-channel transistor has also been proposed for the purpose of improving the switching speed. However, in this case, the reliability of the n-channel transistor used in the switch may be reduced. However, in one aspect of the present invention, due to the above-described boosting effect, the switching speed of cell 140a can be improved when the configuration data is "1" without using overdrive driving. Therefore, it is not necessary to sacrifice reliability to improve the switching speed. However, in one aspect of the present invention, due to the above-described boosting effect, the switching speed of cell 140a can be improved when the configuration data is "1" without using overdrive driving. Therefore, it is not necessary to sacrifice reliability to improve the switching speed. However, in one aspect of the present invention, due to the above-described boosting effect, the switching speed of cell 140a can be improved when the configuration data is "1" without using overdrive driving. Therefore, it is not necessary to sacrifice reliability to improve the switching speed. Therefore, it is not necessary to sacrifice reliability to improve the switching speed.

[0341] Even in the case of cell 140b, the potential of node FD rises due to the boosting effect. The potential of node FD instantaneously returns to its original potential by means of inverters 180 and 181. Therefore, the benefit of the improved switch speed due to the boosting effect cannot be obtained.

[0342] Also, unlike in Document 1 (K.C. Chun, P. Jain, J.H. Lee, and C. H. Kim, “A 3T Gain Cell Embedded DRAM Util izing Preferential Boosting for High Den sity and Low Power On-Die Caches” IEEE Jo urnal of Solid-State Circuits, vol. 46, n o. 6, pp. 1495-1505, June. 2011) and Document 2 (F. Es lami and M. Sima, “Capacitive Boosting fo r FPGA Interconnection Networks” Int. Co nf. on Field Programmable Logic and Appl ications, 2011, pp. 453-458.), a further effect can be expected in cell 140a.

[0343] In Document 1, since DRAM is assumed, the number of memory cells is large, and the read bit line (RBL) connected to the output of the memory cell has a high parasitic capacitance. On the other hand, in cell 140a, since signal OUT is supplied to the gate of CMOS, the parasitic capacitance on the output side of cell 140a is smaller than in the case of Document 1. Therefore, as the potential of node FD increases due to the capacitance Cgs of transistor 130t, further, a form is formed between the drain and the gate. ​​​​​A secondary boosting effect of raising the potential of the signal OUT is obtained according to the capacitance Cod formed. That is, when the cell 140a is used as a switch circuit for controlling the connection between wirings, a further improvement in the switch speed is obtained due to the above-described secondary boosting effect. In addition, in the case of the cell 140a, it is possible to hold the raised potential of the node FD with a smaller number of transistors compared to the case of Document 2.

[0344] To verify the above-described boosting effect, two types of test element groups (TEGs) of a 101-stage ring oscillator (RO) circuit in which the cell 140a or the cell 140b is arranged at the output terminal of each stage were created, and the delay time of the cell 140a or the cell 140b was evaluated from the oscillation frequency. Note that the channel widths W of the n-channel transistors and p-channel transistors of the inverters constituting the TEG of the RO circuit were 16 μm and 32 μm, respectively. In addition, the channel width W of the transistor 130t included in the cell 140a and the cell 140b was 16 μm, the channel width W of the transistor 131t included in the cell 140a was 4 μm, and the channel width W of the transistor 131t included in the cell 140b was 8 μm. Also, the channel widths W of the n-channel transistors and p-channel transistors of the inverters 180 and 181 included in the cell 140b were 4 μm and 8 μm, respectively. In addition, for all the n-channel transistors and p-channel transistors using a silicon film, the channel length L was 0.5 μm. Further, the transistor 131t of the cell 140a used a CAA-OS film containing an In-Ga-Zn-based oxide, and its channel length L was 1 μm. And the transistor 131t was laminated on the transistor using a silicon film. ​​​​​​​​​

[0345] Next, the power supply voltage (VDD RO ) in the TEG of the RO circuit and the power supply voltage (VDD ) of the inverters 180 and 181 of the cell 140b were used to calculate the overdrive voltage as the difference between them, and the delay time per stage of RO1 with respect to the overdrive voltage was measured. Note that the potential difference between the high-level potential and the low-level potential supplied to the wiring 122 and the wiring 121 corresponds to VDD MEM ). Regarding the cell 140b, the overdrive effect in which the switching speed is improved by increasing the overdrive voltage was found to be more prominent when VDD is lower. However, in the cell 140b, when the overdrive voltage is 0.2 times or more of VDD ... MEM corresponds to VDD

[0346] Fig. 31 shows the measurement results of the delay time. In Fig. 31, the horizontal axis represents the overdrive voltage (mV ), and the vertical axis represents the delay time per stage of RO1. Note that in Fig. 31, the delay time on the vertical axis is shown as a relative value with respect to the measured value of the delay time when VDD is 2.00 V and the overdrive voltage is 0 V. Also, in Fig. 31, the delay time when VDD RO is 2.00 V is shown by a solid line, the delay time when it is 2.2 5 V is shown by a dashed-dotted line, and the delay time when it is 2.50 V is shown by a dotted line. RO As shown in Fig. 31, it was confirmed that the RO circuit with the cell 140a added has a shorter delay time than the RO circuit with the cell 140b added, and the delay time varies depending on the configurations of the cells 140a and 140b. ...

[0347] As shown in Fig. 31, for the cell 140b, the overdrive effect in which the switching speed is improved by increasing the overdrive voltage was found to be more prominent when VDD is lower. However, in the cell 140b, when the overdrive voltage is 0.2 times or more of VDD ...

[0348] Also, as shown in Fig. 31, for the cell 140b, the overdrive effect in which the switching speed is improved by increasing the overdrive voltage was found to be more prominent when VDD is lower. However, in the cell 140b, when the overdrive voltage is 0.2 times or more of VDD RO ... ... RO ... Even when the overdrive voltage was supplied, it did not reach the switching speed of cell 140a. Note that , in cell 140a, when configuration data is written, the potential of node FD drops due to the threshold voltage of transistor 131t, so the potential of node FD becomes lower than V DD MEM . Nevertheless, in cell 140a without supplying the overdrive voltage, it is worth noting that the switching speed was higher than that of cell 140b with the overdrive voltage supplied.

[0349] Also, when the overdrive voltage is the same, it was confirmed that the RO circuit with cell 140a has lower power consumption than the RO circuit with cell 140b added.

[0350] Furthermore, from the SPICE simulation corresponding to the TEG of the above RO circuit, in the RO circuit with cell 140a added, the increase in the potential of node FD accompanying the increase in the potential of signal IN was verified. In the calculation, VDD was set to 2.5V. As a result of the calculation, it was confirmed that when the potential of signal IN rises, the potential of node FD rises by 0.75V when the configuration data is "1" and 0.07V when it is "0". RO

[0351] Therefore, it was shown that in the semiconductor device having cell 140a, high performance such as power consumption reduction and switching speed improvement can be obtained even when using a single power supply voltage without using the overdrive voltage.

[0352] Fig. 32 shows a micrograph of the fabricated PLD. In Fig. 32, the switch circuit and the config A drive circuit (Bit Driver, Word Driver) that controls the operation of the gyrator memory, a wiring resource (Routing Fabric) including a switch circuit and wiring, an IO element (User IO), a controller (Configuration Controller), and a PLE (Programmable Logic Element) are shown with corresponding regions enclosed in rectangles. river), a wiring resource (Routing Fabr ic) including a switch circuit and wiring, an IO element (User IO), a controller (Configurat ion Controller), and a PLE (Programmable Logic Element), and the corresponding regions are shown enclosed in rectangles.

[0353] The prototyped PLD has transistors using a CAAC-OS film containing an In-Ga-Zn-based oxide in the configuration memory. Also, in the prototyped PLD, the switch circuit has cell 140a, and a CAAC-OS film containing an In-G a-Zn-based oxide is used for the transistor 131t included in cell 140a. circuit has cell 140a, and a CAAC-OS film containing an In-G a-Zn-based oxide is used for the transistor 131t included in cell 140a.

[0354] In the PLD shown in FIG. 32, the number of PLEs is 20, the number of memory cells in the configuration memory is 7520, the number of IO terminals is 20, and standard functions are mounted on the PLEs. And the transistors using the CAAC-OS film are stacked on the transistors using a silicon film. The n-channel and p-channel transistors using a silicon film all have a channel length L of 0.5 μm. Also, the transistors using a CAAC-OS film containing an In-Ga-Zn-based oxide have a channel length L of 1 μm as well. transistors using a silicon film all have a channel length L of 0.5 μm. Also, the transistors using a CAAC-OS film containing an In-Ga-Zn-based oxide have a channel length L of 1 μm as well. oxide are stacked on the transistors using a silicon film. The n-channel and p-channel transistors using a silicon film all have a channel length L of 0.5 μm. Also, the transistors using a CAAC-OS film containing an In-Ga-Zn-based oxide have a channel length L of 1 μm

[0355] Also, for comparison, a PLD using SRAM in the configuration memory and having cell 140b in the switch circuit was also prototyped. The PLD using cell 140a is the comparison PL D for use. Compared with D, the layout area of the switch circuit can be reduced by 60%, the area of the wiring resources by 52%, and the area of the entire PL D by about 22% respectively.

[0356] In the PLD prototyped using cell 140a, for various circuit configurations such as the up - down counter circuit and the shift circuit for example, at a single power supply voltage of 2.5V and a frequency of 50MHz, it was confirmed that it operates normally. Furthermore, in the PLD prototyped using cell 140a the data holding operation, storing the data necessary for the storage device and intermittently cutting off the power supply the normally - off operation could also be confirmed.

[0357] Fig. 33 shows the change over time of the oscillation frequency when a 13 - stage ring oscillator with PLE for each stage is configured using the PLD prototyped with cell 140a. No significant decrease in the oscillation frequency was observed in the evaluation at room temperature for 250 hours. Therefore, it is suggested that in the PLD prototyped using cell 140a the configuration memory has good data holding characteristics.

[0358] <Examples of Electronic Devices> The semiconductor device or programmable logic device according to one aspect of the present invention can be used in a display device, a personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as an electronic device that can use the semiconductor device or programmable logic device according to one aspect of the present invention, a mobile phone, a game machine including a portable type, a portable information terminal, an e - book, a video camera, a digital still camera, etc. Cameras such as a rear camera, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer multifunction devices, automated teller machines (A TM), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 34.

[0359] FIG. 34(A) is a portable game machine and includes a housing 5001, a housing 5002, a display unit 5003, a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, a start button 5008, and the like. Note that the portable game machine shown in FIG. 34(A) has two display units, the display unit 5003 and the display unit 5004, but the number of display units included in the portable game machine is not limited to this.

[0360] FIG. 34(B) is a portable information terminal and includes a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, and the like. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 02. The first housing 5601 and the second housing 5602 are connected by a connection unit 56 05, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection unit 5605. The video on the first display unit 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 at the connection unit 5605. Alternatively, a display device having a function as a position input device may be used for at least one of the first display unit 5603 and the second display unit 5604. Note that the position input ... ... The function as a force device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0361] Figure 34(C) is a notebook personal computer, which has a housing 5401, a display unit 5402, a keyboard 5403, a pointing device 5404, etc.

[0362] Figure 34(D) is an electric refrigerator-freezer, which has a housing 5301, a refrigerator door 5302, a freezer door 5303, etc.

[0363] Figure 34(E) is a video camera, which has a first housing 5801, a second housing 5802, a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The operation keys 580 4 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by the connection part 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection part 5806. The video on the display unit 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 at the connection part 5806.

[0364] Figure 34(F) is an ordinary automobile, which has a vehicle body 5101, wheels 5102, a dashboard 510 3, lights 5104, etc.

Explanation of Signs

[0365] 31 Multiplexer 32 Multiplexer 33 Multiplexer 34 Multiplexer 35 Multiplexer 36 Multiplexer 37 Multiplexer 41 Multiplexer 42 Multiplexer 43 Multiplexer 44 OR Circuit 100 PLD 101 LE 102 Column 102-1 Column 102-2 Column 102-3 Column 103 Wiring 104 Wiring 104-1 Wiring 104-2 Wiring 104-3 Wiring 105 Wiring 105-1 Wiring 105-2 Wiring 105-3 Wiring 106 Wiring 106-1 Wiring 106-2 Wiring 106-3 Wiring 107 Wiring 108 Wiring 109 Wiring 110 Switch Circuit 111 Wiring 111-1 Wiring 111-2 Wiring 111-3 Wiring 120 Switch Circuit 120-1 Switch Circuit 120-2 Switch Circuit 120-3 Switch Circuit 120a Switch Circuit 120b Switch Circuit 120c Switch Circuit 121 Wiring 122 Wiring 122-1 Wiring 122-2 Wiring 122-3 Wiring 122-n Wiring 123 Wiring 123-1 Wiring 123-n Wiring 125 Wiring 126 Switch 126t Transistor 127 Wiring 128 Wiring 131 Switch 131t Transistor 130 Switch 130t Transistor 132 Capacitor Element 133t Transistor 140 Cell 140-1 Cell 140-2 Cell 140-3 Cell 140-4 Cell 140-n Cell 150 IO 151 Column 152 Wiring 153 Wiring 154 Wiring 155 Wiring 156 Wiring 157 Switch 160 LUT 161 Flip-Flop 162 Configuration Memory 163 Input Terminal 164 Output Terminal 165 Output Terminal 166 AND Circuit 168 Multiplexer 169 Configuration Memory 170 Logic Array 172 PLL 173 RAM 174 Multiplier 175 Wiring Resource 180 Inverter 181 Inverter 182 Latch 183 Inverter 184 Transistor 185 Wiring 195 Wiring 196 Wiring 200 Memory cell 201 Switch 202 Switch 203 Switch 204 Switch 205 Switch 206 Capacitive element 207 Capacitive element 208 Wiring 209 Wiring 210 Wiring 211 Wiring 212 Wiring 213 Wiring 213a Wiring 213b Wiring 214 Wiring 215 Wiring 216 Wiring 217 Switch 220 Set 220a Set 220b Set 220c Set 220d Set 221 LE 222 Wiring 223 Wiring 224 Latch 225 Logic cell 230 IO 231a ExOR circuit 231b ExOR circuit 232 Tri-state buffer 233 Inverter 234 Buffer 236 Terminal 400 Semiconductor substrate 401 Insulating film for element isolation 402 Impurity region 403 Impurity region 404 Gate electrode 405 Gate insulating film 409 Insulating film 410 Wiring 411 Wiring 412 Wiring 415 Wiring 416 Wiring 417 Wiring 420 Insulating film 421 Wiring 430 Semiconductor film 431 Gate insulating film 432 Conductive film 433 Conductive film 434 Gate electrode 435 Conductive film 440 Insulating film 441 Insulating film 442 Insulating film 443 Conductive film 501 NAND circuit 502 Inverter 503 Inverter 504 Inverter 505 NOR circuit 506 Inverter 507 Inverter 508 p-channel transistor 509 n-channel transistor 510 Inverter 511 Inverter 601 Transistor 602 Conductive film 603 Conductive film 604 Gate electrode 605 Insulating film 606 Insulating film 607 Oxide semiconductor film 608 Source electrode 609 Drain electrode 610 Insulating film 611 Gate electrode 612 Insulating film 630 Transistor 631 Semiconductor substrate 632 Element isolation insulating film 633 p-well 634 Impurity region 635 Impurity Region 636 Gate Electrode 637 Gate Insulating Film 638 Insulating Film 639 Wiring 640 Wiring 641 Wiring 642 Wiring 643 Insulating Film 645 Wiring 646 Insulating Film 647 Wiring 648 Wiring 649 Insulating Film 650 Wiring 651 Insulating Film 652 Wiring 653 Insulating Film 654 Wiring 655 Insulating Film 656 Wiring 5001 Housing 5002 Housing 5003 Display Unit 5004 Display Unit 5005 Microphone 5006 Speaker 5007 Operation Key 5008 Stylus 5101 Vehicle Body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigerator Door 5303 Freezer Door 5401 Housing 5402 Display Unit 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display Unit 5604 Display Unit 5605 Connection Part 5606 Operation Key 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection section

Claims

1. A first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor has a region disposed under a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, A semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, and having a function as a gate of the first transistor; a second conductive film having a region disposed above the first insulating film and always electrically connected to one of a source or a drain of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located under the oxide semiconductor film and functioning as a first gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a sixth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a seventh conductive film having a region located above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; Semiconductor device.

2. A first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor has a region disposed under a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, A semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, and having a function as a gate of the first transistor; a second conductive film having a region disposed above the first insulating film and always electrically connected to one of a source or a drain of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located under the oxide semiconductor film and functioning as a first gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a sixth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a seventh conductive film having a region located above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; each of the second conductive film and the third conductive film does not overlap with the fifth conductive film in a cross-sectional view of the second transistor in a channel length direction; Semiconductor device.

3. A first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor has a region disposed under a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, A semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, and having a function as a gate of the first transistor; a second conductive film having a region disposed above the first insulating film and always electrically connected to one of a source or a drain of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located under the oxide semiconductor film and functioning as a first gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a sixth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a seventh conductive film having a region located above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; the sixth conductive film has a region that does not overlap with the oxide semiconductor film and is in contact with the second conductive film; the seventh conductive film has a region that does not overlap with the oxide semiconductor film and is in contact with the third conductive film; Semiconductor device.

4. In any one of claims 1 to 3, the fifth conductive film overlaps with the seventh conductive film; Semiconductor device.

5. In any one of claims 1 to 4, the oxide semiconductor film contains indium oxide; Semiconductor device.

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