Display device

Abstract

To provide a thin film transistor which has excellent electrical characteristics and high reliability, and a display device using the thin film transistor as a switching element.SOLUTION: In a channel protected thin film transistor in which an oxide semiconductor is used for a channel formation region, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region composed of nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphous and microcrystals in which an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an N-type caused by re-entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented, and a contact resistance with source and drain electrodes can be reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a display device using the same, and an electronic apparatus.

Background Art

[0002] In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several nm to several hundred nm) formed on a substrate having an insulating surface has attracted attention. The thin film transistor is widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development as a switching element for an image display device has been urgently required. Metal oxides exist in various forms and are used in various applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

[0003]

[0004]

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[0005]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate the thin film transistor used in the pixel portion is required to have excellent switching characteristics, for example a large on / off ratio. The thin film transistor used in the driving circuit is required to have a high operation speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image. Therefore, the thin film transistor used in the driving circuit preferably has a high operation speed and is preferable.

[0007] One aspect of the present invention is to provide a thin film transistor having good electrical characteristics and high reliability, and a display device using the thin film transistor as a switching element.

Means for Solving the Problems

[0008] A semiconductor device according to one aspect of the present invention includes a gate electrode layer on a substrate, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer in contact with a part of the oxide semiconductor layer, and a source electrode layer and a drain electrode layer in contact with a part of the oxide semiconductor layer. In the oxide semiconductor layer, the regions between the source electrode layer and the oxide insulating layer and between the drain electrode layer and the oxide insulating layer have a film thickness thinner than the regions overlapping with the source electrode layer, the oxide insulating layer, and the drain electrode layer.

[0009] Further, the surface layer portion of the oxide semiconductor layer in contact with the oxide insulating layer has a crystal region.

[0010] In the above configuration, the gate electrode layer, source electrode layer, and drain electrode layer included in the semiconductor device are made of a film mainly composed of a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy film thereof, or a laminated film formed by combining them is used. Further, the source electrode layer and the drain electrode layer are not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used.

[0011] In addition, by using a transparent oxide conductive layer such as indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, or gallium zinc oxide for the source electrode layer, drain electrode layer, and gate electrode layer, the light transmittance of the pixel portion can be improved, and the aperture ratio can be increased.

[0012] In addition, by forming the above-described oxide conductive layer between each of the film mainly composed of the above-described metal element constituting the source electrode layer and the drain electrode layer and the oxide semiconductor layer, a semiconductor device capable of high-speed operation with reduced contact resistance can be configured.

[0013] In the above configuration, the semiconductor device has an oxide semiconductor layer, has an oxide insulating layer on the oxide semiconductor layer, and the oxide insulating layer in contact with the channel formation region of the oxide semiconductor layer functions as a channel protection layer.

[0014] In addition, in the above configuration, the oxide insulating layer that functions as the channel protection layer of the semiconductor device uses an inorganic insulating film formed by a sputtering method, typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride.

[0015] Note that as the oxide semiconductor layer, a thin film represented by InMO3(ZnO) m (m > 0 and m is not an integer) is formed, and a thin film transistor is fabricated using the thin film as the oxide semiconductor layer. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in the case of M being Ga, there may also be cases where other metal elements such as Ga and Ni or Ga and Fe are included. In addition, in the above oxide semiconductor, in addition to the metal elements included as M, there are those that contain impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m > 0 and m is not an integer), an oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O system oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O system thin film. In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al- Zn-O system, In-O system, Sn-O system, or Zn-O system metal oxides can be applied. In addition, silicon oxide may be included in the oxide semiconductor layer composed of the above metal oxides. In addition, for the oxide semiconductor layer, one that has been subjected to high-temperature short-time dehydration or dehydrogenation treatment by the RTA method or the like is used. By the heating process using the RTA method or the like, the surface layer portion of the oxide semiconductor layer has a particle size m (m > 0 and m is not an integer). Among them, an oxide semiconductor having a structure containing Ga as M is called an In-Ga-Zn-O system oxide semiconductor, and its thin film is also called an In-Ga-Zn-O system thin film.

[0016] In addition, in addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Ga -Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al- Zn-O system, In-O system, Sn-O system, or Zn-O system metal oxides can be applied. Also, silicon oxide may be included in the oxide semiconductor layer composed of the above metal oxides. In addition, for the oxide semiconductor layer, one that has been subjected to high-temperature short-time dehydration or dehydrogenation treatment by the RTA method or the like is used. By the heating process using the RTA method or the like, the surface layer portion of the oxide semiconductor layer has a particle size

[0017] In addition, for the oxide semiconductor layer, one that has been subjected to high-temperature short-time dehydration or dehydrogenation treatment by the RTA method or the like is used. By the heating process using the RTA method or the like, the surface layer portion of the oxide semiconductor layer has a particle size is It comes to have a crystal region composed of so-called nanocrystals with a size of 1 nm or more and 20 nm or less. The other parts are amorphous, or a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region.

[0018] By using an oxide semiconductor layer having such a structure, it is possible to prevent deterioration of electrical characteristics due to re-invasion of moisture from the surface layer portion and N-type conversion due to desorption of oxygen. Also, the surface layer portion of the oxide semiconductor layer is on the back channel side, and having a crystal region composed of nanocrystals can suppress the generation of parasitic channels.

[0019] Also, when forming the oxide semiconductor layer in an island shape after dehydration or dehydrogenation, no crystal region is formed on the side surface portion, and a crystal region is formed only on the surface layer portion excluding the side surface portion. However, the area ratio of the side surface portion is small and does not interfere with the above effects.

[0020] Also, by using a thin film transistor which is one aspect of the present invention, a drive circuit portion and a pixel portion can be formed on the same substrate, and a display device can be manufactured using an EL element, a liquid crystal element, an electrophoretic element, or the like.

[0021] In a display device which is one aspect of the present invention, the pixel portion has a plurality of thin film transistors, and in the pixel portion, there is a location where the gate electrode of one thin film transistor is connected to the source wiring or the drain wiring of another thin film transistor. Also, in the drive circuit of a display device which is one aspect of the present invention, there is a location where the gate electrode of a thin film transistor is connected to the source wiring or the drain wiring of that thin film transistor.

[0022] ​​​​​​​​​​​​In addition, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistors in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer.

[0023] Note that the ordinal numbers attached as first and second are used for convenience and do not indicate the process order or the stacking order. Also, the specific names used to identify the invention in this specification do not indicate anything.

[0024] Note that in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and all electro-optical devices, semiconductor circuits, and electronic devices are semiconductor devices.

Advantages of the Invention

[0025] In a thin film transistor using an oxide semiconductor layer, by adopting a configuration in which a crystal region is provided in the surface layer portion of the channel formation region of the oxide semiconductor layer, a thin film transistor and a display device with good electrical characteristics and high reliability can be manufactured.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof will be omitted. Without departing from the spirit and scope of the present invention, those skilled in the art can easily understand that the form and details can be variously changed. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the following, the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof will be omitted. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function in different drawings, and the repeated description thereof will be omitted. The repeated description thereof will be omitted.

[0028] (Embodiment 1) In this embodiment, the structure of the thin film transistor will be described with reference to FIG. 1.

[0029] The channel protection type thin film transistor of this embodiment is shown in FIG. 1.

[0030] The thin film transistor 470 shown in FIG. 1 includes a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 423 including a channel formation region, a source electrode layer 425a, a drain electrode layer 425b, and an oxide insulating layer 426a that functions as a channel protection layer, on a substrate 400 having an insulating surface. The gate electrode layer 421a can be formed as a single layer or a laminate using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components. Preferably, it is effective to form with a low-resistance metal material such as aluminum or copper, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, The gate electrode layer 421a can be formed as a single layer or a laminate using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components. Preferably, it is effective to form with a low-resistance metal material such as aluminum or copper, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance.

[0031] The gate electrode layer 421a can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components, in a single layer or a laminate. Preferably, forming with a low-resistance metal material such as aluminum or copper is effective, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. The gate electrode layer 421a can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components, in a single layer or a laminate. Preferably, forming with a low-resistance metal material such as aluminum or copper is effective, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. The gate electrode layer 421a can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components, in a single layer or a laminate. Preferably, forming with a low-resistance metal material such as aluminum or copper is effective, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. The gate electrode layer 421a can be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components, in a single layer or a laminate. Preferably, forming with a low-resistance metal material such as aluminum or copper is effective, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. Preferably, forming with a low-resistance metal material such as aluminum or copper is effective, but it is better to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, It is possible to use, for example, germanium, scandium, etc.

[0032] Also, for the purpose of improving the aperture ratio of the pixel portion, indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, or zinc gallium oxide, etc., which have light transmissivity, can also be used as the oxide conductive layer.

[0033] The gate insulating layer 402 can be a single-layer film or a laminated film of silicon oxide, silicon oxynitride, nitrided silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, etc., formed by a CVD method, a sputtering method, etc. Or a laminated film can be used.

[0034] The oxide semiconductor layer 423 uses an In-Ga-Zn-O-based film containing In, Ga, and Zn, and has a structure represented by InMO3(ZnO) m (m>0). Here, M represents one metal element or a plurality of metal elements selected from gallium ( Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in some cases, M may be Ga, and in other cases, in addition to Ga, the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, may be included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M, there are those containing impurity elements such as Fe, Ni, other transition metal elements, or oxides of the transition metals.

[0035] The oxide semiconductor layer 423 is formed using a sputtering method. The film thickness is 10 nm or more and 300 nm or less, preferably 20 nm or more and 100 nm or less. However, as shown in FIG. 1, the acid The oxide semiconductor layer 423 has a film thickness thinner than that of a third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a, a first region 424a overlapping with the source electrode layer 425a, a fifth region 424e overlapping with the oxide insulating layer 426a, and a second region 424b overlapping with the drain electrode layer 425b. The oxide semiconductor layer 423 has a film thickness thinner than that of a third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a, a first region 424a overlapping with the source electrode layer 425a, a fifth region 424e overlapping with the oxide insulating layer 426a, and a second region 424b overlapping with the drain electrode layer 425b. The oxide semiconductor layer 423 has a film thickness thinner than that of a third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a, a first region 424a overlapping with the source electrode layer 425a, a fifth region 424e overlapping with the oxide insulating layer 426a, and a second region 424b overlapping with the drain electrode layer 425b. The oxide semiconductor layer 423 has a film thickness thinner than that of a third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a, a first region 424a overlapping with the source electrode layer 425a, a fifth region 424e overlapping with the oxide insulating layer 426a, and a second region 424b overlapping with the drain electrode layer 425b. The oxide semiconductor layer 423 has a film thickness thinner than that of a third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a, a first region 424a overlapping with the source electrode layer 425a, a fifth region 424e overlapping with the oxide insulating layer 426a, and a second region 424b overlapping with the drain electrode layer 425b.

[0036] The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. The oxide semiconductor layer 423 is formed by performing a high-temperature short-time dehydration or dehydrogenation treatment by a method such as the RTA (Rapid Thermal Anneal) method. The dehydration or dehydrogenation treatment can be performed by using high-temperature nitrogen, an inert gas such as a rare gas, or light at a temperature of 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for about 1 minute or more and 10 minutes or less, preferably at 650°C for about 3 minutes or more and 6 minutes or less by an RTA treatment. When the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate.

[0037] The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals. The oxide semiconductor layer 423 is amorphous and has many unbonded hands at the stage of film formation. However, by performing the heating step of the dehydration or dehydrogenation treatment, the unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or the whole is formed of amorphous. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal particles called microcrystals.

[0038] Also, in the fifth region 424e of the oxide semiconductor layer 423 that overlaps with the oxide insulating layer 426a, the surface layer portion of the oxide semiconductor layer 423 becomes a crystalline region, and it is preferable that nanocrystals with a c-axis orientation perpendicular to the layer surface are formed. In this case, the long axis is in the c-axis direction, and the short axis direction is 1 nm or more and 20 nm or less. By using an oxide semiconductor layer having such a configuration, since a dense crystalline region composed of nanocrystals exists in the surface layer portion of the channel formation region, re-invasion of moisture from the surface layer portion and

[0039] deterioration of electrical characteristics due to N-type formation caused by oxygen desorption can be prevented. Also, in the channel formation region, the surface layer portion of the oxide semiconductor layer is on the back channel side, and preventing N-type formation is also effective in suppressing parasitic channels. Here, the In-Ga-Zn-O-based film has a different crystal structure depending on the metal oxide target used. For example, when an In-Ga-Z n-O-based film is formed using a metal oxide target containing In, Ga, and Zn with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:

[0040] 0.5 and crystallized through a heating process, a hexagonal layered compound-type crystal structure in which one or two oxide layers containing Ga and Z n are mixed exists between the In oxide layers. At this time, the crystal structure of the crystal region tends to be a structure represented by In2Ga2ZnO7 (see FIG. 23 ). Also, the molar ratio of the structure in the region where amorphous or a mixture of amorphous and microcrystals exists in the oxide semiconductor layer tends to be In:Ga:Zn = 1:1:0.5. Also, when a metal oxide target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 is used, it tends to take on a structure represented by In2Ga2ZnO7 (see FIG. 23). Also, the molar ratio of the structure in the region where amorphous or a mixture of amorphous and microcrystals exists in the oxide semiconductor layer tends to be In:Ga:Zn = 1:1:0.5. Also, the molar ratio of the structure in the region where amorphous or a mixture of amorphous and microcrystals exists in the oxide semiconductor layer tends to be In:Ga:Zn = 1:1:0.5. Also, the molar ratio of the structure in the region where amorphous or a mixture of amorphous and microcrystals exists in the oxide semiconductor layer tends to be In:Ga:Zn = 1:1:0.5. Also, when a metal oxide target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 is When the film is formed using the In-type Zn-doped AlN-based GaN and then crystallized through a heating process, the Ga and Zn-containing In oxide layers are The oxide layer containing Ga and Zn tends to be two-layered. The stable crystal structure is the latter oxide layer containing Ga and Zn. The layer structure is easy to grow crystals, and the molar ratio is In2O3:Ga2O3:ZnO When a film is formed using a target with a ratio of 1:1:1 and then crystallized through a heating process, Crystals that are connected from the interface of the gate insulating layer may be formed. This can also be called a numerical ratio.

[0041] In this embodiment, the source electrode layer 425a and the drain electrode layer 425b are The three-layer structure is made up of a conductive layer, a second conductive layer, and a third conductive layer. For this, a material similar to that of the gate electrode layer 421a described above can be used as appropriate.

[0042] In addition, similarly to the gate electrode layer 421a, the above-described light-transmitting oxide conductive layer is used as the source electrode layer By using the insulating layer 425a and the drain electrode layer 425b, the light transmittance of the pixel portion is improved, and the aperture ratio can also be made higher.

[0043] The above-mentioned metal material which is to be the source electrode layer 425a and the drain electrode layer 425b is used as a main component. The oxide conductive layer is formed between the film and the oxide semiconductor layer 423, and the contact resistance is reduced. It is also possible to reduce the resistance.

[0044] A channel protective layer is provided over the oxide semiconductor layer 423 and in contact with part of the oxide semiconductor layer 423. The oxide insulating layer 426a functions as a gate insulating film. An insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide film. Aluminum nitride or the like is used.

[0045] In addition, in FIG. 1, the oxide insulating layer 426a serving as a channel protective layer and the gate electrode layer A fifth region 424e of the oxide semiconductor layer overlapping with the gate insulating layer 402 is used as a channel forming region. The channel length L of the thin film transistor is the distance between the source electrode layer and the drain electrode layer. The channel of the channel-protected thin-film transistor 470 is defined as the distance between the gate electrode layer and the The length L of the oxide insulating layer 426a is equal to the width of the oxide insulating layer 426a in the direction parallel to the carrier flow direction. The channel length L of the thin film transistor 470 is determined by dividing the oxide semiconductor layer 423 and the oxide insulating layer 4 26a, that is, in the cross-sectional view shown in FIG. It is shown as a trapezoid, and this is the length of the base of the trapezoid.

[0046] In addition, in a channel protection type thin film transistor, the channel length L of the channel formation region is In order to shorten the width, the width of the oxide insulating layer is narrowed and the source electrode is formed on the narrow oxide insulating layer. In the case where the source electrode layer and the drain electrode layer are provided, the source electrode layer and the drain electrode layer are formed on the oxide insulating layer. To solve this problem, the thin-film transistor shown in Figure 1 has a width of The source electrode layer 425a and the drain electrode layer 425b are spaced apart from the narrow oxide insulating layer 426a. The channel protection type thin film transistor 470 is provided with a channel forming In order to shorten the channel length L of the region to, for example, 0.1 μm or more and 2 μm or less, the oxide insulating layer It is possible to realize a thin film transistor with a narrower width and faster operating speed.

[0047] Hereinafter, a display including the channel-protected thin film transistor shown in FIG. 1 will be described with reference to FIGS. 2 and 3. An example of a manufacturing process of the device will be described. Note that FIG. 3 is a plan view of the display device, and FIG. The cross-sectional views in A1 - A2 and B1 - B2 are shown.

[0048] First, prepare a substrate 400. The substrate 400 can be a barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, etc., an alkali-free glass substrate manufactured by the fusion method or the float method, a ceramic substrate, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process, etc. can be used. Also, a substrate

[0049] with an insulating film provided on the surface of a metal substrate such as stainless alloy can also be applied.

[0050] In addition, an insulating film may be formed as an underlayer film on the substrate 400. As the underlayer film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a nitrided silicon oxide film can be formed as a single layer or in a stack using the CVD method, the sputtering method, etc. When using a substrate containing mobile ions such as a glass substrate as the substrate 400, by using a film

[0051] containing nitrogen such as a silicon nitride film or a silicon oxynitride film as the underlayer film, it is possible to prevent mobile ions from entering the oxide semiconductor layer or the semiconductor layer. Next, a conductive film A resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (gate wiring including a gate electrode layer 421a, capacitor wiring 421b, and a first terminal 421c). At this time, in order to prevent disconnection, it is preferable to perform etching so that a tapered shape is formed at least at the end of the gate electrode layer 421a.

[0052] The gate wiring including the gate electrode layer 421a, the capacitor wiring 421b, and the first terminal 421c of the terminal portion can be formed in a single layer or a laminate using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components. Preferably, formation with a low-resistance metal material such as aluminum or copper is effective, but it is good to use it in combination with a high-melting-point metal material due to problems of heat resistance and corrosiveness. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used. For example, as the laminated structure of the gate electrode layer 421a, a two-layer laminated structure in which molybdenum is laminated on aluminum, or a two-layer structure in which molybdenum is laminated on copper, or a two-layer structure in which titanium nitride or tantalum nitride is laminated on copper, or a two-layer structure in which titanium nitride and molybdenum are laminated is preferable. As a three-layer laminated structure,

[0053] it is preferable to form a structure in which aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as an intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as upper and lower layers. ​​​​​​​​​​​

[0054] At this time, the aperture ratio is improved by using a light-transmitting oxide conductive layer for a part of the electrode layer and the wiring layer. For example, the oxide conductive layer may be made of indium oxide, indium oxide tin oxide, or the like. Alloy, Indium Oxide Zinc Oxide Alloy, Zinc Oxide, Zinc Aluminum Oxide, Zinc Aluminum Oxynitride For example, zinc gallium oxide or zinc oxide gallium can be used.

[0055] Next, a gate insulating layer 402 is formed to cover the gate electrode layer 421a (FIG. 2A). The gate insulating layer 402 is formed by a CVD method, a sputtering method, or the like, and has a thickness of 10 nm to 400 nm. The following applies.

[0056] For example, a silicon oxide film is formed as the gate insulating layer 402 by a CVD method or a sputtering method. The gate insulating layer 402 is formed to a thickness of 100 nm. Of course, the gate insulating layer 402 is not necessarily formed of such a silicon oxide film. Examples of the film include, but are not limited to, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, and an oxide film. Other insulating films such as aluminum oxide and tantalum oxide are used, and single layers of these materials are also used. Alternatively, it may be formed as a laminated structure.

[0057] The gate insulating layer 402 is formed by a high-density plasma apparatus. The plasma device is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of 1000 times or more. For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is The film is formed as follows.

[0058] The chamber is filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gas as material gases. A gas is introduced to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the plasma is then applied to insulating materials such as glass. An insulating film is formed on a substrate having a surface. Thereafter, the supply of monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the atmosphere to perform plasma treatment on the surface of the insulating film. This may be done. The plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N2O) and a rare gas is performed at least after the formation of the insulating film. The insulating film subjected to the above process sequence is an insulating film having a thin film thickness, for example, less than 100 nm, and can ensure reliability.

[0059] When forming the gate insulating layer 402, the flow rate ratio of monosilane gas (SiH4) to nitrous oxide (N2O) introduced into the chamber is in the range of 1:10 to 1:200. Also, as the rare gas introduced into the chamber, helium, argon, krypton, xenon, etc. can be used, but it is preferable to use argon which is inexpensive among them.

[0060] Also, the insulating film obtained by a high-density plasma device can form a film with a constant thickness, so it has excellent step coverage. Also, the insulating film obtained by a high-density plasma device can precisely control the thickness of a thin film.

[0061] The insulating film subjected to the above process sequence is significantly different from the insulating film obtained by a conventional parallel plate type PCVD device. When comparing the etching rates using the same etchant, it is 10% or more or 20% or more slower than the insulating film obtained by a parallel plate type PCVD device, and the insulating film obtained by a high-density plasma device can be said to be a dense film.

[0062] Also, as the gate insulating layer 402, silicon oxide is formed by a CVD method using an organic silane gas. It is also possible to form a layer. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (Si H(OC2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3), etc. of silicon-containing compounds can be used.

[0063] Also, as the gate insulating layer 402, an oxide, nitride, oxynitride, or nitroxide of aluminum, yttrium, or hafnium, or a compound containing at least two kinds of these can also be used.

[0064] In this specification, oxynitride refers to a substance having a larger number of oxygen atoms than nitrogen atoms in its composition, and nitroxide refers to a substance having a larger number of nitrogen atoms than oxygen atoms in its composition. For example, a silicon oxynitride film has a larger number of oxygen atoms than nitrogen atoms in its composition, and in the case of measurement using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering (HFS), it refers to a film containing oxygen in the concentration range of 50 atomic % or more and 70 atomic % or less, nitrogen in the range of 0.5 atomic % or more and 15 atomic % or less, and the number of nitrogen atoms is larger than that of oxygen atoms, and when measured using RBS and HFS, the concentration is in the range where oxygen is 5 atomic % or more and 30 atomic % or less, nitrogen is 20 atomic % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 10 atomic % or more and 30 atomic % or less. Here, when the total of the atoms constituting the silicon oxynitride or the silicon nitride oxide is 100 atomic %, the content ratios of nitrogen, oxygen, silicon, and hydrogen are within the above range.

[0065] Note that before forming the oxide semiconductor film for forming the oxide semiconductor layer 423, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove the dust adhering to the surface of the gate insulating layer. Reverse sputtering is a method in which a voltage is not applied to the target side, but a voltage is applied to the substrate side using an RF power source in an argon atmosphere to form plasma near the substrate to modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, it may be performed in an atmosphere in which oxygen, N2O, etc. are added to the argon atmosphere After the reverse sputtering treatment, by forming the oxide semiconductor film without exposing it to the atmosphere, it is possible to prevent particles (dust) and moisture from adhering to the interface between the gate insulating layer 4 02 and the oxide semiconductor layer 423.

[0066] Next, an oxide semiconductor film having a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 40 nm or less is formed on the gate insulating layer 402.

[0067] The oxide semiconductor film is an In-Ga-Zn-O-based film, an In-Sn-Zn-O-based film, an In-Al-​​​​​​​ Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system or an oxide semiconductor film of the Zn-O system can be used. Further, the oxide semiconductor film is formed by sputtering in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or an inert gas (typically argon) and oxygen mixed atmosphere. Further, when using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization may be included in the oxide semiconductor film.

[0068] Here, a metal oxide target containing In, Ga, and Zn (molar ratio of In2O3: Ga2O3:ZnO = 1:1:0.5, In:Ga:ZnO = 1:1:1, or In :Ga:ZnO = 1:1:2) is used, and the distance between the substrate and the target is 100 mm, pressure 0.6 Pa, DC (direct current) power supply 0.5 kW, in an oxygen (oxygen flow ratio 100%) atmosphere for film formation. Note that when using a pulsed DC power supply, powdery substances (also called particles, dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. In this embodiment form, as the oxide semiconductor film, an In-Ga-Zn-O system metal oxide target is used to form an In-Ga-Zn-O system film with a thickness of 30 nm by sputtering.

[0069] The sputtering method includes an RF sputtering method using a high-frequency power supply for the sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used for forming insulating films, and the DC sputtering method is mainly used for forming metal films​ It is used when doing so.

[0070] There is also a multi-source sputtering apparatus that can install multiple targets made of different materials. The multi-source sputtering apparatus can deposit different material films in the same chamber, or can also discharge multiple types of materials simultaneously in the same chamber to form a film.

[0071] There is also a sputtering apparatus that uses the magnetron sputtering method with a magnet mechanism inside the chamber or an ECR sputtering apparatus that uses plasma generated using microwaves without using glow discharge. method.

[0072] Also, as a film formation method using the sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation. There is also a bias sputtering method.

[0073] Next, a second photolithography process is performed to form a resist mask and etch the In-Ga-Z n-O film. For etching, organic acids such as citric acid and oxalic acid can be used as the etching solution. Here, ITO07N (manufactured by Kanto Chemical Co., Inc.) was used for wet etching to remove unnecessary portions to form the In-Ga-Zn-O film into an island shape and form the oxide semiconductor layer 423. By etching the end portion of the oxide semiconductor layer 423 into a tapered shape, it is possible to prevent disconnection of the wiring due to the step shape. Note that the etching here is not limited to wet etching, and dry etching may also be used.

[0074] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. This dehydration or dehydrogenation is performed The first heat treatment is performed at a temperature of 500°C or higher using high-temperature nitrogen or an inert gas such as a rare gas or light. At 750℃ or less (or at a temperature below the distortion point of the glass substrate), for 1 minute to 10 minutes Preferably, the RTA treatment can be performed at 650° C. for 3 to 6 minutes. By using the TA method, dehydration or dehydrogenation can be performed in a short time, exceeding the strain point of the glass substrate. The heat treatment can be performed at any temperature. This may be performed multiple times before and after a lithography process or a film formation process.

[0075] Here, the surface portion of the oxide semiconductor layer 423 is crystallized by the first heat treatment and becomes nanocrystals. In addition, the oxide semiconductor layer 423 has a crystalline region 106 made of a crystalline material. The other regions are amorphous or a mixture of amorphous and microcrystalline with microcrystalline interspersed among the amorphous regions. Note that the crystalline region 106 is a part of the oxide semiconductor layer 423. The notation of the layer 423 includes the crystalline region 106 .

[0076] In this specification, the heat treatment in an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is called heat treatment for dehydrogenation. Dehydration or dehydrogenation does not simply mean that hydrogen is desorbed as hydrogen or H2. For convenience, this term is used to refer to the elimination of H, OH, etc. .

[0077] When the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated, The water or hydrogen is extracted using the same furnace as the hydration or dehydrogenation, without exposing it to the atmosphere. It is important not to mix it again. Perform dehydration or dehydrogenation to lower the resistance of the oxide semiconductor layer, that is, make it N-type (N , N - , N + , etc.), and then increase the resistance to make it type-I. When manufacturing a thin film transistor using the oxide semiconductor layer, the threshold voltage value of the thin film transistor can be set to a plus pulse, and a switching element with so-called normally-off characteristics can be realized. It is desirable for the display device that the channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. Note that if the threshold voltage value of the thin film transistor is negative, a current will flow between the source electrode and the drain electrode even when the gate voltage is 0 V, which is likely to result in so-called normally-on characteristics. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, when the driving voltage is low, the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied as the gate voltage. A transistor that does not form a channel unless the driving voltage is increased or a transistor that forms a channel and a drain current flows even in a negative voltage state is not suitable as a thin film transistor used in a circuit.

[0078] Also, the gas atmosphere for reducing the heating temperature T may be different from the gas atmosphere when the temperature is raised to the heating temperature T. It may be switched to a gas atmosphere. For example, in the same furnace where dehydration or dehydrogenation has been performed, without exposing it to the atmosphere, the inside of the furnace is filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point is -40 °C or lower, preferably -60 °C or lower) and cooled.

[0079] In the first heat treatment, it is preferable that water, hydrogen, etc. are not contained in the atmosphere. Alternatively, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0080] When the heat treatment is performed in the above-mentioned inert gas atmosphere, the oxide semiconductor layer becomes oxygen-deficient type due to the heat treatment and has a lower resistance, that is, becomes N-type (N - type, etc.). After that, by forming an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer can be said to be made into an oxygen-excessive state and have a higher resistance, that is, become I-type. Thereby, a thin film transistor with good electrical characteristics and high reliability can be manufactured.

[0081] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, a part of the oxide semiconductor layer may crystallize. After the first heat treatment, it becomes an oxygen-deficient type and has a lower resistance oxide semiconductor layer 423. After the first heat treatment, the carrier concentration is higher than that of the oxide semiconductor film immediately after film formation, preferably having a carrier concentration of 1 × 10 18 / cm 3 or higher.

[0082] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus, and the second photolithography process is performed. In this case, a crystal region is not formed on the side portion of the oxide semiconductor layer 423, and the crystal region 106 is formed only on the upper layer portion excluding the side portion.

[0083] Next, a third photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form a contact hole reaching a wiring or electrode layer made of the same material as the gate electrode layer 421a (FIG. 2(B)). This contact hole is provided for direct connection with a conductive film to be formed later. For example, in a drive circuit portion, a contact hole is formed when forming a thin film transistor in direct contact with the gate electrode layer and the source electrode layer or the drain electrode layer, or a terminal electrically connected to the gate wiring of a terminal portion.

[0084] Next, an oxide insulating film is formed by sputtering on the oxide semiconductor layer 423 and the gate insulating layer 402. After that, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form oxide insulating layers 426a, 426b, 426c, and 426d, and then the resist mask is removed (FIG. 2(C)). At this stage, a region in contact with the oxide insulating layer 426a is formed in the oxide semiconductor layer. Among this region, a region that overlaps with the gate electrode layer and the gate insulating layer through the oxide insulating layer 426a and also overlaps with the oxide insulating layer 426a becomes a channel formation region. Also, a contact hole reaching the first terminal 421c is formed by the fourth photolithography process.

[0085] The oxide insulating film is at least 1 nm thick and is formed by an oxide insulating method such as a sputtering method. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In the embodiment, a silicon oxide film is formed as the oxide insulating film by a sputtering method. The substrate temperature during the process may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100° C. The deposition of silicon oxide films by sputtering is carried out under a rare gas (typically argon) atmosphere. The reaction is carried out in an oxygen atmosphere or in a mixed atmosphere of rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to perform sputtering in an oxygen and rare gas atmosphere. A silicon oxide film can be formed by a quenching method. The oxide insulating film formed in contact with the - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside. Representative examples include silicon oxide film. A silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0086] In this embodiment, a columnar polycrystalline B-doped silicon target (resistance value 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 1.01 Ωcm. Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering. The film thickness is 300 nm.

[0087] Next, a conductive film made of a metal material is formed over the oxide semiconductor layer 423 by a sputtering method or a vacuum evaporation method. The conductive film may be formed using the same material as that of the gate electrode layer 421a. It is possible.

[0088] In this embodiment, a conductive film formed by laminating the first to third conductive films shall be formed. For example, titanium, which is a heat-resistant conductive material, is used as the first and third conductive films, and an aluminum alloy containing neodymium is used as the second conductive film. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. Note that in this embodiment, a three-layer structure composed of the first to third conductive films is adopted, but it is not limited to this, and it may be a single-layer structure, a two-layer structure, or a structure with four or more layers. For example, it may be a single-layer structure of a titanium film or a single-layer structure of an aluminum film containing silicon.

[0089] In addition, when forming a conductive film in contact with an oxide semiconductor layer having a dense crystal region 106 composed of nanocrystals on the surface layer portion, the crystal region 106 of the oxide semiconductor layer may be amorphized due to the heat in the film formation process or the damage to the crystal region caused by film formation. However, in the method for manufacturing a thin film transistor shown in this embodiment, an oxide insulating layer 426a that functions as a channel protection layer is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer. Therefore, even when a conductive film is formed, at least in the channel formation region (the fifth region) of the oxide semiconductor layer, a structure having a crystal region 106 in the surface layer portion can be achieved.

[0090] Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form a source electrode layer 425a, a drain electrode layer 425b, and a connection electrode Form 429. As an etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive film and the third conductive film, and an aluminum alloy containing neodymium is used for the second conductive film, hydrogen peroxide solution or heated hydrochloric acid can be used as an etchant for wet etching.

[0091] In this etching step, a part of the oxide semiconductor layer 423 is etched, and the third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, and the fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a overlap with the source electrode layer 425a. The first region 424a, the fifth region 424e overlapping with the oxide insulating layer 426a, and the second region 424b overlapping with the drain electrode layer 425b become regions with a thinner film thickness (FIG. 2(D)). Note that the fifth region 424e of the oxide semiconductor layer 423 is protected by the oxide insulating layer 426a without being etched, so that a dense crystal region composed of nanocrystals exists at least in the surface layer portion of the channel formation region. In the channel formation region, the surface layer portion of the oxide semiconductor layer is on the back channel side, and this crystal region can suppress parasitic channels.

[0092] Also, in this fifth photolithography step, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Note that although not shown here, the source wiring or drain wiring and the gate electrode of the thin film transistor of the driving circuit are directly connected through the same steps as those described above.

[0093] ​​​​​​​​​​Next, an oxide insulating layer 428 covering the thin film transistor 470 is formed (FIG. 2(E)). As the oxide insulating layer 428, an oxide insulating layer such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or a tantalum oxide film obtained by a sputtering method or the like can be used.

[0094] The oxide insulating layer can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer. In this embodiment, a silicon oxide film is formed as the oxide insulating layer by a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and is set to 100°C in this embodiment. Here, as a method of not mixing impurities such as water and hydrogen during film formation, a pre-bake is performed at a temperature of 150°C or higher and 350°C or lower for 2 minutes or more and 10 minutes or less under reduced pressure before film formation, and the oxide insulating layer is formed without being exposed to the atmosphere. It is desirable to form the oxide insulating layer without being exposed to the atmosphere. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by a sputtering method in an atmosphere of oxygen and a rare gas using a silicon target. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is preferably an inorganic insulating film that does not contain impurities such as water, hydrogen ions, and OH - and blocks the intrusion of these from the outside.

[0095] In this embodiment, a silicon target with a purity of 6N and columnar polycrystalline B-doped (resistance value 0) ​​​​​.01 Ωcm) is used, and the distance between the substrate and the target (T-S distance) is 89 mm, and the pressure is 0.4 Pa, a direct current (DC) power supply of 6 kW, and film formation is performed by pulsed DC sputtering in an oxygen (oxygen flow ratio 100%) atmosphere. The film thickness is 300 nm.

[0096] Next, a second heat treatment (preferably at 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. Alternatively, an RTA treatment at a high temperature for a short time may be performed in the same manner as the first heat treatment. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor layer overlapping the oxide insulating layer are heated in a state of being in contact. Note that when the second heat treatment is performed, the oxide semiconductor layer 423 whose resistance has been reduced by the first heat treatment becomes an oxygen-excess state and can be made highly resistive (type I).

[0097] In this embodiment, the second heat treatment is performed after the formation of the silicon oxide film. However, the timing of the heat treatment is not limited to immediately after the formation of the silicon oxide film, and there is no problem as long as it is after the formation of the silicon oxide film.

[0098] Also, in a case where heat-resistant materials are used for the source electrode layer 425a and the drain electrode layer 425b, a process using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment can also be performed only once after the formation of the silicon oxide film.

[0099] Next, a sixth photolithography process is performed to form a resist mask, and a contact hole reaching the drain electrode layer 425b is formed by etching the oxide insulating layer 4 28. ​​​​​​Also, contact holes reaching the connection electrode 429 are also formed by the etching here.

[0100] Next, after removing the resist mask, a transparent conductive film is formed. As the material of the transparent conductive film are indium oxide (In2O3), indium tin oxide alloy (In2O3―SnO 2, abbreviated as ITO), etc., which are formed by using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, especially for the etching of ITO residue is likely to occur, so indium zinc oxide alloy (In2O3―ZnO) may be used to improve the etching processability.

[0101] Next, a seventh photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 110.

[0102] Also, in this seventh photolithography process, using the gate insulating layer 402 in the capacitor portion, the oxide insulating layer 426b, and the oxide insulating layer 428 as dielectrics, a holding capacitor is formed between the capacitor wiring 421b and the pixel electrode layer 110.

[0103] Also, in this seventh photolithography process, the first terminal 421c is covered with a resist mask to leave the transparent conductive film 128 formed on the terminal portion. The transparent conductive film 128 serves as an electrode or wiring to be used subsequently for connection with the FPC. The connection electrode 4 directly connected to the first terminal 421c and the transparent conductive film 128 formed thereon serve as a connection terminal electrode that functions as an input terminal of the gate wiring. Also, although not shown, a connection terminal electrode that functions as an input terminal of the source wiring is simultaneously formed.

[0104] ​​​Also, FIGS. 4(A1) and 4(A2) illustrate a cross-sectional view and a plan view of the gate wiring terminal portion at this stage, respectively. FIG. 4(A1) corresponds to a cross-sectional view along line C1-C2 in FIG. 4(A2). In FIG. 4(A1), a transparent conductive film 415 formed on the oxide insulating layer 428 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(A1), in the terminal portion, a first terminal 411 formed of the same material as the gate wiring and a connection electrode 412 formed of the same material as the source wiring overlap and are in direct contact with each other through the gate insulating layer 402 to allow conduction. Also, the connection electrode 412 and the transparent conductive film 415 are in direct contact with each other through a contact hole provided in the oxide insulating layer 428 to allow conduction. Also, FIGS. 4(B1) and 4(B2) illustrate a cross-sectional view and a plan view of the source wiring terminal portion, respectively. Also, FIG. 4(B1) corresponds to a cross-sectional view along line C3-C4 in FIG. 4(B2). In FIG. 4(B1), a transparent conductive film 418 formed on the oxide insulating layer 428 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(B1), in the terminal portion, an electrode 416 formed of the same material as the gate wiring overlaps below a second terminal 414 that is electrically continuous with the source wiring through the gate insulating layer 402. The electrode 416 is not electrically connected to the second terminal 414. If the electrode 416 is set to a different potential from the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 414 is electrically connected to the transparent conductive film 418 through the oxide insulating layer 428. In FIG. 4(A1), the transparent conductive film 415 formed on the oxide insulating layer 428 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(A1), in the terminal portion, a first terminal 411 formed of the same material as the gate wiring and a connection electrode 412 formed of the same material as the source wiring overlap and are in direct contact with each other through the gate insulating layer 402 to allow conduction. Also, in FIG. 4(A1), in the terminal portion, a first terminal 411 formed of the same material as the gate wiring and a connection electrode 412 formed of the same material as the source wiring overlap and are in direct contact with each other through the gate insulating layer 402 to allow conduction. Also, in FIG. 4(A1), in the terminal portion, a first terminal 411 formed of the same material as the gate wiring and a connection electrode 412 formed of the same material as the source wiring overlap and are in direct contact with each other through the gate insulating layer 402 to allow conduction. Also, the connection electrode 412 and the transparent conductive film 415 are in direct contact with each other through a contact hole provided in the oxide insulating layer 428 to allow conduction. Also, the connection electrode 412 and the transparent conductive film 415 are in direct contact with each other through a contact hole provided in the oxide insulating layer 428 to allow conduction.

[0105] Also, FIGS. 4(B1) and 4(B2) illustrate a cross-sectional view and a plan view of the source wiring terminal portion, respectively. Also, FIG. 4(B1) corresponds to a cross-sectional view along line C3-C4 in FIG. 4(B2). In FIG. 4(B1), a transparent conductive film 418 formed on the oxide insulating layer 428 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(B1), in the terminal portion, an electrode 416 formed of the same material as the gate wiring overlaps below a second terminal 414 that is electrically continuous with the source wiring through the gate insulating layer 402. Also, in FIG. 4(B1), in the terminal portion, an electrode 416 formed of the same material as the gate wiring overlaps below a second terminal 414 that is electrically continuous with the source wiring through the gate insulating layer 402. Also, in FIG. 4(B1), in the terminal portion, an electrode 416 formed of the same material as the gate wiring overlaps below a second terminal 414 that is electrically continuous with the source wiring through the gate insulating layer 402. The electrode 416 is not electrically connected to the second terminal 414. If the electrode 416 is set to a different potential from the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. If the electrode 416 is set to a different potential from the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 414 is electrically connected to the transparent conductive film 418 through the oxide insulating layer 428.

[0106] A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. . Further, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, a second terminal having the same potential as the source wiring, a third terminal having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal may be set to any number, and the implementer may determine it as appropriate.

[0107] In this way, by seven photolithography processes, using seven photomasks, the channel protected thin film transistor 470 and the holding capacitor portion can be completed. Then, by arranging these in a matrix corresponding to individual pixels to form a pixel portion, it can be used as one substrate for manufacturing an active matrix type display device. In this specification for convenience, such a substrate is referred to as an active matrix substrate.

[0108] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode that is electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal that is electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. .

[0109] Further, this embodiment is not limited to the pixel configuration of FIG. 3. For example, without providing a capacitor wiring, a pixel electrode may be overlapped with an adjacent pixel's gate wiring via a protective insulating film and a gate insulating layer to form a holding capacitance. In this case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted. ​

[0110] Also, as shown in FIG. 5, a source electrode layer 425a and a drain electrode layer 425b may overlap on the oxide insulating layer 456a that functions as a channel protection layer. In this case, since the oxide semiconductor layer is not etched during the patterning of the source electrode layer 425a and the drain electrode layer 425b, a region with a thin film thickness is not formed in the oxide semiconductor layer. That is, a first region 424a that overlaps with the source electrode layer 425a, a second region 424b that overlaps with the drain electrode layer 425b, and a fifth region 424e that becomes a channel formation region, each having the same film thickness, are provided in the oxide semiconductor layer. That is, an oxide semiconductor layer having a first region 424a that overlaps with the source electrode layer 425a, a second region 424b that overlaps with the drain electrode layer 425b, and a fifth region 424e that becomes a channel formation region, each having the same film thickness, is formed. That is, an oxide semiconductor layer having a first region 424a that overlaps with the source electrode layer 425a, a second region 424b that overlaps with the drain electrode layer 425b, and a fifth region 424e that becomes a channel formation region, each having the same film thickness, is formed. a second region 424b that overlaps with the drain electrode layer 425b, and a fifth region 424e that becomes a channel formation region, each having the same film thickness, are provided in the oxide semiconductor layer. a second region 424b that overlaps with the drain electrode layer 425b, and a fifth region 424e that becomes a channel formation region, each having the same film thickness, are provided in the oxide semiconductor layer.

[0111] Also, as shown in FIG. 22(A), a thin film transistor 490 having a structure in which the film thickness of a region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e of the oxide semiconductor layer is thicker than the film thicknesses of the third region 424c and the fourth region 424d (that is, the interface between the crystalline region and the region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e is located above the outermost surface of the third region 424c and the fourth region 424d) may be used. Also, as shown in FIG. 22(A), a thin film transistor 490 having a structure in which the film thickness of a region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e of the oxide semiconductor layer is thicker than the film thicknesses of the third region 424c and the fourth region 424d (that is, the interface between the crystalline region and the region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e is located above the outermost surface of the third region 424c and the fourth region 424d) may be used. Also, as shown in FIG. 22(A), a thin film transistor 490 having a structure in which the film thickness of a region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e of the oxide semiconductor layer is thicker than the film thicknesses of the third region 424c and the fourth region 424d (that is, the interface between the crystalline region and the region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e is located above the outermost surface of the third region 424c and the fourth region 424d) may be used. Also, as shown in FIG. 22(A), a thin film transistor 490 having a structure in which the film thickness of a region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e of the oxide semiconductor layer is thicker than the film thicknesses of the third region 424c and the fourth region 424d (that is, the interface between the crystalline region and the region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e is located above the outermost surface of the third region 424c and the fourth region 424d) may be used. Also, as shown in FIG. 22(A), a thin film transistor 490 having a structure in which the film thickness of a region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e of the oxide semiconductor layer is thicker than the film thicknesses of the third region 424c and the fourth region 424d (that is, the interface between the crystalline region and the region that is amorphous or a mixture of amorphous and microcrystalline in the fifth region 424e is located above the outermost surface of the third region 424c and the fourth region 424d) may be used. Such a thin film transistor 490 can be obtained, for example, by adjusting the heating temperature or the heating time in the first heat treatment to form an extremely shallow crystalline region in the oxide semiconductor layer. By adopting the structure of the thin film transistor 490 shown in FIG. 22(A), the off-current can be reduced. the off-current can be reduced. the off-current can be reduced.

[0112] Note that the channel length L of the channel protection type thin film transistor 490 shown in FIG. 22(A) is equal to the width of the oxide insulating layer 426a in the direction parallel to the direction in which carriers flow. Also, FIG. 22 Note that the channel length L of the channel protection type thin film transistor 490 shown in FIG. 22(A) is equal to the width of the oxide insulating layer 426a in the direction parallel to the direction in which carriers flow. Also, FIG. 22 In the thin-film transistor 490 shown in (A), the width L3 in the channel length direction of the third region of the oxide semiconductor layer and the width L4 in the channel length direction of the fourth region are not necessarily the same, but the sum of the width L3 in the channel length direction of the third region and the width L4 in the channel length direction of the fourth region is a certain value. Also, as shown in FIG. 22(B), in the first to fifth regions 424a to 424e of the oxide semiconductor layer, a thin-film transistor 430 having a crystal region in the surface layer portion may be used. By adopting the configuration of the thin-film transistor 430 shown in FIG. 22(B), the on-current can be increased. Also, different thin-film transistors having configurations such as the thin-film transistors 430, 450, 470, or 490 may be formed on the same substrate. When the pixel portion and the drive circuit are formed on the same substrate, the thin-film transistor used in the pixel portion is required to have excellent switching characteristics, and the thin-film transistor used in the drive circuit preferably has a high operating speed. For example, as shown in FIG. 22(C), the thin-film transistor 430 may be disposed in the drive circuit portion, and the thin-film transistor 490 may be disposed in the pixel portion. Since the thin-film transistor 430 disposed in the drive circuit portion can increase the on-current, it is suitable for applications that require a large current driving ability. The thin-film transistor 490 disposed in the pixel portion can reduce the off-current. Therefore, when used as a switching element in the pixel portion, the contrast can be improved. Or, as shown in FIG. 22(D), the thin-film transistor 450 may be disposed in the drive circuit portion, and the thin-film transistor 470 having a low off-current may be disposed in the pixel portion.

[0113]

[0114] ​​​​​​​​​​​​​​​​However, the thin film transistor 430 may be arranged in the drive circuit section, and the thin film transistor 470 may be arranged in the pixel section, or the thin film transistor 450 may be arranged in the drive circuit section, and the thin film transistor 490 may be arranged in the pixel section.

[0115] In addition, in the thin film transistors 430, 450, 470, and 490 shown in this embodiment , the interface of the oxide semiconductor layer 423 in contact with the gate insulating layer 402 is amorphous or a mixture of amorphous and micro crystals, and at least the surface layer portion in contact with the oxide insulating layer 426a has a crystal region .

[0116] In an active matrix liquid crystal display device, a display pattern is formed on the screen by driving the pixel electrodes arranged in a matrix. Specifically, when a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, the optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as the display pattern .

[0117] In the video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there are problems such as afterimages and blurring of the video. In order to improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion, in which full-screen black display is performed every other frame.

[0118] In addition, by increasing the vertical synchronization frequency to 1.5 times, preferably 2 times or more of the normal value, the response speed is improved , and there is also a driving technique called so-called double-speed driving, in which the gradation to be written is selected for each of the plurality of fields divided within each frame.

[0119] In addition, in order to improve the video characteristics of a liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources, etc., and each light source that constitutes the surface light source is driven in an intermittent lighting manner independently within one frame period. As the surface light source three or more types of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. This driving technology can turn off the LEDs partially, so that particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. Since a plurality of LEDs can be controlled independently, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. This driving technology can turn off the LEDs partially, so that particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. By combining these driving technologies, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0120] By combining these driving technologies, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before. By combining these driving technologies, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0121] The n-channel type transistor obtained in this embodiment uses an In-Ga-Zn-O-based film in the channel formation region and has good dynamic characteristics, so these driving technologies can be combined. The n-channel type transistor obtained in this embodiment uses an In-Ga-Zn-O-based film in the channel formation region and has good dynamic characteristics, so these driving technologies can be combined. The n-channel type transistor obtained in this embodiment uses an In-Ga-Zn-O-based film in the channel formation region and has good dynamic characteristics, so these driving technologies can be combined.

[0122] In addition, when manufacturing a light emitting display device, one electrode (also called a cathode) of the organic light emitting element is set to a low power supply potential, for example, GND, 0V, etc., so a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion. In addition, when manufacturing a light emitting display device, one electrode (also called a cathode) of the organic light emitting element is set to a low power supply potential, for example, GND, 0V, etc., so a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc. is provided at the terminal portion. In addition, when manufacturing a light emitting display device, one electrode (also called a cathode) of the organic light emitting element is set to a low power supply potential, for example, GND, 0V, etc., so a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion. In addition, when manufacturing a light emitting display device, one electrode (also called a cathode) of the organic light emitting element is set to a low power supply potential, for example, GND, 0V, etc., so a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion.

[0123] Through the above steps, a thin film transistor with good electrical characteristics and high reliability and a display device using the thin film transistor can be provided.

[0124] The thin film transistor shown in this embodiment is a thin film transistor using an oxide semiconductor layer, and at least the surface layer portion of the channel formation region of the oxide semiconductor layer has a crystal region, and the other portions can be configured to be amorphous or a mixture of amorphous and microcrystals, and it can be a thin film transistor capable of suppressing the generation of parasitic channels.

[0125] Note that the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0126] (Embodiment 2) In this embodiment, an example of a manufacturing process of a display device different from that of Embodiment 1 will be described with reference to FIG. 6. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted.

[0127] First, a conductive film for forming a gate wiring including a gate electrode layer 421a, a capacitor wiring 421b, and a first terminal 421c is formed over the entire surface of a substrate 400 having an insulating surface by a sputtering method or a vacuum evaporation method. Next, after the conductive film is formed over the entire surface of the substrate 400, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (a gate wiring including a gate electrode layer 421a, a capacitor wiring 421b, and a first terminal 421c).

[0128] ​​​​​​​​​​​​Next, a gate insulating layer 402 is formed over the gate electrode layer 421a, the capacitor wiring 421b, and the first terminal 421c. An oxide semiconductor film 103 with a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 40 nm or less, is formed over the gate insulating layer 402. Note that the processes up to this point can be performed in the same manner as in Embodiment 1. Next, an oxide insulating film 105 is formed over the oxide semiconductor film 103 by a sputtering method. Then, a resist mask is formed by a second photolithography process, and selective etching is performed to form a contact hole reaching the first terminal 421c (FIG. 6(A)). The oxide insulating film 105 can be formed in the same manner as the oxide insulating film that becomes the oxide insulating layer 426a shown in Embodiment 1. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Here, the surface layer portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and has a dense crystal region 106 composed of nanocrystals.

[0129] Next, an oxide insulating film 105 is formed over the oxide semiconductor film 103 by a sputtering method. Then, a resist mask is formed by a second photolithography process, and selective etching is performed to form a contact hole reaching the first terminal 421c (FIG. 6(A)). The oxide insulating film 105 can be formed in the same manner as the oxide insulating film that becomes the oxide insulating layer 426a shown in Embodiment 1. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Here, the surface layer portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and has a dense crystal region 106 composed of nanocrystals. Here, the surface layer portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and has a dense crystal region 106 composed of nanocrystals.

[0130] Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process. Next, dehydration or dehydrogenation of the oxide semiconductor film 103 is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by an RTA treatment at 500°C or more and 750°C or less (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably about 650°C for 3 minutes or more and 6 minutes or less, using high-temperature nitrogen, an inert gas such as a rare gas, or light. By using the RTA treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be carried out even at a temperature exceeding the strain point of the glass substrate. Note that the heat treatment is not limited to this timing and may be performed a plurality of times before or after the photolithography process or the film formation process.

[0131] Here, the surface layer portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and has a dense crystal region 106 composed of nanocrystals. Here, the surface layer portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and has a dense crystal region 106 composed of nanocrystals. The other regions of 3 are amorphous, or an amorphous and microcrystalline mixture in which microcrystals are scattered in the amorphous region. Note that the crystal region 106 is part of the oxide semiconductor film 103. Hereinafter, the crystal region 106 shall be included in the notation of the oxide semiconductor film 103.

[0132] When lowering the temperature from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor film, it is important not to expose it to the atmosphere using the same furnace in which dehydration or dehydrogenation was performed, so as not to re-introduce water or hydrogen. Also, the gas atmosphere for lowering the temperature from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere when raising the temperature to the heating temperature T. For example, without exposing it to the atmosphere in the same furnace in which dehydration or dehydrogenation was performed, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) for cooling.

[0133] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0134] After the first heat treatment, the oxide semiconductor film 103 becomes oxygen-deficient and has a lower resistance. After the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10 18 / cm 3 or higher.

[0135] Next, a resist mask is formed by the third photolithography process and selectively etched. Etching is performed to form oxide insulating layers 426a, 426b, 426c, and 426d, and then the resist mask is removed (FIG. 6(B)). Here, the oxide insulating layer 426a functions as a channel protection layer of the thin film transistor. Also, in the oxide semiconductor film 103, the region overlapping with the oxide insulating layer 426a is the region that will

[0136] subsequently become the channel formation region. Next, a conductive film made of a metal material is formed on the oxide semiconductor film 103 and the oxide insulating layers 426a, 426b, 426c, and 426d by sputtering or

[0137] vacuum evaporation. As the material of the conductive film, the same material as that of the gate electrode layer 421a can be used. In this embodiment, a conductive film in which the first to third conductive films are stacked is formed. For example, titanium, which is a heat-resistant conductive material, is used for the first and third conductive films, and an aluminum alloy containing neodymium is used for the second conductive film. By adopting such a configuration, it is possible to reduce the generation of hillocks while taking advantage of the low resistivity of aluminum. Note that in this embodiment, a three-

[0138] layer structure composed of the first to third conductive films is adopted, but it is not limited to this, and a single-layer structure, a two-layer structure, or a structure with four or more layers may be adopted. For example, a single-layer structure of a In the method for manufacturing a thin film transistor according to this embodiment, an oxide insulating layer 426a that functions as a channel protection layer is provided in contact with a region that will become the channel formation region of the oxide semiconductor layer. Therefore, even when a conductive film is formed, at least in the channel formation region of the oxide semiconductor layer, a structure having a crystal region 106 in the surface layer portion can be obtained. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Also, in this fourth photolithography process, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Here, although not shown, the source wiring or drain wiring and the gate electrode of the thin film transistor of the drive circuit are directly connected through the same process as the above-described process. The resist mask 480a in this embodiment is a resist mask having a concave portion or a convex portion. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 480a, the thick region is called the convex portion of the resist mask, and the thin region is called the concave portion of the resist mask.

[0139] Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. Next, a fourth photolithography process is performed to form resist masks 480a and 480b, and unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429 (FIG. 6(C)). As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first and third conductive films and an aluminum alloy containing neodymium is used for the second conductive film, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant.

[0140] Also, in this fourth photolithography process, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Here, although not shown, the source wiring or drain wiring and the gate electrode of the thin film transistor of the drive circuit are directly connected through the same process as the above-described process. Also, in this fourth photolithography process, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Here, although not shown, the source wiring or drain wiring and the gate electrode of the thin film transistor of the drive circuit are directly connected through the same process as the above-described process. Also, in this fourth photolithography process, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Here, although not shown, the source wiring or drain wiring and the gate electrode of the thin film transistor of the drive circuit are directly connected through the same process as the above-described process. Also, in this fourth photolithography process, the connection electrode 429 is directly connected to the first terminal 421c of the terminal portion through a contact hole formed in the gate insulating layer. Here, although not shown, the source wiring or drain wiring and the gate electrode of the thin film transistor of the drive circuit are directly connected through the same process as the above-described process.

[0141] The resist mask 480a in this embodiment is a resist mask having a concave portion or a convex portion. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 480a, the thick region is called the convex portion of the resist mask, and the thin region is called the concave portion of the resist mask. The resist mask 480a in this embodiment is a resist mask having a concave portion or a convex portion. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 480a, the thick region is called the convex portion of the resist mask, and the thin region is called the concave portion of the resist mask. The resist mask 480a in this embodiment is a resist mask having a concave portion or a convex portion. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 480a, the thick region is called the convex portion of the resist mask, and the thin region is called the concave portion of the resist mask. The resist mask 480a in this embodiment is a resist mask having a concave portion or a convex portion. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 480a, the thick region is called the convex portion of the resist mask, and the thin region is called the concave portion of the resist mask.

[0142] In the resist mask 480a, convex portions are formed in the portions where the source electrode layer and the drain electrode layer will be formed later, and concave portions are formed in the peripheral portions of the subsequent island-shaped oxide semiconductor layer.

[0143] The resist mask shown in this embodiment can be formed by using a multi-tone mask. A multi-tone mask is a mask capable of performing exposure with multi-level light amounts, and typically refers to a mask that performs exposure with three levels of light amounts: an exposure region, a semi-exposure region, and a non-exposure region. By using a multi-tone mask, a resist mask having a plurality (typically two types) of thicknesses can be formed by one exposure and development process. Therefore, by using a multi-tone mask, the number of photomasks can be reduced.

[0144] By performing exposure and development using a multi-tone mask, resist masks 480a and 480b having regions with different thicknesses can be formed. However, it is not limited to this, and a resist mask may be formed without using a multi-tone mask.

[0145] After forming the conductive layer 425 and the connection electrode 429 using the resist masks 480a and 480b, the resist masks 480a and 480b are retracted (reduced) to form resist masks 482a, 482b, and 482c. To retract (reduce) the resist mask, ashing with oxygen plasma or the like may be performed. By retracting (reducing) the resist mask, the concave portion in the resist mask 480a disappears and is divided into the resist masks 482a and 482b. Also, between the resist mask 482a and the resist mask 4 The electrode layer 425 in the region sandwiched by 82b is exposed (not shown).

[0146] Next, using the resist masks 482a, 482b, and 482c, the exposed conductive layer 42 5 and a part of the connection electrode 429 are etched to form the source electrode 425a, the drain electrode 425b, and the island-shaped oxide semiconductor layer 423 (FIG. 6(D)).

[0147] In this etching process, a part of the oxide semiconductor film 103 is etched, and the third region 424c between the source electrode layer 425a and the oxide insulating layer 426a, and the fourth region 424d between the drain electrode layer 425 b and the oxide insulating layer 426a become regions thinner than the first region 424a overlapping with the source electrode layer 425a, the second region 424b overlapping with the drain electrode layer 425b, and the fifth region 424e overlapping with the oxide insulating layer 426a. Note that the fifth region 424e of the oxide semiconductor layer 423 is protected by the oxide insulating layer 426a and is not etched, so that a dense crystal region composed of nanocrystals exists at least in the surface layer portion of the channel formation region. In the channel formation region, the surface layer portion of the oxide semiconductor layer is on the back channel side, and this crystal region can suppress the parasitic channel. Note that the first region 424a and the second region 424b have the same film thickness as the fifth region 42 4e, which is the channel formation region. Next, an oxide insulating layer 428 covering the thin film transistor 410 is formed (FIG. 6(E)). The oxide insulating layer 428 is a silicon oxide film, a silicon oxynitride film obtained by a sputtering method or the like Note that the first region 424a and the second region 424b are the channel formation region and have the same film thickness as the fifth region 42

[0148] 4e which is the channel formation region. 4e has the same film thickness.

[0149] Next, an oxide insulating layer 428 covering the thin film transistor 410 is formed (FIG. 6(E)). The oxide insulating layer 428 is a silicon oxide film, a silicon oxynitride film obtained by a sputtering method or the like Oxide insulating layers such as silicon nitride films, aluminum oxide films, and tantalum oxide films can be used.

[0150] Next, a second heat treatment (preferably at 2 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Alternatively, an RTA treatment with high temperature and short time may be performed in the same manner as the first heat treatment. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor layer overlapping the oxide insulating layer are heated in a state of being in contact. Note that when the second heat treatment is performed, the oxide semiconductor layer 423 whose resistance has been reduced by the first heat treatment becomes in an oxygen-excessive state and can be made to have a higher resistance (type I).

[0151] In this embodiment, the second heat treatment is performed after the formation of the silicon oxide film. However, the timing of the heat treatment is not limited to immediately after the formation of the silicon oxide film, and there is no problem as long as it is after the formation of the silicon oxide film.

[0152] In addition, in a case where heat-resistant materials are used for the source electrode layer 425a and the drain electrode layer 425b, a process using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment can also be performed only once after the formation of the silicon oxide film.

[0153] A protective insulating layer may be formed on the oxide insulating layer 428. As the protective insulating layer, for example, a silicon nitride film can be formed using the RF sputtering method. The protective insulating layer does not contain impurities such as water, hydrogen ions, and OH - and uses an inorganic insulating film that blocks these from entering from the outside. Examples of the protective insulating layer include a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, and an aluminum oxynitride film. ​​​​​ Use a film such as a aluminum film. The protective insulating layer can also be formed continuously with the oxide insulating layer 428. It is also possible.

[0154] Next, perform the fifth photolithography process to form a resist mask, and form a contact hole reaching the drain electrode layer 425b by etching the oxide insulating layer 428. Also, a contact hole reaching the connection electrode 429 is formed by the etching here.

[0155] Next, after removing the resist mask, form a transparent conductive film. As the material of the transparent conductive film, indium oxide (In2O3), indium oxide - tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed with a hydrochloric acid - based solution. However, especially for the etching of ITO, residues are likely to occur, so indium oxide - zinc oxide alloy (In2O3 - ZnO) may be used to improve the etching processability.

[0156] Next, perform the sixth photolithography process to form a resist mask, and remove unnecessary portions by etching to form the pixel electrode layer 110.

[0157] Also, in this sixth photolithography process, using the gate insulating layer 402, the oxide semiconductor layer, the oxide insulating layer 426b, and the oxide insulating layer 428 in the capacitance portion as a dielectric, a holding capacitance is formed between the capacitance wiring 421b and the pixel electrode layer 110.

[0158] Also, in this sixth photolithography process, the first terminal 421c is used as a resist mask Cover with C and leave the transparent conductive film 128 formed on the terminal portion. The transparent conductive film 128 will be used as the electrode or wiring in the subsequent connection. Subsequently, it becomes the electrode or wiring to be used. The transparent conductive film 128 formed on the connection electrode 429 directly connected to the first terminal 421c functions as a connection terminal electrode that serves as the input terminal of the gate wiring. Also, although not shown, a connection terminal electrode that functions as the input terminal of the source wiring is also formed simultaneously. In this way, through six photolithography processes and using six photomasks, the channel protection type thin film transistor 410 and the holding capacitor portion can be completed. The thin film transistor shown in this embodiment is a thin film transistor using an oxide semiconductor layer. The surface layer portion of the channel formation region of the oxide semiconductor layer has a crystal region, and the other portions can be configured to be amorphous or a mixture of amorphous and microcrystalline. By having this configuration, the generation of parasitic channels can be suppressed, so that a thin film transistor and a display device with good electrical characteristics and high reliability can be fabricated.

[0159] Note that the configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used. (Embodiment 3)

[0160] In this embodiment, an example of fabricating at least a part of the driving circuit and the thin film transistor disposed in the pixel portion on the same substrate will be described below. The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or Embodiment 2.

[0161]

[0162]

[0163] (Embodiment 3) In this embodiment, an example of fabricating at least a part of the driving circuit and the thin film transistor disposed in the pixel portion on the same substrate will be described below. The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or Embodiment 2.

[0163] The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or Embodiment 2. In addition, the thin film transistor described in Embodiment 1 or Embodiment 2 is an n-channel type TF T. Therefore, in the driving circuit, a part of the driving circuit that can be configured by n-channel type TFTs is formed on the same substrate as the thin film transistor in the pixel portion.

[0164] An example of a block diagram of an active matrix display device is shown in Fig. 7(A). On the substrate 5300 of the display device, there are a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. In the pixel portion 5301, a plurality of signal lines are extended and arranged from the signal line driving circuit 5304, and a plurality of scanning lines are extended and arranged from the first scanning line driving circuit 5 302 and the second scanning line driving circuit 5303. Note that in the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC ) via a connection portion such as an FPC (Flexible Printed Cir cuit).

[0165] In Fig. 7(A), the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. Also the number of connections at the connection portion due to extending the wiring when the driving circuit is provided outside the substrate 5300 can be reduced, and the reliability or the yield can be improved.

[0166] Note that the timing control circuit 5305, for example, with respect to the first scanning line driving circuit 5302 Then, it supplies a start signal (GSP1) for the first scanning line driving circuit and a clock signal (GCK1) for the scanning line driving circuit. Also, the timing control circuit 5305 supplies, as an example, a start signal (GSP2) for the second scanning line driving circuit (also referred to as a start pulse) and a clock signal (GCK2) for the second scanning line driving circuit 5303. It supplies a start signal (SSP) for the signal line driving circuit, a clock signal (SCK) for the signal line driving circuit, data for the video signal (DATA) (simply also referred to as the video signal), and a latch signal (LAT) to the signal line driving circuit 5304. Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 53 03. In FIG. 7(B), a configuration is shown in which a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301. With this configuration, compared with a transistor using a single crystal semiconductor, a thin film transistor with a small field effect mobility can be used to configure the driving circuit formed on the substrate 5300. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in the number of processes, a reduction in cost, or an improvement in yield.

[0167] Also, the thin film transistor shown in Embodiment 1 or Embodiment 2 is an n-channel type TFT. FIGS. 8(A) and 8(B) show the configuration of a signal line driving circuit configured by n-channel type TFTs.

[0168] ​​​​​​​​​ An example of the formation and operation will be shown and described.

[0169] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits such as switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). An example where the thin film transistors 5603_1 to 5603_k are N-channel type TFTs will be described.

[0170] The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_ k are connected to the wiring 5605_1.

[0171] The shift register 5601 outputs signals of H level (also referred to as H signal , high power supply potential level) to the wirings 5605_1 to 5605_N in sequence, and has a function of selecting the switching circuits 5602_1 to 56 02_N in sequence.

[0172] The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of controlling whether to supply the potentials of the wirings 5604_ 1 to 5604_k to the signal lines S1 to Sk. ​​Thus, the switching circuit 5602_1 has a function as a selector. Also, the thin film transistors 5603_1 to 5603_k each have a function of controlling the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of supplying the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. Thus, the thin film transistors 56 03_1 to 5603_k each have a function as a switch.

[0173] Note that video signal data (DATA) is input to the wirings 5604_1 to 5604_k, respectively. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

[0174] Next, the operation of the signal line driving circuit in FIG. 8(A) will be described with reference to the timing chart in FIG. 8(B). FIG. 8(B) shows an example of signals Sout_1 to Sout_N and signals Vda ta_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata_k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row.

[0175] During the periods T1 to TN, the shift register 5601 outputs H-level signals to the wirings 560 5_1 to 5605_N in order. For example, during the period T1, the shift register 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0176] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the writing This can prevent under-crowding.

[0177] Note that the shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. Alternatively, a circuit including the thin film transistor described in Embodiment 2 can be used. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type. Alternatively, it may be constructed with only one polarity of the P-channel type.

[0178] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter, a buffer, etc. may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S P) is input to generate a selection signal. The generated selection signal is buffered The signal is buffered and amplified at the 10th line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on at the same time, so the buffer must be capable of passing a large current. is used.

[0179] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 9 and FIG.

[0180] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3) (see FIG. 9(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the A first clock signal CK1 is output from the first wiring 11, a second clock signal CK2 is output from the second wiring 12, and a third clock signal CK3 is output from the third wiring 13. The third wiring 13 transmits a third clock signal CK3, and the fourth wiring 14 transmits a fourth clock signal C In the first pulse output circuit 10_1, a start signal from the fifth wiring 15 is supplied. The first start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the previous stage (called the previous stage signal OUT(n-1)) (n is a natural number of 2 or more) is input. In the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, A signal is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, a signal (referred to as the subsequent stage signal OUT(n + 2 ) from the (n + 2)-th pulse output circuit 10_(n + 2) two stages later is input. Therefore, from each stage's pulse output circuit, a first output signal (OUT(1)(SR) to OUT )(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before, and a second output signal (OUT(1) to O UT(N)) electrically connected to another wiring or the like are output. As shown in FIG. 9(A), the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register. As an example, a second start pulse SP2 from a separate sixth wiring 16 and a third start pulse S P3 from a seventh wiring 17 may be respectively input. Or, it may be a signal generated separately inside the shift register. For example, a signal from the (n + 1)-th pulse output circuit 10 that does not contribute to the pulse output to the pixel section, the (n + 2)-th pulse output circuit 10 is provided (also referred to as a dummy stage), and a configuration may be adopted in which signals corresponding to the second start pulse (SP2) and the third start pulse (SP3) are generated from the dummy stage. Moreover, the clock signal (CK) is a signal that repeats H level and L level (also referred to as L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the (n+1) fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first (n+2) clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal is GCK according to the input driving circuit. Moreover, the clock signal (CK) is a signal that repeats H level and L level (also referred to as L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal is GCK according to the input driving circuit.

[0181] Moreover, the clock signal (CK) is a signal that repeats H level and L level (also referred to as L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal is GCK according to the input driving circuit. 4's clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal is GCK according to the input driving circuit. circuit is performed. Note that the clock signal is GCK according to the input driving circuit. 、Although it may also be referred to as SCK, it will be described as CK here.

[0182] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 ~ the fourth wiring 14. For example, in FIG. 9(A), In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11 and the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is connected to the third wiring 13 electrically, and the third input terminal 23 is electrically connected to the fourth wiring 14 and is.

[0183] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 9(B) ). In the first pulse output circuit 10_1, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the input terminal 23, a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, and a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27 and will be.

[0184] Next, an example of the specific circuit configuration of the pulse output circuit shown in FIG. 9(B) will be described with reference to FIG. 9(C ).

[0185] The pulse output circuit shown in FIG. 9(C) includes the first transistor 31 to the eleventh transistor 41. In addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the eleventh transistor 41. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 9(C) is such that the first power supply potential VDD is at a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is at a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals and are assumed to be VDD when at the H level and VSS when at the L level. By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, it is possible to suppress the shift of the threshold value of the transistor and suppress deterioration without affecting the operation and to keep the potential applied to the gate electrode of the transistor low . . . . . .

[0186] In FIG. 9(C), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39 . is connected, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34 The third transistor 33 has its first terminal electrically connected to the first input terminal 21, and its second terminal electrically connected to the first output terminal 26. The fourth transistor 34 has its first terminal electrically connected to the power supply line 53, and its second terminal electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power supply line 53, and its second terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 and its gate electrode electrically connected to the fourth input terminal 24. The sixth transistor 36 has its first terminal electrically connected to the power supply line 52, and its second terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 and its gate electrode electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power supply line 52, and its second terminal electrically connected to the second terminal of the eighth transistor 38 and its gate electrode electrically connected to the third input terminal 23 The eighth transistor 38 has its first terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 and its gate electrode electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminals of the first transistor 31 and the second transistor 32, and its second terminal electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40 and its gate electrode electrically connected to the power supply line 52. The tenth transistor The resistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. In FIG. 9(C), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A. Also, the connection point of the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is defined as node B (see FIG. 10(A)). Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source, having a channel region between the drain region and the source region, and capable of passing current through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure and operating conditions of the thin film transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, they may be denoted as the first terminal and the second terminal, respectively.

[0187]

[0188]

[0189] ​​​​​​​​​​​​​​​ Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 10B corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0190] As shown in FIG. 10A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0191] In the absence of the ninth transistor 39 having the gate electrode to which the second potential VCC is applied, the boot When the potential of the node A rises due to the strap operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, increases and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source, and the gate and drain are In addition, a large bias voltage is applied, which causes a large stress and leads to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing the transistor 39, the potential of the node A is set by the bootstrap operation. However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This makes it possible to suppress the deterioration of the transistor 31.

[0192] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0193] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor using an oxide semiconductor can be used. Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0194] The gate electrode of the seventh transistor 37 is connected to the third input terminal 23. A lock signal is supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38. The clock signal to be input to the gate electrode of the seventh transistor is provided by the second input terminal 22. A clock signal is supplied to the eighth gate electrode by the third input terminal 23. The same effect can be achieved by changing the wiring relationship so that the clock signal is In the shift register shown in (A), the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. On, then the seventh transistor 37 is off, and the eighth transistor 38 is off. By setting the input terminal 22 and the input terminal 23 in this state, the potentials of the second input terminal 22 and the third input terminal 23 are reduced. The drop in the potential of the node B is a drop in the potential of the gate electrode of the seventh transistor 37. , and occurs twice due to a drop in the potential of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. The seventh transistor 37 is off, the eighth transistor 38 is off, and the seventh transistor 39 is off. By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 are The drop in the potential of node B caused by the drop in the potential of The number of times the seventh transistor is turned on can be reduced by a drop in the potential of the seventh transistor. A clock signal is supplied to the gate electrode of the eighth transistor 37 from the third input terminal 23. The gate electrode of the second input terminal 22 is connected to the gate electrode of the second input terminal 23. This is because the number of times the potential of the node B changes is reduced, and noise is reduced. This is because it can be reduced.

[0195] In this way, by configuring such that a signal of H level is periodically supplied to node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, malfunction of the pulse output circuit can be suppressed. During the period when the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, a signal of H level is periodically supplied to node B, whereby malfunction of the pulse output circuit can be suppressed.

[0196] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It is assumed that they can be used in appropriate combination.

[0197] (Embodiment 4) The thin film transistors shown in Embodiments 1 and 2 can be fabricated, and a semiconductor device (also referred to as a display device) having a display function can be fabricated by using the thin film transistors in a pixel portion and further in a driving circuit. Also, a part or all of the driving circuit having the thin film transistors shown in Embodiments 1 and 2 can be integrally formed on the same substrate as the pixel portion to form a system on panel. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes, within its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, electronic ink or a display medium whose contrast changes by an electrical action can also be applied. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device, the element substrate is as follows.

[0198] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes, within its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, electronic ink or a display medium whose contrast changes by an electrical action can also be applied. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes, within its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, electronic ink or a display medium whose contrast changes by an electrical action can also be applied.

[0199]

[0199] Also, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device, the element substrate is as follows. , each of the plurality of pixels includes means for supplying current to the display element. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming the conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable.

[0200] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) attached module, a module provided with a printed wiring board at the tip of the TAB tape or TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method are all included in the display device.

[0201] In this embodiment, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11 is a top view of the panel in which the reliable thin film transistors 4010, 4011, and the liquid crystal element 4013 including the In-Ga-Zn-O-based film shown in Embodiments 1 and 2 as an oxide semiconductor layer on the first substrate 4001 are sealed with a sealing material 4005 between the second substrate 4006. FIG. 11(B) corresponds to the cross-sectional view taken along M-N in FIGS. 1 1(A1)(A2). The pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 are surrounded

[0202] In this way, the sealing material 4005 is provided. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006 . Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001 . Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method,

[0203] a wire bonding method, or a TAB method can be used. FIG. 11(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 11(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0204] Also, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 have a plurality of thin film transistors. In FIG. 11(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4020 and 402 1 are provided on the thin film transistors 4010 and 4011.

[0205] The thin film transistors 4010 and 4011 can be applied to the thin film transistors shown in highly reliable Embodiments 1 and 2 including an In-Ga-Zn-O-based film as an oxide semiconductor layer . In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. ​

[0206] Also, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Although not shown, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006.

[0207] As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0208] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. It is possible. By using the common connection portion, the counter electrode layer 40 can be electrically connected to the 31 and the common potential line through the conductive particles disposed between the pair of substrates. Note that the conductive particles are contained in the sealing material 4005. It is possible to electrically connect the 31 and the common potential line through the conductive particles disposed between the pair of substrates. Note that the conductive particles are contained in the sealing material 4005. 05.

[0209] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, and thus does not require alignment treatment, and has a small viewing angle dependence.

[0210] Note that this embodiment is an example of a transmissive liquid crystal display device, but the present invention can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device. Note that this embodiment is an example of a transmissive liquid crystal display device, but the present invention can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0211] Also, in the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate and a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided. Also, in the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate and a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided. Also, in the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate and a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided. Also, in the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate and a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided. Also, in the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate and a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light shielding film that functions as a black matrix may be provided.

[0212] Also, in this embodiment, in order to reduce the surface unevenness caused by the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in Embodiment 1 or 2 is used. The is covered with insulating layers (insulating layer 4020, insulating layer 4021) that function as a protective film or a planarization insulating film. The protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film may be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, as the first layer of the insulating layer 4020, a silicon oxide film is formed using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing hillock formation of the aluminum film used as the source electrode layer and the drain electrode layer. Also, an insulating layer is formed as the second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. Also, after forming the protective film, annealing (300 °C or higher and 400 °C or lower) of the oxide semiconductor layer may be performed. Also, an insulating layer 4021 is formed as the planarization insulating film. As the insulating layer 4021, acrylic

[0213]

[0214]

[0215]

[0216] Organic materials with heat resistance such as polyimide, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials. 4021 may be formed.

[0217] The siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group. The siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

[0218] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, annealing of the oxide semiconductor layer (300 °C or higher and 400 °C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device. spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, annealing of the oxide semiconductor layer (300 °C or higher and 400 °C or lower) may be performed simultaneously in the baking step. When forming the insulating layer 4021 using a material liquid, annealing of the oxide semiconductor layer (300 °C or higher and 400 °C or lower) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, it becomes possible to efficiently manufacture a semiconductor device.

[0219] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO). indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO). ​​Transparent materials such as indium zinc oxide and indium tin oxide added with silicon oxide can be used. Conductive materials can be used.

[0220] In addition, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less. As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0221] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018.

[0222]

[0223] In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010 and 4011.

[0224] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

[0225] ​​​​​​​In FIG. 11, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0226] FIG. 12 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by applying the TFTs shown in Embodiments 1 and 2.

[0227] FIG. 12 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to each of the red, green, and blue colors are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer.

[0228] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode. ​​​​​​​​​​​Switching mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. Alignment mode, PVA (Patterned Vertical Alignment nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0229] Through the above steps, a highly reliable liquid crystal display panel can be fabricated as a semiconductor device. can be fabricated.

[0230] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. shall be able to be used.

[0231] (Embodiment 5) In this embodiment, an example of electronic paper is shown as a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied. shall be able to be used.

[0232] FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. As the thin film transistor 581 used in the semiconductor device, the thin film transistors shown in Embodiments 1 and 2 can be applied. The thin film transistor shown in Embodiments 1 and 2 can be applied. can be applied.

[0233] The electronic paper in FIG. 13 is an example of a display device using the twist ball display method. The twist ball display method is a method in which spherical particles painted white and black are used in the electrode layer used for the display element. The twist ball display method is a method in which spherical particles painted white and black are used in the electrode layer used for the display element. A method of performing display by disposing between a first electrode layer and a second electrode layer and controlling the orientation of spherical particles by causing a potential difference between the first electrode layer and the second electrode layer. This is a method of performing display by disposing between a first electrode layer and a second electrode layer and controlling the orientation of spherical particles by causing a potential difference between the first electrode layer and the second electrode layer.

[0234] The thin film transistor 581 sealed between the substrate 580 and the substrate 596 has a bottom gate structure. The thin film transistor is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the source electrode layer or the drain electrode layer and the insulating layers 584 and 585. Between the first electrode layer 587 and the second electrode layer 588, there are provided spherical particles 589 including black regions 590a and white regions 590b and a cavity 594 filled with a liquid around them. The spherical particles 589 are provided with black regions 590a and white regions 590b and a cavity 594 filled with a liquid around them. The spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In the present embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 and 2, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates. connection portions shown in Embodiments 1 and 2, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates. connection portions shown in Embodiments 1 and 2, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates. connection portions shown in Embodiments 1 and 2, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates.

[0235] Alternatively, an electrophoretic element can be used instead of the twisted ball. Microcapsules having a diameter of 10 μm or more and 2 00 μm or less, which are filled with a transparent liquid, positively charged white fine particles, and negatively charged black fine particles, are used. The microcapsules provided between the first electrode layer and the second electrode layer are given an electric field by the first electrode layer and the second electrode layer, and the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. given an electric field by the first electrode layer and the second electrode layer, and the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. given an electric field by the first electrode layer and the second electrode layer, and the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, the power consumption is small, and it is possible to recognize the display portion even in a dim place. In addition, even when no power is supplied to the display portion, the image once displayed can be retained. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device including a display device) is separated from the radio wave transmission source, the displayed image can be saved.

[0236] As described above, a highly reliable electronic paper can be obtained as a semiconductor device.

[0237] Note that the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0238] (Embodiment 6) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied. As the display element included in the display device, a light-emitting element using electroluminescence is shown here. The light-emitting element using electroluminescence is classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0239] In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state. ​ When the excited state returns to the ground state, light is emitted. Based on such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0240] Inorganic EL elements are classified into distributed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Distributed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination light emission that utilizes a donor level and an acceptor level. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0241] FIG. 14 is a diagram showing an example of a pixel configuration applicable to digital time-graded driving as an example of a semiconductor device to which the present invention is applied.

[0242] The configuration and operation of a pixel applicable to digital time-graded driving will be described. Here, an example in which two n-channel transistors using an oxide semiconductor layer (In-Ga-Zn-O-based film) in the channel formation region, as shown in Embodiments 1 and 2, are used in one pixel is shown.

[0243] Pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor element 6403. The gate of the switching transistor 64 01 is connected to the scanning line 6406, one of the first electrodes (either the source electrode or the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (the other of the source electrode and the drain electrode) is connected to the driving It is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode connected to the power supply line 640 7, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to the common potential line formed on the same substrate. This connection part can be regarded as the common connection part. That's fine.

[0244] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential that satisfies the low power supply potential < high power supply potential with respect to the high power supply potential set on the power supply line 6407. For example, GND, 0V, etc. may be set as the low power supply potential. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or greater than the forward threshold voltage of the light-emitting element 6404. Each potential is set accordingly.

[0245] Note that the capacitive element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode. It may be formed.

[0246] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, fully on or fully off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. That is, the driving transistor 6402 operates in the linear region. That is, the driving transistor 6402 operates in the linear region. The driving transistor 6402 is operated in the linear region, so a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. In addition, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 14 can be used by changing the signal input. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0247] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 14 can be used by changing the signal input. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving.

[0248] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light emitting element 6404, thereby performing analog gradation driving.

[0249] Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 14. Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 14.

[0250] Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the case where the driving TFT is of the n-type will be taken as an example to describe the cross-sectional structure of the pixel. In FIGS. 15(A), (B), and (C) Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the case where the driving TFT is of the n-type will be taken as an example to describe the cross-sectional structure of the pixel. In FIGS. 15(A), (B), and (C) The TFTs 7001, 7011, and 7021, which are driving TFTs used in a semiconductor device, can be fabricated in the same manner as the thin-film transistors shown in Embodiments 1 and 2, and are highly reliable thin-film transistors including an In-Ga-Zn-O-based film as an oxide semiconductor layer. For the light-emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission structures that form thin-film transistors and light-emitting elements on a substrate and extract light from the surface opposite to the substrate, bottom emission structures that extract light from the surface on the substrate side, and double-sided emission structures that extract light from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present invention can be applied to light-emitting elements having any of these emission structures.

[0251] The light-emitting element will be described with reference to Fig. 15(A) for the case of a bottom emission structure. Fig. 15(A) shows a cross-sectional view of a pixel in the case where the driving TFT 7011 is of the n-type and light emitted from the light-emitting element 7012 is emitted to the side of the first electrode 7013. In Fig. 15(A), the first electrode 7013 of the light-emitting element 7012 is formed on a light-transmissive conductive film 7017 that is electrically connected to the drain electrode layer of the driving TFT 7011. The EL layer 7014 and the second electrode 7015 are sequentially stacked on the first electrode 7013. As the light-transmissive conductive film 7017, a light-transmissive conductive film such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon is added can be used.

[0252]

[0253]

[0254] ​​​​​​​​​​​​

[0255] Also, various materials can be used for the first electrode 7013 of the light-emitting element. For example, when the first electrode 7013 is used as a cathode, materials with a small work function, specifically, for example, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (such as Mg:Ag and Al:Li), as well as rare earth metals such as Yb and Er are preferable. In FIG. 15(A), the film thickness of the first electrode 7013 is set to a degree that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the first electrode 7013.

[0256] Note that after laminating and forming a transparent conductive film and an aluminum film, they may be selectively etched to form a transparent conductive film 7017 and the first electrode 7013. In this case, since etching can be performed using the same mask, it is preferable.

[0257] Also, the peripheral portion of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane to be formed. The partition wall 7019 is preferably formed using a photosensitive resin material to form an opening on the first electrode 70 13, and the side wall of the opening is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used as the partition wall 7019, the step of forming a resist mask can be omitted.

[0258] Also, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 may include at least a light-emitting layer, and may be composed of a single layer or may be configured such that a plurality of layers are laminated. Even if it is either one, it is acceptable. When the EL layer 7014 is composed of a plurality of layers, as the cathode An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole Injection layer are laminated in this order. Note that it is not necessary to provide all of these layers.

[0259] Also, it is not limited to the above lamination order. The first electrode 7013 functions as an anode, and the first electrode 7013 may be laminated with a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in this order. However, when comparing power consumption, it is preferable that the first electrode 7013 functions as a cathode, and the electron injection layer, the electron transport layer, the light-emitting layer, the hole transport layer, and the hole injection layer are laminated on the first electrode 7013 in this order. This can suppress the voltage rise of the drive circuit section and reduce the power consumption. Therefore, it is preferable.

[0260] Also, as the second electrode 7015 formed on the EL layer 7014, various materials can be used. For example, when the second electrode 7015 is used as an anode, materials with a large work function, such as ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO, ZnO are preferable. Also, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, etc. is used on the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015, and a Ti film is used as the shielding film 7016.

[0261] The region where the EL layer 7014 including the light-emitting layer is sandwiched between the first electrode 7013 and the second electrode 7015 corresponds to the light-emitting element 7012. In the case of the element structure shown in FIG. 15(A), the light emitted from the light-emitting element 7012 is emitted toward the first electrode 7013 side as indicated by the arrow.

[0262] ​ In FIG. 15A, the light emitted from the light emitting element 7012 is reflected by the color filter layer 7013. 7033, the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7060, and The light is then emitted through the substrate 7010.

[0263] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0264] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 15A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as an acrylic resin, and is colored. It has the function of flattening unevenness caused by the -filter layer 7033.

[0265] In addition, a protective insulating layer 7035 and an insulating layer 7032 are formed on the connecting electrode layer 7030. The contact hole is disposed at a position overlapping with the partition wall 7019 .

[0266] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0267] In FIG. 15B, a transparent TFT 7021 is electrically connected to the drain electrode layer of the driving TFT 7021. A first electrode 7023 of a light-emitting element 7022 is formed over a conductive film 7027 having the On the first electrode 7023, an EL layer 7024 and a second electrode 7025 are laminated in this order.

[0268] The light-transmitting conductive film 7027 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, silicon oxide A conductive film having translucency such as indium tin oxide to which iodine is added can be used.

[0269] Also, various materials can be used for the first electrode 7023. For example, when the first electrode 70 23 is used as a cathode, materials with a small work function, specifically, for example, alkali metals such as Li and Cs and alkaline earth metals such as Mg, Ca, Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and its film thickness is such that light can pass through it (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode. (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode. um film is used as the cathode.

[0270] Note that after laminating and forming a conductive film having translucency and an aluminum film, they may be selectively etched to form a conductive film 7027 having translucency and the first electrode 7023. In this case, etching can be performed using the same mask, which is preferable.

[0271] Also, the peripheral portion of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide , acrylic, polyamide, epoxy and other organic resin films, inorganic insulating films or organic polysiloxane ane. The partition wall 7029 is preferably formed using a photosensitive resin material, and an opening is formed on the first electrode 70 23, and the side wall of the opening is formed as an inclined surface having a continuous curvature and formed. When a photosensitive resin material is used as the partition wall 7029 , the step of forming a resist mask can be omitted.

[0272] Also, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 only needs to include at least a light-emitting layer, and it may be composed of a single layer or a plurality of layers may be stacked. When the EL layer 7024 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7023 that functions as a cathode. Note that it is not necessary to provide all of these layers. Also, it is not limited to the above stacking order. The first electrode 7023 may be used as an anode, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the anode. However,

[0273] when comparing power consumption, it is preferable to use the first electrode 7023 as a cathode and stack an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the cathode because the power consumption is lower.

[0274] Also, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, materials with a large work function, such as

[0275] transparent conductive materials such as ITO, IZO, and ZnO, can be preferably used. In this embodiment, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is formed.

[0275] The region sandwiching the EL layer 7024 including the light-emitting layer between the first electrode 7023 and the second electrode 7025 corresponds to the light-emitting element 7022. In the case of the element structure shown in Fig. 15(B), the light emitted from the light-emitting element 7022 is emitted to both the second electrode 7025 side and the first electrode 7023 side as indicated by the arrows.

[0276] In FIG. 15(B), the light emitted from the light-emitting element 7022 toward the first electrode 7023 side One of the lights passes through the color filter layer 7043, and passes through the insulating layer 7042, the oxide insulating layer 704 1, the gate insulating layer 7070, and the substrate 7020 and is emitted.

[0277] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography graphy technique, etc. respectively.

[0278] Further, the color filter layer 7043 is covered with an overcoat layer 7044, and is further covered with a protective insulating layer 7045.

[0279] Also, the contact holes formed in the protective insulating layer 7045 and the insulating layer 7042 and reaching the connection electrode layer 7040 are arranged at positions overlapping the partition wall 7029. However, when using a light-emitting element with a double-sided emission structure and both display surfaces are full-color displays,

[0280] Since the light from the second electrode 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate with a separate color filter layer above the second electrode 7025.

[0281] Next, the light-emitting element with the top emission structure will be described with reference to FIG. 15(C).

[0282] FIG. 15(C) shows a cross-sectional view of a pixel when the TFT 7001, which is a driving TFT, is of n-type and the light emitted from the light-emitting element 7002 escapes toward the second electrode 7005 side. In FIG. 15(C), the light-emitting element 7002 electrically connected to the drain electrode layer of the driving TFT 7001 ​​The first electrode 7003 is formed, and an EL layer 7004 and a second electrode 7005 are sequentially stacked on the first electrode 7003.

[0283] Also, various materials can be used for the first electrode 7003. For example, when the first electrode 70 03 is used as a cathode, materials with a small work function, specifically, for example, alkali metals such as Li and Cs and alkaline earth metals such as Mg, Ca, Sr, and alloys containing these (such as Mg:Ag, Al:Li), as well as rare earth metals such as Yb and Er are preferred.

[0284] Also, the EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 only needs to include at least a light-emitting layer, and it may be composed of a single layer or may be configured such that a plurality of layers are stacked. When the EL layer 7004 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7003 used as a cathode. Note that it is not necessary to provide all of these layers.

[0285] Also, it is not limited to the above stacking order, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the first electrode 7003 used as an anode.

[0286] In FIG. 15(C), a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are stacked in this order on a stacked film formed by stacking a Ti film, an aluminum film, and a Ti film in this order, and a stack of an Mg: A g alloy thin film and an ITO film is formed thereon.

[0287] However, when the TFT 7001 is of the n-type, an electron injection layer and an electron transport layer are formed on the first electrode 7003 、It is preferable to stack them in the order of the light-emitting layer, the hole transport layer, and the hole injection layer because it can suppress the voltage rise in the drive circuit and reduce the power consumption.

[0288] The second electrode 7005 is formed using a conductive material having translucency, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, or the like. A conductive film having translucency may be used.

[0289] The region where the EL layer 7004 including the light-emitting layer is sandwiched between the first electrode 7003 and the second electrode 7005 corresponds to the light-emitting element 7002. In the case of the element structure shown in FIG. 15(C), the light emitted from the light-emitting element 7002 is emitted toward the second electrode 7005 as indicated by the arrow.

[0290] Also, in FIG. 15(C), the drain electrode layer of the TFT 7001 is electrically connected to the first electrode 7003 through the contact holes provided in the oxide insulating layer 7051, the protective insulating layer 7052, and the insulating layer 7055. The planarization insulating layer 7053 can be formed using a resin material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the above resin materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), BPSG (borophosphorus glass), or the like can be used. Note that the planarization insulating layer 7053 may be formed by laminating a plurality of insulating films formed of these materials. The method for forming the planarization insulating layer 7053 is not particularly limited, and depending on the material, a sputtering method, an S The OG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, etc.), doctor knife, roll coater, curtain coater , knife coater, etc. can be used.

[0291] Also, in order to insulate the first electrode 7003 from the first electrodes 7003 of adjacent pixels, a partition wall 7009 is provided. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is preferably formed using a photosensitive resin material, by forming an opening on the first electrode 7003 such that the side wall of the opening becomes an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7009, the step of forming a resist mask can be omitted.

[0292] Also, in the structure of FIG. 15(C), when performing full-color display, for example, the light-emitting element 7002 is a green light-emitting element, one adjacent light-emitting element is a red light-emitting element, and the other light-emitting element is a blue light-emitting element. Moreover, a light-emitting display device capable of full-color display may be manufactured using four types of light-emitting elements including not only three types of light-emitting elements but also a white element.

[0293] Also, in the structure of FIG. 15(C), all of the plurality of light-emitting elements to be arranged are white light-emitting elements, and a sealing substrate having a color filter or the like is arranged above the light-emitting element 7002, and a light-emitting display device capable of full-color display may be manufactured. By forming a material that exhibits single-color light emission such as white, and combining a color filter and a color conversion layer, full-color display can be achieved.

[0294] Of course, a single-color light emission display may be performed. For example, an illumination device may be formed using white light emission or a light-emitting device of an area color type may be formed using single-color light emission.

[0295] Also, if necessary, an optical film such as a polarizing film such as a circular polarizing plate may be provided.

[0296] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0297] Note that an example in which a thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected has been shown, but a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be acceptable.

[0298] Note that the semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 15, and various modifications based on the technical idea of the present invention are possible.

[0299] Next, with respect to the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied, description will be given with reference to FIG. 16. FIG. 16(A) is a top view of the panel in which the thin film transistor and the light-emitting element formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 16(B) corresponds to a cross-sectional view taken along the line H-I in FIG. 16(A). is a cross-sectional view corresponding to the cross-sectional view taken along the line H-I in FIG. 16(A).

[0300] A pixel portion 4502, signal line driver circuits 4503a, 450 3b, and scanning line driver circuits 4504a, 4504b provided on the first substrate 4501 are surrounded by a sealing material 4505 is provided. Also, a second substrate 4506 is provided over the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b. Thus, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 45 04a and 4504b are sealed together with the filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it is highly airtight and not exposed to the outside air, and it is preferable to package (enclose) it with a protective film (laminated film, ultraviolet curable resin film, etc.) with little outgassing or a cover material.

[0301] Also, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of thin film transistors. In FIG. 16(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are exemplified.

[0302] The thin film transistors 4509 and 4510 can be applied to the thin film transistors shown in highly reliable Embodiments 1 and 2 including an In-Ga-Zn-O-based film as an oxide semiconductor layer. In this embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0303] A conductive layer 4540 is provided at a position overlapping the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit over the insulating layer 4544. By providing the conductive layer 4540 at a position overlapping the channel formation region of the oxide semiconductor layer, before and after the BT test ​​​​​​​​​​The change amount of the threshold voltage of the thin film transistor 4509 can be reduced. Also, the conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509, or may be different, and can also function as a second gate electrode layer. Further, the potential of the conductive layer 4 540 may be GND, 0V, or in a floating state.

[0304] Also, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is the pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the configuration shown in this embodiment. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511, etc.

[0305] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Particularly, using a photosensitive material, an opening is formed on the first electrode layer 4517, and it is preferably formed such that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0306] The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are stacked.

[0307] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0308] ​​​ Also, various signals and potentials applied to the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b , or the pixel section 4502 are supplied from the FPCs 4518a and 4518 b.

[0309] In this embodiment, the connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4 517 of the light emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4 510.

[0310] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519 .

[0311] The second substrate located in the light extraction direction of the light from the light emitting element 4511 must be translucent . In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0312] Also, as the filler 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler .

[0313] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element Yes. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, due to the unevenness of the surface The reflected light can be diffused, and an antiglare treatment that can reduce reflection can be performed.

[0314] The signal line drive circuits 4503a and 4503b and the scan line drive circuits 4504a and 4504b are implemented by drive circuits formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or only a part thereof may be separately formed and implemented, and the present embodiment is not limited to the configuration of FIG. 16. By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0315]

[0316] Note that the configurations shown in the present embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0317] (Embodiment 7) A semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied can be applied as an electronic paper. The electronic paper can be used in any field of electronic devices as long as it can display information. For example, using the electronic paper, it can be applied to electronic books (e-books), posters, in-vehicle advertisements on vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 17 and 18.

[0318] FIG. 17(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper print, the advertisement is replaced manually, but if electronic paper is used ​​​​​​​​​ can change the display of the advertisement in a short time. Also, a stable image can be obtained without the display being disrupted. Note that the poster may be configured to be able to transmit and receive information wirelessly.

[0319] Also, FIG. 17(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper print, the advertisement is exchanged manually, but if electronic paper is used the display of the advertisement can be changed in a short time without much manual effort. Also, a stable image can be obtained without the display being disrupted. Note that the in-vehicle advertisement may be configured to be able to transmit and receive information wirelessly.

[0320] Also, FIG. 18 shows an example of an e-book. For example, the e-book 2700 is composed of two housings, a housing 27 01 and a housing 2703. The housing 2701 and the housing 270 3 are integrated by a shaft portion 2711, and can perform an opening and closing operation around the shaft portion 2711. With such a configuration, it becomes possible to perform operations similar to those of a paper book.

[0321] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen, or may be configured to display different screens. When configured to display different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 18), and an image can be displayed on the left display unit (display unit 2707 in FIG. 18). (

[0322] Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit and the like is shown. For example, the housing 2 ​In 701, it is equipped with a power supply 2721, operation keys 2723, a speaker 2725, etc. . Pages can be sent by the operation keys 2723. Note that keys boards, pointing devices, etc. may be provided on the same surface as the display part of the housing. Also, on the back or side of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, etc. may be provided. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0323] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is possible to purchase and download desired book data, etc. from an electronic book server.

[0324] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0325] (Embodiment 8) The semiconductor device using the thin film transistor shown in Embodiment 1 or 2 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, a television device (also referred to as a TV or a television receiver), a monitor for a computer, etc., a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a pachinko machine and other large gaming machines, etc.

[0326] FIG. 19(A) shows an example of a television apparatus. The television apparatus 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605.

[0327] The operation of the television apparatus 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided on the remote control unit 9610, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control unit 9610.

[0328] Note that the television apparatus 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and can further be connected to a communication network by wire or wirelessly via the modem to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0329] FIG. 19(B) shows an example of a digital photo frame. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 970 3 can display various images, and can function in the same manner as a normal photo stand by displaying image data taken with, for example, a digital camera.

[0330] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals, various terminals connectable to various cables such as US B cables), a recording medium insertion part, etc., and has a configuration These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because the design property is improved. For example, an image data memory captured by a digital camera is inserted into the recording medium insertion part of the digital photo frame to capture the image data and display the captured image data on the display unit 9703.

[0331] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0332] FIG. 20(A) shows a portable game machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected in an openable and closable manner by a connecting part 9893. A display unit 9882 is incorporated in the casing 9881, and a display unit 9883 is incorporated in the casing 9891. Also, the portable game machine shown in FIG. 20(A) further includes a speaker part 9884, a recording medium insertion part 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable game machine is not limited to the above, and it may be a configuration including at least the semiconductor device related to the present invention, and other accessory equipment is appropriately provided It can. The portable gaming machine shown in Fig. 20(A) has functions such as reading programs or data recorded on a recording medium and displaying them on a display unit, and wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 20(A) are not limited to this, and it can have various functions. It reads the program or data recorded on the recording medium and displays it on the display unit, and has a function of sharing information by performing wireless communication with other portable gaming machines. Note that the functions of the portable gaming machine shown in Fig. 20(A) are not limited to this, and it can have various functions. It is not limited to this, and it can have various functions.

[0333] Fig. 20(B) shows an example of a slot machine, which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in the housing 9901. In addition, the slot machine 9900 is provided with other operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration having at least the semiconductor device according to the present invention, and other accessories may be appropriately provided. The slot machine 9900 has a display unit 9903 incorporated in the housing 9901. In addition, the slot machine 9900 is provided with other operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration having at least the semiconductor device according to the present invention, and other accessories may be appropriately provided. It is not limited to the above, and it may be a configuration having at least the semiconductor device according to the present invention, and other accessories may be appropriately provided. It can be a configuration in which other accessories are appropriately provided.

[0334] Fig. 21(A) shows an example of a mobile phone. The mobile phone 1000 includes an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc., in addition to a display unit 1002 incorporated in the housing 1001. In addition to the display unit 1002 incorporated in the housing 1001, the mobile phone 1000 shown in Fig. 21(A) includes an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc. It is provided with an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc.

[0335] For the mobile phone 1000 shown in Fig. 21(A), information can be input by touching the display unit 1002 with a finger or the like. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1002 with a finger or the like. For the mobile phone 1000 shown in Fig. 21(A), information can be input by touching the display unit 1002 with a finger or the like. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1002 with a finger or the like. It can be performed by touching the display unit 1002 with a finger or the like.

[0336] The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display... The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display... This is a display + input mode that combines the display mode and the input mode.

[0337] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0338] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0339] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0340] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0341] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. If a ring-shaped light source is used, it is also possible to image finger veins, palm veins, etc.

[0342] Figure 21(B) is also an example of a mobile phone. The mobile phone in Figure 21(B) has a housing 9411 , a display device 9410 including a display unit 9412 and operation buttons 9413, and a housing 9401 with operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting unit 9406 that emits light when receiving an incoming call. The display device 9410 having a display function is detachably attachable to the communication device 9400 having a telephone function in two directions indicated by arrows. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information through wireless communication or wired communication, and each has a rechargeable battery.

[0343] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0344] (Embodiment 9) In this embodiment, regarding the phenomenon of oxygen movement due to the contact between an oxide semiconductor layer and a metal layer (conductive layer) or an oxide insulating layer, the scientific calculation results of the difference between the case where the oxide semiconductor layer is amorphous and the case where it is crystalline will be explained.

[0345] Figure 24 shows the structure of a thin film transistor according to an aspect of the present invention. In the structure, the oxide semiconductor layer and the source ​​​- A schematic diagram of a state where a metal layer and an oxide insulating layer serving as a source electrode layer and a drain electrode layer are in contact exists. The arrow directions in the figure indicate the movement directions of oxygen in the state where they are in contact with each other or in the heated state.

[0346] When the type-I oxide semiconductor layer causes oxygen deficiency, it exhibits N-type conductivity. Conversely, an oxide semiconductor layer that has become N-type due to oxygen deficiency becomes type-I when an excessive amount of oxygen is supplied. In an actual device process, this effect is utilized. For the oxide semiconductor layer in contact with the metal layer serving as the source electrode layer and the drain electrode layer, oxygen is pulled towards the metal side, and a part of the contacted region (the entire thickness direction when the film thickness is thin) causes oxygen deficiency and becomes N-type, enabling good contact with the metal layer. Also, for the oxide semiconductor layer in contact with the oxide insulating layer, oxygen is supplied from the oxide insulating layer to the oxide semiconductor layer, and a part of the contacted region (the entire thickness direction when the film thickness is thin) becomes oxygen-excessive and type-I, functioning as the channel formation region of the thin-film transistor.

[0347] In one aspect of the present invention, a crystal region is formed in the region where the oxide semiconductor layer is in contact with the metal layer and the oxide insulating layer serving as the source electrode layer and the drain electrode layer, and the presence or absence of a difference in the oxygen movement form between the amorphous state and the crystal region was confirmed by scientific calculation. The model used for the scientific calculation was an amorphous and crystal structure of the In-Ga-Zn-O system, and one with 10% oxygen deficiency from one side region in the longitudinal direction of a rectangular parallelepiped was used (see Fig. 25). The calculation content

[0348] is to compare the oxygen distribution after 10 nsec under an acceleration condition of 650 °C. The respective conditions are shown in Table 1 and Table 2. ​​​​​​​​​​​​

[0349]

Table 1

[0350]

Table 2

[0351] Figure 26(A) shows the oxygen distribution when using amorphous material, and Figure 26(B) shows the oxygen distribution when using crystalline material. The dotted line represents the initial state, and the solid line represents the result (after 10 nsec). It can be seen from the change in the distribution that oxygen is moving regardless of

[0352] whether it is amorphous or crystalline. In the region with oxygen deficiency, the increase rate of oxygen atoms before and after the calculation was 15.9% for amorphous and 11.3% for crystalline. That is, oxygen moves more easily in amorphous than in crystalline, and the result is that it is easier to fill the oxygen deficiency. That is, relatively, oxygen moves less easily in crystalline than in amorphous.

[0353] Therefore, even in the structure where the oxide semiconductor layer in one aspect of the present invention has a crystalline region, it was confirmed that oxygen moves in the same way as when the oxide semiconductor layer is amorphous. Also, since oxygen moves relatively less easily in crystalline than in amorphous, it was confirmed that there is an effect of suppressing the desorption of oxygen from the oxide semiconductor layer.

Explanation of Reference Numerals

[0354] 400 Substrate 402 Gate Insulating Layer 410 Thin Film Transistor 411 Terminal 412 Connection Electrode 414 Terminal 415 Transparent Conductive Film 416 Electrode 418 Transparent Conductive Film 421a Gate Electrode Layer 421b Capacitor Wiring 421c Terminal 423 Oxide Semiconductor Layer 424a First Region 424b Second Region 424c Third Region 424d Fourth Region 424e Fifth Region 425a Source Electrode Layer 425b Drain Electrode Layer 426a Oxide Insulating Layer 426b Oxide Insulating Layer 428 Oxide Insulating Layer 429 Connection Electrode 430 Thin Film Transistor 450 Thin Film Transistor 456a Oxide Insulating Layer 470 Thin Film Transistor 480a Resist Mask 480b Resist Mask 482a Resist Mask 482b Resist Mask 482c Resist Mask 490 Thin Film Transistor

Claims

[Claim 1] a first gate electrode layer; a first gate insulating layer on the first gate electrode layer; a first oxide semiconductor layer on the first gate insulating layer; a first oxide insulating layer in contact with a portion of the first oxide semiconductor layer; a pixel portion having a first transistor including a first source electrode layer and a first drain electrode layer in contact with a part of the first oxide semiconductor layer; a driver circuit including a second transistor having a second oxide semiconductor layer; having a region of the first oxide semiconductor layer that is located between a region in contact with the first source electrode layer and a region in contact with the first oxide insulating layer and that is not in contact with the first oxide insulating layer, and a region between a region in contact with the first drain electrode layer and a region in contact with the first oxide insulating layer, the region that is not in contact with the first oxide insulating layer has a smaller thickness than a region overlapping with the first source electrode layer, a region overlapping with the first oxide insulating layer, and a region overlapping with the first drain electrode layer; the first oxide semiconductor layer has a region including nanocrystals; The display device, wherein the first oxide semiconductor layer and the second oxide semiconductor layer contain In, Ga, and Zn.

Images