Semiconductor device, method for manufacturing semiconductor device, and power conversion device

Abstract

To provide a semiconductor device which achieves both of reduction in conduction loss and reduction in recovery loss, and a manufacturing method of the same and a power conversion device.SOLUTION: A MOS control diode 1 includes: a semiconductor substrate having a first conductivity type drift layer 104; a second conductivity type anode layer 103 arranged on the drift layer and constituting a PN junction diode with the drift layer; a first conductivity type well layer 113 arranged on the anode layer; a second conductivity type lower concentration source layer 112 arranged on the well layer; a second conductivity type higher concentration source layer 111 arranged on a part of the lower concentration source layer; a gate electrode 101 adjacent to the anode layer, the well layer, and the lower concentration source layer via a gate oxide film 102, and constituting a MOSFET together with the anode layer, the well layer, and the lower concentration source layer; an insulation film 107 which covers the anode layer, the lower concentration source layer, the higher concentration source layer, and the gate electrode; and a contact hole 109 which penetrates the insulation film, the higher concentration source layer, the lower concentration source layer and the well layer.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor device, a method for manufacturing the same, and a power conversion device using the same, and particularly relates to a technique effective when applied to a MOS controlled diode in which a MOS control function is added to a pn diode.

Background Art

[0002] With the recent demands for energy conservation and the spread and expansion of renewable energy, many power conversion devices such as inverters and converters are used in a wide range of fields such as power, industry, transportation, and households. To realize a decarbonized society, the spread of these power conversion devices has become indispensable.

[0003] In an inverter for realizing energy conservation, electrical energy from a DC power supply Vcc is converted into AC of a desired frequency using an IGBT (Insulated Gate Bipolar Transistor), which is a type of power semiconductor device, to vary the rotational speed of a motor. A flywheel diode (freewheeling diode) is connected in antiparallel to the IGBT in the IGBT that can supply power of a desired frequency to the motor. To promote the spread of the inverter by making it more efficient, smaller, and less costly, it is necessary to reduce the conduction loss and switching loss of the flywheel diode as well as the IGBT.

[0004] In a power semiconductor device having a rated voltage of several hundred volts or more, generally, a pn diode using silicon that can increase conductivity by injecting charges is used for this flywheel diode in order to reduce the forward voltage drop.

[0005] Also, there is a Schottky diode as a diode in which charge injection is small and the reverse recovery current is extremely small with respect to the pn diode. However, in silicon, the forward voltage is large, and the loss increases in an inverter that handles a large current.

[0006] As a technique for reducing the conduction loss and recovery loss of a diode, a technique of connecting in parallel diodes having a switching function described in Patent Document 1 and Patent Document 2 is known.

[0007] The diode described in Patent Document 1 is configured with a structure in which a constantly-connected diode and a diode with a switch whose conduction / non-conduction can be controlled by a control gate are connected in parallel, and is composed of a constantly-connected diode part and a diode part added with a conduction / non-conduction control function by a vertical MOSFET switch composed of a trench-embedded gate, and the two are connected in parallel.

[0008] Also, the diode described in Patent Document 2 has a structure in which a constantly-connected diode and a diode with a switch whose conduction / non-conduction can be controlled by a control gate are connected in parallel, similar to the diode described in Patent Document 1, and is composed of a constantly-connected diode part and a diode part added with a conduction / non-conduction control function by a vertical MOSFET switch composed of a trench-embedded gate, and the two are connected in parallel.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] However, in the above Patent Document 1, since hole carriers are injected from the p-type anode auxiliary layer (204) in the diode portion that is constantly connected regardless of the gate voltage, even if the switched diode portion is turned off immediately before the recovery state, hole carriers in the cathode drift layer (202) remain. Due to the presence of these hole carriers, there is a limit to reducing the recovery current, and it has been difficult to improve the trade-off characteristics between the conduction loss and the recovery loss of such a diode with such a structure.

[0011] Also, in the above Patent Document 2, as shown in FIG. 1 of Patent Document 2, the thickness of the p + layer (high-concentration source layer) 16 is equal to that of the p layer (low-concentration source layer) 15, and since the p + layer 16 is in direct contact with the n layer (well layer) 14, holes are directly injected from the p + layer 16 into the n layer 14, and there is a risk of device breakdown due to the thyristor operation composed of the p + layer 16, the n layer 14, the p layer (anode layer) 13, and the n - layer (drift layer) 12.

[0012] Therefore, an object of the present invention is to provide a high-performance semiconductor device and a manufacturing method thereof, and a power conversion device using the same, in which both conduction loss reduction and recovery loss reduction are possible in a MOS-controlled diode obtained by adding a MOS control function to a pn diode.

Means for Solving the Problems

[0013] To solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate having a drift layer of a first conductivity type, a second conductivity type anode layer provided on the drift layer and forming a PN junction diode with the drift layer, a first conductivity type well layer provided on the anode layer, a second conductivity type low-concentration source layer provided on the well layer, a second conductivity type high-concentration source layer provided only on a part of the low-concentration source layer, a gate electrode adjacent to the anode layer, the well layer, and the low-concentration source layer via a gate oxide film and constituting a MOSFET together with the anode layer, the well layer, and the low-concentration source layer, an insulating film covering the anode layer, the low-concentration source layer, the high-concentration source layer, and the gate electrode, and a contact hole penetrating the insulating film, the high-concentration source layer, the low-concentration source layer, and the well layer. , the low-concentration source layer is disposed between the high-concentration source layer and the gate oxide film, and between the high-concentration source layer and the well layer. It is characterized by the above.

[0014] Also, a method for manufacturing a semiconductor device of the present invention is as follows. In the method for manufacturing a semiconductor device having the above characteristics, (a) A step of forming a second conductivity type anode layer on a semiconductor substrate having a first conductivity type drift layer; (b) a step of forming a first conductivity type well layer on the anode layer; (c) a step of forming a second conductivity type low-concentration source layer on the well layer; (d) a step of forming an insulating film on the low-concentration source layer and forming a contact hole in the insulating film by photolithography and dry etching; (e) a step of forming a second conductivity type high-concentration source layer only on a part of the low-concentration source layer by oblique ion implantation through the contact hole; and (f) a step of extending the contact hole by dry etching using the insulating film as a mask to penetrate the high-concentration source layer, the low-concentration source layer, and the well layer. It is characterized by including the above steps.

[0015] Also, a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having the above characteristics. (a) A step of forming a second conductivity type anode layer on a semiconductor substrate having a first conductivity type drift layer; (b) a step of forming a first conductivity type well layer on the anode layer; (c) a step of forming a second conductivity type low-concentration source layer on the well layer; (d) on the low-concentration source layerconstituting a part of the insulating film Forming a first insulating film, and forming a contact hole in the first insulating film by photolithography and dry etching; (e) forming a high-concentration source layer of a second conductivity type only in a part of the low-concentration source layer by vertical ion implantation through the contact hole; (f) forming a second insulating film on the high-concentration source layer, and thinning the second insulating film by dry etching to form an insulating film spacer in the contact hole constituting a part of the insulating film ; (g) extending the contact hole by dry etching using the first insulating film and the insulating film spacer as masks, and penetrating the high-concentration source layer, the low-concentration source layer, and the well layer. It is characterized by including the above steps.

[0016] In addition, the power conversion device of the present invention includes a pair of DC terminals, AC terminals equal in number to the number of phases of the AC output, and a switching leg equal in number to the number of phases of the AC output, in which a parallel circuit of a switching element and a diode connected in anti-parallel to the switching element is connected in series twice, and a gate circuit for controlling the switching element and the diode. The diode is a semiconductor device having the above characteristics.

Advantages of the Invention

[0017] According to the present invention, in a MOS-controlled diode in which a MOS control function is added to a pn diode, it is possible to realize a high-performance semiconductor device capable of achieving both low conduction loss and low recovery loss, a manufacturing method thereof, and a power conversion device using the same.

[0018] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

MODE FOR CARRYING OUT THE INVENTION

[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and detailed descriptions of overlapping portions are omitted.

[0021] In the following examples, an example in which the anode layer 103, the high-concentration source layer 111, and the low-concentration source layer 112 are formed of a p-type conductive layer, the drift layer 104, the cathode layer 105, and the well layer 113 are formed of an n-type conductive layer, and the MOSFET 3 is formed as a p-channel MOSFET will be described. However, the present invention is applicable even when they are formed with opposite conductivity types, and the same effects can be obtained.

EXAMPLE

[0022] With reference to FIGS. 1 to 4, the structure, operation, and manufacturing method of the semiconductor device according to Example 1 of the present invention will be described.

[0023] FIG. 1 is a cross-sectional view and an equivalent circuit diagram of the MOS controlled diode 1 of this embodiment. FIG. 2 is a diagram showing a manufacturing method of the MOS controlled diode 1 in FIG. 1. FIG. 3 is a diagram showing the forward characteristics of the MOS controlled diode 1 in FIG. 1. FIG. 4 is a diagram showing the relationship between the ratio (Ws / ds) of the width and thickness of the p+ source layer in the MOS controlled diode 1 in FIG. 1 and the forward voltage.

[0024] As shown in FIG. 1, the MOS controlled diode 1 of this embodiment includes an n - drift layer 104 which is a first conductivity type (n-type) drift layer, a P2 layer (anode layer) 103 of a second conductivity type (p-type) formed on the n - drift layer 104, an n-well layer 113 which is a first conductivity type (n-type) well layer formed on the P2 layer 103, a P1 layer (low-concentration source layer) 112 of a second conductivity type formed on the n-well layer 113, and a high-concentration source p + layer 111 formed on a part of the P1 layer 112. The n - drift layer 104 is an n - type semiconductor substrate.

[0025] In the P2 layer 103, a plurality (two in FIG. 1) of trench gates 101 which are embedded type gate electrodes are formed via a gate oxide film 102.

[0026] On the trench gate 101, the gate oxide film 102, the high-concentration source p + layer 111, and the P1 layer 112, an insulating oxide film 107 is formed so as to cover them.

[0027] An anode electrode 108 is formed on the insulating oxide film 107.

[0028] On the other hand, on the lower layer side of the n - drift layer 104, that is, on the side opposite to the side where the P2 layer 103 is formed, an n + layer (cathode layer) 105 is formed, and a cathode electrode 106 is further formed on the lower layer thereof.

[0029] n-well layer 113, P1 layer 112, high-concentration source p + layer 111, an insulating oxide film 107 is formed with a contact hole 109 that penetrates these and reaches the P2 layer 103. Inside the contact hole 109, a metal material such as aluminum (Al) or tungsten (W) is embedded to form a contact. Through the contact, the anode electrode 108 and the high-concentration source p + layer 111, P1 layer 112, n-well layer 113 and P2 layer 103 are electrically connected.

[0030] Here, the high-concentration source p + The width Ws measured from the contact hole 109 of the layer 111 is such that it is at least 1 / 2 of the thickness ds of the high-concentration source p + layer 111. Also, the width Ws measured from the contact hole 109 of the high-concentration source p+ layer 111 is configured to be equal to or less than the thickness ds of the high-concentration source p+ layer 111.

[0031] Using the equivalent circuit diagram shown on the right side of FIG. 1, the operating principle and effects of the MOS-controlled diode 1 of this embodiment will be described.

[0032] In the equivalent circuit diagram of FIG. 1, the pn diode 2 is composed of the P2 layer 103 and the n - drift layer 104, the p-channel MOSFET 3 is composed of the P2 layer 103, P1 layer 112 and n-well layer 113, the p-type Schottky diode 4 is composed of the P2 layer 103 and the contact hole 109, the n-type Schottky diode or pn diode 5 is composed of the contact hole 109 and the n-well layer 113, p + source resistance 6 corresponds to the high-concentration source p + layer 111 and P1 layer 112 respectively.

[0033] When a positive potential is applied to the anode electrode 108 (anode A), a negative potential is applied to the cathode electrode 106 (cathode K), and a negative potential with respect to the potential of the anode electrode 108 (anode A) is applied to the trench gate 101 (gate G), a p-channel is formed on the surface of the gate oxide film 102 side of the P1 layer 112, the n-well layer 113, and the P2 layer 103, and the p-channel MOSFET composed of the P1 layer 112, the n-well layer 113, and the P2 layer 103 conducts.

[0034] Then, the P2 layer 103 and n - drift layer 104 is forward-biased, and a large amount of holes from the P2 layer 103 are injected into the n - drift layer 104. The n - holes injected into the drift layer 104 promote the injection of electrons from the n + layer 105, and the n - drift layer 104 becomes a state in which a large amount of holes and electrons are accumulated, and conductivity modulation occurs with low resistance. As a result, the forward voltage decreases and the conduction loss is reduced.

[0035] On the other hand, when a negative potential is applied to the anode electrode 108 (anode A), a positive potential is applied to the cathode electrode 106 (cathode K), and when reverse recovery is performed in the blocking state, the potential of the trench gate 101 (gate G) is set to the same potential or a positive potential with respect to the potential of the anode electrode 108 (anode A) immediately before reverse recovery, and the p-channel MOSFET is turned off.

[0036] Thereby, the injection of holes from the P2 layer 103 is suppressed, and the accumulated charges of holes and electrons in the n-drift layer 104 are reduced. After that, when reverse recovery is performed, the reverse recovery current is reduced and the reverse recovery loss is also reduced. At this time, the potential of the cathode electrode 106 (cathode K) rises rapidly to a high voltage, and dv / dt is applied.

[0037] In the MOS controlled diode 1 of this embodiment, since the gate oxide film 102 is surrounded by the P2 layer 103, the n-well layer 113, and the P1 layer 112 that are substantially equal to the potential of the anode electrode 108, displacement current due to dv / dt does not flow into the trench gate 101, and the gate potential is stable. As a result, the gate potential can be maintained at the same potential or a positive potential with respect to the potential of the anode electrode 108.

[0038] Therefore, gate oxide film breakdown at high dv / dt can be prevented.

[0039] Thus, the MOS controlled diode 1 of this embodiment controls the potential of the trench gate 101 with respect to the anode electrode 108 to turn on / off the p-channel MOSFET composed of the P1 layer 112, the n-well layer 113, and the P2 layer 103, enabling reduction of conduction loss and reverse recovery loss.

[0040] Here, if holes are directly injected from the high-concentration source p + layer 111, the thyristor composed of the high-concentration source p + layer 111, the n-well layer 113, the P2 layer 103, the n - drift layer 104, and the n + layer 105 operates, and there is a possibility of device breakdown or loss of controllability.

[0041] To suppress the direct injection of holes from the high-concentration source p + layer 111, it is effective to arrange the P1 layer 112 with low hole injection efficiency between the high-concentration source p + layer 111 and the gate oxide film 102, and between the high-concentration source p + layer 111 and the n-well layer 113, and connect between the high-concentration source p + layer 111 and the gate oxide film 102, and between the high-concentration source p + layer 111 and the n-well layer 113 via the P1 layer 112 with low hole injection efficiency.

[0042] Also, the high-concentration source p +Layer 111 is in contact with the anode electrode 108 through a barrier metal (not shown) embedded in the contact hole 109, and forms part of the source resistance of the p-channel MOSFET. Therefore, to reduce conduction loss, it is necessary to reduce the resistance of the high-concentration source p + layer 111. To reduce the resistance of the high-concentration source p + layer 111, there are a method of increasing the concentration and a method of adjusting the shape and dimensions.

[0043] Figure 3 shows the forward characteristics of the MOS-controlled diode 1 in FIG. 1. The horizontal axis in FIG. 3 indicates the forward voltage FV between the anode (A) and the cathode (K), and the vertical axis indicates the forward current FC flowing through the anode (A). V GA is the applied voltage between the gate (G) and the anode (A). Also, reference numeral 8 indicates the forward characteristics of the present invention, and reference numeral 9 indicates the forward characteristics of the prior art.

[0044] As shown in FIG. 3, by setting the ratio (Ws / ds) of the width Ws to the thickness ds of the high-concentration source p+ layer 111 measured from the contact hole 109 to 1 / 2 or more, the conduction loss can be reduced due to the effect of reducing the source resistance.

[0045] Figure 4 shows the ratio (Ws / ds) of the width Ws to the thickness ds of the high-concentration source p + layer 111 and the results of examining the forward voltage, measured from the contact hole 109 that penetrates the layer 111, the P1 layer 112, and the n-well layer 113. + layer 111, provided in the P1 layer 112 by the inventors of the present application.

[0046] As shown in FIG. 4, the larger the ratio (Ws / ds) of the width Ws to the thickness ds of the high-concentration source p + layer 111, the more the forward voltage FV can be reduced, and the forward direction can be stably reduced when it is 1 / 2 or more.

[0047] The manufacturing method of the MOS-controlled diode 1 in FIG. 1 will be described with reference to FIG. 2.

[0048] First, as shown in Fig. 2(a), a semiconductor substrate for fabricating the MOS controlled diode 1 is prepared. In this embodiment, an n-type Si wafer having an n - drift layer 104 is used. - Here, a wafer having a specific resistance corresponding to the breakdown voltage can be used for the Si wafer. For example, for a diode with a breakdown voltage of 1.2 kV, it can be about 50 - 60 Ωcm, and for a diode with a breakdown voltage of 3.3 kV, it can be about 250 - 300 Ωcm, and the n

[0049] drift layer 104 is formed. - In the first step (not shown), a silicon oxide film is formed on the entire surface of the Si wafer by thermal oxidation. Next, the trench formation region is patterned with a resist in a photolithography process. Using the resist as a mask, the silicon oxide film is etched by dry etching, and then Si is processed by dry etching using the silicon oxide film as a mask to form a trench. After that, a gate oxide film 102 is formed on the entire surface of the Si wafer including the inside of the trench by thermal oxidation, and then a polysilicon (Poly-Si) film is deposited to fill the inside of the trench and processed by dry etching to form a trench gate 101.

[0050] Subsequently, as shown in Fig. 2(b), the active region of the diode is patterned with a resist in a photolithography process, and boron ions are implanted to form a P2 layer 103. Next, using the photolithography process for resist patterning, phosphorus (P) ions are implanted to form an n-well layer 113, and further boron (B) ions are implanted to form a P1 layer 112.

[0051] Subsequently, as shown in Fig. 2(c), after depositing an insulating oxide film 107, it is patterned with a resist in a photolithography process, the insulating oxide film 107 is etched, and boron (B) ion implantation is performed using the insulating oxide film 107 as a mask to form a high-concentration source p

[0052] layer 111. At this time, the high-concentration source p + layer 111 is formed.+ Layer 111 is formed in the P1 layer 112 using oblique ion implantation 7.

[0053] For source resistance reduction, the high-concentration source p provided in the P1 layer 112 + The width Ws of layer 111, measured from the contact hole 109, which will be described later, that penetrates layer 111, the P1 layer 112, and the n-well layer 113, of the high-concentration source p + The width Ws of layer 111 of the high-concentration source p + The tilt angle of the oblique ion implantation 7 is adjusted so that the width Ws of layer 111 is at least 1 / 2 of the thickness ds of the high-concentration source p layer 111. Preferably, a tilt angle of 27° or more is effective for source resistance reduction. However, since the oblique ion implantation 7 is performed through the contact hole formed in the insulating oxide film 107, the upper limit of the tilt angle of the oblique ion implantation 7 is about 45°. When the tilt angle of the oblique ion implantation 7 is 45°, the width Ws of the high-concentration source p layer 111 measured from the contact hole 109 + The ratio (Ws / ds) of the width Ws to the thickness ds of layer 111 of the high-concentration source p is 1.

[0054] Subsequently, as shown in Fig. 2(d), using the insulating oxide film 107 as a mask, the contact hole 109 is processed by dry etching until it reaches the P2 layer 103.

[0055] Thereafter, as shown in Fig. 2(e), a barrier metal (for example, a laminated structure of Ti / TiN) is formed by sputtering on the entire surface of the insulating oxide film 107 including the inside of the contact hole 109, and then a metal material such as tungsten (W) is deposited so as to fill the inside of the contact hole 109. After filling the inside of the contact hole 109, planarization is performed by etch-back. Subsequently, a metal material (for example, AlSi) is formed by sputtering on the entire surface of the insulating oxide film 107, resist patterning is performed in a photolithography process, and the anode electrode 108 is processed using the resist as a mask.

[0056] Subsequently, as shown in Fig. 2(f), after grinding the back surface of the Si wafer to the desired wafer thickness for each breakdown voltage, phosphorus (P) is ion-implanted from the back surface side and activated by laser annealing to form an n +Layer 105 is formed. The thickness of the wafer is preferably about 90 to 120 μm for a diode with a breakdown voltage of, for example, 1.2 kV, and about 330 to 400 μm for a diode with a breakdown voltage of 3.3 kV. Finally, the cathode electrode 106 is formed by sputtering, and the MOS controlled diode 1 is completed.

[0057] Thus, in the MOS controlled diode in which the MOS control function is added to the pn diode, it is possible to achieve both reduction of conduction loss and reduction of recovery loss.

Example

[0058] With reference to FIGS. 5 and 6, the structure and manufacturing method of the semiconductor device according to Example 2 of the present invention will be described.

[0059] FIG. 5 is a cross-sectional view and an equivalent circuit diagram of the MOS controlled diode 1 of this example. FIG. 6 is a diagram showing the manufacturing method of the MOS controlled diode 1 of FIG. 5.

[0060] The MOS controlled diode 1 of this example is different from the MOS controlled diode 1 of Example 1 (FIG. 1) in that, as shown in FIG. 5, an insulating film spacer 110 having a sidewall shape with a narrower lower surface than the upper surface is provided on the sidewall of the contact hole 109 provided in the insulating oxide film 107. That is, the contact hole 109 has a sidewall shape with a narrower lower surface than the upper surface. Other configurations are the same as those of Example 1 (FIG. 1) including the point that the ratio (Ws / ds) of the width Ws to the thickness ds of the high-concentration source p + layer 111 is 1 / 2 or more.

[0061] Using FIG. 6, the manufacturing method of the MOS controlled diode 1 of FIG. 5 will be described. Since (a) and (b) of FIG. 6 are the same as (a) and (b) of FIG. 2, the description thereof will be omitted.

[0062] After forming the trench gate 101, n-well layer 113, and P1 layer 112, as shown in FIG. 6(c), after depositing the insulating oxide film 107, it is resist-patterned in a photolithography process. After etching the insulating oxide film 107, boron (B) ion implantation is performed using the insulating oxide film 107 as a mask to form a high-concentration source p + layer 111. At this time, the high-concentration source p + layer 111 is formed in the P1 layer 112 using vertical ion implantation 10.

[0063] Subsequently, as shown in FIG. 6(d), an insulating film (e.g., TEOS film or SiN film) is deposited and then etched back by dry etching to form an insulating film spacer 110. Thereafter, the contact hole 109 is processed by dry etching until it reaches the P2 layer 103 using the insulating oxide film 107 and the insulating film spacer 110 as masks.

[0064] Thereafter, as shown in FIG. 6(e), a barrier metal (e.g., a stacked structure of Ti / TiN) is formed by sputtering on the entire surface of the insulating oxide film 107 including the inside of the contact hole 109 and the insulating film spacer 110, and then a metal material such as tungsten (W) is deposited so as to fill the inside of the contact hole 109 and the insulating film spacer 110. After filling the inside of the contact hole 109 and the insulating film spacer 110, planarization is performed by etch-back. Subsequently, a metal material (e.g., AlSi) is formed by sputtering on the entire surface of the insulating oxide film 107, and then resist-patterning is performed in a photolithography process, and the anode electrode 108 is processed using the resist as a mask.

[0065] Subsequently, as shown in FIG. 6(f), after grinding the back surface of the Si wafer to a desired wafer thickness for each breakdown voltage, phosphorus (P) is ion-implanted from the back surface side and activated by laser annealing to form an n + layer 105. The thickness of the wafer is preferably about 90 - 120 μm for a diode with a breakdown voltage of, for example, 1.2 kV, and about 330 - 400 μm for a diode with a breakdown voltage of 3.3 kV. Finally, the cathode electrode 106 is formed by sputtering, and the MOS controlled diode 1 is completed.

[0066] In this embodiment, due to the insulating film spacer 110, the high-concentration source p provided in the P1 layer 112 + The width Ws of the high-concentration source p layer 111 measured from the contact hole 109 that penetrates the p layer 111, the P1 layer 112, and the n-well layer 113 + is equal to or greater than 1 / 2 of the thickness ds of the high-concentration source p layer 111, reducing the forward voltage and achieving stable characteristics. Also, different from the manufacturing method of Example 1, the degree of freedom to adjust the ratio (Ws / ds) of the width Ws to the thickness ds of the high-concentration source p layer 111 measured from the contact hole 109 is high, and it is also possible to make it greater than 1. + In the manufacturing method by the oblique ion implantation 7 of Example 1 (FIG. 2), as the aspect ratio of the contact portion due to device miniaturization progresses, it is shielded by the insulating oxide film 107, and there is a limit to the formation of the high-concentration source p layer 111. However, in this embodiment (FIG. 6), vertical ion implantation 10 is performed, and the contact hole 109 is formed using the insulating film spacer 110. Therefore, the high-concentration source p layer 111 can be formed self-aligned with the contact hole 109 even in the case of a high aspect ratio. + In the manufacturing method by the oblique ion implantation 7 of Example 1 (FIG. 2), as the aspect ratio of the contact portion due to device miniaturization progresses, it is shielded by the insulating oxide film 107, and there is a limit to the formation of the high-concentration source p layer 111. However, in this embodiment (FIG. 6), vertical ion implantation 10 is performed, and the contact hole 109 is formed using the insulating film spacer 110. Therefore, the high-concentration source p layer 111 can be formed self-aligned with the contact hole 109 even in the case of a high aspect ratio.

[0067] In the manufacturing method by the oblique ion implantation 7 of Example 1 (FIG. 2), as the aspect ratio of the contact portion due to device miniaturization progresses, it is shielded by the insulating oxide film 107, and there is a limit to the formation of the high-concentration source p layer 111. However, in this embodiment (FIG. 6), vertical ion implantation 10 is performed, and the contact hole 109 is formed using the insulating film spacer 110. Therefore, the high-concentration source p layer 111 can be formed self-aligned with the contact hole 109 even in the case of a high aspect ratio. + In the manufacturing method by the oblique ion implantation 7 of Example 1 (FIG. 2), as the aspect ratio of the contact portion due to device miniaturization progresses, it is shielded by the insulating oxide film 107, and there is a limit to the formation of the high-concentration source p layer 111. However, in this embodiment (FIG. 6), vertical ion implantation 10 is performed, and the contact hole 109 is formed using the insulating film spacer 110. Therefore, the high-concentration source p layer 111 can be formed self-aligned with the contact hole 109 even in the case of a high aspect ratio. + In the manufacturing method by the oblique ion implantation 7 of Example 1 (FIG. 2), as the aspect ratio of the contact portion due to device miniaturization progresses, it is shielded by the insulating oxide film 107, and there is a limit to the formation of the high-concentration source p layer 111. However, in this embodiment (FIG. 6), vertical ion implantation 10 is performed, and the contact hole 109 is formed using the insulating film spacer 110. Therefore, the high-concentration source p layer 111 can be formed self-aligned with the contact hole 109 even in the case of a high aspect ratio.

Example

[0068] With reference to FIG. 7, a semiconductor device according to Embodiment 3 of the present invention will be described. FIG. 7 is a cross-sectional view of the MOS controlled diode 1 of this embodiment.

[0069] The MOS controlled diode 1 of this embodiment has a side gate structure in which a gate electrode is provided on the side surface of a semiconductor substrate, as shown in FIG. 7. The side gate 201 is adjacent to the P2 layer 103, the n-well layer 113, and the P1 layer 112 through a gate oxide film 102 having a substantially L-shaped cross section, and the upper width is formed narrower than the lower width.

[0070] The area of the semiconductor substrate facing the side gate 201 is approximately half that of the trench gate 101 in Example 2 (Figure 5), and the gate capacitance is also approximately half. As a result, the driving of the gate is facilitated. Also, this structure can be configured in the same manner as in Example 2 in Example 1 as well.

Example

[0071] Referring to Figure 8, a power conversion device according to Example 4 of the present invention will be described. Figure 8 is a circuit diagram showing a schematic configuration of the power conversion device of this example. Figure 8 shows an example of the circuit configuration of the power conversion device 500 and the connection relationship between a DC power supply and a three-phase AC motor (AC load).

[0072] In the power conversion device 500 of this example, for example, the MOS control diode 1 of Example 1 is used as diodes 521 to 526. 501 to 506 are power switching elements.

[0073] As shown in Figure 8, the power conversion device 500 of this example includes a pair of DC terminals, a P terminal 531 and an N terminal 532, and AC terminals, a U terminal 533, a V terminal 534, and a W terminal 535, the number of which is the same as the number of phases of the AC output.

[0074] Also, it includes a switching leg composed of a series connection of a pair of power switching elements 501 and 502, and having the U terminal 533 connected to the series connection point as an output. Also, it includes a switching leg composed of a series connection of power switching elements 503 and 504 having the same configuration, and having the V terminal 534 connected to the series connection point as an output. Also, it includes a switching leg composed of a series connection of power switching elements 505 and 506 having the same configuration, and having the W terminal 535 connected to the series connection point as an output.

[0075] The three-phase switching leg composed of power switching elements 501 to 506 is connected between the DC terminals of the P terminal 531 and the N terminal 532, and DC power is supplied from a DC power source (not shown). The U terminal 533, V terminal 534, and W terminal 535, which are the three-phase AC terminals of the power conversion device 500, are connected to a three-phase AC motor (not shown) as a three-phase AC power source.

[0076] Diodes 521 to 526 are connected in anti-parallel to the power switching elements 501 to 506 respectively. Gate circuits 511 to 516 are connected to the input terminals of the respective gates of the power switching elements 501 to 506 and the input terminals of the respective gates of the diodes 521 to 526 each composed of the MOS control diode 1. The power switching elements 501 to 506 and the diodes 521 to 526 are respectively controlled by the gate circuits 511 to 516. Note that the gate circuits 511 to 516 are comprehensively controlled by a central control circuit (not shown).

[0077] By the gate circuits 511 to 516, the power switching elements 501 to 506 and the diodes 521 to 526 are appropriately and comprehensively controlled, and the DC power of the DC power source Vcc is converted into three-phase AC power and output from the U terminal 533, V terminal 534, and W terminal 535.

[0078] By applying the MOS control diode 1 of Examples 1 to 3 to the power conversion device 500 of this example, it is possible to provide a power conversion device with a low on-voltage and low switching loss.

[0079] Note that the present invention is not limited to the above-described examples, and various modifications are included. For example, the above-described examples have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one example can be replaced with the configuration of another example, and the configuration of another example can be added to the configuration of one example. Further, for a part of the configuration of each example, addition, deletion, or replacement with other configurations is possible.

Explanation of Reference Numerals

[0080] 1…MOS control diode 2…pn diode 3…p-channel MOSFET 4…p-type Schottky diode 5…n-type Schottky diode or pn diode 6…p + Source resistance 7…Oblique ion implantation 8…The present invention 9…Prior art 10…Vertical ion implantation 101…Trench gate 102…Gate oxide film 103…P2 layer (anode layer) 104…n - Drift layer 105…n + Layer (cathode layer) 106…Cathode electrode 107…Insulating oxide film 108…Anode electrode 109…Contact hole 110…Insulating film spacer 111…High-concentration source p + Layer 112…P1 layer (low-concentration source layer) 113…n-well layer 201…Side gate 500…Power conversion device 501~506…Power switching element 511~516…Gate circuit 521~526…Diode 531…P terminal 532…N terminal 533…U terminal 534…V terminal 535…W terminal A…Anode K…Cathode G…Gate FV…Forward voltage FC…Forward current

Claims

1. A semiconductor substrate having a drift layer of a first conductivity type, a second conductivity type anode layer provided on the drift layer and constituting a PN junction diode with the drift layer, a first conductivity type well layer provided on the anode layer, a second conductivity type low-concentration source layer provided on the well layer, a second conductivity type high-concentration source layer provided only on a part of the low-concentration source layer, a gate electrode adjacent to the anode layer, the well layer, and the low-concentration source layer via a gate oxide film and constituting a MOSFET together with the anode layer, the well layer, and the low-concentration source layer, an insulating film covering the anode layer, the low-concentration source layer, the high-concentration source layer, and the gate electrode, and a contact hole penetrating the insulating film, the high-concentration source layer, the low-concentration source layer, and the well layer, wherein the low-concentration source layer is disposed between the high-concentration source layer and the gate oxide film and between the high-concentration source layer and the well layer. A semiconductor device characterized by this.

2. In the semiconductor device according to claim 1, the width of the high-concentration source layer measured from the contact hole is 1 / 2 or more and equal to or less than the thickness of the high-concentration source layer. A semiconductor device characterized by this.

3. In the semiconductor device according to claim 1, the contact hole has a side wall shape that is narrower at the bottom than at the top. A semiconductor device characterized by this.

4. In the semiconductor device according to claim 1, the gate electrode is a trench gate in which polysilicon is embedded in a trench provided in the anode layer. A semiconductor device characterized by this.

5. In the semiconductor device according to claim 1, the gate electrode is adjacent to the anode layer, the well layer, and the low-concentration source layer via a gate oxide film having a substantially L-shaped cross section, and has a side gate structure in which the width of the upper part is narrower than the width of the lower part. A semiconductor device characterized by this.

6. In a method of manufacturing a semiconductor device that manufactures the semiconductor device according to any one of claims 1 to 2 and 4 to 5, (a) a step of forming a second conductivity type anode layer on a semiconductor substrate having a drift layer of a first conductivity type, (b) a step of forming a first conductivity type well layer on the anode layer, (c) a step of forming a second conductivity type low-concentration source layer on the well layer, (d) Forming an insulating film on the low-concentration source layer, and forming a contact hole in the insulating film by photolithography and dry etching; (e) Forming a high-concentration source layer of the second conductivity type only in a part of the low-concentration source layer by oblique ion implantation through the contact hole; (f) Extending the contact hole by dry etching using the insulating film as a mask, and penetrating the high-concentration source layer, the low-concentration source layer, and the well layer; A method for manufacturing a semiconductor device including the above steps.

7. In a method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any one of Claims 1 to 5, (a) Forming a second-conductivity-type anode layer on a semiconductor substrate having a first-conductivity-type drift layer; (b) Forming a first-conductivity-type well layer on the anode layer; (c) Forming a second-conductivity-type low-concentration source layer on the well layer; (d) Forming a first insulating film constituting a part of the insulating film on the low-concentration source layer, and forming a contact hole in the first insulating film by photolithography and dry etching; e) Forming a high-concentration source layer of the second conductivity type only in a part of the low-concentration source layer by vertical ion implantation through the contact hole; f) Forming a second insulating film on the high-concentration source layer, and thinning the second insulating film by dry etching to form an insulating film spacer constituting a part of the insulating film in the contact hole; g) Extending the contact hole by dry etching using the first insulating film and the insulating film spacer as masks, and penetrating the high-concentration source layer, the low-concentration source layer, and the well layer; A method for manufacturing a semiconductor device including the above steps.

8. A pair of DC terminals; AC terminals equal in number to the number of phases of the AC output; Switching legs equal in number to the number of phases of the AC output, in which a parallel circuit of a switching element and a diode connected in anti-parallel to the switching element is connected in series twice between the pair of DC terminals; A gate circuit for controlling the switching element and the diode; and The diode is a semiconductor device according to any one of Claims 1 to 5. A power conversion device characterized by this.

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