Field-Effect Transistor (FET) Device

Abstract

A field effect transistor (FET) device is provided. The device includes an insulating region on a supporting substrate separating a first back gate from a second back gate, and a gate dielectric layer on the first channel region and the second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, where the first back gate can adjust a threshold voltage for the first channel region and the second back gate can adjust a threshold voltage for the second channel region.

Description

Technical Field

[0001] The present invention generally relates to field effect transistor (FET) devices, and more particularly to metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance field effect transistor devices on fully depleted silicon-on-insulator (FD-SOI, FDSOI).

Background Art

[0002] A field effect transistor (FET) typically has a source, a channel, and a drain, and a gate that controls the flow of current through the device channel, where the current flows from the source to the drain. The field effect transistor (FET) can have various different structures. For example, the FET is manufactured with the source, channel, and drain formed in the substrate material itself, in which case the current flows horizontally (i.e., in the plane of the substrate). A FinFET is formed with the channel extending outward from the substrate, but in this case, the current also flows horizontally from the source to the drain. The channel for a FinFET can generally be a thin rectangular silicon (Si) upright slab called a fin, having a gate on the fin, as compared to a metal-oxide-semiconductor field effect transistor (MOSFET) having a single gate parallel to the plane of the substrate. Depending on the doping of the source and drain, an NFET or a PFET can be formed. Two FETs can also be connected to form a complementary metal oxide semiconductor (CMOS) circuit, in which case a p-type MOSFET and an n-type MOSFET are connected together.

Summary of the Invention

[0003] According to an embodiment of the present invention, a field effect transistor (FET) device is provided. The device includes an insulating region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value, and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

[0004] According to another embodiment of the present invention, a complementary metal oxide semiconductor (CMOS) circuit is provided. The device includes a first dielectric layer between a support substrate and a first back gate, and a gate dielectric layer on a first channel region on the first back gate. The device further includes a first pair of source / drains on both sides of the first channel region, a conductive gate layer having a work function value, and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region.

[0005] According to yet another embodiment of the present invention, a method for manufacturing a field effect transistor (FET) device is provided. The method includes forming a first back gate and a second back gate between a first dielectric layer and a second dielectric layer on a support substrate, and forming a first pair of source / drains on both sides of a first channel region, wherein the first channel region is on the first back gate. The method further includes forming a second pair of source / drains on both sides of a second channel region, wherein the second channel region is on the second back gate, and forming a gate dielectric layer on the first channel region and the second channel region. The method further includes forming a conductive gate layer having a work function value on the gate dielectric layer, and forming a ferroelectric layer on the conductive gate layer.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in conjunction with the accompanying drawings.

[0007] The following description provides details of the preferred embodiments with reference to the following figures.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 10

DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of the present invention provide an FDSOI MFMIS NCFET having separate NFET and PFET back gates in addition to a shared internal metal gate (IMG) between the NFET and the PFET, where the FET includes a metal ferroelectric metal insulator semiconductor (MFMIS) gate structure. The separate NFET / PFET back gates can be used to individually adjust each of the NFET and PFET threshold voltages V t between the menu ends tN and V tP respectively.

[0010] The lowest V tThe pair can provide the best complementary capacitance matching with the most extreme SS. This approach utilizes the parallel complementary FET capacitance to achieve improved C in across the full V gate sweep range and matching between C FE and C t . The back-gate can be used to individually adjust the V t of the NFET and PFET to achieve a pair with low V t . This can provide an improved subthreshold swing below the threshold compared to independent NCFETs (non-complementary FETs) with the same dielectric stack. Using the back-gate type structure to freely modulate V t can adjust the complementary capacitance matching and provide a pair of low V t NFET / PFET. Complementary capacitance matching can improve the subthreshold swing of NCFET CMOS. Using the back-gate pair to individually adjust the threshold voltages Vt of both the NFET and PFET can achieve a pair with low V t . As the pair of V t becomes lower, the subthreshold swing becomes more extreme. The pair with the lowest V

[0011] inv

[0012]

[0013] In various embodiments, using complementary C can achieve capacitance matching in the off state with the shared ferroelectric (FE) layer between complementary devices. Negative capacitance in ferroelectrics arises from the incomplete screening of spontaneous polarization. When the ferroelectric bound charges are physically separated from the metal screening charges, a depolarization field is created inside the ferroelectric, destabilizing the polarization. Negative capacitance results from the mechanics of the stored energy during the phase transition of the ferroelectric material and, when integrated into the gate stack, amplifies the internal voltage of the MOS device.​Exemplary applications / uses for which the present invention can be applied include, but are not limited to, logic devices and memory devices using CMOS circuits.

[0014] In an n-channel enhancement-mode device, a conductive channel does not naturally exist within the transistor, and a voltage from the positive gate to the source is required to create a conductive channel. In a fully depleted silicon-on-insulator (FDSOI) device, the channel region is sufficiently thin such that the depletion region covers the entire thickness of the channel. The depletion region is an insulating region within a conductive doped semiconductor material where mobile charge carriers have moved away under the electric field. The depletion region is formed from a conductive region by removing all free charge carriers and allowing no current to flow through it. An N-type semiconductor has too many free electrons (in the conduction band) compared to a P-type semiconductor, and a P-type semiconductor has too many holes (in the valence band) compared to an N-type. Most charge carriers (free electrons for an N-type semiconductor and holes for a P-type semiconductor) become depleted in the depletion region.

[0015] The power consumption of a CMOS integrated circuit includes static power consumption and dynamic power consumption, where static power consumption is the power used when the transistor is not in the switching process and includes leakage current, and dynamic power consumption includes the power consumed when the device changes its logic state, i.e., “switches,” and the amount of power used to charge the load capacitance.

[0016] When a positive voltage is applied to the gate of a field-effect transistor, the holes with positive charge in the semiconductor closest to the gate are repelled by the electric field generated by the positive charge on the gate. The repelled charge carriers move away from the insulating depletion region since no mobile positive charge carriers remain in the channel region.

[0017] The depolarization instability in ferroelectrics causes an effective negative dielectric constant, which, when integrated into the gate stack of a transistor, amplifies the differential voltage and reduces the subthreshold swing. The gate stack is no longer a passive part of the transistor but contributes to signal amplification. As a result of the reduction in subthreshold swing, the supply voltage required to provide the same on-current is reduced.

[0018] The subthreshold swing of conventional devices is

Number

[0019] The subthreshold gradient is

Number

Number

[0020] Aspects of the present invention are described from the perspective of a given exemplary architecture, but it should be understood that other architectures, structures, substrate materials, as well as process features and steps, may be varied within the scope of the aspects of the present invention.

[0021] Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a side cross-sectional view of a substrate having a first dielectric layer on a support substrate, a first semiconductor layer on the first dielectric layer, a second dielectric layer on the first semiconductor layer, and a second semiconductor layer on the second dielectric layer, according to an embodiment of the present invention, is shown.

[0022] In one or more embodiments, the substrate 110 can include a first dielectric layer 130 on a support substrate 120, a first semiconductor layer 140 on the first dielectric layer 130, a second dielectric layer 150 on the first semiconductor layer 140, and a second semiconductor layer 160 on the second dielectric layer 150. The support substrate 120 can provide structural integrity to the other layers. In various embodiments, the substrate 110 can be a fully depleted silicon-on-insulator (FDSOI) substrate, in which case at least one of the dielectric layers is ultrathin and at least one of the semiconductor layers is ultrathin.

[0023] In various embodiments, the support substrate 120 can be a semiconductor material including, but not limited to, group-IV semiconductors such as silicon (Si) and germanium (Ge), group-IV-IV compound semiconductors such as silicon-germanium (SiGe) and silicon carbide (SiC), group-III-V compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), group-II-VI compound semiconductors such as cadmium selenide (CdSe) and zinc sulfide (ZnS), and combinations thereof. In various embodiments, the support substrate 110 can be an electrically insulating dielectric material such as, for example, silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (AlO), or combinations thereof.

[0024] In various embodiments, the first dielectric layer 130 can be a buried insulator layer, such as a buried oxide layer (i.e., BOX layer), which can be, for example, silicon oxide (SiO) formed on or in the support substrate 120.

[0025] In various embodiments, the first dielectric layer 130 can be made of an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2), a low-k dielectric material having a dielectric constant less than that of silicon dioxide (SiO2) (e.g., carbon-doped silicon oxide (SiO:C)), and combinations thereof.

[0026] In various embodiments, the first semiconductor layer 140 can be on the first dielectric layer 130. In various embodiments, the first semiconductor layer 140 and the first dielectric layer 130 can be formed on the support substrate 120, for example, by a Smart Cut(R) process, or the first dielectric layer 130 can be formed in the substrate through a SIMOX(R) process.

[0027] In one or more embodiments, the second dielectric layer 150 can be formed on the first semiconductor layer 140, and the second semiconductor layer 160 can be formed on the second dielectric layer 150, for example, by a Smart Cut(R) process.

[0028] In various embodiments, the first semiconductor layer 140 or the second semiconductor layer 160 or both can each be a semiconductor material including, but not limited to, group-IV semiconductors such as silicon (Si) and germanium (Ge), group-IV-IV compound semiconductors such as silicon-germanium (SiGe) and silicon carbide (SiC), group-III-V compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), group-II-VI compound semiconductors such as cadmium selenide (CdSe) and zinc sulfide (ZnS), and combinations thereof.

[0029] In various embodiments, the second dielectric layer 150 can be made of an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2), a low-k dielectric material having a dielectric constant less than that of silicon dioxide (SiO2) (e.g., carbon-doped silicon oxide (SiO:C)), and combinations thereof.

[0030] FIG. 2 is a cross-sectional side view showing a pair of back-gates formed on a first dielectric layer and a pair of source / drains formed on a second dielectric layer, according to an embodiment of the present invention.

[0031] In various embodiments, the insulating region 170 can be formed within the substrate 110, in which case the insulating region 170 can be formed through the first dielectric layer 130, the first semiconductor layer 140, the second dielectric layer 150, and the second semiconductor layer 160. The insulating region 170 can be formed by forming a trench through the first dielectric layer 130, the first semiconductor layer 140, the second dielectric layer 150, and the second semiconductor layer 160 and filling the trench with an electrically insulating dielectric material.

[0032] In various embodiments, the insulating region 170 can be made of an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2), a low-k dielectric material having a dielectric constant less than that of silicon dioxide (SiO2) (e.g., carbon-doped silicon oxide (SiO:C)), and combinations thereof.

[0033] In various embodiments, the first back gate 180 can be formed between the first dielectric layer 130 and the second dielectric layer 150. In this case, the first back gate 180 can be formed, for example, by selective etching (e.g., wet chemical etching, dry plasma etching) to remove a portion of the first semiconductor layer 140. Metal can be deposited in the cavity formed by removing a portion of the first semiconductor layer 140, or a doped semiconductor layer (n-type or p-type) can be formed by an epitaxial process using the remaining portion of the first semiconductor layer with respect to the epitaxial growth surface.

[0034] In various embodiments, the second back gate 190 can be formed between the first dielectric layer 130 and the second dielectric layer 150. In this case, the second back gate 190 can be formed by removing a portion of the first semiconductor layer 140. The second back gate 190 can be formed on the side surface of the insulating region 170 opposite to the first back gate 180. In this case, the insulating region 170 physically and electrically separates the second back gate 190 from the first back gate 180.

[0035] In various embodiments, the first back gate 180 and the second back gate 190 can be metal conductors, such as, for example, tungsten (W), tantalum (Ta), molybdenum (Mo), titanium aluminum (TiAl), a conductive metal compound such as titanium nitride (TiN), or a combination thereof. The first back gate 180 and the second back gate 190 can be formed by metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), low-pressure CVD (LPCVD), and combinations thereof.

[0036] In various embodiments, the first back gate 180 and the second back gate 190 can be semiconductors appropriately doped to be conductive, in which case the dopant can be, for example, an n-type dopant such as phosphorus (P) or arsenic (As), or a p-type dopant such as, for example, boron (B) or indium (In). In various embodiments having doped semiconductors such as back gates 180, 190, the first dielectric layer 130 can be appropriately replaced with a counter-doped well.

[0037] In one or more embodiments, the first doped semiconductor region 200 can be formed on the second dielectric layer 150, in which case the first doped semiconductor region 200 can be formed by doped epitaxy on the second semiconductor layer 160, or dopant implantation into the second semiconductor layer 160 or an epitaxial layer on the second semiconductor layer 160, or both. In various embodiments, the first doped semiconductor region 200 can be formed in situ or ex situ. In various embodiments, the first doped semiconductor region 200 can be n-doped to form an n-type field effect transistor device, for example, and an NFET.

[0038] In one or more embodiments, the second doped semiconductor region 210 can be formed on the second dielectric layer 150, in which case the second doped semiconductor region 210 can be formed by doped epitaxy on the second semiconductor layer 160, or dopant implantation into the second semiconductor layer 160 or an epitaxial layer on the second semiconductor layer 160, or both. In various embodiments, the second doped semiconductor region 210 can be formed in situ or ex situ.

[0039] In various embodiments, the first doped semiconductor region 200 and the second doped semiconductor region 210 can be semiconductor materials including, but not limited to, group-IV semiconductors such as silicon (Si) and germanium (Ge), group-IV-IV compound semiconductors such as silicon-germanium (SiGe) and silicon carbide (SiC), group-III-V compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP), and group-II-VI compound semiconductors such as cadmium selenide (CdSe) and zinc sulfide (ZnS), as well as combinations thereof. In various embodiments, the second doped semiconductor region 210 can be p-doped to form, for example, p-type field effect transistor devices and NFETs. N-type and p-type field effect transistors can be electrically connected to form a CMOS circuit.

[0040] In various embodiments, a first dielectric slab 220 and a second dielectric slab 230 can be formed on the second dielectric layer 150 to electrically insulate the first doped semiconductor region 200 and the second doped semiconductor region 210 from other layers and other components of the field effect transistor device.

[0041] FIG. 3 is a side cross-sectional view showing a complementary metal oxide semiconductor (CMOS) circuit including an NFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device and a PFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device according to an embodiment of the present invention.

[0042] In one or more embodiments, a complementary metal oxide semiconductor (CMOS) circuit 100 can be formed on a support substrate 120 of a substrate 110, in which case the CMOS circuit can include n-type field effect transistor (NFET) devices and p-type field effect transistor (PFET) devices. The n-type field effect transistor (NFET) device can be a negative capacitance field effect transistor (NCFET) device, and the p-type field effect transistor (PFET) device can be a negative capacitance field effect transistor (NCFET) device. In various embodiments, the NFET can be a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance field effect transistor device, and the PFET can be a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance field effect transistor device. The NFET and PFET can be on a fully depleted silicon-on-insulator (FD-SOI, FDSOI) substrate.

[0043] In various embodiments, the substrate 110 can be a fully depleted silicon-on-insulator (FD-SOI, FDSOI) substrate having a first dielectric layer 130 that can be, for example, a buried insulator layer such as a buried oxide layer (i.e., BOX layer) on the support substrate 120, with a first back gate 180 and a second back gate 190 on the first dielectric layer 130. A second dielectric layer 150 can be on the first back gate 180 and the second back gate 190, in which case the first dielectric layer 130 electrically insulates the first back gate 180 and the second back gate 190 from the support substrate 120, and the second dielectric layer 150 electrically insulates the first back gate 180 and the second back gate 190 from the overlying first channel region 240 or the second channel region 250 or both.

[0044] In various embodiments, the first back gate 180 can form the back gate of a field effect transistor formed on a first region of the substrate 110, and the second back gate 190 can form the back gate of a field effect transistor formed on a second region of the substrate 110. In various embodiments, the field effect transistor formed on the first region can be an NFET, and the field effect transistor formed on the second region can be a PFET.

[0045] In various embodiments, the second dielectric layer 150 can electrically insulate the source / drain, gate structure, and channel region of the field effect transistor device from the underlying back gates 180, 190. The second dielectric layer 150 can be an original layer of the substrate 110 and can be formed, for example, by conformal deposition such as atomic layer deposition (ALD), plasma enhanced ALD (PEALD), low pressure chemical vapor deposition (LPCVD), and combinations thereof. In various embodiments, the second dielectric layer 150 can be formed, for example, by wafer bonding using a Smart Cut(R) process.

[0046] In various embodiments, the first channel region 240 can be a portion of the second semiconductor layer 160 on the second dielectric layer 150. In various embodiments, the first channel region 240 can be on the second dielectric layer 150, in which case the first channel region 240 can be formed from the second semiconductor layer 160 on the second dielectric layer 150. The first channel region 240 can be formed by an epitaxial growth process on the second semiconductor layer 160.

[0047] In various embodiments, the second channel region 250 can be a portion of the second semiconductor layer 160 on the second dielectric layer 150. In various embodiments, the second channel region 250 can be on the second dielectric layer 150, in which case the second channel region 250 can be formed from the second semiconductor layer 160 on the second dielectric layer 150. The second channel region 250 may be formed by an epitaxial growth process on the second semiconductor layer 160.

[0048] In various embodiments, the first channel region 240 and the second channel region 250 can be semiconductor materials including, but not limited to, group-IV semiconductors such as silicon (Si) and germanium (Ge), group-IV-IV compound semiconductors such as silicon-germanium (SiGe) and silicon carbide (SiC), group-III-V compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), group-II-VI compound semiconductors such as cadmium selenide (CdSe) and zinc sulfide (ZnS), and combinations thereof.

[0049] In various embodiments, the second dielectric layer 150 can have a thickness in the range from about 2 nanometers (nm) to about 20 nm, or from about 2 nm to about 10 nm, or from about 3 nm to about 5 nm, although other thicknesses are also contemplated. The thickness of the second dielectric layer 150 provides sufficient voltage sensitivity to adjust the threshold voltage V t of the NFET or PFET devices thereon at the supply voltage available to the integrated circuit (IC) chip, and at the same time may be sufficient to prevent leakage current between the back gates 180, 190 and the device source / drains 200, 210, or the channel regions 240, 250, or both.

[0050] In various embodiments, the first dielectric slab 220 and the second dielectric slab 230 are formed on the second dielectric layer 150 and can electrically insulate the first channel region 240 and the second channel region 250 from other layers and other components of the field effect transistor device.

[0051] In various embodiments, the first dielectric slab 220 and the second dielectric slab 230 can each be made of an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2), a low-k dielectric material having a dielectric constant less than that of silicon dioxide (SiO2) (e.g., carbon-doped silicon oxide (SiO:C)), and combinations thereof. The first dielectric slab 220 and the second dielectric slab 230 can be the same dielectric material as the second dielectric layer 150 or can be different dielectric materials to enable selective etching.

[0052] In one or more embodiments, the insulating region 170 can be formed on the support substrate 120 of the substrate 110. In this case, the insulating region 170 can physically and electrically separate the first back gate 180 from the second back gate 190 and can physically and electrically separate the first channel region 240 from the second channel region 250. The insulating region 170 can be formed through the second dielectric layer 150, the back gates 180, 190, and the first dielectric layer 130 to the surface of the support substrate 120. In various embodiments, the insulating region 170 can be a shallow trench isolation region.

[0053] In one or more embodiments, the gate dielectric layer 260 can be formed over the source / drains 200, 210 and channel regions 240, 250 for NFETs and PFETs. The gate dielectric layer 260 can be formed across the top surface of the insulating region 170, in which case the gate dielectric layer 260 serves to electrically isolate the source / drain 200 (e.g., an n-doped source / drain) from the source / drain 200 (e.g., a p-doped source / drain). The gate dielectric layer 260 can be formed by conformal deposition, such as, for example, atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or low pressure CVD (LPCVD).

[0054] In various embodiments, the gate dielectric layer 260 can be made from insulating dielectric materials including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), high-k dielectric materials, and combinations thereof. In various embodiments, the high-k dielectric can include, for example, metal oxides such as hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalate (PbScTaO), and lead zinc niobate (PbZnNbO). The high-k material may further include dopants such as lanthanum, aluminum, magnesium, or combinations thereof. In various embodiments, the gate dielectric layer 260 can include multiple layers of dielectric materials, such as, for example, silicon dioxide (SiO2) over hafnium dioxide (HfO2).

[0055] In various embodiments, the gate dielectric layer 260 can have a thickness in the range of from about 1 nm to about 3 nm, or about 2 nm, although other thicknesses are contemplated.

[0056] In one or more embodiments, the conductive gate layer 270 can be formed on the gate dielectric layer 260, in which case the conductive gate layer 270 can be, for example, a work function material that can be a metal such as titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), titanium aluminum (TiAl), for example, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and combinations thereof. The conductive gate layer 270 can be formed by metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), and combinations thereof.

[0057] In various embodiments, the minimum V t The device can have an NFET work function from about 4.3 to about 4.4 eV, and a PFET work function from about 4.8 to about 4.9 eV. In various embodiments, the conductive gate layer 270 can have a work function in the range from about 4.3 to about 4.9 eV, which can function as a shared internal metal gate (IMG) for both NFET and PFET. In various embodiments, the V adjusted from the back gates 180, 190 t can cover the same range by using the voltage applied to obtain an appropriate V for the NFET or PFET or both. t

[0058] In one or more embodiments, the same conductive gate layer 270 is used for both NFETs and PFETs, and the threshold voltage of one or both gates of the NFET or PFET or both increases. Selecting a material for the conductive gate layer 270 that provides an intermediate work function value for both the NFET and PFET gates can reduce the complementary capacitance matching between the gate and the ferroelectric layer 280. The first back-gate 180 and the second back-gate 190 can function as separate back-gates such that the NFETs and PFETs can individually adjust the threshold voltage Vt of the NFETs and PFETs. This can provide complementary capacitance matching while also providing the most extreme sub-threshold swing.

[0059] In a non-limiting exemplary embodiment, the shared IMG can have a mid-gap work function of about 4.6 eV that is adjusted (e.g., reduced) by about 0.3 V for both NFETs and PFETs to achieve the intended threshold voltage. In another non-limiting exemplary embodiment, the shared IMG can have a work function at one end of the intended range (e.g., 4.3 eV for the NFET work function metal or 4.9 eV for the PFET work function metal), and the complementary FETs should thus have a threshold voltage V t that is adjusted / reduced by about 0.6 V. (For example, if the shared IMG has a given work function of 4.9 eV, the threshold voltage V t of the PFET remains unchanged, and the threshold voltage V t of the NFET is adjusted by about 0.6 V.) t

[0060] In various embodiments, the conductive gate layer 270 can have a thickness in the range from about 1 nm to about 10 nm, or from about 3 nm to about 5 nm, although other thicknesses are also contemplated. The thickness of the conductive gate layer 270 may be sufficient to form a continuous layer while minimizing capacitance.

[0061] In one or more embodiments, the ferroelectric (FE) layer 280 can be formed on the conductive gate layer 270, in which case the ferroelectric layer 280 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), and combinations thereof.

[0062] In various embodiments, the ferroelectric layer 280 can be a ferroelectric material including, but not limited to, hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), hafnium silicate (HfSiO x ), barium titanate (BaTiO), potassium niobate (KNbO), bismuth titanate (BiTiO), and combinations thereof. The ferroelectric layer 280 provides a negative capacitance to the layer before the gate electrode is formed by the conductive gate layer 270, in which case the negative capacitance can improve the subthreshold slope and ratio of the on-current and off-current (I on / I off ). This can reduce the leakage current in the subthreshold region of the device.

[0063] In one or more embodiments, the conductive gate electrode layer 290 can be formed on the ferroelectric layer 280, in which case the conductive gate electrode layer 290 can be a metal such as titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), titanium aluminum (TiAl), and metal compounds such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and combinations thereof.

[0064] In various embodiments, the conductive gate electrode layer 290 can be formed by metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), low pressure CVD (LPCVD), and combinations thereof. The conductive gate electrode layer 290 can have multiple conductive layers of different metals or metal compounds or both.

[0065] In one or more embodiments, the gate structure can include a continuous stack of metal 290 / ferroelectric 280 / metal 270 / dielectric 260, in which case the gate structure is over both the NFET and PFET of the CMOS circuit. The gate structure is over the first channel region 240 and the second channel region 250 and can span the insulating region 170 to form a shared gate structure. The combination of gate structure layers can provide a negative capacitance gate structure, and the shared gate structure can provide appropriate capacitance matching.

[0066] In various embodiments, the gate sidewall spacer 300 is formed over the conductive gate electrode layer 290 and can surround the gate structures of the NFET and PFET. In various embodiments, the gate sidewall spacer 300 is formed by conformal deposition (e.g., ALD, PEALD) and can be etched back using selective directional etch or chemical / mechanical polishing (CMP) or both. The gate sidewall spacer 300 can be a dielectric material such as, for example, silicon nitride (SiN) or silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), and combinations thereof.

[0067] FIG. 4 is a top view showing the layout of the source / drain and gate structures for an NFET negative capacitance field effect transistor device and a PFET negative capacitance field effect transistor device according to an embodiment of the present invention.

[0068] In various embodiments, the first doped semiconductor region 200 can form the first source / drain 203 on both sides of the first channel region 240, and the second doped semiconductor region 210 can form the second source / drain 213 on both sides of the second channel region 250. In this case, the source / drains 203, 213 and the channel regions 240, 250 can be adjacent to the insulating region 170 and arranged in parallel with the insulating region 170. In various embodiments, the first source / drain 203 can be an n-type source / drain, and the second source / drain 213 can be a p-type source / drain, forming an NFET and a PFET respectively. The first dielectric slab 220 can be adjacent to the first source / drain 203, and the second dielectric slab 230 can be adjacent to the second source / drain 213. The gate sidewall spacer 300 can be on the first and second dielectric slabs 220, 230, and the insulating region 170.

[0069] In various embodiments, a gate structure including the conductive gate electrode layer 290 and the gate sidewall spacer 300 can extend over the channel regions 240, 250 and across the insulating region 170.

[0070] FIG. 5 is a top view showing formed electrical contacts to the source / drain and gate structures according to an embodiment of the present invention.

[0071] In various embodiments, a bridge contact 310 can be formed between one of the first source / drains 203 and one of the second source / drains 213. In this case, the first source / drain 203 and the second source / drain 213 can be on the same side of the gate structure. The bridge contact 310 can be a conductive metal such as, for example, tungsten (W).

[0072] In various embodiments, a first back-gate contact 320 can be formed with respect to the first back-gate 180. The first back-gate contact 320 can be configured to supply a voltage to the first back-gate 180.

[0073] In various embodiments, a second back-gate contact 330 can be formed with respect to the second back-gate 190. The second back-gate contact 330 can be configured to supply a voltage to the second back-gate 190.

[0074] In various embodiments, a first source / drain contact 340 can be formed with respect to one of the other ones of the first source / drains 203, and a second source / drain contact 350 can be formed with respect to one of the other ones of the second source / drains 213.

[0075] In various embodiments, a gate contact can be formed with respect to the gate structure.

[0076] The placement of the electrical contacts can be configured to form a complementary metal oxide semiconductor (CMOS) circuit including an NFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device and a PFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device.

[0077] FIG. 6 is a partial cross-sectional view showing a side of a complementary metal oxide semiconductor (CMOS) circuit having source / drain and back-gate contacts according to an embodiment of the present invention.

[0078] In various embodiments, the bridge contact 310, the first back-gate contact 320, the second back-gate contact 330, the first source / drain contact 340, the second source / drain contact 350, and the gate contact can include vias at the electrical contacts with the corresponding components of the FET device, and conductive lines at the electrical contacts with the vias. In FIG. 6, the bridge contact 310 is shown in front of the gate structure.

[0079] In various embodiments, the first dielectric layer 130 and the second dielectric layer 150, together with the insulating region 170, can surround the first back-gate 180 to form a back-gate buried under the n-type source / drain 203.

[0080] In various embodiments, the first back-gate contact 320 and the second back-gate contact 330 can each be a conductive material including, but not limited to, copper (Cu), tungsten (W), cobalt (Co), tantalum (Ta), molybdenum (Mo), and combinations thereof. The back-gate contacts 320, 330 can be in electrical contact with the first back-gate 180 or the second back-gate 190, respectively, through the interlayer dielectric (ILD) layer 400 and the first dielectric slab 220 or the second dielectric slab 230.

[0081] In various embodiments, the interlayer dielectric (ILD) layer 400 can be made of an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material with a dielectric constant greater than that of silicon dioxide (SiO2), a low-k dielectric material with a dielectric constant less than that of silicon dioxide (SiO2) (e.g., carbon-doped silicon oxide (SiO:C)), and combinations thereof.

[0082] FIG. 7 is a side cross-sectional view along the B-B plane showing a gate structure over a channel region and a back-gate under the channel region according to an embodiment of the present invention.

[0083] In one or more embodiments, the second back gate 190 can be formed within the first semiconductor layer 140, in which case the second back gate 190 is between the first dielectric layer 130 and the second channel region 250. The second back gate 190 can be under the second channel region 250 and between the second source / drains 213. A portion of the bridge contact 310 can be on the second source / drain 213 on the first side of the gate structure, and the second source / drain contact 350 can be on the second source / drain 213 on the opposite side of the gate structure.

[0084] In one or more embodiments, the metal 290 / ferroelectric 280 / metal 270 / dielectric 260 gate stack can be over the second channel region 250 of the PFET. In various embodiments, a portion of the gate sidewall spacer 300 can be on the second source / drain 213.

[0085] In various embodiments, the second source / drain contact 350 can be formed to the source / drain 213 of the PFET, and the first source / drain contact 340 can be formed to the source / drain 203 of the NFET.

[0086] In one or more embodiments, the first back gate 180 and the device components thereon can have the same configuration as that shown for the second back gate 190 and the device thereon.

[0087] In various embodiments, the first source / drain contact 340 can be formed to the first source / drain 203 on one side of the gate structure of the NFET.

[0088] FIG. 8 is a graph showing capacitance matching for a combination of NFET gate capacitance and PFET gate capacitance without Vt correction, where the NFET and PFET share a gate structure including a work function material.

[0089] A ferroelectric capacitor connected to the gate stack of the MOS transistor creates a series connection between C FE and C MOS The negative capacitance of the ferroelectric can be stabilized when placed in series with a positive capacitor of an appropriate value. To achieve negative capacitance, the charge line of the baseline transistor can have an intersection with the negative slope of the polarization. Thus, the negative value of C FE should match well with C MOS This allows the parallel complementary FET capacitance to be utilized to achieve improved matching between C in and C gate over the full sweep range of V FE

[0090] FIG. 8 shows capacitance matching (e.g., mid-gap internal metal gate work function of about 4.6 eV without back-gate bias) for a combination of NFET gate capacitance and PFET gate capacitance without Vt correction.

[0091] In various embodiments, the conductive gate layer 270 is an internal metal gate (IMG) having a shared work function between both the NFET and PFET. In one or more embodiments, the work function of the conductive gate layer 270 can be selected in combination with other parameters of the NFET and PFET devices to match the capacitance of the ferroelectric layer 280. The selected work function value of the conductive gate layer 270 will result in some separation of the C-V curves of the NFET and PFET. Capacitance "matching" results from choices of dielectric and ferroelectric materials as well as thicknesses. To flatten the shared C-V curve, the V of the NFET and PFET t ​This can be supplemented by complementary capacitance matching by reducing it. The combined gate capacitance is the sum of the PFET gate capacitance and the NFET gate capacitance. Each of these gate capacitances can be in series with the capacitance of the ferroelectric layer 280.

[0092] FIG. 9 is a graph showing capacitance matching for a combination of an NFET gate capacitance and a PFET gate capacitance to which an appropriate back-gate bias is applied when an NFET and a PFET share a gate structure including a work function material, according to an embodiment of the present invention.

[0093] In various embodiments, the first back-gate 180 and the second back-gate 190 are used to apply an appropriate back-gate bias to either or both of the NFET and the PFET in order to flatten the shared C-V curve by individually adjusting V t It is possible to do so.

[0094] FIG. 10 is a block / flow diagram showing a manufacturing process for a complementary metal oxide semiconductor (CMOS) circuit including an NFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device and a PFET metal ferroelectric metal insulator semiconductor (MFMIS) negative capacitance field effect transistor device, according to an embodiment of the present invention.

[0095] In block 910, the first back-gate 180 and the second back-gate 190 can be formed within the first semiconductor layer 140 and on the first dielectric layer 130. The first back-gate 180 and the second back-gate 190 can be formed by replacing a portion of the semiconductor layer 140 with a metal or a doped semiconductor material.

[0096] In block 920, a dummy gate dielectric layer can be formed over the region of the second semiconductor layer 160 that becomes the first channel region 240, the second channel region 250, or both.

[0097] In block 930, a dummy gate and gate sidewall spacers 300 can be formed over the dummy gate dielectric layer.

[0098] In block 940, a first pair of source / drains 203 and a second pair of source / drains 213 can be formed within the second semiconductor layer 160 on both sides of the dummy gate and the sidewall spacers. The first pair of source / drains 203 and the second pair of source / drains 213 can be formed by implanting dopants into the region of the second semiconductor layer 160 on both sides of the first channel region 240, the second channel region 250, or both.

[0099] In block 950, the dummy gate and the dummy gate dielectric layer can be removed using selective etching.

[0100] In block 960, a gate dielectric layer 260 can be formed over the second semiconductor layer 160 within the gate sidewall spacers 300.

[0101] In block 970, a conductive gate layer 270 can be formed over the gate dielectric layer 260 within the gate sidewall spacers 300.

[0102] In block 980, a ferroelectric layer 280 can be formed over the conductive gate layer 270.

[0103] In block 990, a conductive gate electrode layer 290 can be formed over the ferroelectric layer 280.

[0104] The ILD layer 400 can be formed on the surface of the features formed on the substrate.

[0105] In various embodiments, the bridge contact 310, the first back-gate contact 320, the second back-gate contact 330, the first source / drain contact 340, the second source / drain contact 350, and the gate contact can be formed within the ILD layer for their respective device features.

[0106] Using a “gate-first” process flow, the final structure can be made similarly.

[0107] This embodiment can include the design of an integrated circuit chip, which is made in a graphical computer programming language and can be stored in a computer storage medium (such as a virtual hard drive like a disk, tape, physical hard drive, or storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer can transmit the resulting design directly or indirectly to such an entity physically (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a format (e.g., GDSII) suitable for the manufacture of a photolithography mask, typically including a plurality of copies of the chip design that are to be formed on the wafer. The photolithography mask is used to define the area of the wafer (or a layer thereon or both) that is to be etched or otherwise processed.

[0108] The methods as described herein can be used during the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer shape (i.e., as a single wafer having a plurality of unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chip can be mounted within a single chip package (such as a plastic carrier having leads attached to a motherboard or other higher-level carrier), or within a multi-chip package (such as a ceramic carrier having either or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-cost applications to advanced computer products having a display, keyboard or other input device, and a central processor.

[0109] It should also be understood that material compounds are described in terms of the listed elements, such as SiGe for example. These compounds contain different ratios of the elements of the compound, for example, SiGe contains SixGe1-x, where x is less than or equal to 1. Additionally, in accordance with this principle, other elements can be included in the compound and still function. Compounds that include additional elements will be referred to herein as alloys.

[0110] References in this specification to "one embodiment" or "an embodiment" and other variations thereof mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and variations thereof in various places throughout this specification are not necessarily all references to the same embodiment.

[0111] It should be recognized that, for example, in the cases of "A / B", "A and / or B", and "at least one of A and B", any use of the following: " / ", "and / or", and "at least one of" is intended to encompass the selection of only the first-listed option (A), or only the second-listed option (B), or the selection of both options (A and B). As a further example, in the cases of "A, B, and / or C" and "at least one of A, B, and C", such expressions are intended to encompass the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or the selection of only the first and second-listed options (A and B), or the selection of only the first and third-listed options (A and C), or the selection of only the second and third-listed options (B and C), or the selection of all three options (A and B and C). As will be readily apparent to those skilled in the art, this can be extended for as many listed items as there are.

[0112] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes" or "including", or combinations thereof, when used herein, specify the presence of the stated feature, integer, step, operation, element, or component, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0113] Spatial relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, may be used herein for ease of description to explain the relationship of one element or feature to another as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device may otherwise be oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, this can mean that there is just one layer between the two layers or that one or more intervening layers may also be present.

[0114] To describe various elements, terms such as first, second, etc. may be used in this specification, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the scope of this concept.

[0115] When an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it should be understood that this can be directly on the other element or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it should be understood that this can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0116] (It is intended to be illustrative and not limiting) Preferred embodiments of a device and a method of manufacturing the device have been described, and it is pointed out that modifications and changes can be made by those skilled in the art in light of the above teachings. Thus, it should be understood that changes to the disclosed specific embodiments within the scope of the present invention as outlined by the appended claims may be made. In this way, although the aspects of the present invention have been described in detail and specifically as required by patent law, what is claimed and desired to be protected by the patent is shown in the appended claims.

[0117] In a preferred embodiment of the present invention, a complementary metal oxide semiconductor (CMOS) circuit is provided that includes a first dielectric layer between a support substrate and a first back gate, a gate dielectric layer over a first channel region on the first back gate, a first pair of source / drains on both sides of the first channel region, a conductive gate layer having a work function value, and a ferroelectric layer over the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region. The circuit can further include a second back gate on the first dielectric layer and a second channel region on the second back gate. The circuit can further include a second pair of source / drains on both sides of the second channel region, wherein the first pair of source / drains is n-doped and the second pair of source / drains is p-doped. The circuit can further include an insulating region on the support substrate that separates the first back gate from the second back gate and separates the first channel region from the second channel region. The gate dielectric layer can be over the first channel region and the second channel region. The conductive gate layer can have a predetermined work function value in the range from 4.3 to 4.9 eV. The circuit can further include a bridge contact over one of the first pair of source / drains on both sides of the first channel region and over one of the second pair of source / drains on both sides of the second channel region, wherein the bridge contact forms an electrical connection between one of the first pair of source / drains and one of the second pair of source / drains to form a complementary metal oxide semiconductor (CMOS) circuit.

Claims

Claim 1. A complementary metal oxide semiconductor (CMOS) circuit, comprising: an insulating region on a support substrate that separates a first back gate from a second back gate; a gate dielectric layer on a first channel region and a second channel region; a conductive gate layer having a work function value on the gate dielectric layer above the first channel region and the second channel region; a ferroelectric layer on the conductive gate layer; wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region. A complementary metal oxide semiconductor (CMOS) circuit. Claim 2. The complementary metal oxide semiconductor (CMOS) circuit according to claim 1, further comprising a first dielectric layer between the support substrate and the first back gate and between the support substrate and the second back gate. Claim 3. The complementary metal oxide semiconductor (CMOS) circuit according to claim 1, further comprising a first pair of source / drains on both sides of the first channel region. Claim 4. The complementary metal oxide semiconductor (CMOS) circuit according to claim 3, further comprising a second pair of source / drains on both sides of the second channel region. Claim 5. The complementary metal oxide semiconductor (CMOS) circuit according to claim 4, wherein the first pair of source / drains is n-doped and the second pair of source / drains is p-doped. Claim 6. The complementary metal oxide semiconductor (CMOS) circuit according to claim 5, wherein the conductive gate layer has a predetermined work function value in the range from 4.3 to 4.9 eV. Claim 7. The complementary metal oxide semiconductor (CMOS) circuit according to claim 1, wherein the ferroelectric layer is a ferroelectric material selected from the group consisting of hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HZO), hafnium silicate (HfSiO x), barium titanate (BaTiO), potassium niobate (KNbO), bismuth titanate (BiTiO), and combinations thereof. Claim 8. A complementary metal oxide semiconductor (CMOS) circuit according to claim 4, further comprising a bridge contact over one of the first pair of source / drains on both sides of the first channel region and over one of the second pair of source / drains on both sides of the second channel region, the bridge contact forming an electrical connection between the one of the first pair of source / drains and the one of the second pair of source / drains for forming the complementary metal oxide semiconductor (CMOS) circuit.

9. A method for manufacturing a field effect transistor (FET) device, comprising: forming a structure having a first dielectric layer on a support substrate, a first back gate and a second back gate on the first dielectric layer, and a second dielectric layer on the first back gate and the second back gate; forming a first pair of source / drains on both sides of a first channel region, the first channel region being over the first back gate; forming a second pair of source / drains on both sides of a second channel region, the second channel region being over the second back gate; forming a gate dielectric layer over the first channel region and the second channel region; forming a conductive gate layer having a work function value over the gate dielectric layer; forming a ferroelectric layer over the conductive gate layer The method includes.

10. The method according to claim 9, further comprising forming a conductive gate electrode layer over the ferroelectric layer, the ferroelectric layer having a range of negative capacitance.

11. The method according to claim 10, wherein the conductive gate layer is a work function material selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), titanium aluminum (TiAl), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and combinations thereof.

12. The method of claim 9, further comprising forming a first back-gate contact to the first back gate and a second back-gate contact to the second back gate.

13. The method of claim 12, further comprising forming bridge contacts over one of the first pair of source / drains on opposite sides of the first channel region and over one of the second pair of source / drains on opposite sides of the second channel region, the bridge contacts forming an electrical connection between the one of the first pair of source / drains and the one of the second pair of source / drains to form a complementary metal oxide semiconductor (CMOS) circuit.

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