Method and apparatus for seam reduction or elimination

Abstract

A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, the barrier layer being TiN, and forming a metal layer in the feature and over the barrier layer, the metal layer being at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to thin film manufacturing techniques.

Background Art

[0002]

[0002] The inventors have observed that in many 3D structures, seams are often formed in films deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). For example, stacks of titanium nitride (TiN) and tungsten (W) have been observed to always result in seams in trenches after the field is pinched off. By way of illustration, FIG. 1 schematically shows a substrate 100 having a base layer 102 on which a feature 104 is formed. A titanium nitride (TiN) layer 106 is first formed on the upper surface of the base layer 102 including on the surface of the feature 104 (e.g., along the sidewalls and bottom of the feature 104). Thereafter, a tungsten (W) layer 108 is formed on the TiN layer 106. A seam 110 is observed within the feature 104 after being filled with the TiN layer 106 and the W layer 108. The presence of such seams is undesirable and harmful to subsequent processes such as chemical mechanical planarization (CMP) or etching processes. For example, an etchant or CMP polishing slurry may undesirably diffuse into the feature through the seam. In addition, the inventors have observed that such seams can also undesirably cause an increase in stack resistance.

[0003]

[0003] Accordingly, the inventors have provided embodiments of methods and apparatuses for filling features with reduced or eliminated seams.

Summary of the Invention

[0004] Embodiments of a method and apparatus for filling features with reduced or eliminated seams are provided herein. Specifically, embodiments of the present disclosure advantageously provide a method and apparatus for minimizing, reducing, or eliminating seam formation while maintaining the properties of a lower titanium nitride (TiN) layer while filling the feature with a metal other than tungsten (W). The metal film has been proven to provide good gap filling while minimizing the impact on electrical performance. Further, as described below, since the properties of the underlying TiN material are preserved, the process can be more easily integrated in a multi-chamber processing tool.

[0005]

[0005] In some embodiments, a contact structure in a semiconductor device having a feature includes a barrier layer within the feature, the barrier layer being TiN, and a metal layer within the feature and on the barrier layer, the metal layer being at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo), and the metal layer being seam-free.

[0006]

[0006] In some embodiments, a system for forming a fill material within a feature of a semiconductor device includes an apparatus configured to form a barrier layer of TiN within the feature and an apparatus configured to form a metal layer of at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo) within the feature and on the barrier layer, the barrier layer and the metal layer being the fill material and the fill material being seam-free.

[0007]

[0007] In some embodiments, in a semiconductor device having a feature, a method of forming a contact structure includes forming a barrier layer of TiN within the feature and forming a metal layer within the feature and on the barrier layer, the metal layer being at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

[0008] Other and further embodiments of the present disclosure are described below.

[0009]

[0009] The embodiments of the present disclosure, briefly summarized above and described in detail below, can be understood by reference to the exemplary embodiments of the present disclosure shown in the accompanying drawings. However, since the present disclosure may admit other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be regarded as limiting the scope.

Brief Description of the Drawings

[0010]

Figure 1

[0010] A schematic diagram of a prior art feature filled in a substrate and including a seam.

Figure 2

[0011] A schematic diagram of a feature filled in a substrate and not including a seam according to an embodiment of the present disclosure.

Figure 3

[0012] A flowchart of a method for forming a semiconductor structure having gap filling in a feature according to an embodiment of the present disclosure.

Figures 4A - 4C

[0013] A cross-sectional view of a semiconductor structure having gap filling in a feature according to an embodiment of the present disclosure.

Figures 4D - 4E

Figure 5

[0014] A schematic top view of an exemplary multi-chamber processing system according to an embodiment of the present disclosure.

Modes for Carrying Out the Invention

[0011]

[0015] For ease of understanding, the same reference numbers were used, where possible, to denote identical elements common to multiple figures. The figures are not to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0012]

[0016] Embodiments of methods and apparatuses for filling features with reduced or eliminated seams are provided herein. Specifically, embodiments of the present disclosure advantageously provide methods and apparatuses for reducing or eliminating seam formation while maintaining the properties of underlying titanium nitride (TiN) layers while filling features with a metal other than tungsten (W). The metal film has proven to provide good gap filling while minimizing the impact on electrical performance. Further, as described below, since the properties of the underlying TiN material are preserved, the process can be more easily integrated in a multi-chamber processing tool.

[0013]

[0017] Embodiments of the present disclosure provide a new solution for achieving seam-free (or reduced seam) filling of features formed on a substrate. Instead of using TiN and W as fill materials, a family of metal films including aluminum (Al), ruthenium (Ru), molybdenum (Mo), etc. have proven to achieve good gap filling without or with substantially no seam formation. One suitable non-limiting use is in metal gate manufacturing schemes.

[0014]

[0018] As used herein, terms such as "seamless", "seamless" are intended to mean "seamless" and / or "substantially seamless".

[0015]

[0019] As used herein, terms such as "substantially seam-free" are intended to include structures where seams are detectable by transmission electron microscopy (TEM) but the seams have a width of about 3 angstroms or less over the entire length of the feature.

[0016]

[0020] Alternatively or additionally, terms such as "substantially seam-free" as used herein are intended to mean that there are seams detectable by transmission electron microscopy, but that even if there are seams, the impact on the electrical performance of the semiconductor having the feature to be filled is minimal.

[0017]

[0021] Terms such as "minimal impact on electrical performance" as used herein are intended to mean that when a semiconductor fills a feature within the semiconductor, it undergoes a change in flat band voltage (Vfb) of from about 0% to about 5% or less (e.g., from about 0 to about 5%) and / or a change in equivalent oxide thickness (EOT) of 5% or less (e.g., from about 0 to about 5%).

[0018]

[0022] FIG. 2 schematically shows a substrate 200 that can surround a feature 204 and has a base layer 202 formed according to an embodiment of the present disclosure. In an embodiment, the substrate 200 may be for a contact structure 210 such as a metal gate.

[0019]

[0023] In an embodiment, the base layer 202 can be a layer of a single material or compound that can include silicon (Si). Alternatively, the base layer 202 can include a plurality of layers (e.g., a film stack) that can be present during the manufacture of a device such as a transistor. The feature 204 can generally be a space 211 disposed between opposing sidewalls 204a (or both sides of a circular or curved sidewall) of the base layer 202, and this space can extend vertically to the bottom 204b of the feature 204. For example, the feature 204 can be a trench, via, or the like.

[0020]

[0024] In an embodiment, the barrier layer 206 can be formed on the upper surface 202a of the base layer 202 and on other surfaces of the feature 204 (e.g., on and along the sidewalls 204a and the bottom 204b of the feature 204). The barrier layer 206 can generally be deposited to form a conformal layer on and within the base layer 202 and the feature 204. In an embodiment, the barrier layer 206 may be directly adjacent to the base layer 202. In other embodiments, the barrier layer 206 may be adjacent to, but not directly adjacent to, the base layer 202, and one or more other layers may be intermediate the base layer 202 and the barrier layer 206.

[0021]

[0025] According to an embodiment, the barrier layer 206 can be one layer of a single material or compound. Alternatively, the barrier layer 206 can include multiple layers.

[0022]

[0026] In an embodiment, the barrier layer 206 can be one or more layers of titanium nitride (TiN). In other embodiments, the barrier layer 206 can be a mixture containing TiN. In an embodiment, the barrier layer 206 can be about 50 to about 100 weight percent TiN. In an embodiment, the barrier layer 206 can be deposited, for example, by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0023]

[0027] In an embodiment, the barrier layer 206 can have a total volume within the feature 204 that is about 5% to about 95% of the total volume of the unfilled feature 204. In an embodiment, the barrier layer 206 can have a thickness 206a within the feature 204 that is about 5% to about 95% of the width / diameter (i.e., critical dimension) 204c of the feature 204.

[0024]

[0028] In an embodiment, the metal (or contact) layer 208 can then be formed on the barrier layer 206. In an embodiment, the metal layer 208 may be directly adjacent to the barrier layer 206. In other embodiments, the metal layer 208 may be adjacent to the barrier layer 206 but not directly, with one or more other layers being intermediate the metal layer 208 and the barrier layer 206. The metal layer 208 can extend within and over the feature 204 and over the top surface 202a of the base layer 202. Thereby, the metal layer 208 can function as an electrical contact layer.

[0025]

[0029] According to an embodiment, the metal layer 208 can be one layer of a single material or compound. Alternatively, the metal layer 208 can include multiple layers.

[0026]

[0030] According to an embodiment, the metal layer 208 can be one of aluminum (Al), molybdenum (Mo), or ruthenium (Ru). In an embodiment, the metal layer 208 can be one of the aforementioned alloys. In an embodiment, the metal layer 208 can be one or more combinations of the aforementioned elements and / or alloys.

[0027]

[0031] In an embodiment, the metal layer 208 can be about 80 to about 100 weight percent Al. In an embodiment, the metal layer 208 can be about 80 to about 100 weight percent Mo. In an embodiment, the metal layer 208 can be about 80 to about 100 weight percent Ru. In an embodiment, the metal layer 208 can be about 97 to about 100 weight percent Ru.

[0028]

[0032] In an embodiment, the metal layer 208 can have a total volume within the feature that is about 5% to about 95% of the total volume of the unfilled feature 204. In an embodiment, the metal layer 208 can have a thickness 208a within the feature 204 that is about 5% to about 95% of the width / diameter (i.e., critical dimension) 204c of the feature 204.

[0029]

[0033] In some embodiments, feature 204 has a critical dimension of about 25 nm or less. In some embodiments, feature 204 has a critical dimension of from about 13 nm to about 25 nm. The barrier layer 206 has a thickness of from about 5 to about 95% of the critical dimension of feature 204, and the metal layer 208 has a thickness of from about 5 to about 95% of the critical dimension of feature 204. In some embodiments, the barrier layer has a thickness of from about 20 angstroms to about 40 angstroms. In some embodiments, the metal layer has a thickness of from about 20 angstroms to about 40 angstroms.

[0030]

[0034] The metal layer 208 can be seamless, and thus the gap fill or fill material (i.e., the combined barrier layer and metal layers 206, 208) can be seamless.

[0031]

[0035] In embodiments, the process of forming one or more TiN barrier layers 206 can include ALD. The base layer 202 can be exposed to a titanium precursor to form titanium species on the base layer 202. In some embodiments, the titanium precursor can include one or more of titanium chloride (TiCl4), titanium fluoride (TiF4), titanium iodide (TiI4), titanium bromide (TiBr4), and tetrakis(dimethylamino)titanium (TDMAT). In certain embodiments, the titanium precursor includes titanium chloride (TiCl4). In some embodiments, the base layer 202 can be exposed to the titanium precursor at a temperature in the range of from about 200°C to about 600°C, or from about 200°C to about 550°C. The base layer 202 can then be exposed to a nitrogen-containing reactant to form a titanium nitride film on the base layer 202. In one or more embodiments, the nitrogen-containing reactant can be ammonia (NH3) or hydrazine (N2H4).

[0032]

[0036] In embodiments, the process of forming one or more TiN barrier layers 206 can include performing a periodic metal deposition process on the base layer 202 and annealing one or more TiN barrier layers 206.

[0033]

[0037] In other embodiments, the process of forming one or more TiN barrier layers 206 may include exposing the base layer 202 to a deposition mixture gas to deposit one or more TiN barrier layers 206 on the base layer 202, and exposing the one or more TiN barrier layers 206 to a plasma treatment process.

[0034]

[0038] In a further embodiment, the process of forming one or more TiN barrier layers 206 may include optionally performing a pretreatment process on the base layer 202 (e.g., when the base layer 202 is a substrate), performing a wetting layer deposition to deposit a wetting layer on the base layer 202, performing a periodic metal deposition to deposit one or more TiN barrier layers 206 on the base layer 202, and performing an annealing process on the one or more TiN barrier layers 206.

[0035]

[0039] In still other embodiments, the process of forming one or more TiN barrier layers 206 may include optionally performing a pretreatment process on the base layer 202 (e.g., when the base layer 202 is a substrate), performing a barrier layer deposition to deposit a barrier layer on the base layer 202, performing a wetting layer deposition process to deposit a wetting layer on the base layer 202, performing an annealing process on the wetting layer, performing a metal deposition to deposit one or more TiN barrier layers 206, exposing the one or more TiN barrier layers 206 to a plasma treatment process, and performing an annealing process on the one or more TiN barrier layers 206.

[0036]

[0040] In some embodiments, when the metal layer 208 is molybdenum (Mo), the Mo layer can be deposited using, for example, ALD. For example, the Mo film can be deposited on the TiN barrier layer 206 using an ALD process at a temperature from about 350°C to about 600°C and a pressure from about 1 to 50 Torr. Suitable precursors can include molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum. The resulting Mo film can fill spaces with critical dimensions (CD) exceeding 3 nm.

[0037]

[0041] In other embodiments, when the metal layer 208 is Mo, atomic layer deposition can be used to expose the base layer 202 to a molybdenum precursor to deposit a film on the barrier layer 206. In one or more embodiments, the molybdenum precursor can include one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum. In some embodiments, the barrier layer 206 can be exposed to the molybdenum precursor at a pressure in the range from about 10 Torr to about 50 Torr and a temperature in the range from about 400°C to about 550°C.

[0038]

[0042] Subsequently, in some embodiments, the gap filling process may include exposing the barrier layer 206 to a molybdenum precursor and reactants (e.g., hydrogen (H2)) to form a bulk molybdenum film. In one or more embodiments, the molybdenum precursor may include one or more of molybdenum chloride (MoCl5), molybdenum fluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), hexacarbonyl molybdenum (Mo(CO)6), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum. In some embodiments, the barrier layer is exposed to the molybdenum precursor at a pressure in the range of about 10 Torr to about 50 Torr and a temperature in the range of about 400 °C to about 550 °C. Subsequently, the substrate 200 can be annealed at a temperature in the range of about 600 °C to about 1200 °C in an atmosphere of nitrogen (N2), helium (He), argon (Ar), hydrogen (H2) gas, or a combination thereof.

[0039]

[0043] In some embodiments, when the metal film layer 208 is aluminum (Al), the Al layer can be deposited, for example, by CVD. For example, an Al film can be deposited on the TiN barrier layer 206 using a CVD process at a temperature of about 100 °C to about 300 °C and a pressure of about 1 to 50 Torr. Suitable precursors may include triethylaluminum (TEA), dimethylaluminum hydride (DMAH), or trimethylaluminum (TMA).

[0040]

[0044] In some embodiments, when the metal layer 208 is ruthenium (Ru), the Ru layer can be deposited, for example, by ALD. For example, using an ALD process at a temperature from about 250 °C to about 350 °C, a Ru film can be deposited on the TiN barrier layer 206. Suitable precursors can include zerovalent Ru precursors having an open diene as one of the ligands. In this process, an alkyl halide is used as a catalyst to adsorb the halide on the surface and cleave the Ru-ligand bond. The inventors have observed that depositing a Ru film under the aforementioned conditions can minimize the roughness of the deposited film and reduce the presence of seams in the final structure.

[0041]

[0045] After the deposition of the aforementioned Ru film, an annealing process can be performed at a temperature above about 400 °C (e.g., from about 400 °C to 450 °C) for about 1 to 30 minutes in an environment of hydrogen gas (H2) maintained at about 1 to 50 Torr. The annealing process can be performed in the same process chamber or in a separate chamber configured to perform the annealing process.

[0042]

[0046] In some embodiments, when the metal layer 208 is Ru and the Ru layer is deposited by ALD, there may be no vacuum break between the deposition of the metal layer 208 and the deposition of the barrier layer 206. In some embodiments where there is a vacuum break between the deposition of the metal layer 208 and the deposition of the barrier layer 206, the barrier layer 206 can be pretreated. In an embodiment, the pretreatment can utilize N or H radicals, or direct plasma. For example, using a metal clean version xT (MCxT) or a similar chamber, an inductively coupled plasma with H2 or an H2 / N2 mixture and a biased pedestal can be employed to react oxygen from the TiN barrier layer. In an embodiment, the plasma power can be from about 400 W to about 900 W, and the bias can be from about 50 W to about 300 W.

[0043]

[0047] In some embodiments, the metal layer 208 is Ru. When the Ru layer is deposited by ALD, the precursor can be a Ru-diene such as p-cymene Ru hexadiene or p-cymene Ru cyclohexadiene. The catalyst can be an alkyl halide such as alkyl iodide or alkyl bromide. In an embodiment, the barrier layer 206 may be pre-soaked in the catalyst at a temperature from about 250 °C to about 350 °C. The pressure may be about 20 Torr for about 10 seconds to about 60 seconds. In an embodiment, after the aforementioned pre-soaking, one cycle of Ru deposition follows, and then up to 5 cycles can be repeated.

[0044]

[0048] In some embodiments, the metal layer 208 is Ru. When the Ru layer is deposited by ALD, the deposited metal layer 208 can be annealed at up to about 450 °C (e.g., a temperature from about 400 °C to about 450 °C). The metal layer 208 can be annealed for about 5 minutes to about 30 minutes. In some embodiments, the metal layer 208 can be annealed in an H2 environment. The inventors have observed that annealing in the presence of H2 can advantageously shorten the time required for annealing.

[0045]

[0049] To evaluate the electrical impact of the material of the metal fill layer 208, a MOSCAP test was performed. The data advantageously shows that the electrical impact is minimal.

[0046]

[0050] In some embodiments, the deposition of the films for the metal fill layer 208 and the barrier layer 206 can be performed in a stand-alone processing chamber. Alternatively and advantageously, the deposition of the films for the metal layer 208 and the barrier layer 206 can be integrated within a multi-chamber processing system (e.g., a cluster tool), such as a line of ENDURA® processing tools available from Applied Materials, Santa Clara, California.

[0047]

[0051] FIG. 3 is a flow diagram of a method 300 that may be employed to fabricate a semiconductor device structure on a substrate, such as the embodiments shown in FIGS. 2A-2F. In an embodiment, method 300 may be employed to fabricate a contact structure for a semiconductor gate. Method 300 may correspond to the manufacturing stages shown in FIGS. 4A-4E. For illustrative purposes, the method of FIG. 3 is provided with reference to a barrier layer and / or a metal contact layer deposited by CVD, ALD, or PVD. In an embodiment, method 300 can eliminate / prevent seams formed in the contact structure.

[0048]

[0052] Method 300 may begin at block 310 by providing a substrate, such as substrate 402 shown in FIG. 4A, within a processing chamber. Substrate 402 shown in FIG. 4A includes a semiconductor device structure 408 (e.g., a gate structure or other structure configured to form a contact structure) formed on substrate 402.

[0049]

[0053] A silicon layer 404 may be formed on substrate 402 on which one or more features 406 are formed. One or more features 406 (which may be contact openings, contact vias, contact trenches, contact channels, etc.) may be formed within device structure 408 and have sidewalls 412 and a bottom 414 that form an opening channel to expose the underlying silicon layer 404. Silicon layer 404 may include any suitable layer (e.g., a single silicon layer or a plurality of layer stacks in which at least one silicon layer is formed).

[0050]

[0054] In one embodiment where silicon layer 404 is in monolayer form, silicon layer 404 may be a silicon oxide layer, an oxide layer, a silicon nitride layer, a nitride layer, a silicon oxynitride layer, a titanium nitride layer, a polycrystalline silicon layer, a microcrystalline silicon layer, a single crystal silicon, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped single crystal silicon.

[0051]

[0055] In embodiments where the silicon layer 404 is a film stack, the stack may include a composite layer of oxide and nitride, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof. Suitable dopants to be doped in the silicon layer 404 may include p-type dopants and n-type dopants (e.g., boron (B)-containing dopants or phosphine (P)-containing dopants).

[0052]

[0056] In embodiments where the silicon layer 404 is in the form of a plurality of film stacks having at least one silicon-containing layer, the silicon layer 404 may include a repetition of pairs of layers including a silicon layer and a dielectric layer. In embodiments, the silicon layer 404 may include a polycrystalline silicon layer and / or other metal materials, and / or dielectric layers disposed therein. Suitable examples of dielectric layers may be selected from the group consisting of, among others, oxide layers, silicon oxide layers, silicon nitride layers, nitride layers, titanium nitride layers, composite layers of oxide and nitride, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof.

[0053]

[0057] In block 310, prior to transporting the substrate 402 into the processing chamber, in block 320, a pre-cleaning process may optionally be performed to treat the substrate surface 411, the sidewalls 412 and the bottom 414 of the opening / feature 406 to remove native oxide or other sources of contamination. By removing the native oxide or other sources of contamination from the substrate 402, a low contact resistance surface is provided and a good contact surface for forming a barrier layer can be formed.

[0054]

[0058] The pre-cleaning process may include, at block 320, supplying a pre-cleaning mixed gas into a pre-cleaning chamber. The pre-cleaning chamber may be a PreClean PCII, PCXT or Siconi™ chamber available from Applied Materials, Santa Clara, California. The pre-cleaning process may include supplying a cleaning mixed gas into the pre-cleaning chamber to form plasma from the pre-cleaning mixed gas to remove native oxides. In an embodiment, the pre-cleaning mixed gas may be a mixture of ammonia and nitrogen trifluoride gas. The amount of each gas introduced into the processing chamber may be varied and adjusted to suit, for example, the thickness of the native oxide layer to be removed, the shape dimensions of the substrate to be cleaned, the volume capacity of the plasma, the volume capacity of the chamber body, and the function of the vacuum system connected to the chamber body.

[0055]

[0059] Also, at block 320, a pre-treatment process may optionally be performed to pre-treat the substrate surface 411, and thus, as shown in FIG. 4B, a treated surface region 410 may be formed on the surface 411, and sidewalls 412 and bottoms 414 of features 406 may be formed within the silicon layer 404. The pre-treatment process of block 320 is performed to change the surface bonding structure of the silicon layer 404, thereby providing a surface with good adsorption ability that promotes the adhesion of metal atoms provided from a subsequent barrier layer deposition process. The pre-treatment mixed gas may include at least a hydrogen-containing gas such as H2, H2O, H2O2. An inert gas such as Ar, He, Kr may be supplied into the pre-treatment mixed gas.

[0056]

[0060] In block 330, as shown in FIG. 4C, a barrier layer deposition process may be performed to deposit a barrier layer 416 on the substrate and / or on the processed surface region 410. The barrier layer 416 may prevent the diffusion of the contact metal layer into the bonding material on the substrate (typically a compound of silicon or silicon germanium). The barrier layer 416 may be deposited, for example, by atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or physical vapor deposition (PVD). In an embodiment, the barrier layer 416 may have a thickness in the range of about 2 Å to about 100 Å, or about 3 Å to about 80 Å, or about 4 Å to about 50 Å.

[0057]

[0061] In block 335, as shown in FIG. 4D, an optional wetting layer deposition for depositing a wetting layer 418 on the barrier layer 416 may be performed. The wetting layer may be deposited, for example, by a process selected from CVD TiN, PVD TiN, CVD Ru, PVD Ru, nitridation of PVD Ti, or combinations thereof.

[0058]

[0062] In embodiments where a CVD process is used to deposit the wetting layer 418, the desired precursor gas may be provided to the chamber and may be further provided in the presence of a carrier gas.

[0059]

[0063] In an embodiment where a PVD process is used to deposit the wetting layer 418, a target containing the desired material to be deposited is provided, and a PVD process is performed to deposit the PVD wetting layer. In one embodiment, the wetting layer comprises PVD TiN. In such an embodiment, a Ti target is provided, and Ti can be sputtered by colliding with ions to deposit the wetting layer 418 on the barrier layer 416. A nitriding process using a nitrogen-containing precursor such as NH3 in the presence of plasma can be performed on the PVD Ti layer to form the TiN wetting layer 418. In such an embodiment, the wetting layer 418 comprises a nitrided Ti layer, and only the top few angstroms of titanium are converted to the TiN compound.

[0060]

[0064] In block 340, an optional annealing process can be performed on the wetting layer 418. The annealing process can reduce the surface roughness of the wetting layer 418, increase the grain size of the crystal structure, and reduce impurities (such as carbon) that may be present in the wetting layer 418. The annealing process can be performed at a temperature from about 200°C to about 500°C. In an embodiment, the annealing process can be performed for about 10 seconds to about 1000 seconds.

[0061]

[0065] In block 350, as shown in FIG. 4E, a contact metal deposition process can be performed in the processing chamber to deposit the metal contact layer 420. The metal contact layer 420 can be deposited using a periodic deposition process. Thereby, the metal contact layer 420 can fill the feature 406 without seams inside.

[0062]

[0066] The metal contact layer 420 can be deposited using a multi-step deposition process that includes a plurality of cycles of performing a periodic metal deposition process to deposit the metal contact layer 420.

[0063]

[0067] The metal contact layer 420 can be deposited, for example, by atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or physical vapor deposition (PVD). In an embodiment, the thickness of the metal contact layer 420 can be less than 50% of the feature diameter (critical dimension) of the smallest feature to be filled.

[0064]

[0068] In an embodiment, a periodic metal deposition process can be performed to partially fill the feature to less than half of the feature diameter, followed by an optional annealing process at block 350. Then, the periodic deposition process can be repeated, followed by an optional annealing until the metal contact layer 420 reaches a predetermined thickness. In an alternative embodiment, the metal contact layer 420 can be deposited to completely fill the feature in a single non-periodic deposition process. In such an embodiment, the metal contact layer 420 can then be optionally annealed.

[0065]

[0069] At block 360, the metal contact layer 420 may optionally be subjected to a plasma treatment process. The plasma treatment process can provide a process gas (e.g., H2) to the chamber and apply an RF current to form the process gas in the plasma. In one embodiment, the frequency of the RF current can be from about 200 W to about 800 W. The plasma treatment process can be performed for from about 1 second to about 60 seconds. In one embodiment, the substrate 402 is heated to a temperature of from about 100 °C to about 200 °C to further reduce the surface roughness of the metal contact layer 420 and reduce the percentage of impurities that may be present in the metal contact layer 420.

[0066]

[0070] In block 370, an annealing process can be optionally performed on the metal contact layer 420. The annealing process can reduce the surface roughness of the metal contact layer 420 and can reduce impurities (such as carbon) that may be present in the metal contact layer 420. Further, the annealing process can increase the crystal grain size, result in lower resistance, and improve the performance of the integrated circuit. The annealing process can be performed at a temperature from about 250 °C to about 350 °C. The annealing process can be performed in a chamber environment in which an inert gas (such as argon) and a process gas (such as H2) are provided in the chamber. In some embodiments, the annealing process can be performed for about 30 seconds to about 90 seconds.

[0067]

[0071] FIG. 5 shows a schematic top view of an exemplary multi-chamber processing system 500 that can be adapted to perform the processes disclosed above. The multi-chamber processing system 500 includes a plurality of processing chambers configured to perform various processes incorporated into the multi-chamber processing system 500.

[0068]

[0072] The multi-chamber processing system 500 includes one or more load lock chambers 502, 504 for transporting substrates to and from the system 500. Typically, since the system 500 is under vacuum, the load lock chambers 502, 504 can "pump down" the substrates introduced into the multi-chamber processing system 500. A first robot 510 disposed in the first transfer chamber can transport substrates between the load lock chambers 502, 504 and a first set of one or more substrate processing chambers (e.g., processing chambers 511, 512, 513, 514). Each processing chamber 511, 512, 513, 514 is configured to perform at least one substrate processing step, such as an etching process, a processing process, a deposition process (e.g., ALD, CVD, PECVD, PVD, etc.), degassing, pre-cleaning, orientation, and other substrate processes including the processes of the present disclosure.

[0069]

[0073] In some embodiments, the first robot 510 may also transfer substrates to / from one or more pass-through chambers 522, 524. The pass-through chambers 522, 524 can be used to enable transfer of substrates within the system 500 to the second transfer chamber while maintaining ultra-high vacuum conditions. The second robot 530 is disposed within the second transfer chamber and can transfer substrates between the pass-through chambers 522, 524 and a second set of one or more processing chambers 532, 534, 536, 538. The processing chambers 532, 534, 536, 538 are configured to perform one or more specific substrate processes including the processes described herein and other suitable processes that may be performed before or after the processes disclosed herein. For example, at least one of the processing chambers 532, 534, 536, 538 is configured to perform a substrate processing step such as a deposition process (e.g., ALD, CVD, PECVD, PVD, etc.) by the methods described herein.

[0070]

[0074] Any of the processing chambers 511, 512, 513, 514, 532, 534, 536, 538 can be removed from the multi-chamber processing system 500 if not required for the processes executed by the system 500.

[0071]

[0075] In some embodiments, the multi-chamber processing system 500 includes at least one first deposition chamber configured to deposit a first layer within features (e.g., the barrier layer 206 described above) formed on and within a substrate. In some embodiments, the multi-chamber processing system 500 further includes at least one second deposition chamber configured to deposit a metal fill layer (e.g., the metal fill layer 208 described above). For example, the first deposition chamber and the second deposition chamber can be one of an ALD chamber, a CVD chamber, a PECVD chamber, a PVD chamber, etc., and are specifically configured to deposit one or more of the above materials. In some embodiments, for example, when a Ru film is used, one or more of the processing chambers of the multi-chamber processing system 500 can be an annealing chamber configured to perform the annealing process described above on the deposited Ru film.

[0072]

[0076] The microprocessor controller 540 can be provided to and coupled with various components of the multi-chamber processing system 500 to control their operations. The controller 540 includes a central processing unit (CPU) 542, a memory 546, and support circuitry 544. The controller 540 can control the multi-chamber processing system 500 directly or through other computers (or controllers) associated with components of a particular process chamber and / or support system. The controller 540 can be one of any form of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The memory 546 of the controller 540 or the computer-readable medium can be one or more of readily available memories such as random access memory (RAM), read only memory (ROM), floppy disks, hard disks, optical storage media (e.g., compact disks or digital video disks), flash drives, or any other form of digital storage, local or remote. The support circuitry 544 is coupled to the CPU in a conventional manner to support the processor. These circuits include caches, power supplies, clock circuits, input / output circuits, and subsystems, among others. The method of the present invention described herein can be stored in the memory 546 as software routines that can be executed or called to control the operation of the multi-chamber processing system 500 in the manner described herein, or as individual processing chambers coupled to the multi-chamber processing system 500. The software routines can also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU.

[0073]

[0077] While the foregoing description is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

Claim 1 A method of forming a contact structure in a semiconductor device having features, comprising: forming a barrier layer of TiN pretreated using inductively coupled plasma having H2 or an H2 / N2 mixture within the features; forming a metal layer of ruthenium (Ru) directly adjacent to and on the barrier layer and within the features using an atomic layer deposition (ALD) process at a temperature of 250° C. to 350° C.; The method as described above. Claim 2 in an atmosphere of hydrogen (H ２ ) gas, the method according to claim 1, further comprising annealing the metal layer at a temperature exceeding 400 °C. Claim 3 The method according to claim 1 or 2, further comprising eliminating seams in the contact structure. Claim 4 The method according to any one of claims 1 to 3, wherein the metal layer is formed by periodically repeating a deposition process and an annealing process. Claim 5 The method according to any one of claims 1 to 4, wherein the barrier layer has a thickness of 40 angstroms or less and the metal layer has a thickness of 40 angstroms or less. Claim 6 The method according to any one of claims 1 to 5, wherein the features have a critical dimension (CD) of 13 nm to 25 nm.

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