Multi-chip module, and electronic control device including the multi-chip module

Abstract

To provide a multichip module in which noise to a communication path is reduced.SOLUTION: A multichip module 100 includes a module substrate 1 having a plurality of substrate electrodes and a plurality of wirings, and a semiconductor element 2 and a power supply circuit 3 mounted on the module substrate. The semiconductor element includes a plurality of communication terminals 211 having a communication interface function as element terminals, and an element power supply terminal 212 and an element ground terminal 213 connected to a power supply path including a part of the wiring and a part of the substrate electrode, which are paths to the power supply circuit. The power supply circuit includes a circuit terminal connected to the power supply path. The module substrate includes a communication path that includes a part of the wiring and a part of the substrate electrode that are different from the power supply path, and is connected to the communication terminal. The communication path is provided outside the opposing area of the power supply path in the direction in which the semiconductor element is mounted on the module substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a multi-chip module and an electronic control device including the multi-chip module.

Background Art

[0002] Patent Document 1 discloses an example of a multi-chip module. The multi-chip module has a module substrate and semiconductor elements mounted on the module substrate, and is mounted on a main substrate. The semiconductor elements are supplied with power via surface power wirings provided on the surface layer of the main substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, although not in the prior art, a multi-chip module may have a configuration in which a semiconductor element having a communication function and a power supply circuit for supplying power to the semiconductor element are mounted on the mounting surface of the module substrate. Further, the module substrate may have a configuration including a conductor pattern laminated via an insulator as wiring and an interlayer connection portion for connecting conductor patterns of different layers. This multi-chip module includes a power supply path that is wiring connecting the semiconductor element and the power supply circuit, and a communication path that is wiring used for communication of the semiconductor element.

[0005] However, in the multi-chip module, in the power supply path and the communication path, wiring between adjacent layers or adjacent vias may run parallel to each other. When the multi-chip module runs parallel in this way, noise may be superimposed on the communication path.

[0006] One of the disclosed objectives is to provide a multi-chip module with reduced noise on the communication path. Another disclosed objective is to provide an electronic control device capable of suppressing the propagation of noise from the multi-chip module.

Means for Solving the Problems

[0007] The multi-chip module disclosed herein has a plurality of substrate electrodes (13a to 13e, 14) and a plurality of wirings connected to the substrate electrodes. As the wirings, it has a module substrate (1) having a conductor pattern laminated via an insulator and an interlayer connection portion connecting conductor patterns of different layers, a semiconductor element (2) having a plurality of element terminals (21, 211 to 213), with the element terminals connected to the substrate electrodes and mounted on the module substrate, and a power supply circuit (3) having a plurality of circuit terminals (32a, 32b), with the circuit terminals connected to the substrate electrodes and mounted on the module substrate to supply power to the semiconductor element. The semiconductor element has, as element terminals, a plurality of communication terminals (211) having a communication interface function and power supply terminals (212, 213) connected to a power supply path including a part of the wiring and a part of the substrate electrodes that is a path between the semiconductor element and the power supply circuit. The power supply circuit has the circuit terminals connected to the power supply path, The module substrate has a communication path including a part of the wiring and a part of the substrate electrodes different from the power supply path and connected to the communication terminals and , a plurality of low-speed chip terminals (16) on the opposite surface of the mounting surface on which the semiconductor element and the power supply circuit are mounted and has The communication path is provided outside the opposing region of the power supply path in the mounting direction of the semiconductor element with respect to the module substrate. The communication terminals are used for high-speed communication. In addition to the communication terminals, the semiconductor element provided in a part of the opposing region of the plurality of low-speed chip terminals in the mounting direction, is provided with low-speed communication terminals (26a) used for low-speed communication slower than high-speed communication. The module substrate has a low-speed communication path including a part of the wiring and a part of the substrate electrodes different from the power supply path and the communication path and connected to the low-speed communication terminals. At least a part of the low-speed communication path is provided in the opposing region of the power supply path in the mounting direction. and the power supply path is linearly arranged between the power supply circuit and the semiconductor element in a plan view It exists.

[0008] In this way, in the multi-chip module, the communication path is arranged outside the opposing region of the power supply path. Therefore, the multi-chip module can reduce the region where the communication path and the power supply path run parallel compared to the configuration where the communication path is arranged in the opposing region of the power supply path. Thus, the multi-chip module can reduce the noise superimposed from the power supply path to the communication path.

[0009] The electronic control device disclosed herein includes the above multi-chip module, and a wiring board (200) on which the multi-chip module is mounted, and the wiring board includes an insulating substrate (201), a plurality of wiring layers (202) laminated via the insulating substrate, and a plurality of through vias (203) penetrating the insulating substrate and electrically connecting the respective wiring layers.

[0010] The electronic control device includes a multi-chip module. Therefore, in the electronic control device, the noise superimposition from the power supply path to the communication path in the multi-chip module is reduced. Thus, the electronic control device can suppress the noise propagated from the multi-chip module to the multilayer wiring board via the communication path. Also, the electronic control device uses a wiring board provided with through vias. Therefore, the electronic control device can more easily suppress the deterioration of noise than using a build-up board as the wiring board.

[0011] In the plurality of aspects disclosed in this specification, different technical means are adopted to achieve their respective purposes. The claims and the reference signs in parentheses described in this section are for illustrative purposes of the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The objects, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the attached drawings.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Modes for Carrying Out the Invention

[0013] Hereinafter, with reference to the drawings, a plurality of modes for carrying out the present disclosure will be described. In each mode, the same reference signs may be given to the parts corresponding to those described in the preceding mode, and redundant explanations may be omitted. In each mode, when only a part of the configuration is described, other parts of the configuration may be referred to and applied with reference to other modes described previously.

[0014] (First Embodiment) With reference to FIGS. 1 and 2, the multi-chip module 100 and the electronic control unit 1000 will be described. The electronic control unit 1000 is configured to be mountable on a vehicle, for example. That is, the electronic control unit 1000 can be adopted in, for example, an in-vehicle electronic control unit. The electronic control unit 1000 includes the multi-chip module 100 and the mother board 200. Hereinafter, the multi-chip module will also be referred to by the abbreviation MCM.

[0015] <Multi-chip module> The MCM 100 includes a module substrate 1, semiconductor elements 2, and a power supply circuit 3. In the MCM 100, mounting components such as the semiconductor elements 2 and the power supply circuit 3 are mounted on the module substrate 1. Further, the MCM 100 may include a memory device and the like in addition to the semiconductor elements 2 and the power supply circuit 3.

[0016] The module substrate 1 includes an insulating substrate 10, a protective film 11, a pattern wiring 12a, an interlayer connection portion 12b, a plurality of pads 13e to 13e, 14, and chip connection terminals 15. The insulating substrate 10 is mainly composed of an electrically insulating member such as resin or ceramics. The insulating substrate 10 corresponds to an insulator. The module substrate 1 has a mounting surface on which the semiconductor elements 2 and the power supply circuit 3 are mounted and a surface opposite to the mounting surface.

[0017] The protective film 11 is mainly composed of an electrically insulating member. The protective film 11 covers the surface of the insulating substrate 10 and the pattern wiring 12a provided on the surface of the insulating substrate 10 so that at least a part of each of the pads 13e to 13e, 14 is exposed. The protective film 11 is provided to ensure electrical insulation between the pads 13e to 13e, 14 as necessary. Further, the protective film 11 is provided to protect the surface of the insulating substrate 10 and the pattern wiring 12a provided on the surface of the insulating substrate 10.

[0018] The pattern wiring 12a and the interlayer connection part 12b constitute the wiring. The pattern wiring 12a and the interlayer connection part 12b are mainly composed of conductive members. The pattern wiring 12a is laminated via the insulating substrate 10. The pattern wiring 12a is provided on the inner layer and the surface layer of the insulating substrate 10. The interlayer connection part 12b connects the pattern wirings 12a of different layers. The module substrate 1 is provided with a plurality of pattern wirings 12a and a plurality of interlayer connection parts 12b. The pattern wiring 12a corresponds to a conductor pattern.

[0019] The plurality of pads 13a to 13e, 14 are mainly composed of conductive members. Each of the pads 13a to 13e, 14 is connected to the pattern wiring 12a and the interlayer connection part 12b, respectively. The plurality of pads 13a to 13e are provided on the mounting surface side of the module substrate 1. The back surface pad 14 is provided on the opposite surface side of the module substrate 1. Each of the pads 13a to 14 corresponds to a substrate electrode.

[0020] The module substrate 1 has a power supply path constituted by a part of the wiring and a part of the substrate electrodes. The module substrate 1 has a supply path and a ground path as the power supply paths. The supply path includes a part of the wiring, the first power supply pad 13a, and the second power supply pad 13b. The first power supply pad 13a and the second power supply pad 13b are electrically connected via a part of the wiring. The ground path includes a part of the wiring different from the supply path, the first ground pad 13c, and the second ground pad 13d. The first ground pad 13c and the second ground pad 13d are electrically connected via a part of the wiring different from the supply path.

[0021] In addition, the module substrate 1 has a communication path constituted by a part of the wiring different from the power supply path and a part of the substrate electrodes different from the power supply path. The communication path includes a part of the wiring different from the power supply path and the communication pad 13e. Further, the communication path includes the back surface pad 14. The communication pad 13e and the back surface pad 14 are electrically connected via a part of the wiring different from the power supply path.

[0022] The first power pad 13a, the first ground pad 13c, and the communication pad 13e are arranged to face the semiconductor element 2. The first power pad 13a is electrically connected to the element power terminal 212. The module substrate 1 is provided with the same number of first power pads 13a as the number of element power terminals 212. Therefore, when the module substrate 1 is provided with a plurality of element power terminals 212, it can be said that a first power pad group composed of a plurality of first power pads 13a is provided.

[0023] The first ground pad 13c is electrically connected to the element ground terminal 213. The module substrate 1 is provided with the same number of first ground pads 13c as the number of element ground terminals 213. Therefore, when the module substrate 1 is provided with a plurality of element ground terminals 213, it can be said that a first ground pad group composed of a plurality of first ground pads 13c is provided.

[0024] The communication pad 13e is electrically connected to the communication terminal 211. The module substrate 1 is provided with the same number of communication pads 13e as the number of communication terminals 211. Therefore, when the module substrate 1 is provided with a plurality of communication terminals 211, it can be said that a communication pad group composed of a plurality of communication pads 13e is provided.

[0025] The second power pad 13b and the second ground pad 13d are arranged to face the power supply circuit. The second power pad 13b is electrically connected to the circuit power terminal 32a. The module substrate 1 is provided with the same number of second power pads 13b as the number of circuit power terminals 32a. Therefore, when the module substrate 1 is provided with a plurality of circuit power terminals 32a, it can be said that a second power pad group composed of a plurality of second power pads 13b is provided.

[0026] The second ground pad 13d is electrically connected to the circuit ground terminal 32b. The module substrate 1 is provided with the same number of second ground pads 13d as the number of circuit ground terminals 32b. Therefore, when a plurality of circuit ground terminals 32b are provided on the module substrate 1, it can be said that a second ground pad group composed of a plurality of second ground pads 13d is provided.

[0027] The back surface pad 14 is electrically connected to the mother substrate 200. The module substrate 1 is provided with the same number of back surface pads 14 as the number of communication terminals 211. Therefore, when a plurality of communication terminals 211 are provided on the module substrate 1, it can be said that a communication pad group composed of a plurality of back surface pads 14 is provided.

[0028] The chip connection terminal 15 is electrically connected to the back surface pad 14. The chip connection terminal 15 is a terminal for connecting to the mother substrate 200 in the MCM100. The chip connection terminal 15 corresponds to a substrate terminal.

[0029] The semiconductor element 2 includes an element substrate 20 and element terminals 21. The semiconductor element 2 constitutes a communication circuit. In other words, the semiconductor element 2 has a communication function. The semiconductor element 2 includes, as element terminals 21, communication terminals 211, element power supply terminals 212, and element ground terminals 213. The element terminals 21 are mainly composed of a conductive member. The element terminals 21 are provided at a portion (hereinafter referred to as the opposing portion) of the element substrate 20 that faces the module substrate 1. The semiconductor element 2 is provided with a plurality of element terminals 21. The semiconductor element 2 is mounted on the module substrate 1 with the element terminals 21 connected to the substrate electrodes.

[0030] The communication terminal 211 has a communication interface function. The semiconductor element 2 includes a plurality of communication terminals 211. The communication terminals 211 are arranged to face the communication pads 13e. The communication terminals 211 are connected to the communication pads 13e via a conductive adhesive such as solder. Hereinafter, solder is adopted as an example of the conductive adhesive.

[0031] The semiconductor element 2 includes a plurality of element power terminals 212 and a plurality of element ground terminals 213. The plurality of element power terminals 212 are electrically connected to the first power pad 13a via solder. The plurality of element ground terminals 213 are electrically connected to the first ground pad 13c via solder. The element power terminals 212 and the element ground terminals 213 correspond to power terminals.

[0032] As shown in FIG. 1, the semiconductor element 2 is provided with a first terminal group 21a, a second terminal group 21b, a third terminal group 21c, a fourth terminal group 21d, and a power terminal group 21e. Each of the first terminal group 21a to the fourth terminal group 21d includes a plurality of communication terminals 211. The power terminal group 21e includes a plurality of element power terminals 212 and a plurality of element ground terminals 213.

[0033] The semiconductor element 2 has the power terminal group 21e disposed at the center in the opposing portion. The semiconductor element 2 has the first terminal group 21a to the fourth terminal group 21d disposed around the power terminal group 21e in the opposing portion.

[0034] In the present embodiment, as an example, an example in which one semiconductor element 2 is mounted on the module substrate 1 is adopted. The present disclosure may have a plurality of semiconductor elements 2 mounted on the module substrate 1.

[0035] The power supply circuit 3 includes a circuit board 30, a circuit power terminal 32a, and a circuit ground terminal 32b. The power supply circuit 3 is a circuit element that supplies power to the semiconductor element 2. That is, the power supply circuit 3 supplies power to the semiconductor element 2 via a power path.

[0036] The circuit power terminal 32a and the circuit ground terminal 32b are provided at a portion of the circuit board 30 that faces the module substrate 1. The power supply circuit 3 is provided with a plurality of circuit power terminals 32a and a plurality of circuit ground terminals 32b. The power supply circuit 3 is mounted on the module substrate 1 with the circuit power terminal 32a and the circuit ground terminal 32b connected to the substrate electrodes.

[0037] The plurality of circuit power terminals 32a are electrically connected to the second power pad 13b via solder. The plurality of circuit ground terminals 32b are electrically connected to the second ground pad 13d via solder. The circuit power terminal 32a and the circuit ground terminal 32b correspond to circuit terminals.

[0038] As shown in FIG. 2, in the stacking direction of the MCM1 configured as described above, the communication path is provided outside the opposing region of the power path. That is, the pattern wiring 12a, the communication pad 13e, and the back surface pad 14 are provided outside the opposing region of the power path in the stacking direction. The communication path is provided including the opposing region of the power path in the direction orthogonal to the stacking direction.

[0039] Note that the stacking direction is the direction in which the pattern wiring 12a is stacked. Further, the stacking direction coincides with the mounting direction of the semiconductor element with respect to the module substrate. Furthermore, the stacking direction also coincides with the thickness direction of the module substrate 1.

[0040] <Mother substrate> The mother substrate 200 is a wiring substrate in which a plurality of wirings 202 mainly composed of conductive members are provided on an insulating substrate 201 such as resin or ceramics. In the mother substrate 200, the plurality of wirings 202 are provided inside and on the surface of the insulating substrate 201. The mother substrate 200 has the plurality of wirings 202 stacked via the insulating substrate 201. The wiring 202 corresponds to a wiring layer.

[0041] The mother substrate 200 is a through-substrate in which through-vias 203 penetrating the insulating substrate 201 are formed. The through-via 203 is electrically connected to the wiring 202. The through-via 203 electrically connects the wirings 202 in different layers. Specifically, the mother substrate 200 has a metal film provided on the surface of a through-hole that penetrates from one surface of the insulating substrate 201 to the opposite surface as the through-via 203. In other words, the mother substrate 200 includes through-vias 203 with metal plating applied to the surface of the through-holes. Note that the surface of the through-hole is the surface of the annular wall surface surrounding the through-hole in the insulating substrate.

[0042] In the mother board 200, part of the through vias 203 are provided as electrodes on one surface and the opposite surface of the insulating substrate 201. The mother board 200 has the electrodes and the chip connection terminals 15 connected via solder. The mother board 200 corresponds to a wiring board. Note that the mother board 200 has wirings 202 and through vias 203 provided at a plurality of locations. However, in FIG. 2, for simplicity of the drawing, only part of the wirings 202 and through vias 203 are illustrated.

[0043] <Electronic control device> The electronic control device 1000 is configured by mounting the MCM 100 on the mother board 200. In the present embodiment, as an example, the electronic control device 1000 with one MCM 100 mounted on the mother board 200 is adopted. However, the present disclosure is not limited thereto. The electronic control device 1000 may have a plurality of MCMs 100 mounted thereon. Also, the electronic control device 1000 may have circuit elements and connectors different from the MCM 100 mounted thereon.

[0044] <Effect> When the MCM 100 configured as described above supplies power from the power supply circuit 3 to the semiconductor element 2, a large current flows through the power supply path. Then, as shown by the one-dot chain line in FIG. 2, a power supply loop is formed in the part including the power supply path in the MCM 100. Also, as shown by the two-dot chain line in FIG. 2, a current flows through the communication path in the MCM 100.

[0045] Therefore, in the MCM 100, the communication path is arranged outside the opposing region of the power supply path. For this reason, the MCM 100 can reduce the region where the communication path and the power supply path run parallel to each other, as compared with the configuration where the communication path is arranged in the opposing region of the power supply path. Thus, the MCM 100 can reduce the noise (propagation) from the power supply path to the communication path. Along with this, the MCM 100 can improve the establishment margin of the communication by the semiconductor element 2 and the power supply to the semiconductor element 2.

[0046] In this way, for the communication path, the propagation of noise generated by the current flowing through the power supply path is suppressed in the MCM100. Therefore, the noise generated by the current flowing through the power supply path is closed within the MCM100. For this reason, the MCM100 can suppress the noise diffusion from the MCM100 to the mother board 200.

[0047] The electronic control device 1000 has a higher EMC (Electromagnetic Compatibility) improvement effect when the MCM100 is mounted on the mother board 200 than when the mother board 200 and the MCM100 are configured on a single board. Furthermore, in the electronic control device 1000, the periphery of the semiconductor element having a plurality of high-speed terminal groups is the MCM100. For this reason, the electronic control device 1000 can be made inexpensive and highly reliable, and can suppress noise. Also, the electronic control device 1000 can reduce the number of layers of the mother board 200 compared to the case where the mother board 200 and the MCM100 are configured on a single board. For this reason, the electronic control device 1000 can reduce the cost of the mother board 200. Therefore, the electronic control device 1000 is more likely to exhibit the above effects. Note that the low-layer board is, for example, a board with 8 layers or less, preferably 6 layers or less. However, the mother board 200 is not limited to the low-layer board.

[0048] Also, the electronic control device 1000 includes the MCM100. This MCM100 can reduce the noise generated on the MCM100 as described above and can suppress the diffusion of noise to the mother board 200. For this reason, the electronic control device 1000 can improve the noise tolerance.

[0049] The preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments at all, and various modifications are possible without departing from the gist of the present disclosure. Hereinafter, as other forms of the present disclosure, the second to fourth embodiments will be described. The above embodiments and the second to fourth embodiments can be implemented independently, but can also be implemented in appropriate combination. The present disclosure can be implemented by various combinations without being limited to the combinations shown in the embodiments.

[0050] (Second Embodiment) The MCM100 and the electronic control device 1000 of the second embodiment will be described with reference to FIGS. 3 and 4. In this embodiment, mainly, the configuration of the module substrate 1 is different from that of the first embodiment. Note that in FIG. 4, the mother board 200 is shown in a simplified manner. The mother board 200 is the same as in the above embodiment. The same applies to the mother board 200 in other embodiments.

[0051] As shown in FIGS. 3 and 4, the module substrate 1 includes a plurality of chip terminal groups 15a to 15d. Each chip terminal group 15a to 15d includes a plurality of chip connection terminals 15. That is, each chip terminal group 15a to 15d indicates a collection of a plurality of chip connection terminals 15 included in each chip terminal group 15a to 15d. For example, the first chip terminal group 15a indicates a collection of a plurality of chip connection terminals 15 included in the first chip terminal group 15a. Each chip terminal group 15a to 15d is provided on the opposite surface of the mounting surface of the module substrate 1.

[0052] As shown in FIG. 3, the chip connection terminals 15 of each chip terminal group 15a to 15d are electrically connected to the element terminals 21 via the respective wirings 12c1 to 12c4. Each of the wirings 12c1 to 12c4 is included in the communication path. Also, it can be said that the module substrate 1 includes a plurality of wirings 12c1 to 12c4 included in different communication paths. Note that in FIG. 3, the wirings 12c1 to 12c4 are shown in a simplified manner as lines.

[0053] Specifically, the chip connection terminals 15 of the first chip terminal group 15a are connected to the element terminals 21 of the first terminal group 21a via the first wiring 12c1. The chip connection terminals 15 of the second chip terminal group 15b are connected to the element terminals 21 of the second terminal group 21b via the second wiring 12c2. The chip connection terminals 15 of the third chip terminal group 15c are connected to the element terminals 21 of the third terminal group 21c via the third wiring 12c3. The chip connection terminals 15 of the fourth chip terminal group 15d are connected to the element terminals 21 of the fourth terminal group 21d via the fourth wiring 12c4.

[0054] Each of the chip terminal groups 15a to 15d is arranged along the side of the opposite surface of the module substrate 1. The module substrate 1 has a plurality of chip connection terminals 15 arranged in a plurality of rows along the side of the opposite surface. It can be said that the module substrate 1 has a plurality of chip connection terminals 15 arranged in a rectangular frame shape. Each of the chip terminal groups 15a to 15d includes a part of the plurality of chip connection terminals 15 arranged in this way. Also, each of the chip terminal groups 15a to 15d is arranged avoiding the opposing region of the power terminal group 21e. The electronic control device 1000 has the MCM100 configured in this way mounted thereon.

[0055] Therefore, it is easy for the module substrate 1 to provide the wirings 12c1 to 12c4 outside the opposing region of the power path in the stacking direction. That is, the module substrate 1 can suppress the overlapping of the power path and the communication path including the wirings 12c1 to 12c4 in the stacking direction. Also, it can be said that the module substrate 1 can suppress the parallel running of the power path and the wirings 12c1 to 12c4 (communication path) in the stacking direction. In this embodiment, as an example, the module substrate 1 in which all the wirings 12c1 to 12c4 are arranged outside the opposing region of the power path in the stacking direction is adopted.

[0056] Also, it is preferable that each chip terminal group 15a to 15d be arranged in the vicinity of each wiring 12c1 to 12c4 at the connection destination. In other words, each chip terminal group 15a to 15d is provided at a position where each wiring 12c1 to 12c4 can be arranged without the wirings 12c1 to 12c4 crossing each other. Thereby, the MCM100 can suppress the crossing or parallel running of each communication path including the wirings 12c1 to 12c4. For this reason, the MCM100 can suppress the noise due to crosstalk between the communication paths.

[0057] Furthermore, the MCM100 can arrange many chip connection terminals 15 on the opposite surface side. Therefore, the electronic control device 1000 can improve the wiring density of the mother board 200. Of course, the electronic control device 1000 and the MCM100 of the second embodiment can achieve the same effects as those of the first embodiment.

[0058] (Third Embodiment) The MCM100 and the electronic control device 1000 of the third embodiment will be described with reference to FIGS. 5 and 6. In this embodiment, mainly, the configurations of the semiconductor element 2 and the module substrate 1 are different from those of the first embodiment.

[0059] The semiconductor element 2 is configured with a high-speed communication circuit for performing high-speed communication and a low-speed communication circuit having a lower communication speed than the high-speed communication circuit. That is, it can be said that the semiconductor element 2 has a high-speed communication function and a low-speed communication function having a lower communication speed than the high-speed communication function.

[0060] As shown in FIGS. 5 and 6, the semiconductor element 2 includes a plurality of communication terminals 211 for high-speed communication and a plurality of low-speed communication terminals 26a for low-speed communication. Each terminal group 21a to 21d can be referred to as a high-speed terminal group. The communication terminal 211 of this embodiment is a terminal used for high-speed communication. Each chip terminal group 15a to 15d and each wiring 12c1 to 12c4 are used for high-speed communication. Therefore, the communication path including the wirings 12c1 to 12c4 can be referred to as a high-speed communication path.

[0061] On one hand, the low-speed terminal group 26 includes a plurality of low-speed communication terminals 26a. The low-speed communication terminals 26a are terminals used for low-speed communication.

[0062] The module substrate 1 is provided with a plurality of low-speed chip terminals 16 on the opposite surface of the module substrate 1. Each low-speed chip terminal 16 is electrically connected to each low-speed communication terminal 26a and the fifth wiring 12c5. The plurality of low-speed chip terminals 16 are provided at the center on the opposite surface of the module substrate 1. The low-speed chip terminals 16 correspond to substrate terminals. The fifth wiring 12c5 includes some wirings and some substrate electrodes, which are different from the high-speed communication path and the power supply path. The semiconductor element 2 is provided with a low-speed communication path including the fifth wiring 12c5.

[0063] Note that the pattern wiring 12a of the power supply path is provided around the fifth wiring 12c5 in a direction orthogonal to the stacking direction. The pattern wiring 12a of the power supply path is not mechanically connected to the fifth wiring 12c5. In FIG. 6, only a part of the pattern wiring 12a of the power supply path is shown. However, the pattern wiring 12a of the power supply path is also provided outside the portion shown in FIG. 6. And the whole of the pattern wiring 12a of the power supply path is provided around the fifth wiring 12c5 in a direction orthogonal to the stacking direction. In FIG. 6, the fifth wiring 12c5 is shown in white for easy viewing of the drawing.

[0064] As shown in FIG. 6, at least a part of the low-speed communication path is provided in the opposing region of the power supply path in the stacking direction. That is, the high-speed communication path is arranged outside the opposing region of the power supply path in the stacking direction. On the other hand, the low-speed communication path is arranged inside the opposing region of the power supply path in the stacking direction. Note that the low-speed communication path may be arranged outside the opposing region of the power supply path in the stacking direction. The electronic control device 1000 has the MCM100 configured as described above mounted thereon.

[0065] The electronic control device 1000 and the MCM 100 of the third embodiment can achieve the same effects as those of the first embodiment. Further, in the MCM 100 of the third embodiment, the low-speed communication path is arranged within the opposing region of the power supply path. However, even if noise propagates through the low-speed communication path, it is less likely to have an adverse impact on communication. Therefore, the MCM 100 of the third embodiment can increase the number of wirings that can be electrically connected to board terminals such as the chip connection terminal 15 and the low-speed chip terminal 16. That is, the MCM 100 of the third embodiment can increase the number of wirings that can be electrically connected to board terminals compared to the case where the chip connection terminal 15 is provided only in a frame shape. In other words, the MCM 100 of the third embodiment can improve the wiring density of the module board 1.

[0066] Furthermore, in the MCM 100 of the third embodiment, a plurality of low-speed chip terminals 16 are provided at the center on the opposite surface of the module board 1. Therefore, the electronic control device 1000 of the third embodiment can disperse the stress generated by the warping of the MCM 100 and the mother board 200 to each board terminal. That is, the electronic control device 1000 of the third embodiment can disperse the stress to each board terminal more than in the case where the chip connection terminal 15 is provided only in a frame shape. Thus, the electronic control device 1000 of the third embodiment can improve the mounting reliability of the MCM 100 with respect to the mother board 200.

[0067] (Fourth Embodiment) The MCM 100 and the electronic control device 1000 of the fourth embodiment will be described with reference to FIG. 7. In this embodiment, mainly, the point that the bypass capacitor 4 is provided in the MCM 100 is different from that of the first embodiment.

[0068] As described above, the semiconductor element 2 has the power supply terminal group 21e arranged at the center in the opposing portion. That is, the semiconductor element 2 is provided with a plurality of element power supply terminals 212 and a plurality of element ground terminals 213 at the center in the opposing portion.

[0069] The bypass capacitor 4 is mounted on the opposite side of the module substrate 1. The bypass capacitor 4 includes a first electrode 41 and a second electrode 42. The bypass capacitor 4 is disposed between the element power supply terminal 212 and the element ground terminal 213. The first electrode 41 is connected to the element power supply terminal 212 via the pattern wiring 12a, the interlayer connection portion 12b, etc. On the other hand, the second electrode 42 is connected to the element ground terminal 213 via the pattern wiring 12a, the interlayer connection portion 12b, etc.

[0070] The bypass capacitor 4 is mounted on the opposite side of the module substrate 1 and in the facing area of the element power supply terminal 212 and the element ground terminal 213 in the mounting direction. That is, the bypass capacitor 4 is mounted in the facing area of the power supply terminal group 21e in the mounting direction.

[0071] Preferably, in the mounting direction, the module substrate 1 has the element power supply terminal 212 and the element ground terminal 213 connected to the mounting surface, and the first electrode 41 and the second electrode 42 provided on the opposite side are connected at the shortest distance. The electronic control device 1000 has the MCM100 configured in this way mounted thereon.

[0072] The electronic control device 1000 and the MCM100 of the fourth embodiment can achieve the same effects as those of the first embodiment. The MCM100 can connect the path from the element power supply terminal 212, through the bypass capacitor 4, to the element ground terminal 213 in the shortest way. Therefore, the MCM100 can minimize the impedance and maximize the power supply noise cutting effect by the bypass capacitor 4. That is, the MCM100 can connect with a lower impedance path than when the bypass capacitor 4 is placed horizontally, so the power supply noise cutting effect by the bypass capacitor 4 can be maximized. Also, for the MCM100, a reduction in the capacitance or the number of the bypass capacitors 4 can be expected.

[0073] Although the present disclosure has been described in accordance with embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and variations within the equivalent scope. In addition, although various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more than one element, or less than one element thereof are also within the scope and spirit of the present disclosure.

Description of Reference Numerals

[0074] 1... module substrate, 10... insulating substrate, 11... protective film, 12a... pattern wiring, 12b... interlayer connection portion, 12c1... first wiring, 12c2... second wiring, 12c3... third wiring, 12c4... fourth wiring, 13a... first power pad, 13b... second power pad, 13c... first ground pad, 13d... second ground pad, 13e... communication pad, 14... back surface pad, 15... chip connection terminal, 15a... first chip terminal group, 15b... second chip terminal group, 15c... third chip terminal group, 15d... fourth chip terminal group, 2... semiconductor element, 20... element substrate, 21... element terminal, 211... communication terminal, 212... element power terminal, 213... element ground terminal, 21a... first terminal group, 21b... second terminal group, 21c... third terminal group, 21d... fourth terminal group, 21e... power terminal group, 3... power supply circuit, 30... circuit board, 32a... circuit power terminal, 32b... circuit ground terminal, 100... multi-chip module, 200... mother board, 1000... electronic control device

Claims

1. A module substrate (1) having a plurality of substrate electrodes (13a to 13e, 14) and a plurality of wirings connected to the substrate electrodes, wherein the wirings include a conductor pattern laminated via an insulator and an interlayer connection portion connecting the conductor patterns of different layers, A semiconductor element (2) having a plurality of element terminals (21, 211 to 213), wherein the element terminals are connected to the substrate electrodes and mounted on the module substrate, A power supply circuit (3) having a plurality of circuit terminals (32a, 32b), wherein the circuit terminals are connected to the substrate electrodes and mounted on the module substrate to supply power to the semiconductor element, and comprising: The semiconductor element has, as the element terminals, a plurality of communication terminals (211) having a communication interface function and power supply terminals (212, 213) connected to a power supply path including a part of the wirings and a part of the substrate electrodes that are a path between the semiconductor element and the power supply circuit, The power supply circuit has the circuit terminals connected to the power supply path, The module substrate includes a communication path including a part of the wirings and a part of the substrate electrodes different from the power supply path and connected to the communication terminals, and has a plurality of low-speed chip terminals (16) on the opposite surface of the mounting surface on which the semiconductor element and the power supply circuit are mounted, The communication path is provided outside an opposing region of the power supply path in the mounting direction of the semiconductor element with respect to the module substrate, The communication terminals are used for high-speed communication, In addition to the communication terminals, the semiconductor element includes low-speed communication terminals (26a) provided in a part of an opposing region of the plurality of low-speed chip terminals in the mounting direction and used for low-speed communication slower than the high-speed communication, The module substrate has a low-speed communication path including a part of the wirings and a part of the substrate electrodes different from the power supply path and the communication path and connected to the low-speed communication terminals, At least a part of the low-speed communication path is provided in an opposing region of the power supply path in the mounting direction, The power supply path is linearly arranged between the power supply circuit and the semiconductor element in a plan view, a multi-chip module.

2. The module substrate further includes a plurality of terminal groups (15a to 15d) including a plurality of substrate terminals (15) on the opposite surface of the mounting surface of the semiconductor element and the power supply circuit. The multi-chip module according to claim 1, wherein the plurality of terminal groups are connected to the communication path and arranged along the sides of the opposite surface.

3. A multi-chip module according to claim 1 or 2, and a wiring board (200) on which the multi-chip module is mounted. The wiring board is an electronic control device including an insulating substrate (201), a plurality of wiring layers (202) laminated via the insulating substrate, and a plurality of through vias (203) passing through the insulating substrate and electrically connecting the wiring layers.

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