Through-electrode substrate

Abstract

To provide a through electrode substrate structured to easily control the capacity of a capacitor.SOLUTION: A through electrode substrate comprises: a substrate 11 including a first face 11a and a second face at an opposite side with respect to the first face 11a; a through electrode conducting the first face 11a and the second face; a first conductive layer 12 disposed on the first face 11a of the substrate 11 and electrically connected with the through electrode; a first insulating layer 14 disposed on the first conductive layer 12; and an intermediate layer 13 disposed between the first conductive layer 12 and the first insulating layer 14. The first insulating layer 14 includes: a first insulating portion 14a disposed on the intermediate layer 13; a second insulating portion 14b extending from the first insulating portion 14a and covering a side face of the intermediate layer 13 and a side face 12b of the first conductive layer 12; and a third insulating portion 14c extending from the second insulating portion 14b and covering at least a part of the first face 11a of the substrate 11.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a through electrode substrate.

Background Art

[0002] In recent years, in electronic devices, a form in which a semiconductor chip is attached to a wiring substrate via a through electrode substrate has been widely used. Patent Document 1 discloses a through electrode substrate using glass as a substrate material.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The above-described through electrode substrate has a MIM (Metal-Insulator-Metal) structure in which an insulating layer is sandwiched between metals. The MIM structure can be used, for example, as a MIM capacitor. When designing the capacitance of a capacitor, it is conceivable to adjust the size of the electrode pattern and the dielectric constant of the dielectric. However, when forming a MIM structure at a high density on a through electrode substrate, there are restrictions on the size of the electrode pattern. Conventionally, a silicon nitride (SiN) layer has been used as the dielectric, but since silicon nitride has a high dielectric constant, the degree of freedom in controlling the dielectric constant is small.

[0005] The present disclosure provides a through electrode substrate having a structure in which the capacitance of a capacitor can be easily controlled.

Means for Solving the Problems

[0006] This application includes multiple means for solving the above problems. For example, a substrate having a first surface and a second surface on the side opposite to the first surface, a through electrode that electrically connects the first surface and the second surface, a first conductive layer disposed on the first surface of the substrate and electrically connected to the through electrode, a first insulating layer disposed on the first conductive layer, and an intermediate layer disposed between the first conductive layer and the first insulating layer. The first insulating layer has a first insulating portion disposed on the intermediate layer, a second insulating portion extending from the first insulating portion to cover the side surfaces of the intermediate layer and the first conductive layer, and a third insulating portion extending from the second insulating portion to cover at least a part of the first surface of the substrate, and provides a through electrode substrate.

Effect of the Invention

[0007] According to the technology of the present disclosure, a through electrode substrate having a structure in which the capacitance of a capacitor can be easily controlled can be provided. Further features related to the present disclosure will become apparent from the description of this specification and the accompanying drawings. In addition, problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0009] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to this specification, for the convenience of illustration and easy understanding, the scale, the aspect ratio of the vertical and horizontal dimensions, etc. are appropriately changed and exaggerated from those of the actual object.

[0010] In this specification and the like, a numerical range represented by "~" means a range including the numerical values described before and after "~" as the lower limit value and the upper limit value, respectively.

[0011] Hereinafter, the form of an interposer disposed between a wiring substrate and a semiconductor chip or the like will be used for explanation, but it is not limited thereto. That is, the following embodiments can also be used as a through electrode substrate. Here, the through electrode substrate includes not only an interposer disposed between a wiring substrate and a semiconductor chip or the like, but also an IPD (Integrated Passive Device) or the like on which a semiconductor chip or the like is not installed. In this case, one of the upper and lower wiring substrates exists so as to be electrically connected to the through electrode.

[0012] FIG. 1 is a schematic cross-sectional view showing an interposer 10 according to an embodiment of the present disclosure, and FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. The interposer 10 has, for example, a MIM (Metal-Insulator-Metal) structure in which an insulating layer is sandwiched between metals. The MIM structure can be used as a MIM capacitor. In this case, a part of the first conductive layer 12 serves as the lower electrode, the first insulating layer 14 serves as the dielectric layer, and the second conductive layer 15 serves as the upper electrode.

[0013] The interposer 10 includes a substrate 11 having a first surface 11a and a second surface 11b on the side opposite to the first surface 11a, a first conductive layer 12 disposed on the first surface 11a of the substrate 11, a first insulating layer 14 disposed on the first conductive layer 12, an intermediate layer 13 disposed between the first conductive layer 12 and the first insulating layer 14, and a second conductive layer 15 disposed on the first insulating layer 14. Note that the first conductive layer 12 may be directly disposed on the first surface 11a of the substrate 11, or may be disposed on the first surface 11a of the substrate 11 via at least one layer of a conductive or insulating layer. For example, by disposing an insulating resin selected from an epoxy resin and a polyimide resin on the first surface 11a of the substrate 11, the stress generated due to the difference in the thermal expansion coefficient between the first conductive layer 12 and the substrate 11 can be alleviated.

[0014] The substrate 11 has a through hole 16 that conducts the first surface 11a and the second surface 11b. The first conductive layer 12 is electrically connected to a fourth conductive layer 22 disposed on the second surface 11b via a through electrode 17 formed in the through hole 16. The form of the through hole 16 is not limited to the illustration, and the through hole 16 may have a shape in which the width decreases as it goes from the first surface 11a and the second surface 11b of the substrate 11 toward the central portion in the thickness direction of the substrate 11, or the side wall of the through hole 16 may extend along the normal direction of the first surface 11a of the substrate 11, or may narrow along the normal direction of the first surface 11a of the substrate 11, or a part of the side wall may have a curved shape. The through hole 16 is formed by performing processing such as etching, laser processing, a combination of laser processing and etching, sandblasting, electrical discharge machining, and drilling on the substrate 11. The through electrode 17 is not limited to the form in FIG. 1, and may be a form in which a conductive material is filled in the through hole 16.

[0015] A resin layer 21 is formed on the first surface 11a and the second surface 11b of the substrate 11. On the first surface 11a of the substrate 11, the resin layer 21 is formed so as to cover the MIM structure. A connection hole 18 is provided at a position corresponding to the second conductive layer 15 of the resin layer 21. The connection hole 18 is filled with a conductive member 19. Further, a third conductive layer 20 is formed on the surface 21a of the resin layer 21. On the first surface 11a side of the substrate 11, the second conductive layer 15 is connected to the semiconductor chip 50 via the conductive member 19, the third conductive layer 20, and the solder ball 24.

[0016] On the second surface 11b of the substrate 11, a connection hole 18 is provided at a position corresponding to the fourth conductive layer 22 of the resin layer 21. The connection hole 18 is filled with a conductive member 19. Further, a fifth conductive layer 23 is formed on the surface 21b of the resin layer 21. On the second surface 11b side of the substrate 11, the fourth conductive layer 22 is connected to the wiring substrate 40 via the conductive member 19, the fifth conductive layer 23, and the solder ball 24.

[0017] According to this configuration, a semiconductor device is provided that includes an interposer 10, a semiconductor chip 50 disposed on the first surface 11a side of the substrate 11 and electrically connected to the through electrode 17, and a wiring substrate 40 disposed on the second surface 11b side of the substrate 11 and electrically connected to the through electrode 17. According to the interposer 10 of the present embodiment, mounting of the semiconductor chip 50 with a narrow terminal pitch to a large-sized wiring substrate (such as a mother board) 40 is simplified.

[0018] As the substrate 11, a glass substrate, a glass ceramic substrate, a quartz substrate, a sapphire substrate, a resin substrate, a glass epoxy substrate, a silicon substrate, an SOI (Silicon on Insulator) substrate, an SOS (Silicon on Sapphire) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, etc., or a substrate in which these are laminated can be used.

[0019] Preferably, the substrate 11 is a glass substrate. Generally, in an interposer, the displacement due to thermal deformation increases in the region closer to its edge. In the case of an interposer using a glass substrate, there is an advantage that the difference in the coefficient of thermal expansion with a wiring substrate or the like disposed above and below the interposer can be reduced for this region.

[0020] More preferably, a non-alkali glass is used as the substrate 11. Since non-alkali glass does not contain alkali components such as Na and K unlike soda glass, alkali components do not precipitate on the glass surface. Therefore, in this aspect, there is an advantage that a factor causing reliability degradation that corrodes the terminals of the semiconductor chip to be connected to the interposer does not occur in principle. Also, non-alkali glass has a coefficient of thermal expansion approximately the same as that of silicon, and has good compatibility in terms of the coefficient of thermal expansion with the semiconductor chip to be connected.

[0021] As the material of each of the above conductive layers, materials having conductivity such as gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium (Ru), tungsten (W), etc. are used. Among them, it is preferable to use copper (Cu) which has high conductivity and low material cost. Also, the thickness of the first conductive layer 12 is preferably 0.5 μm to 20 μm, and the thickness of the second conductive layer 15 is preferably 0.5 μm to 5 μm. Regarding the wiring pattern, in addition to subtractive formation by etching of a metal foil (for example, Cu, etc.), additive formation such as application of a conductive paste (for example, a metal nanopaste, etc.) or formation by plating can also be adopted.

[0022] The intermediate layer 13 is a layer containing at least one of titanium (Ti), nickel (Ni), and gold (Au). In the example of FIG. 2, the intermediate layer 13 is titanium (Ti). The thickness of the titanium layer is 20 nm to 200 nm, and preferably 50 nm to 100 nm.

[0023] The first insulating layer 14 of this embodiment is silicon nitride (SiN) containing carbon (C). When the amount of carbon (C) in the dielectric first insulating layer 14 increases, the relative permittivity decreases, making it easier to control the capacitance of the capacitor. Also, when the amount of carbon (C) in the dielectric first insulating layer 14 increases, the adhesion to the titanium (Ti) intermediate layer 13 increases. In this embodiment, the thickness of the first insulating layer 14 is 50 nm to 800 nm, preferably 200 nm to 400 nm.

[0024] As shown in FIG. 2, the first insulating layer 14 includes a first insulating portion 14a disposed between the upper surface 13d of the intermediate layer 13 and the second conductive layer 15, a second insulating portion 14b continuously extending from the first insulating portion 14a to cover the side surface 13e of the intermediate layer 13 and the side surface 12b of the first conductive layer 12, and a third insulating portion 14c continuously extending from the second insulating portion 14b to cover at least a part of the first surface 11a of the substrate 11. When the silicon nitride (SiN) of the first insulating layer 14 contains carbon (C), the adhesion between the third insulating portion 14c of the first insulating layer 14 and the substrate 11 can also be improved.

[0025] In the embodiments of the present disclosure, as the film formation processes of the above-described conductive layer and insulating layer, chemical vapor deposition (CVD) (for example, plasma CVD, atomic layer deposition (ALD)), physical vapor deposition (PVD) (for example, sputtering or evaporation), or electroplating can be used. Also, photolithography can be used to form patterns of the conductive layer and insulating layer. Further, as the planarization processes of the conductive layer and insulating layer, etch-back, chemical mechanical polishing (CMP), etc. can be used.

[0026] FIG. 3 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 may be composed of a first layer 13-1 of nickel (Ni) on the first conductive layer 12 and a second layer 13-2 of gold (Au) disposed on the first layer 13-1. In the present embodiment, the thickness of the first layer 13-1 of nickel (Ni) is preferably 1 μm to 5.0 μm, and the thickness of the second layer 13-2 of gold (Au) is preferably 0.05 μm to 0.5 μm. The intermediate layer 13 in this example also has the feature of high adhesion to the first insulating layer 14. Note that, when comparing the example of FIG. 2 and the example of FIG. 3, it is preferable to use titanium (Ti) as the intermediate layer 13 because the adhesion is higher.

[0027] FIG. 4 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 has a first portion 13a disposed between the upper surface 12a of the first conductive layer 12 and the first insulating portion 14a of the first insulating layer 14, a second portion 13b continuously extending from the first portion 13a and covering the side surface 12b of the first conductive layer 12, and a third portion 13c continuously extending from the second portion 13b and covering at least a part of the first surface 11a of the substrate 11. In this example, the second insulating portion 14b of the first insulating layer 14 is disposed so as to cover at least a part of the second portion 13b of the intermediate layer 13, and the third insulating portion 14c of the first insulating layer 14 is disposed so as to cover at least a part of the third portion 13c of the intermediate layer 13. According to this configuration, since the intermediate layer 13 extends to the first surface 11a of the substrate 11, the adhesion between the first insulating layer 14 and the first surface 11a of the substrate 11 is improved.

[0028] FIG. 5 shows another example of the configuration of the intermediate layer 13 and the first insulating layer 14. The third insulating portion 14c of the first insulating layer 14 may be disposed so as to cover the end portion of the third portion 13c of the intermediate layer 13 and at least a part of the first surface 11a of the substrate 11.

[0029] Next, samples 1 to 5 of a plurality of silicon nitride (SiN) layers were prepared, and the relative permittivity and adhesion were evaluated. The layers of each of samples 1 to 5 were formed on a Si wafer, and the layer thickness was 500 nm. Samples 1 to 3 are samples that do not contain carbon (C), and samples 4 to 5 are samples that contain carbon (C).

[0030] Figure 6 shows the quantitative values of Samples 1 to 5 obtained by performing XPS (X-ray Photoelectron Spectroscopy) measurement on Samples 1 to 5 using ESCA-3400 (manufactured by Shimadzu Corporation). The measurement conditions are as follows. [XPS Measurement] Incident X-ray: Mg Kα (non-monochromatized X-ray) Measurement area: 6 mm φ X-ray output: 120 W [Depth Direction Analysis] Ion gun: Ar Acceleration voltage: 0.3 kV Emission: 30 mA Etching time: 30 s / Cycle (up to 1 - 20 Cycles), 100 s / Cycle (up to 21 - 45 Cycles)

[0031] Regarding Samples 1 to 5 in Figure 6, the relative permittivity and the adhesion to the intermediate layer 13 were investigated. Samples 4 and 5 containing carbon (C) had a lower relative permittivity compared to Samples 1 to 3. Also, Samples 4 and 5 had a higher adhesion to the intermediate layer 13 compared to Samples 1 to 3. Thus, when Samples 4 and 5 are used as the first insulating layer 14, the relative permittivity becomes lower, making it easier to control the capacitance of the capacitor. Also, it was found that when the amount of carbon (C) in the dielectric first insulating layer 14 increases, the adhesion to titanium in the intermediate layer 13 becomes higher.

[0032] Note that Samples 4 and 5, which are silicon nitride (SiN) containing carbon (C), can be manufactured by the following method. For example, when manufacturing Sample 4, raw material gas tetramethylsilane 30 sccm and nitrogen gas 100 sccm are introduced into the vacuum processing chamber in advance, and the film formation pressure is set to 1 Pa. A heater is installed on the support, and the substrate temperature is controlled at 200°C. High-frequency radio waves of 3 kW are applied from the top plate of the vacuum processing chamber through the matching box to generate plasma. When this plasma is generated, a silicon nitride (SiN) film containing carbon (C) is formed on the film-forming object placed on the support in the vacuum processing chamber from the gas phase through a chemical reaction. For example, for Sample 5, using the same film formation method, the introduction amount of tetramethylsilane was set to 60 sccm, and film formation was carried out under the same conditions as Sample 4 for other conditions.

[0033] The above-described interposer and through electrode substrate can be applied to devices selected from the group of mobile phones, smartphones, wireless local area network (LAN) devices, set-top boxes, music players, video players, entertainment units, navigation devices, communication devices, personal digital assistants (PDAs), fixed position data units, and computers.

[0034] Note that the present disclosure is not limited to the above-described embodiments and includes various other modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present disclosure, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, it is possible to add, delete, or replace other configurations.

Explanation of Reference Numerals

[0035] 10 … Interposer 11 … Substrate 11a … First surface 11b … Second surface 12 … First conductive layer 13... Intermediate layer 14... First insulating layer 15... Second conductive layer 16... Through-hole 17... Through electrode 18... Connection hole 19... Conductive member 20... Third conductive layer 21... Resin layer 22... Fourth conductive layer 23... Fifth conductive layer 24... Solder ball 40... Wiring board 50... Semiconductor chip

Claims

1. a substrate having a first surface and a second surface on the side opposite to the first surface; a through electrode that electrically connects the first surface and the second surface; a first conductive layer disposed on the first surface of the substrate and electrically connected to the through electrode; a first insulating layer disposed on the first conductive layer; an intermediate layer disposed between the first conductive layer and the first insulating layer, comprising: The first insulating layer has a first insulating portion disposed on the intermediate layer, a second insulating portion extending from the first insulating portion to cover at least a part of the side surface of the intermediate layer and the side surface of the first conductive layer, and a third insulating portion extending from the second insulating portion to cover at least a part of the first surface of the substrate. A through electrode substrate.

2. The intermediate layer has a first portion disposed between the first insulating layer and the first conductive layer, a second portion extending from the first portion to cover at least a part of the side surface of the first conductive layer, and a third portion extending from the second portion to cover at least a part of the first surface of the substrate. The second insulating portion extends from the first insulating portion to cover at least a part of the second portion of the intermediate layer. The third insulating portion extends from the second insulating portion to cover at least a part of the third portion of the intermediate layer. The through electrode substrate according to claim 1.

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