Circuit and method for transmitting a signal in an integrated circuit device

Abstract

A circuit for transmitting a signal in an integrated circuit device is described, the circuit comprising a first die (501), a second die (502) stacked on the first die (501), and a buffer (513) for transmitting data between the first die (501) and the second die (502), wherein a first inverter (512) of the buffer (513) is on the first die (501) and a second inverter (514) of the buffer (513) is on the second die (502). A method for transmitting a signal in an integrated circuit device is also described.

Description

Technical Field

[0001] Technical Field The present invention generally relates to integrated circuit devices, and more particularly, to circuits and methods for transmitting signals in integrated circuit devices.

Background Art

[0002] Background The implementation of integrated circuit devices continues to change while addressing miniaturization, power reduction, and performance improvement of integrated circuit devices. As with any product, efforts are always being made to increase the yield of integrated circuit devices during the manufacturing process. Recently, integrated circuit devices having multiple dies have been developed. Here, the multiple dies can be placed on an interposer that enables signal communication between these multiple dies. Other embodiments of integrated circuit devices include multiple stacked dies, and the circuits on the stacked dies may transmit signals via wiring elements between the dies, for example, through through-silicon vias (TSVs).

[0003] However, during the manufacture of stacked integrated circuit devices, defects may occur in the connection between the dies or between the dies. This can reduce the yield and potentially affect the performance.

[0004] Therefore, there is a need for circuits and methods for transmitting signals in integrated circuit devices having multiple dies that reduce problems associated with conventional devices.

Summary of the Invention

Means for Solving the Problems

[0005] Summary A circuit for transmitting signals in an integrated circuit device will be described. The circuit may include a first die, a second die stacked on the first die, and a buffer for transmitting data between the first die and the second die. The first inverter of the buffer is on the first die, and the second inverter of the buffer is on the second die.

[0006] In some embodiments, the first inverter may be configured to receive a reference voltage, and the second inverter may be configured to receive a gated reference voltage based on the reference voltage.

[0007] In some embodiments, the second die may further include a third inverter, and the third inverter is configured to receive the output of the first inverter and the reference voltage.

[0008] In some embodiments, the second die may further include a third die stacked on the second die, and the third inverter is configured to transmit data from the first die to the third die.

[0009] In some embodiments, the second die may include a wiring element configured to receive a second gated reference voltage.

[0010] In some embodiments, the wiring element may include a selection circuit having a selection input configured to receive a control signal from a memory element configured to receive a second gated reference voltage.

[0011] In some embodiments, the first inverter may include a tri-state inverter and be configured to receive a tri-state signal, and the second inverter may be configured to receive a gated reference voltage.

[0012] In some embodiments, the first inverter and the second inverter may be coupled to a columnar connection extending between the first die and the second die.

[0013] In some embodiments, the circuit may further include a power gating circuit coupled to the second inverter of the buffer, and the power gating circuit is configured to apply a gated reference voltage to the second inverter.

[0014] In some embodiments, the first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die.

[0015] Also, a method for transmitting a signal in an integrated circuit device will be described. This method may include providing a first die, stacking a second die on the first die, and transmitting data between the first die and the second die via a buffer, where the first inverter of the buffer is on the first die and the second inverter of the buffer is on the second die.

[0016] In some embodiments, the method may further include configuring the first inverter to receive a reference voltage and configuring the second inverter to receive a gated reference voltage based on the reference voltage.

[0017] In some embodiments, the method may further include implementing a third inverter on the second die, where the third inverter is configured to receive a reference voltage.

[0018] In some embodiments, the method may further include stacking a third die on the second die, where the third inverter is configured to transmit data from the first die to the third die.

[0019] In some embodiments, the method may further include configuring the wiring elements of the second die to receive a second gated reference voltage.

[0020] In some embodiments, configuring the wiring elements may include configuring a selection circuit having a selection input coupled to receive a control signal from a memory element configured to receive a second gated reference voltage.

[0021] In some embodiments, the first inverter may comprise a tri-state inverter and may be configured to receive a tri-state signal.

[0022] In some embodiments, the method may further include coupling the first inverter and the second inverter to a columnar connection extending between the first die and the second die.

[0023] In some embodiments, the method may further include coupling a power gating circuit to the second inverter of the buffer, the power gating circuit being configured to apply a gated reference signal to the second inverter.

[0024] In some embodiments, the first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0026] Detailed Description Implementing a plurality of integrated circuit dies in an integrated circuit package can lead to higher integration and improved performance. However, there may be defects or unusable parts in some of the dies of the packaged integrated circuit device. Stacking dies, such as in AOA (Active-On-Active) devices, brings the circuits of the integrated circuit (IC) package closer together, leading to improved performance. After stacking wafers (known as wafer-to-wafer bonding), the stacked wafers can be diced to form individual stacked dies that are implemented in the integrated circuit package, thereby forming the stacked dies used in the integrated circuit package. However, since the wafers are stacked during the manufacturing process before dicing the stacked wafers, it is not possible to stack "known-good-dies" in the stacked die architecture. That is, there may be defects in the bonding between the dies included in the die stack or defects in the dies themselves. This can only be identified after dicing the stacked wafers. As a result, having tolerance and redundancy against defects is an advantage. The circuit and method for transmitting data in an integrated circuit device described below are advantageous for implementing a redundancy scheme in a stacked die architecture.

[0027] The circuits and methods described below enable power gating necessary to switch off the current flowing through a die or a part of a die with a defect included in a multi-die integrated circuit device, such as a stacked FPGA (Field Programmable Gate Array) subsystem formed using inter-wafer bonding. According to some embodiments, this circuit and method provide a 3D stacked die that performs double power gating, such as supplying a high voltage (e.g., VGG) to a memory device and a low voltage (e.g., VCCINT) to a circuit such as a logic circuit that does not require a high voltage. Power gating suppresses the static leakage of unused dies. However, in some embodiments, since a power-gated region and a non-power-gated region can coexist on the same die, there may be a spurious current path between the non-gated region and the gated region. These spurious current paths can be blocked by using insulating cells between the non-gated region and the gated region. Insulation is provided by a circuit and method that divides the inverter of the buffer. Here, there is a first inverter on the non-gated power supply region of the circuit, and a second inverter on the gated power supply that shares the power supply with the gated region.

[0028] According to some embodiments, the driver's inverter may be split between two dies. Here, a gated reference voltage may be supplied to one of the inverters, such as the second inverter of the buffer. Thus, the power-gated inverter acts as an isolation cell between the gated power supply and the ungated power supply, insulating the driver in the active die from the source / drain load of the defective die. This circuit arrangement has no area issues and improves the implementation of die-to-die connections. That is, in a conventional device, two inverters of the buffer needed to be on the same die, so the inverter of the buffer was split between two dies, and the second inverter of the die in the conventional buffer arrangement that would have occupied the area of the inverter was moved to the next die. Therefore, since the inverter used is completely moved to another die, there are no area issues.

[0029] This specification includes claims that set forth the features of one or more embodiments of the invention as new. However, this circuit and method will be better understood by considering the description together with the accompanying drawings. Although various circuits and methods are disclosed, it should be understood that these are merely examples of the arrangement of the invention and can be embodied in various forms. Therefore, the specific structural and functional details disclosed herein should not be construed as limitations, but rather as a basis for the claims and as a representative basis for teaching those skilled in the art to employ these inventive arrangements in all substantially suitable structures in various ways. Furthermore, the terms and phrases used herein are not intended to be limiting, but rather are intended to provide an understandable description of the circuits and methods.

[0030] First, referring to FIG. 1, a block diagram of an exemplary stacked integrated circuit device 100 is shown. More specifically, a substrate 102 (here shown as a package substrate as an example) is configured to accommodate a plurality of dies electrically connected by wiring elements, which will be described in more detail in FIG. 2. Alternatively, the substrate can comprise an interposer disposed on the package substrate, or other elements used to accommodate the dies of the integrated circuit device. As shown in FIG. 1, the first die stack comprises a first substrate 106 having a corresponding wiring layer 108 with wiring elements that enable signals to be sent to the package substrate. For example, these wiring elements may comprise solder bumps, hybrid wiring technology, or other conductor elements for transmitting and receiving signals to and from the die. The second substrate 110 has a corresponding wiring layer 112 with wiring elements that enable signals to be sent. The third substrate 114 has a corresponding wiring layer 116 with wiring elements that also enable signals to be sent. A package lid 118 may be included to cover the substrate 114 or encapsulate these plurality of dies. The pairs of substrates and wiring layers shown in the figure (106 and 108, 110 and 112, and 114 and 116) form three dies, which will be described in more detail in FIG. 2 and are configured to send signals between the dies. It should be understood that the arrangement in FIG. 1 is an arrangement for showing, as an example, a general arrangement of stacked dies. The specific arrangement of the dies may have different configurations such as face-to-face configured dies (also known as active-on-active configured dies) and face-to-back configured dies, where face means the BEOL (Back End-Of-Line) on the metal layer side and back means the substrate. Depending on the die configuration, the wiring elements may include the TSV metal layer or the BEOL metal layer of the die. In the case of face-to-back bonding, the wiring between the dies is implemented within the substrate (i.e., where the TSVs are). According to an example, the wiring layer 112 may comprise a metal layer (i.e., on the face) of the substrate 110 (i.e., the back), where the wiring layer 112 and the die 110 are combined to form one die layer.Depending on the die orientation, the wiring from one die to another or between the substrate package and the die may include metal layers or TSVs. Note that via-first TSVs fabricated before elements such as transistors, capacitors, or resistors are generated during the FEOL (front end of line) process; via-middle TSVs fabricated after transistor elements, capacitor elements, or resistor elements are patterned and before metal layers are formed in the BEOL (back-end-of-line) process; and via-last TSVs fabricated during or after the BEOL (back-end-of-line) process. Stacked IC devices may include different types of TSVs. Currently, via-middle TSVs are common for advanced 3D-IC and interposer stacking.

[0031] The integrated circuit device may include additional die sets including the second die set 120. The second die set 120 may be implemented similarly to the die set 104, and the substrate 102 enables signal transmission between the first die set and the second die set. Although an exemplary stacked integrated circuit device 100 is illustrated as an example, it should be understood that other die arrangements can be introduced, including dies arranged adjacent to each other on the horizontal plane of the package substrate. Further, examples of circuits and methods related to the stacked dies of the integrated circuit device will be described, but it should be understood that the circuits and methods can be implemented with dies adjacent to each other on the horizontal plane of the package substrate, and the dies included in the first die set 104 may communicate with the dies included in the second die set 120. According to one embodiment, the inverters of the buffer that enable signal transfer between the dies are divided between these dies, the first inverter of the buffer is on the first side of the boundary between the first die and the second die, and the second inverter of the buffer is on the second side of the boundary between the first die and the second die. This boundary can be, for example, the top and bottom surfaces of two stacked dies. Alternatively, in the case of non-stacked dies (e.g., dies on the horizontal plane of the substrate or on the interposer, or dies included in different die sets on the horizontal plane that are stacked), the boundary can include, for example, one of the top or bottom of one of these dies. For example, a circuit and method for dividing the inverter of the buffer between two dies can include one inverter of the buffer in a die included in one die stack and the other inverter of the buffer in a die included in another die stack. Here, the boundary includes at least one of the top or bottom of one of these dies.

[0032] Referring now to FIG. 2, a partial cross-sectional view of an exemplary stacked integrated circuit device 200 (which may be a cross-section of the integrated circuit device of FIG. 1 and has five dies) is shown. The stacked integrated circuit device 200 includes a plurality of dies. In this specification, these plurality of dies are shown as die 1 to die 5 as an example. Each of the dies may comprise the same type of elements, such as active elements, metal wirings, and vias, all formed of silicon. These elements are denoted by the same reference numerals in each die. For example, each die may include a substrate 202 having an active element 204. In this specification, the substrate 202 is shown as a transistor having a source 206 and a drain 208 in a well region 209 and a gate region 210, as an example.

[0033] The active elements of the die substrates are connected to each other and are also connected to the elements of another die via wiring elements. This wiring element may include metal wirings of a plurality of metal layers separated by non-conductive layers and vias that connect some of the plurality of metal layers through these non-conductive layers. More specifically, as shown in the figure, the wiring elements 212 are coupled to each other by vias 214. The vias 216 passing through the substrate are often referred to as through-silicon vias (TSVs), extend from a contact element 218 on the back side of the substrate, and may be coupled to a contact element 220. This enables connection to a contact pad 222 that provides an external connection through an insulating layer 224. Also, other contact elements for electrically connecting the dies may be mounted. For example, the first contact element 226 of the first die may be electrically coupled to the second contact element 228 of the second die. Here, the contact elements 226 and 228 may be part of a hybrid contact element 230. The example of FIG. 2 is provided to show an example of a device capable of implementing the circuits of FIGS. 3 and 4, which will be described in more detail later.

[0034] The circuit of FIG. 2 is shown as an example and may include any number of dies that can be implemented in any orientation. A face-to-face arrangement of the dies is shown between die 1 and die 2, and a face-to-backside arrangement is shown for the other dies, but it should be understood that the dies may be implemented in other orientations. Some or all of the dies may be of the same type of device, such as a programmable logic device (PLD), and may have specific functions such as memory or logic in different dies.

[0035] Referring now to FIG. 3, a block diagram of a portion 300 of an integrated circuit having an area that receives a power-gated reference voltage is shown. The circuits and methods for transmitting signals can be implemented in any type of integrated circuit device. However, the circuits and methods have advantages in integrated circuit devices having repetitive circuit elements dedicated to a specific function, such as the PLD illustrated and described as an example in FIGS. 10 and 11 below.

[0036] According to the example of FIG. 3, the circuit may be divided into four regions including a first circuit region 302 having a corresponding power-gating circuit 303, a second circuit region 304 having a corresponding power-gating region 305, a third power-gating region 306 having a corresponding power-gating circuit 307, and a fourth circuit region 308 having a corresponding power-gating circuit 309. For each circuit region, a first reference voltage (first Vref) is coupled to a first input 310 and an input 312 of the corresponding power-gating circuit, and its gated output is coupled to a second input 314 of the circuit region. As will be described in more detail later, a gated reference voltage corresponding to the first reference voltage is coupled to the circuit region in response to corresponding control signals (shown as control 1 to control 4 in FIG. 3). A second reference voltage (second Vref) is coupled to input 316.

[0037] The second reference voltage is not coupled to the corresponding power gating circuit, but a second power gating circuit can be implemented between the second reference voltage and the input 316. According to one embodiment, the first reference voltage can be a low voltage (e.g., VCCINT), and the second reference voltage can be a high voltage (e.g., VGG). Although four regions are shown as an example, it should be understood that any number of regions can be implemented and any number of gated reference voltages and ungated reference voltages can be used. Further, one reference voltage can be implemented, or three or more reference voltages can be implemented.

[0038] Here, referring to FIG. 4, a block diagram of a portion 400 of the layout of an integrated circuit having a circuit block that receives a power-gated reference voltage is shown. The circuit layout of FIG. 4 includes a configurable logic element (CLE) 402 having a corresponding power gating circuit 403, a wiring element block 404 having a corresponding power gating circuit 405, and a CRAM (Configuration Random Access Memory) 406 having a corresponding power gating circuit 407. The details of the CLE, the wiring element block, and the CRAM will be described in more detail with reference to FIGS. 10 and 11.

[0039] According to the embodiment of FIG. 4, some of the CLE402 are configured to receive a first reference voltage (e.g., VCCINT) at input 410, while other CLEs may be configured to receive a gated first reference voltage at input 410. More specifically, in the case of the gated first reference voltage, the first reference voltage is coupled to input 412 of power gating circuit 403. Also, power gating circuit 403 is coupled to receive a CLE gating control signal (e.g., CC1... CCn) at control input 414. The CLE402 receive only one reference voltage (gated voltage or ungated voltage), but it should be understood that each CLE can be configured to receive a gated voltage and an ungated voltage, and can be configured to receive two or more gated voltages and ungated voltages.

[0040] Also, the circuit arrangement of FIG. 4 includes a plurality of wiring element blocks 404. Each wiring element block 404 is illustrated as receiving, as an example, a first reference voltage and a gated first reference voltage. More specifically, the first reference voltage is provided to input 420 of the wiring block 404. Also, for each wiring element block 404, a corresponding power gating circuit is configured to generate a gated reference voltage coupled to input 424 of the wiring element block 404 in response to a corresponding control wiring signal (CI1~CIn) coupled to control input 426 and receiving a reference voltage at input 422.

[0041] Also, the circuit arrangement of FIG. 4 includes a plurality of CRAM blocks 406. Each CRAM block 406 is shown to receive, as an example, a second reference voltage (VGG) and a gated second reference voltage (gated VGG). More specifically, for each CRAM block 406, a corresponding power gating circuit 407 receives the second reference voltage (e.g., VGG) at input 432 and is configured to generate a gated second reference voltage coupled to input 430 of CRAM 406 in response to corresponding CRAM control signals (CC1~CCn) at control input 434. The circuit arrangement of FIG. 4 includes three types of circuit blocks having different power gating arrangements, but the arrangement of FIG. 4 is provided as an example, and it should be understood that different types of circuit blocks having different power gating configurations can be implemented.

[0042] In integrated circuit devices such as programmable logic devices that perform dual voltage supply (e.g., a higher voltage (VGG) may be supplied to the memory cells and a nominal voltage (VCCINT) may be supplied to the core), there is an advantage in power gating VCCINT. Also, in some circuits (e.g., CRAM (Configuration Random Access Memory) cells that receive a higher voltage), leakage that can be up to 15% of the total power of the IC device can occur in 7nm technology, so there is also an advantage in power gating the higher voltage VGG. Therefore, as will be described in more detail later, gating both voltages on a defective die will be beneficial not only to save static power but also to improve the yield.

[0043] Although there are merits in cutting off (gating) the power supply, there are also circuits that need to be on the non-gated power supply to supply always-on blocks. For example, in 3D-ICs such as the integrated circuit devices in FIGS. 1 and 2, when the power supply of one die among the defective dies is power-gated, there is still a need to propagate active signals between the defective power-gated dies. As a result, a power-gated load is applied to the defective die (the signals between the dies generally being referred to as Z signals (i.e., extending in the Z direction between the stacked dies)). Transmission of signals to the defective die may create spurious leakage paths from the non-gated power supply to the gated power supply, and spurious leakage on the path that can significantly affect performance may result in an indefinite hanging capacitance in the power-gated die. Therefore, until now, expensive and undesirable isolation circuits have been required in FPGA wiring blocks, which have limited area in conventional devices. The arrangement of the isolation circuits in FIGS. 5 and 6 overcomes the defects of the conventional isolation circuits by splitting the buffer inverter between two dies, thereby eliminating the need for additional circuits.

[0044] The active Z signal (i.e., the vertical signal between two stacked dies) can be coupled to different types of loads, including loads on adjacent dies and loads between multiple dies. The circuits and methods described in FIGS. 5 and 6 overcome the problems of conventional devices by splitting two inverters of a buffer (i.e., a driver) of a wiring element of a die into two conversion stages. Here, the first inverter is on the first die including a signal driving part, and the second inverter is on the second die which is a load die. The first inverter may be implemented using a non-power-gated power supply to enable signal transfer between multiple dies, and the second inverter may receive a power-gated power supply. The second inverter receiving the power-gated power supply functions as an isolation cell. Different from the conventional isolation cells that require (not required if not necessary) circuits, the circuit and method for splitting the driver provide a finite load capacitance and improve the performance of connections shared between dies, such as the Z connection shared between dies.

[0045] That is, the circuit and method provide an inverter connected to a power-gated power supply. This can be implemented without the need to add a circuit footprint by the splitting technique and can improve the performance compared to the solution without power gating. Also, the circuit and method enable full power gating of the VGG which helps to further save power and improve the product yield, but can improve the performance of the wiring on the 3D-IC by utilizing the strategy of splitting the inverter between dies regardless of power gating.

[0046] Referring now to FIG. 5, a partial block diagram of a circuit 500 for transmitting signals between stacked dies of an integrated circuit device is shown. The circuit of FIG. 5 includes a plurality of elements that are part of two dies, more specifically, a plurality of elements including buffers associated with drivers on a first die 501 and a second die 502. The circuit 500 may include a first selection circuit 503, illustrated as an example, as a multiplexer adapted to receive input signals (Input_1 and Input_2) at a first input 504 and a second input 506. A select value (of the Input_1 and Input_2 signals) can be generated at an output 510 by a control signal provided at the input and generated in response to a memory element 509. Note that the memory element 509 may be part of a CRAM and can receive the reference voltage (e.g., VGG) described above with reference to FIG. 4. Note that the selection circuit 503 is configured to receive a selection signal for selecting an input of the selection circuit at an input 508, and the selection circuit 530 is configured to receive a selection signal at an input 537 via a memory element that receives the VGG reference voltage, it being understood that the memory element can receive different reference voltages that are not gated. That is, the selection circuits 503 and 530 are controlled by a selection input signal that is always on to enable signal transfer between dies, such as between die 1 and die 3, even if there is a defect in die 2 or a part of die 2. The control signal is provided to the control input of the selection circuit via the memory element, it being understood that the control signal can be provided by other circuit elements that enable the selection circuits 503 and 530 to always be on.

[0047] The output signal generated at the output 510 is coupled to the first inverter 512 of the buffer 513, and the output of the first inverter 512 is coupled to the second inverter 514 via the wiring element 516. The first inverter 512 and the second inverter 514 are part of a buffer divided between the first die and the second die. The wiring element 516 can be any kind of contact element that enables signal transfer between the first inverter on the first die and the second inverter on the second die. As an example, the wiring element 516 can include elements of both dies, such as contact pads, TSVs, metal wiring, or elements included in hybrid bonding elements.

[0048] The second inverter 514 may be coupled to the selection circuit 518 at the first input 520 among a plurality of inputs. The output signal of the selection circuit 518 is generated at the output 522 in response to the input at the selection input 523. According to some embodiments, the selection input 523 receives the outputs of the memory cells 524 and 526. The memory cells 524 and 526 may be part of a CRAM that receives a gated reference voltage, such as a gated VGG voltage. By gating the second inverter 514, it is possible to reduce leakage current / spurious current from the ungated circuit region to the gated circuit region. There are a plurality of leakage paths in the circuit of the integrated circuit device. For example, there may be a leakage path in the drive path of die 2, such as the transistors of the selection circuit 518 coupled to the input 520. More specifically, there may be a leakage current in the transmission gate including the P-channel transistor coupled to the input 520. Here, the current may leak from the source of the P-channel transistor to the bulk of the transistor. There may be a leak in the path including the P-channel transistor between the input 520 and the input 521. By providing insulation between the wiring element 516 that transmits a signal to the inverter 514 using a gated reference voltage for the inverter 514, current leakage in die 2, such as current leakage in the selection circuit 518, can be suppressed. Note that current leakage generally exists between the ungated region and the gated region. In addition to current leakage, by actively turning on the path, a current path is generated from the ungated region to the gated region. Here, these current paths are turned off by insulation using a gated power supply.

[0049] To enable the transfer of signals from the inverter 512 to other parts of the integrated circuit device, including other parts of die 2 or die 3 of the stacked die arrangement of the integrated circuit device, via the wiring element 516, additional elements are provided in die 2. For example, an inverter 528 that receives a reference voltage (e.g., VCCINT) but not a gated reference voltage (e.g., gated VCCINT) is provided to ensure that the signal applied to die 2 via the wiring element 516 is always applied to other parts of die 2 or die 3. The inverter 528 receives the signal generated in the wiring element 516 and applies the signal to other circuit elements for sending this signal. For example, these other circuit elements include a multiplexer 530 having inputs 532 and 534 configured to receive the signal. The signal can be selected as the signal applied to the output 536 in response to receiving, at the selection input 537, a signal that can be received from a storage element that is a CRAM memory cell 538 receiving a reference signal. The output 536 is coupled to an inverter 540. The inverter 540 receives a reference voltage Vref and provides an output to other parts of the integrated circuit device, such as other parts of die 2 or die 3 (541), via a wiring element 542 that enables the transfer of the signal to die 3. By providing other elements and the inverter 528 that enable the transfer of signals from the wiring element 516 to other parts of the integrated circuit, signals from die 1 can be transferred to other parts of the integrated circuit device. Thereby, the inverter 514 can be controlled by the gated reference voltage to avoid defective parts of the integrated circuit and prevent current leakage in devices such as the selection circuit 518 that would not be used.

[0050] A circuit and method provide the benefit that there is a short circuit, such as a VCCINT-GND short circuit, on the die. Without power gating, the die would have to be discarded. However, with power gating, the short circuit becomes a substantial Vccint-Gnd short circuit, and it is then used to avoid the VCCINT-GND short circuit. VCCINT is the overall power supply and can be common to all the dies in the stack, and the substantial VCCINT is a power supply local to a particular die. The short circuit on this local power supply can be isolated from the overall external power supply. By avoiding the use of defective dies, the yield is improved. For example, if there is a stack of three dies and a VCCINT-GND short circuit on one die, a device with multiple dies would have to be discarded if power gating were not performed at the defective location on the die. With power gating, a stack composed of two dies would still function.

[0051] Referring now to FIG. 6, another block diagram of a portion of a circuit 600 for transmitting signals between stacked dies of an integrated circuit device is shown. The circuit of FIG. 6 is similar to the circuit of FIG. 5, except that a columnar connection 603 extends between die 601 and die 602, and a tri-state inverter is adapted to provide a tri-state signal to the columnar connection and receive a tri-state signal from the columnar connection. As shown in FIG. 6, inverter 604 of buffer 605 is configured to receive an input signal and is controlled by a tri-state signal such that the output of the tri-state inverter floats when the tri-state inverter does not send a signal to the columnar connection. The output of tri-state inverter 604 is coupled to columnar connection 603. The output is also coupled to inverter 606 to receive a signal from columnar connection 603. Inverter 606 is controlled by a gated reference voltage and, together with inverter 604, forms a buffer divided between die 1 and die 2. The output of inverter 606 is coupled to selection circuit 608 at input 610. The selected input of selection circuit 608 is generated at output 612 in response to a signal received at control signal input 613. According to some embodiments, the signal applied to the control signal input may be a signal from memory elements 614 and 616. Memory elements 614 and 616 may be CRAM cells that receive a gated voltage, such as a gated VGG. Other tri-state inverters, such as tri-state inverter 618, may be coupled to columnar connection 603 to allow data to be transferred from inverter 604 to other parts of the die or to die 3. In the case of columnar connections, a split inverter with a fixed inverter load can be used to better control the delay and reduce the delay compared to a solution without splitting.

[0052] Referring now to FIG. 7, there is shown a block diagram of an exemplary gating circuit 700 that may be implemented in the circuits of FIGS. 5 and 6. A gated reference voltage may be generated using a series of transistors coupled between a reference voltage Vref and ground. The P-channel transistor 702 has a source configured to receive the reference voltage and a drain coupled to the drain of the N-channel transistor 704. The first control signal (Control_1) is coupled to the gate 706 of the transistor 702, and the second control signal (Control_2) is coupled to the gate 708 of the transistor 704. The gated reference voltage (gated Vref) may be generated at the node between the drain of the transistor 702 and the drain of the transistor 704 in response to these control signals. A specific example of the gated VGG signal will be described with reference to FIG. 8.

[0053] Referring now to FIG. 8, the timing diagram shows the operation for generating the gated VGG signal of the gating circuit of FIG. 7. In the case of a die without defects, the Control_1 signal remains LOW, keeping the transistor 702 on. The Control_2 signal remains HIGH until VGG turns on, and then goes LOW to follow the gated VGG signal to VGG. In the case of a die with defects, the Control_2 signal remains HIGH, keeping the transistor 704 on and maintaining the gated VGG signal LOW. Control 1 follows the VGG signal.

[0054] In the case of a defective die, both Control_1 and Control_2 are fixed LOW. The Control_2 signal remains at VCCINT, and Control_1 increases linearly up to Vgg. During startup, a pull-down circuit is provided on the gated Vref signal (such as the gated VGG signal) to ensure startup in a known state. This can be achieved by the VCCINT-controlled N-channel transistor 704. During the startup sequence, transistor 704 initially remains on. Then, depending on whether there is a defect in the device or not, the gate switch (transistor 704) passing Vgg either remains off or turns on.

[0055] There is an advantage in fully gating VGG using the insulation as described in FIGS. 5 and 6. Because without these insulated inverters, the PMOS transistors included in the selection multiplexer turn on and a current path occurs, so VGG power gating cannot be performed. Further, better yield can be achieved if the short circuit between the gated VGG and ground can be recovered.

[0056] Here, referring to FIG. 9, the flowchart shows a method of transmitting a circuit in an integrated circuit device. In block 902, a first die, such as die 1 of FIGS. 5 and 6, is provided. In block 904, a second die, such as die 2 of FIGS. 5 and 6, is coupled to the first die. In block 906, a first inverter of the buffer is provided on the first side of the boundary between the first die and the second die described above. In block 908, a second inverter of the buffer is provided on the second side of the boundary between the first die and the second die. For example, the first inverter and the second inverter can be, for example, inverters 512 and 514 of FIG. 5 or inverters 604 and 606 of FIG. 6. In block 910, data is transmitted between the first die and the second die via the buffer. In block 912, power gating is provided for the inverter, such as the second inverter of the buffer.

[0057] According to some embodiments, the second inverter may be configured to receive a gated reference voltage based on a reference voltage, and the first inverter is configured to receive a reference voltage. A third inverter may be implemented on the second die, and the third inverter is configured to receive a reference voltage. According to some embodiments, the first inverter may include a tri-state inverter, and the use of a tri-state inverter configured to receive a tri-state signal may be advantageous, for example, when used with a column connection as shown in FIG. 6. A power gating circuit may be implemented according to various embodiments, and the power gating circuit may be coupled to the first inverter of the buffer, and the power gating circuit is configured to apply a gated reference signal to the first inverter. Further, the second die may include a wiring element configured to receive a second gated reference voltage. The wiring element may include a selection circuit having a selection input configured to receive a control signal from a memory element configured to receive the second gated reference voltage. The first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die.

[0058] The method of FIG. 9 may be implemented using the circuits of FIGS. 1-8 and 10-11 described above, or some other suitable circuit. Although specific elements of the method have been described, it should be understood that additional elements of the method, or further details regarding these elements, may be implemented in accordance with the disclosure of FIGS. 1-9.

[0059] Referring now to FIG. 10, a block diagram of a programmable logic device is shown. A device having programmable resources may be implemented in any type of integrated circuit device, such as an application specific integrated circuit (ASIC) having programmable resources, while other devices include a dedicated programmable logic device (PLD). One type of PLD is a CPLD (Complex Programmable Logic Device). A CPLD includes two or more "function blocks" connected to each other by a wiring switch matrix and connected to I / O (input / output) resources. Each function block of the CPLD includes a two-level AND / OR structure similar to the two-level AND / OR structure used in a PLA (Programmable Logic Array) or PAL (Programmable Array Logic) device. Another type of PLD is an FPGA (Field Programmable Gate Array). In a typical FPGA, an array composed of configurable logic blocks (CLBs) is coupled to programmable IOBs (Input / Output Blocks). The CLBs and IOBs are connected to each other in a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are typically customized by streaming a configuration bitstream from off-chip memory to the configuration memory cells of the FPGA. In both cases of these types of programmable logic devices, the function of the device is controlled by the configuration data bits of the configuration bitstream provided to the device for control (or the configuration data bits sent during partial reconfiguration). The configuration data bits may be stored in volatile memory (e.g., static memory cells such as those included in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory such as those included in some CPLDs), or other types of memory cells.

[0060] The device of FIG. 10 is composed of an FPGA architecture 1000 having a number of different programmable tiles including a multi-gigabit transceiver (MGT) 1001, a CLB 1002, a RAM block (BRAM) 1003, an I / O block (IOB) 1004, a configuration / clock logic (CONFIG / CLOCKS) 1005, a digital signal processing block (DSP) 1006, a dedicated I / O block (I / O) 1007 (e.g., a configuration port and a clock port), and other programmable logic 1008 such as a digital clock manager, an analog / digital converter, and system monitoring logic. Some FPGAs also include a dedicated processor block (PROC) 1010 that can be used, for example, to implement a software application.

[0061] In some FPGAs, each programmable tile includes a programmable wiring element (INT) 1011 having a standardized connection with corresponding wiring elements in each adjacent tile. Thus, when these programmable wiring elements are grouped together, the programmable wiring structure of the illustrated FPGA is implemented. Also, as shown by the embodiment included at the top of FIG. 10, the programmable wiring element 1011 also includes a connection with programmable logic elements within the same tile.

[0062] For example, CLB1002 may include a configurable logic element (CLE) 1012 that can be programmed to implement user logic and one programmable wiring element 1011. BRAM1003 may include a BRAM logic element (BRL) 1013 in addition to one or more programmable wiring elements. BRAM includes dedicated memory different from the distributed RAM of the configuration logic block. Usually, the number of wiring elements included in one tile varies depending on the height of that tile. In the illustrated embodiment, the BRAM tile is the same height as five CLBs, but other numbers may be used. DSP tile 1006 may include a DSP logic element (DSPL) 1014 in addition to an appropriate number of programmable wiring elements. IOB1004 may include, for example, two instances of an input / output logic element (IOL) 1015 in addition to one instance of a programmable wiring element 1011. The circuit and method can be implemented using IOL1015. The position of the device connection is controlled by the configuration data bits of the configuration bitstream provided to the device for control. Depending on the bits of the configuration bitstream, various signals can be coupled to the circuit implemented by programmable logic, or to a circuit implemented by other circuits or processors such as BRAM, using connections including wiring lines by programmable wiring.

[0063] In the illustrated embodiment, the columnar area near the center of the die is used for configuration, clock, and other control logic. The configuration / clock distribution area 1009 extending from this column is used to distribute clock and configuration signals from end to end of the FPGA. Some FPGAs utilizing the architecture shown in FIG. 10 include additional logic blocks, thereby disturbing the normal columnar structure that occupies most of the FPGA. The additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC1010 shown in FIG. 10 spans multiple columns of CLBs and BRAMs.

[0064] Note that FIG. 10 merely shows an exemplary FPGA architecture. The number of logic blocks included in one column, the relative widths of the columns, the number and order of the columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the implementation of the wiring / logic included at the top of FIG. 10 are merely illustrative. For example, in an actual FPGA, in order to facilitate an efficient implementation of user logic, there are usually two or more adjacent columns composed of CLBs where there are CLBs. The embodiment of FIG. 10 relates to an integrated circuit having programmable resources, but it should be understood that the circuits and methods described above can be implemented in any type of device having a combination of programmable resources and hardware blocks.

[0065] Referring now to FIG. 11, there is shown a block diagram of the configurable logic elements of the programmable logic device of FIG. 10. In particular, FIG. 11 shows a simplified configurable logic element, which is an example of the programmable logic of configuration logic block 1002 of FIG. 10. In the embodiment of FIG. 11, slice M1101 includes four look-up tables (LUTM) 1101A-1101D. Each look-up table is driven by six LUT data input terminals A1-A6, B1-B6, C1-C6, D1-D6 and provides two LUT output signals O5 and O6. The O6 output terminals from LUTs 1101A-1101D drive slice output terminals A-D, respectively. The LUT data input signals are supplied by the FPGA wiring structure via input multiplexers. The input multiplexers may be implemented by programmable wiring elements 1111, and the LUT output signals are also supplied to the wiring structure. Also, slice M includes output selection multiplexers 1111A-1111D that drive output terminals AMUX-DMUX, multiplexers 1112A-1112D that drive the data input terminals of storage elements 1102A-1102D, combinational multiplexers 1116, 1118, and 1119, bounce multiplexer circuits 1122-1123, and circuits represented by inverter 1105 and multiplexer 1106 (together, any inversion on the input clock path can be obtained), and carry logic having multiplexers 1114A-1114D, 1115A-1115D, 1120-1121 and exclusive OR gates 1113A-1113D. All of these elements are coupled as shown in FIG. 11. The selection inputs are not shown for the multiplexers shown in FIG. 11, but the selection inputs are controlled by configuration memory cells. That is, the configuration bits of the configuration bit stream stored in the configuration memory cells are coupled to the selection inputs of the multiplexers to select the correct inputs for the multiplexers. These well-known configuration memory cells are omitted in FIG. 11 for clarity and are also omitted in other figures selected in this specification.

[0066] In the illustrated embodiment, each of the memory elements 1102A to 1102D may be programmed to function as a synchronous or asynchronous flip-flop or latch. Whether to select the synchronous function or the asynchronous function is performed for all four memory elements included in the slice by programming the Sync / Asynch selection circuit 1103. When the memory element is programmed such that the S / R (set / reset) input signal provides a set function, the REV input terminal provides a reset function. When the memory element is programmed such that the S / R input signal provides a reset function, the REV input terminal provides a set function. The memory elements 1102A to 1102D are clock-controlled by a clock signal CK that may be provided, for example, by a global clock network or a wiring structure. Such programmable memory elements are well known in the field of FPGA design. Each of the memory elements 1102A to 1102D provides output signals AQ to DQ stored in a register to a wiring structure. Since each of the LUTs 1101A to 1101D provides two output signals O5 and O6, the LUT may be configured to function as two 5-input LUTs having five shared input signals (IN1 to IN5), or may be configured as one 6-input LUT having input signals IN1 to IN6.

[0067] In the embodiment of FIG. 11, each of the LUTs M1101A to M1101D may function in any of a plurality of modes. In the case of the look-up table mode, each LUT has six data input signals IN1 to IN6 supplied by the FPGA wiring structure via an input multiplexer. Based on the values of the signals IN1 to IN6, one of the 64 data values is programmably selected from the configuration memory cells. In the case of the RAM mode, each LUT functions as one 64-bit RAM or two 32-bit RAMs sharing the addressing. The RAM write data is supplied to the 64-bit RAM via the input terminal DI1 (through the multiplexers 1117A to 1117C of the LUTs 1101A to 1101C), or is supplied to the two 32-bit RAMs via the input terminals DI1 and DI2. The RAM write operation in the LUT RAM is controlled by the clock signal CK from the multiplexer 1106 and the write enable signal WEN from the multiplexer 1107. The multiplexer 1107 may selectively pass either the clock enable signal CE or the write enable signal WE. In the shift register mode, each LUT functions as two 16-bit shift registers, or forms one 32-bit shift register together with two 16-bit shift registers connected in series. The shift-in signal is provided through one or both of the input terminals DI1 and DI2. The 16-bit shift-out signal and the 32-bit shift-out signal may be provided through the LUT output terminals, and the 32-bit shift-out signal may be provided more directly through the LUT output terminal MC31. Also, the 32-bit shift-out signal MC31 of the LUT 1101A may be provided to the general wiring structure via the output selection multiplexer 1111D and the CLE output terminal DMUX in order to change the shift register. Therefore, the above-described circuit and method may be implemented in a device such as the devices of FIGS. 10 and 11, or other suitable devices.

[0068] Thus, it will be appreciated that a new circuit and method for transmitting signals in an integrated circuit device have been described. Those skilled in the art will come to understand that there will be numerous alternative forms and equivalents incorporating the disclosed invention. As a result, the present invention is not limited by the above embodiments, but only by the appended claims.

Claims

1. A circuit for transmitting a signal in an integrated circuit device, the circuit comprising: a first die; a second die stacked on the first die; and a buffer for transmitting data between the first die and the second die, wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die, the first inverter is configured to receive a reference voltage, and the second inverter is configured to receive the gated reference voltage as a power supply voltage and receive the output of the first inverter as an input, the first inverter is mounted in a non-gated region, and the second inverter is mounted in a gated region, the second inverter functions as an isolation cell to reduce current leakage between the non-gated region and the gated region, the second die further comprises a third inverter, and the third inverter is configured to receive the output of the first inverter and the reference voltage.

2. The gated reference voltage is based on the reference voltage, the circuit according to claim 1.

3. The circuit according to claim 1, further comprising a third die stacked on the second die, wherein the third inverter is configured to transmit the data from the first die to the third die.

4. The circuit according to claim 2, wherein the second die comprises a wiring element configured to receive a second gated reference voltage.

5. The circuit according to claim 4, wherein the wiring element comprises a selection circuit having a selection input configured to receive a control signal from a memory element configured to receive the second gated reference voltage.

6. The circuit according to claim 1, wherein the first inverter comprises a tri-state inverter configured to receive a tri-state signal, and the second inverter is configured to receive a gated reference voltage.

7. The circuit according to claim 6, wherein the first inverter and the second inverter are coupled to a columnar connection extending between the first die and the second die.

8. The circuit according to claim 1, further comprising a power gating circuit coupled to the second inverter of the buffer, wherein the power gating circuit is configured to apply a reference voltage gated to the second inverter.

9. The circuit according to claim 1, wherein the first inverter is associated with the input / output block of the first die, and the second inverter is associated with the input / output block of the second die.

10. A method for transmitting a signal in an integrated circuit device, comprising: providing a first die; stacking a second die on the first die; transmitting data between the first die and the second die via a buffer, wherein a first inverter of the buffer is on the first die, and a second inverter of the buffer is on the second die; the first inverter is configured to receive a reference voltage, and the second inverter is configured to receive the gated reference voltage as a power supply voltage and receive the output of the first inverter as an input; the first inverter is implemented in a non-gated region, and the second inverter is implemented in a gated region; the second inverter functions as an isolation cell to reduce current leakage between the non-gated region and the gated region; The method further includes implementing a third inverter on the second die, wherein the third inverter is configured to receive the output of the first inverter and the reference voltage.

11. The method according to claim 10, further comprising configuring the first inverter to receive the reference voltage and configuring the second inverter to receive the gated reference voltage based on the reference voltage.

12. The method according to claim 10, further comprising stacking a third die on the second die, wherein the third inverter is configured to transmit the data from the first die to the third die.

13. The method of claim 11, further comprising the step of configuring the wiring element of the second die to receive a second gated reference voltage, the step of configuring the wiring element including the step of configuring a selection circuit having a selection input coupled to receive a control signal from a memory element configured to receive the second gated reference voltage.

Images