Inspection Pattern and Pattern Evaluation Method

Abstract

This test pattern T is for testing the processing state of a mesa 202 used as a real element M. The real element M includes the mesa 202, which is formed by etching a substrate 200, and an electrode 201 formed on the mesa 202. The test pattern T includes a mesa 204 formed by etching the substrate 200, and a thin film 203 that is formed at least on an upper surface 204a of the test pattern T and is thinner than the electrode 201. The state of etching of the mesa 202 is evaluated on the basis of the difference between the shape of the test pattern T and the shape of the thin film 203. As a result of this configuration, the lateral etching amount during etching is evaluated quantitatively and accurately, even though the testing is non-destructive.

Description

Technical Field

[0001] The present invention relates to an inspection pattern and a method for evaluating the pattern.

Background Art

[0002] Compound semiconductor devices are used as light sources and photodetectors for various applications, including optical communication. Further, compound semiconductor optical devices are used as transistors that constitute integrated circuits that require high gain and high breakdown voltage, and the fabrication of such transistors is difficult to achieve with known silicon-based technologies. In many cases, dry etching or wet etching techniques are used in the fabrication of compound semiconductor devices. Regarding the etching of compound semiconductors, for example, it is described in Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3.

[0003] Non-Patent Document 1 discloses forming a semiconductor optical waveguide by dry etching when fabricating a semiconductor laser used in various light sources. Non-Patent Document 2 discloses that mesa processing by dry etching or wet etching is required for the fabrication of a photodiode used in a photodetector. Patent Document 3 discloses that when fabricating a heterojunction bipolar transistor, the collector and the base are processed to a desired size by etching, and an electrode is provided on top of them.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] The accuracy of etching processing in the above fields is extremely important for each device to obtain desired characteristics in any case. For example, in the optical waveguide of a semiconductor laser, variations in the width of the waveguide affect the beam characteristics to be propagated and can lead to excessive optical loss. Furthermore, in the case of a photodiode, it is known that the processing accuracy of the mesa affects the parasitic capacitance and dark current of the element, and in the case of a heterojunction bipolar transistor, the processing accuracy of the collector or the like affects the parasitic capacitance.

[0006] As one of the factors that reduce etching accuracy, a phenomenon is known in which etching also progresses laterally during the process of etching to a desired depth. Such etching is called lateral etching or side etching, and in this specification, it will be hereinafter referred to as lateral etching. The amount of lateral etching (lateral etching amount) is often managed for each etching process. As a method of managing the lateral etching amount, for example, prior to the fabrication of a semiconductor chip, it is conceivable to perform etching under the same conditions as the etching conditions for fabricating the semiconductor chip in advance and measure the lateral etching amount. Also, for example, it is conceivable to extract a semiconductor chip during mass production after the etching process and measure the lateral etching amount. Furthermore, the measurement of the lateral etching amount can be realized by exposing the cross-section of the semiconductor chip by FIB (Focused Ion Beam) processing and observing it with an electron microscope.

[0007] However, the lateral etching amount varies due to slight differences in conditions (such as temperature, etching gas or the flow rate of the etchant, etc.) that change for each etching, or due to subtle differences in the crystal composition ratio of the element. For this reason, the lateral etching amount during the previously performed etching does not necessarily match the lateral etching during mass production. Also, since cross-section observation is a destructive inspection, it is difficult to apply it to each wafer during mass production.

[0008] In addition to the above, the measurement of the lateral etching amount is also possible by observing from the upper surface of the wafer using an optical microscope or the like. However, in the case of an element that is mass-produced and can actually operate (hereinafter referred to as a "practical element"), electrodes and various passivation films are formed on its upper surface, and there may be a case where the state of a pattern below the electrode cannot be observed from above the electrode.

[0009] FIG. 1 is a diagram for explaining the problems of observation from the upper surface of a wafer, showing an actual pattern portion 102 formed by etching a substrate (wafer) 100 and an insulating film D formed on the actual pattern 102. Such an example is an example of a mesa-type transistor, and the actual pattern portion 102 corresponds to the mesa portion of the mesa-type transistor. The two-dot chain line A shown in FIG. 1 indicates an ideal mesa shape, and the actual actual pattern portion 102 is thinner than the ideal mesa shape due to lateral etching.

[0010] As shown in FIG. 1, when the lateral etching of the substrate 100 proceeds under the insulating film D, it is difficult to accurately measure the lateral etching amount of the actual pattern portion 102 by observation from the upper surface. Further, even if the lateral etching of the actual pattern portion 102 has not proceeded to the lower layer of the insulating film D, when the film thickness of the insulating film D is large, both an optical microscope and an electron microscope have difficulty in simultaneously focusing on both the edge of the insulating film D and the edge of the actual pattern portion 102, and it is difficult to quantify the lateral etching amount. That is, semiconductor etching is a very important process for determining the characteristics of semiconductor elements, and it is desirable that the amount of lateral etching accompanying etching be managed with high precision. However, according to the conventional technology, it has been difficult to evaluate and manage the amount of lateral etching in actual elements in each semiconductor process.

[0011] The present disclosure has been made in view of the above points, and relates to an inspection pattern and a pattern evaluation method that can quantitatively and accurately measure the amount of lateral etching during etching while being a non-destructive inspection.

Means for Solving the Problems

[0012] An inspection pattern according to an aspect of the present disclosure for achieving the above object is an inspection pattern for inspecting the processing state of a pattern used in an actual element, where the actual element includes an actual pattern portion formed by etching a substrate and an actual upper layer portion formed on the actual pattern portion, and the inspection pattern includes an inspection pattern portion formed by etching the substrate. It includes an inspection layer portion that is formed at least on the inspection pattern portion and has a thickness thinner than that of the actual upper layer portion, and based on the difference between the shape of the inspection pattern portion and the shape of the inspection layer portion, the etching state of the actual pattern portion is evaluated.

[0013] A method for evaluating a pattern according to an aspect of the present disclosure is a method for evaluating a pattern for evaluating the processing state of an actual element including an actual pattern portion formed by etching a substrate and an actual upper layer portion formed on the actual pattern portion. It is a method for manufacturing an inspection pattern including an inspection pattern portion formed by etching the substrate and an inspection layer portion formed at least on the inspection pattern portion and having a thickness thinner than that of the actual upper layer portion, and observing the inspection pattern portion and the inspection layer portion from the side of the inspection layer portion, and evaluating the etching state of the actual pattern portion based on the difference between the shape of the inspection pattern portion and the shape of the inspection layer portion.

Advantages of the Invention

[0014] According to the above form, it is possible to provide an inspection pattern and a method for evaluating a pattern that can quantitatively and accurately measure the lateral etching amount during etching while being a non-destructive inspection.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Hereinafter, a first embodiment and a second embodiment of the present disclosure will be described. In this specification, the first embodiment and the second embodiment are also collectively referred to as "the present embodiment". In addition, the drawings used in the description of the present embodiment are for the purpose of explaining the technical idea, shape, and arrangement of the components of the present disclosure, and do not limit the specific shape and configuration of the present disclosure, nor necessarily accurately represent the balance and aspect ratio of each component.

[0017] [First Embodiment] FIG. 2(a) and FIG. 2(b) are diagrams for explaining the inspection pattern of the first embodiment. FIG. 2(a) is a top view for explaining the inspection pattern T on the semiconductor chip, and FIG. 2(b) is a cross-sectional view taken along the arrow lines IIb, IIb shown in FIG. 2(a). Such a first embodiment will be described by taking an element having a mesa among photodiodes manufactured by a compound semiconductor as an example. Further, FIGS. 2(a) and 2(b) show the state during the manufacturing process of the semiconductor chip, and the upper wiring layer and insulating layer are not formed yet.

[0018] As shown in FIGS. 2(a) and 2(b), the substrate 200 during the manufacturing process includes both the actual element M, which is a photodiode, and the inspection pattern T. The actual element M includes a mesa 202, which is an actual pattern portion formed by etching the substrate 200, and an electrode 201, which is an actual upper layer portion. The inspection pattern T includes a mesa 204, which is an inspection pattern portion, and a thin film 203, which is an inspection layer. In the present embodiment, in the following description, the direction in which the mesas 202 and 204 are formed from the substrate 200 is defined as "up" or "above" the chip, and the direction from the mesas 202 and 204 toward the substrate 200 is defined as "down" or "below". The inspection pattern T is used to evaluate the etching state of the mesa 202 based on the difference between the shape of the mesa 204 and the shape of the thin film 203.

[0019] The electrode 201 is formed on the mesa 202 and is used to supply power to the mesa. The thin film 203 is a layer formed at least on the mesa 204 and is thinner than the electrode 201. At this time, the substrate 200 is in the state of a wafer before dicing.

[0020] In the first embodiment, both the mesas 202 and 204 have a cylindrical shape. The electrode 201 is made of Au. The thin film 203 is an insulating film including an inorganic material film, and may be, for example, a film including SiN, SiO2, SiON, or at least one of these. The thin film 203 of the first embodiment covers the surface including the upper part of the mesa 204 and a part of the substrate 200 around the mesa 204. The outer edges of the peripheral part 203a of the thin film formed on the substrate 200 are indicated by straight lines L1 and L2 in FIGS. 2(a) and 2(b). Also, the outer edges of the upper surface of the mesa 204 are indicated by straight lines L2 and L4. The lateral etching amount of the mesa 202 of the actual element M cannot be observed from above by the electrode 201. On the other hand, when the mesa 204 of the inspection pattern T is observed from above, as shown in FIG. 2(a), it appears to overlap with the thin film 203. The thin film 203 may be a film that is thin enough to observe the upper surface of the mesa 204 and has transparency. For example, its thickness is preferably about 0.02 μm to 0.2 μm. Such an inspection pattern T can focus on both the edge of the upper surface 204a and the edge of the peripheral part 203a in the observation from above, so that the state of the shape difference (diameter difference) between the two can be clearly visually recognized.

[0021] The shape of the mesa 204 in the first embodiment refers to the diameter r1 of the upper surface 204a of the cylindrical mesa 204. By observing the upper surface 204a from above without destroying the chip, accurately measuring the diameter r1, and comparing it with the designed value of the diameter of the upper surface 202a of the actual element M, the lateral etching amount of the mesa 204 can be obtained. Then, the lateral etching amount of the mesa 204 can be used as the lateral etching amount of the mesa 202 generated below the electrode 201, or the lateral etching amount of the mesa 202 under the electrode 201 can be estimated based on the lateral etching amount of the mesa 204.

[0022] That is, as will be described in detail later, the etching of the mesas 202 and 204 is performed simultaneously. For this reason, conditions such as the flow rate of the etching gas, the discharge, and the state inside the etching chamber during the etching of the mesas 202 and 204 are the same. Also, since the mesas 202 and 204 are formed on the same substrate 200, conditions such as the composition of the wafer are also the same. Furthermore, in the first embodiment, the mesas 202 and 204 are formed within a range where the etching state does not change depending on the position of the wafer. Therefore, the amount of lateral etching occurring in the mesa 204 can be regarded as the same as the amount of lateral etching occurring in the mesa 202.

[0023] Furthermore, in the first embodiment, the thin film 203 including the peripheral portion 203a has a shape based on the design value of the mesa 202. The shape of the thin film 203 referred to in this embodiment refers to the diameter r2 of the peripheral portion 203a, and in the peripheral portion 203a of the first embodiment, its diameter r2 is equal to the design value of the diameter of the mesa 202. In this way, the inspector can observe the inspection pattern T from above and measure the length between the straight lines L1 and L2 or between the straight lines L3 and L4 to immediately evaluate the amount of lateral etching. At this time, as shown in FIG. 2(a), according to the inspection pattern T, the diameter r1 of the upper surface 204a of the mesa 204 can be clearly visually recognized based on the diameter r2 of the edge of the peripheral portion 203a, facilitating the measurement of the amount of lateral etching and making it possible to intuitively grasp it. Here, "evaluation" refers to the magnitude of the difference between the dimensional shape of the fabricated actual pattern M and the design value, and the smaller the difference, the higher the evaluation. Also, in the first embodiment, a threshold value may be set for the difference, and when the difference is less than or equal to the threshold value, the actual element may be evaluated to allow a difference from the design value.

[0024] As described above, according to the first embodiment, the lateral etching amount of the actual element M that is difficult to measure nondestructively can be quantified by observing the inspection pattern T from above. Furthermore, if the outer edge of the peripheral portion 203a is designed to match the outer edge of an ideal mesa, it becomes easier to measure and easier to sensuously recognize the degree of lateral etching. Therefore, the first embodiment can provide an inspection pattern that can quantitatively and accurately evaluate the lateral etching amount during etching while being a non-destructive inspection.

[0025] Furthermore, the first embodiment does not limit the shapes of the mesas 202 and 204 to a cylindrical shape. For example, the mesas 202 and 204 may have a prismatic shape with a rectangular upper surface. Even in such a case, the size of the rectangle on the upper surface can be measured to determine the lateral etching amount. Furthermore, the first embodiment can determine the degree of overetching not only by lateral etching but also, for example, by the shape of the corner portion of the rectangle on the upper surface (such as the corner portion being rounded). Furthermore, the first embodiment can be applied to determining the presence or absence of taper etching by observing a cylindrical or prismatic inspection pattern from above and depending on the length of the interval between the upper surface and the peripheral portion.

[0026] Next, a method for manufacturing an inspection pattern according to the first embodiment will be described. FIGS. 3(a) to 6(b) are diagrams for explaining a method for manufacturing an inspection pattern T according to the first embodiment. Among these, FIGS. 3(a), 4(a), 5(a), and 6(a) are schematic top views of the chip during manufacturing, and FIGS. 3(b), 4(b), 5(b), and 6(b) are cross-sectional views along the cutting lines of the corresponding top views, respectively. In manufacturing the inspection pattern, first, as shown in FIGS. 3(a) and (b), an electrode 201 made of Au and an alignment mark 205 are formed on a substrate 200 in the state of a wafer. The alignment mark 205 is used for alignment when performing exposure a plurality of times at the position of the inspection pattern in subsequent processes. The substrate 200 of the first embodiment is a semiconductor epitaxial substrate. The formation of the electrode 201 is performed, for example, by a known method. This method may be, for example, a method in which a resist is applied to the surface of the substrate 200, a mask is fabricated by photolithography, the electrode 201 is formed by, for example, electron beam evaporation from above the mask, and then lift-off is performed. The alignment mark 205 can be formed, for example, by putting a pattern for making an alignment mark in the mask and depositing an Au member by electron beam evaporation.

[0027] Next, in the first embodiment, a resist mask (not shown) is formed on the electrode 201 with reference to the alignment mark 205. At this time, a resist mask having the same material, dimensions, and shape is also formed at the position where the inspection pattern is to be formed. Then, the wafer-state substrate 200 is etched, for example, by a wet technique using this resist mask, whereby mesas 202 and 204 shown in FIGS. 4(a) and 4(b) are formed. The etching for forming the mesa 204 is performed simultaneously with the etching of the mesa 202. The mesa 204 is formed by etching a position different from the position where the electrode 201 is formed. However, the formation position of the mesa 204 is within a range where it is considered that the conditions are the same as those for the etching of the mesa 202 on the wafer.

[0028] The mesa 202 in the state shown in FIG. 4(b) is formed directly under the electrode 201, and the mesa 204 is in a state where the upper surface 204a is exposed on the substrate 200. Also, lateral etching occurs during the etching when forming the mesas 202 and 204. Due to the lateral etching, as shown in FIG. 4(b), the mesa 202 becomes smaller in diameter than the electrode 201, and its edge enters under the electrode 201 and cannot be observed from above. On the other hand, after the resist layer is peeled off, the upper surface 204a of the mesa 204 is in an exposed state, and the edge of the upper surface can be observed from above. Further, for the mesa 204 shown in FIG. 4(b), in order to observe the amount of lateral etching, it is necessary to measure the diameter of the upper surface 204a and subtract this from the ideal value (design value). In the first embodiment, a thin film 203 is formed on the mesa 204 so that the degree of lateral etching can be grasped immediately by observing the upper surface 204a of the mesa 204 from above.

[0029] Next, the formation of the thin film 203 will be described with reference to FIGS. 5(a) to 6(b). As shown in FIGS. 5(a) and 5(b), in the first embodiment, the thin film 203 is formed on the entire surface of the substrate 200. The thin film 203 of the first embodiment is, for example, a 20-nm SiN film formed by plasma CVD (Chemical Vapor Deposition). Then, in the first embodiment, a resist mask (not shown) is formed on the upper surface 202a of the mesa 202 from above the thin film 203, and the thin film 203 except for the portion covered by the resist mask is dry-etched, for example. At this time, in the first embodiment, the diameter of the resist mask is made to match the ideal diameter of the mesa 202. When the thin film 203 is etched, since lateral etching occurs on the mesa 204, when etching is performed using a resist mask that matches the ideal diameter of the mesa 202, as shown in FIG. 5(b), a thin film serving as the peripheral portion 203a remains not only on the surface of the mesa 204 but also on the substrate 200 around the mesa 204.

[0030] Also, during the etching of the thin film 203, lateral etching may occur in the same manner as during the formation of the mesas 202 and 204. However, as described above, the thickness of the thin film 203 is very thin at 20 nm, and the etching time is sufficiently shorter compared to the etching time of the mesa. For this reason, the amount of lateral etching occurring in the thin film is negligible, and the outer edge of the peripheral portion 203a can be regarded as coinciding with the ideal diameter of the mesa 202. Regarding the thickness of the thin film 203, since it is necessary that the mesa 204 of the actual device M can be visually recognized from above when the mesa 202 cannot be visually recognized from above, it is conditioned to be thinner than the electrode 201. However, the thickness of the thin film 203 is appropriately determined according to the light transmittance of the material, the etching rate, etc.

[0031] The evaluation of the mesa 202 using the inspection pattern T of the first embodiment described above is performed during the manufacturing process of the semiconductor chip with the mesas 204 and the thin film 203 exposed. Note that the state where the mesas 204 and the thin film 203 are exposed means, for example, a state where no layers of any kind are yet formed on at least the upper layer of the inspection pattern T.

[0032] [Second Embodiment] Next, a second embodiment of the present disclosure will be described. FIGS. 7(a) and 7(b) are diagrams for explaining the inspection pattern of the second embodiment, FIG. 7(a) is a top view, and FIG. 7(b) is a cross-sectional view taken along the arrow lines VIIb and VIIb shown in FIG. 7(a). The inspection patterns T1, T 2、 T3 of the second embodiment are provided in plurality around the same chip as the actual device M, and at least a part of the plurality of inspection patterns T1, T 2、 T3 each include similar thin films 303a, 303b, 303c that have the same shape and different sizes. The inspection patterns T1, T 2、Similar to the first embodiment, T3 has a mesa 304 formed by etching an amorphous substrate 300 and one of thin films 303a, 303b, and 303c formed on the upper surface 304a of the mesa 304. Also, similar to the first embodiment, the actual element M includes a mesa 302 formed by etching the substrate 300 and an electrode 301 formed on the upper surface 302a of the mesa 302.

[0033] As is clear from FIGS. 7(a) and 7(b), among the thin films 303a, 303b, and 303c, the diameter of the thin film 303a is smaller than the upper surface 304a, the diameter of the thin film 303b is the same as the diameter of the upper surface 304a, and the diameter in the top view of the thin film 303c including the peripheral portion 303ca is larger than the upper surface 304a. Also, the three inspection patterns T1, T 2、 The diameters of the upper surface 304a of T3 are all the same.

[0034] FIG. 8 is a top view for explaining the thin films 303a, 303b, and 303c. The diameters of the thin films 303a, 303b, and 303c increase by 0.2 μm in this order. That is, as shown in FIG. 8, the distance d a,b 、d b,cThey are each 0.1 μm. Also, in FIG. 8, the outer edge of the resist mask 801 used for the etching to form the mesa 304 is indicated by a broken line. The resist mask 801 is circular in top view, and all of its diameters are the same. The diameter ra of the thin film 303a is 0.2 μm smaller than that of the resist mask 801, the diameter rb of the thin film 303b is 0.1 μm smaller than the diameter of the resist mask 801, and the diameter rc of the thin film 303c is designed to match the diameter of the resist mask 801. According to the inspection pattern T3 in the state shown in FIG. 8, since the diameter of the upper surface 304a is smaller than the diameter rc of the thin film 303c, it can be seen that lateral etching occurs during the formation of the mesa 304 and the diameter of the mesa 304 is smaller than that of the resist mask 801. Also, according to the inspection pattern T1, since the upper surface 304a is larger than the diameter ra of the thin film 303a, it can be seen that the amount of lateral etching is 0.2 μm or less. Furthermore, according to the inspection pattern T2, since the upper surface 304a coincides with the diameter rb of the thin film 303a, it can be seen that the amount of lateral etching is about 0.1 μm. As described above, the second embodiment can not only determine the presence or absence of lateral etching during the etching of the mesa, but also evaluate the approximate degree thereof without measuring the diameter of the mesa.

[0035] Next, a method for manufacturing the inspection pattern of the second embodiment will be described. FIGS. 9(a) to 13(b) are diagrams for explaining a method for manufacturing the inspection pattern T of the second embodiment. Among these, FIGS. 9(a), 10(a), 11(a) and 12(a) are schematic top views of the chip during manufacturing, and FIGS. 9(b), 10(b), 11(b) and 12(b) are cross-sectional views along the cut lines of the corresponding top views, respectively. In the second embodiment, as shown in FIGS. 9(a) and 9(b), similar to the first embodiment, an electrode 301 and an alignment mark 305 are formed on the substrate 300. Then, as shown in FIGS. 10(a) and 10(b), thin films 303a, 303b, and 303c having the same shape and different sizes (diameters) are formed at predetermined positions different from the formation positions of the electrodes 301, respectively. The thin films 303a, 303b, and 303c of the second embodiment are SiN films formed by plasma CVD, similar to the first embodiment.

[0036] Next, in the second embodiment, as shown in FIGS. 11(a) and 11(b), a resist mask 801 is formed on the electrode 301 by known photolithography. Also, a resist mask 801 having the same diameter as the resist mask 801 on the electrode 301 is formed on each of the thin films 303a, 303b, and 303c. Next, in the second embodiment, the substrate 300 is etched using the resist mask 801 as a mask to form the mesas 302 and 304. FIGS. 12(a) and 12(b) show the state of the substrate 300 after etching and before peeling the resist mask 801. According to FIGS. 12(a) and 12(b), it can be seen that the diameters of the mesas 302 and 304 are smaller than that of the resist mask 801, and lateral etching has occurred during etching. Also, although the diameters of the mesas 304 are all equal, the diameters of the thin films 303a, 303b, and 303c on the upper surface 304a are different, and the approximate degree of lateral etching can be evaluated without measuring it by comparing the edges of the thin films 303a, 303b, and 303c and the edge of the upper surface 304a.

[0037] FIGS. 13(a) and 13(b) show the state in which the resist mask 801 has been peeled off from the inspection pattern and the actual pattern in the state shown in FIGS. 12(a) and 12(b). Note that the peeling of the resist mask 801 is performed using, for example, acetone and ethanol.

[0038] Note that in the first and second embodiments of the present disclosure described above, examples in which the shapes of the mesas and the upper surfaces of the thin films are circular in top view are shown, but the shapes of the mesas and the upper surfaces of the thin films in top view are not limited to circular, and may be rectangular such as elliptical, rectangular, or square. It is obvious that this shape can take any shape according to the original purpose of the actual element itself.

Explanation of Reference Numerals

[0039] 200, 300 Substrate 201, 301 Electrode 202, 204, 302, 304 Mesa Above 202a, 204a, 302a, 304a Thin films 203, 303a, 303b, 303c Peripheral parts 203a, 303c, a Alignment marks 205, 305 Resist mask 801 Actual element M Inspection pattern T Observation hole H

Claims

1. An inspection pattern for inspecting the processing state of a pattern used in a real device, wherein the real device includes a real pattern portion formed by etching a substrate and a real upper layer portion formed on the real pattern portion, and the inspection pattern includes an inspection pattern portion formed by etching the substrate, and an inspection layer portion formed at least on the inspection pattern portion and having a thickness thinner than that of the real upper layer portion, and an inspection pattern for evaluating the etching state of the real pattern portion based on a difference between the shape of the inspection pattern portion and the shape of the inspection layer portion.

2. The inspection pattern according to claim 1, wherein the shape of the inspection layer portion as viewed from above coincides with the shape of the real pattern portion as viewed from above based on the design value of the real pattern portion.

3. The inspection pattern according to claim 1 or 2, wherein a plurality of the inspection patterns are provided on the substrate, and at least a part of the plurality of inspection patterns each include similar inspection layer portions having the same shape and different sizes.

4. The inspection pattern according to any one of claims 1 to 3, wherein the real upper layer portion is an electrode for supplying power to the real pattern portion.

5. The inspection pattern according to any one of claims 1 to 4, wherein the inspection layer portion includes a film of an inorganic material.

6. A pattern evaluation method for evaluating the processing state of a real device including a real pattern portion formed by etching a substrate and a real upper layer portion formed on the real pattern portion, the method including a step of manufacturing an inspection pattern including an inspection pattern portion formed by etching the substrate and an inspection layer portion formed at least on the inspection pattern portion and having a thickness thinner than that of the real upper layer portion, and a step of observing the inspection pattern portion and the inspection layer portion from the side of the inspection layer portion and evaluating the etching state of the real pattern portion based on a difference between the shape of the inspection pattern portion and the shape of the inspection layer portion.

7. The pattern evaluation method according to claim 6, wherein the step of evaluating the etching state of the real pattern portion is performed at least in a state where the inspection pattern is exposed.

Images