Method and apparatus for time-dependent degradation of symmetry of a clock tree

Abstract

In a particular aspect, an apparatus includes a gating circuit having an enable input, a signal input, and an output, where the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, where the toggle circuit is configured to toggle a logic state at an output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, where the first input of the multiplexer is coupled to the output of the gating circuit and the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and to couple the selected one of the first input and the second input to the output of the multiplexer.

Description

Background Art

[0001] (Cross - Reference to Related Applications) This application claims priority and benefit to non - provisional application Ser. No. 17 / 655,697, filed with the United States Patent and Trademark Office on Mar. 21, 2022, the entire contents of which are hereby incorporated by reference herein in their entirety as if fully set forth below and for all applicable purposes.

[0002] Field Aspects of the present disclosure generally relate to degradation over time, and more particularly, to mitigating degradation over time.

[0003] Background A system may include a clock source (e.g., a phase - locked loop) configured to generate a clock signal to adjust the timing of the operation of one or more circuits (e.g., sequential logic, processors, memories, etc.) within the system. The system may also include a clock path for distributing the clock signal from the clock source to one or more circuits. The problem faced by clock distribution is that asymmetric degradation over time in the clock path can cause duty - cycle distortion in the clock signal, which may lead to timing problems (e.g., timing violations) in one or more circuits.

Summary of the Invention

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This "Summary of the Invention" is not an overview of all contemplated implementations, nor is it intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as an introduction to the "Detailed Description of the Invention" that follows.

[0005] The first aspect relates to an apparatus. The apparatus includes a gating circuit having an enable input, a signal input, and an output, where the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, where the toggle circuit is configured to toggle a logical state at the output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, where the first input of the multiplexer is coupled to the output of the gating circuit and the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and couple the selected one of the first input and the second input to the output of the multiplexer.

[0006] The second aspect relates to a method for balancing aging over time in a clock path. The method includes receiving an enable signal, passing a clock signal through the clock path when the enable signal has a first logical state, gating the clock signal when the enable signal has a second logical state, toggling a logical state of a toggle circuit in response to an edge of the enable signal, and passing the logical state of the toggle circuit through the clock path when the clock signal is gated. BRIEF DESCRIPTION OF THE DRAWINGS

[0007]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

DETAILED DESCRIPTION OF THE INVENTION

[0008] In connection with the accompanying drawings, the "Modes for Carrying Out the Invention" described below is intended as an explanation of various configurations and is not intended to represent the only configuration capable of practicing the concepts described in this specification. The "Modes for Carrying Out the Invention" includes specific details for the purpose of providing a complete understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0009] FIG. 1 shows an embodiment of a system 110 including a clock source 115, a gating circuit 120, a clock path 130, and a circuit 140 according to a particular aspect. Circuit 140 may include sequential logic, a processor, a memory, and the like. Clock source 115 is configured to generate a clock signal and output that clock signal at output 118. Clock source 115 can be implemented using a phase-locked loop (PLL) or another type of clock source. The clock signal is used to regulate the timing of the operation of circuit 140.

[0010] Clock path 130 has an input 132 and an output 134. Output 134 is coupled to circuit 140. Clock path 130 is configured to receive a clock signal at input 132 and distribute that clock signal to circuit 140. As used herein, a "clock signal" can be a periodic signal that oscillates between high and low. The clock signal has a duty cycle, which can be expressed as a percentage or ratio of the clock period (i.e., the clock cycle) during which the clock signal is high (i.e., 1).

[0011] The gating circuit 120 (also referred to as a clock gating cell) has a signal input 122, an enable input 124, and an output 126. The signal input 122 is coupled to the output 118 of the clock source 115, and the output 126 is coupled to the input 132 of the clock path 130. The enable input 124 is configured to receive an enable signal, and the signal input 122 is configured to receive a clock signal. During operation, the gating circuit 120 is configured to pass the clock signal to the output 126 or gate (i.e., block) the clock signal based on the enable signal. For example, the gating circuit 120 can be configured to pass the clock signal to the output 126 when the enable signal has a first logic state and to gate the clock signal when the enable signal has a second logic state. The first logic state can be high (i.e., 1), the second logic state can be low (i.e., 0), or vice versa. Therefore, in this embodiment, when the enable signal transitions from the first logic state to the second logic state, the gating circuit 120 begins gating the clock signal. When the enable signal transitions from the second logic state to the first logic state, the gating circuit 120 stops gating the clock signal.

[0012] In certain embodiments, the enable signal is provided by a power management circuit 160 coupled to an enable input 124. In these embodiments, the power management circuit 160 uses the enable signal to control whether the gating circuit 120 passes the clock signal to the clock path 130 or gates (i.e., blocks) the clock signal. In one example, the power management circuit 160 uses the enable signal to pass the clock signal to the gating circuit 120 (e.g., by setting the enable signal to a first logic state) when circuit 140 is active, and to gate the clock signal to the gating circuit 120 (i.e., by setting the enable signal to a second logic state) when circuit 140 is in an idle mode (i.e., not active), thereby saving power. Clock gating is a known technique for reducing dynamic power consumption when a circuit is not active.

[0013] In FIG. 1, one gating circuit 120 is shown between the clock source 115 and the clock path 130, but it should be understood that the system 110 may include two or more clock gating circuits (e.g., at various locations along the clock path 130). Also, it should be understood that the clock path 130 may include a plurality of branches (not shown) forming a clock tree for distributing the clock signal to one or more other circuits (not shown) other than the circuit 140 shown in FIG. 1.

[0014] Due to aging effects such as bias temperature instability (BTI), the performance of the clock path 130 may degrade over time. For example, BTI stress in the clock path 130 during the idle mode may cause a duty cycle shift in the clock path 130 over time, which may lead to timing problems (e.g., timing violations) in circuit 140.

[0015] Next, with reference to FIGS. 2A to 2E, an example of a duty cycle shift caused by aging is discussed. FIG. 2A shows an example in which a clock path 130 includes clock buffers 220-1 to 220-4 connected in series between an input 132 and an output 134. In FIG. 2A, four clock buffers 220-1 to 220-4 are shown for simplicity, but it should be understood that the clock path 130 may include a large number of clock buffers. In the example shown in FIG. 2A, each of the clock buffers 220-1 to 220-4 is implemented using a corresponding complementary inverter including a corresponding one of transistors 225-1 to 225-4 (e.g., n-type field effect transistors) and a corresponding one of transistors 230-1 to 230-4 (e.g., p-type field effect transistors). However, it should be understood that each of the clock buffers 220-1 to 220-4 can be implemented using another type of circuit or logic gate.

[0016] When circuit 140 is in the active mode, gating circuit 120 passes a clock signal to input 132 of clock path 130, and the clock signal propagates through clock buffers 220-1 to 220-4 to circuit 140. When circuit 140 is in the idle mode, gating circuit 120 gates the clock signal and holds input 132 of clock path 130 at high or low (i.e., holds).

[0017] Figure 2B shows an example in which the gating circuit 120 holds the input 132 of the clock path 130 low (i.e., logic 0) in the idle mode. Figure 2B also shows the logic states at the inputs and outputs of each of the clock buffers 220-1 to 220-4. In this example, the output 134 of the clock path 130 is low (i.e., logic 0) in the idle mode. In this example, the transistors 230-1, 225-2, 230-3, and 225-4 are turned on in the idle mode, and the transistors 225-1, 230-2, 225-3, and 230-4 are turned off in the idle mode. In Figure 2B, the transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in the idle mode are shown in thick lines. The transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in the idle mode are stressed in the idle mode, while the transistors 225-1, 230-2, 225-3, and 230-4 that are turned off in the idle mode are not stressed in the idle mode. This leads to an asymmetric aging over time in which the transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in the idle mode age faster than the transistors 225-1, 230-2, 225-3, and 230-4 that are not stressed in the idle mode.

[0018] In this embodiment, the asymmetric aging increases the fall edge delay at the output 134 of the clock path 130 with respect to the rise edge delay at the output 134 of the clock path 130 by shifting the threshold voltages of the transistors 230-1, 225-2, 230-3, and 225-4. The increase in the fall edge delay with respect to the rise edge delay causes a duty cycle shift in the clock path 130. An example of this duty cycle shift is shown in the timing diagram of FIG. 2C. In the example shown in FIG. 2C, a clock signal 250 having a 50% duty cycle is input to the clock path 130 in the active mode. FIG. 2C also shows the clock signal 260 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rise edge of the clock signal 250 by a delay T r until the delay T f and delays the fall edge of the clock signal 250 by a delay T f until the delay T r . As shown in FIG. 2C, the fall edge delay T f is longer than the rise edge delay T r due to the asymmetric aging. In this embodiment, the longer fall edge delay increases the duty cycle of the clock signal 260 at the output 134 of the clock path 130 (i.e., results in a duty cycle greater than 50%).

[0019] In the embodiments shown in FIGS. 2B and 2C, the gating circuit 120 holds the input 132 of the clock path 130 low in the idle mode. Asymmetric aging degradation also occurs when the gating circuit 120 holds the input 132 of the clock path 130 high in the idle mode. In this regard, FIG. 2D shows an embodiment in which the gating circuit 120 holds the input 132 of the clock path 130 high (i.e., logic 1) in the idle mode. FIG. 2D also shows the logic states at the inputs and outputs of each clock buffer 220-1 to 220-4. In this embodiment, the output 134 of the clock path 130 is high (i.e., logic 1) in the idle mode. In this embodiment, transistors 225-1, 230-2, 225-3, and 230-4 are turned on in the idle mode, and transistors 230-1, 225-2, 230-3, and 225-4 are turned off in the idle mode. In FIG. 2D, the transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are shown in thick lines. The transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are stressed in the idle mode, while the transistors 230-1, 225-2, 230-3, and 225-4 that are turned off in the idle mode are not stressed in the idle mode, which leads to asymmetric aging degradation in which the transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in the idle mode degrade faster than the transistors 230-1, 225-2, 230-3, and 225-4.

[0020] In this embodiment, the asymmetric aging increases the delay of the rising edge at the output 134 of the clock path 130 with respect to the delay of the falling edge at the output 134 of the clock path 130 by shifting the threshold voltages of the transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in the idle mode. The increase in the delay of the rising edge with respect to the delay of the falling edge causes a duty cycle shift in the clock path 130. One example of this duty cycle shift is shown in the timing diagram of FIG. 2E. In the embodiment shown in FIG. 2E, a clock signal 250 having a 50% duty cycle is input to the clock path 130 in the active mode. FIG. 2E also shows the clock signal 270 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rising edge of the clock signal 250 by a delay T r up to a delay T f and delays the falling edge of the clock signal 250 by a delay T r up to a delay T. As shown in FIG. 2E, the delay T r of the rising edge is longer than the delay T f of the falling edge due to the asymmetric aging. In this embodiment, the longer delay of the rising edge reduces the duty cycle of the clock signal 270 at the output 134 of the clock path 130 (i.e., results in a duty cycle of less than 50%).

[0021] Therefore, the aging degradation of the asymmetry in the idle mode causes a duty cycle shift (i.e., duty cycle distortion) in the clock path 130 over time. The duty cycle shift is caused, for example, by whether the gating circuit 120 holds the input 132 of the clock path 130 low or high in the idle mode, and by the number of clock buffers 220-1 to 220-4 in the clock path 130, increasing or decreasing the duty cycle of the clock signal. The duty cycle shift may lead to timing problems in the circuit 140. For embodiments where the circuit 140 includes sequential logic (e.g., flip-flops), the duty cycle shift may result in violations of setup time and / or hold time.

[0022] To address the duty cycle shift (i.e., distortion) caused by the aging degradation of the asymmetry, aspects of the present disclosure provide a toggle circuit that alternates between holding the input of the clock path low and high in the idle mode, instead of holding the input of the clock path in the same logic state in the idle mode. By alternating between holding the input of the clock path low and high, the toggle circuit helps to balance the aging degradation of the transistors in the clock path and reduce the duty cycle distortion, as further discussed below.

[0023] FIG. 3 shows an embodiment of a system 310 that includes the clock source 115, the gating circuit 120, the clock path 130, and the circuit 140 discussed above. The system 310 also includes a toggle circuit 320 and a multiplexer 330 that, according to certain aspects, help to balance the aging degradation in the clock path 130, as further discussed below.

[0024] In this embodiment, the toggle circuit 320 has an input 322 and an output 324. The toggle circuit 320 is configured to receive an enable signal at the input 322 and, in response to an edge of the enable signal, toggle (i.e., change) the logical state at the output 324. Therefore, if the current logical state at the output 324 is 1 (i.e., high), the toggle circuit 320 changes the logical state at the output 324 to 0 (i.e., low) at the edge of the enable signal. If the current logical state at the output 324 is 0, the toggle circuit 320 changes the logical state at the output 324 to 1 at the edge of the enable signal. In one embodiment, the toggle circuit 320 is a positive edge-triggered type that toggles the logical state at the output 324 at the rising edge of the enable signal. In another embodiment, the toggle circuit 320 is a negative edge-triggered type that toggles the logical state at the output 324 at the falling edge of the enable signal. The toggle circuit 320 can be implemented using a toggle flip-flop or another type of toggle circuit. As further discussed below, the toggle circuit 320 is used to alternately hold the input 132 of the clock path 130 low and high in the idle mode to balance the degradation over time in the clock path 130.

[0025] The multiplexer 330 has a first input 332, a second input 334, an output 336, and a selection input 338. The first input 332 is coupled to the output 126 of the gating circuit 120, the second input 334 is coupled to the output 324 of the toggle circuit 320, and the output 336 is coupled to the input 132 of the clock path 130. In a particular aspect, the multiplexer 330 is configured to receive an enable signal at the selection input 338 and, based on the enable signal, select one of the first input 332 and the second input 334 and couple the selected one of the first input 332 and the second input 334 to the output 336.

[0026] In one embodiment, multiplexer 330 is configured to select the first input 332 when the enable signal has a first logic state and to select the second input 334 when the enable signal has a second state. As described above, gating circuit 120 is configured to pass the clock signal when the enable signal has a first logic state and to gate the clock signal when the enable signal has a second logic state. Therefore, in this embodiment, multiplexer 330 couples the output 126 of gating circuit 120 to the input 132 of clock path 130 when gating circuit 120 passes the clock signal. In this case, multiplexer 330 passes the clock signal from gating circuit 120 to clock path 130. Also, in this embodiment, multiplexer 330 couples the output 324 of toggle circuit 320 to the input 132 of clock path 130 when gating circuit 120 gates the clock signal in the idle mode. As a result, the output 324 of toggle circuit 320 controls whether the input 132 of clock path 130 is held low or high in the idle mode.

[0027] Next, an exemplary operation of system 310 will be described according to a particular aspect.

[0028] In this embodiment, power management circuit 160 causes gating circuit 120 to gate the clock signal when circuit 140 is in the idle mode (i.e., not active) in order to conserve power. To do this, power management circuit 160 sets the enable signal to the second logic state in the idle mode, which causes gating circuit 120 to gate the clock signal and causes multiplexer 330 to select the second input 334. Since multiplexer 330 selects the second input 334 in the idle mode, the output 324 of toggle circuit 320 is coupled to the input 132 of clock path 130 in the idle mode, and therefore determines whether the input 132 of clock path 130 is held low or high in the idle mode.

[0029] Over time, the power management circuit 160 gates the clock signal to the gating circuit 120 over many idle periods, where each "idle period" is the period while circuit 140 is in the idle mode (i.e., not active). The idle periods are separated by active periods, where each "active period" is the period while circuit 140 is active. During each active period, the power management circuit 160 passes the clock signal to the gating circuit 120 (e.g., by setting an enable signal to a first logic state) and causes the multiplexer 330 to select the first input 332.

[0030] For each idle period, the enable signal has a rising edge and a falling edge. This is because the enable signal transitions from a first logic state to a second logic state at the start of the idle period to gate the clock signal, and transitions from the second logic state to the first logic state at the end of the idle period to release the gating of the clock signal. For an embodiment where the first logic state is 1 and the second logic state is 0, the gating circuit 120 starts gating the clock signal at the start of the idle period at the falling edge of the enable signal, and stops gating the clock signal at the end of the idle period at the rising edge of the enable signal. For an embodiment where the first logic state is 0 and the second logic state is 1, the gating circuit 120 starts gating the clock signal at the start of the idle period at the rising edge of the enable signal, and stops gating the clock signal at the end of the idle period at the falling edge of the enable signal. Therefore, in both embodiments, the enable signal has both a rising edge and a falling edge for each idle period.

[0031] Since the enable signal has both rising edges and falling edges for each idle period, the toggle circuit 320 toggles the logic state at the output 324 once for each idle period, regardless of whether the toggle circuit 320 is positive-edge triggered or negative-edge triggered. By toggling for each idle period, the output 324 of the toggle circuit 320 alternates between low (i.e., 0) and high (i.e., 1) over a plurality of idle periods. Therefore, if the output 324 of the toggle circuit 320 is 1 during the current idle period, the output 324 will be 0 during the next idle period, and vice versa.

[0032] The output 324 of the toggle circuit 320 alternates between low and high over a plurality of idle periods, and the multiplexer 330 couples the output 324 of the toggle circuit 320 to the input 132 of the clock path 130 in the idle mode. Therefore, the output 324 of the toggle circuit 320 holds the input 132 of the clock path 130 alternately low and high over a plurality of idle periods. Therefore, if the input 132 of the clock path 130 is held low during the current idle period, the input 132 of the clock path 130 will be held high during the next idle period, and vice versa.

[0033] Assuming that the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is approximately equal to the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, the input 132 of the clock path 130 spends approximately equal amounts of time held low and held high in the idle mode. As a result, the aging over time of the transistors (e.g., transistors 225-1 to 225-4 and transistors 230-1 to 230-4) within the clock path 130 becomes approximately balanced (i.e., symmetric). The balanced (i.e., symmetric) aging over time reduces the duty cycle distortion compared to the case where the input 132 of the clock path 130 causes an asymmetric aging over time of the transistors within the clock path 130 by being held at the same logical state for each idle period.

[0034] FIG. 4A shows an exemplary implementation of a toggle circuit 320 according to a particular aspect. In this example, the toggle circuit 320 includes a flip-flop 410 (e.g., a D flip-flop) and an inverter 420. The flip-flop 410 has a clock input 412, a data input 414, and an output 416. The clock input 412 is coupled to the input 322 of the toggle circuit 320 to receive an enable signal, and the output 416 is coupled to the output 324 of the toggle circuit 320. The inverter 420 has an input 422 and an output 424. The input 422 of the inverter 420 is coupled to the output 416 of the flip-flop 410, and the output 424 of the inverter 420 is coupled to the data input 414 of the flip-flop 410. Therefore, the inverter 420 inverts the logical state at the output 416 of the flip-flop 410 and inputs the inverted logical state to the data input 414 of the flip-flop 410.

[0035] In one embodiment, the flip-flop 410 is positive-edge triggered, in which case the flip-flop 410 is configured to latch the logical state at the data input 414 at the rising edge of the enable signal and output the latched logical state at the output 416. In this embodiment, the inverter 420 between the output 416 of the flip-flop 410 and the data input 414 of the flip-flop 410 toggles the logical state at the output 416 of the flip-flop 410 (and thus the output 324 of the toggle circuit 320) at the rising edge of the enable signal.

[0036] In another embodiment, the flip-flop 410 is negative-edge triggered, in which case the flip-flop 410 is configured to latch the logical state at the data input 414 at the falling edge of the enable signal and output the latched logical state at the output 416. In this embodiment, the inverter 420 between the output 416 of the flip-flop 410 and the data input 414 of the flip-flop 410 toggles the logical state at the output 416 of the flip-flop 410 (and thus the output 324 of the toggle circuit 320) at the falling edge of the enable signal.

[0037] FIG. 4B shows another exemplary implementation of the toggle circuit 320 according to a particular aspect. In this embodiment, the toggle circuit 320 includes a flip-flop 430 (e.g., a D flip-flop) having a clock input 432, a data input 434, a first output 436, and a second output 438. The first output 436 and the second output 438 are complementary (i.e., the logical state at the second output 438 is the inversion of the logical state at the first output 436). In this embodiment, the clock input 432 is coupled to the input 322 of the toggle circuit 320 to receive the enable signal, and the first output 436 is coupled to the output 324 of the toggle circuit 320. The second output 438 of the flip-flop 430 is coupled to the data input 434 of the flip-flop 430.

[0038] In one embodiment, the flip-flop 430 is positive edge-triggered. In this case, the flip-flop 430 latches the logical state at the data input 434 at the rising edge of the enable signal, outputs the latched logical state at the first output 436, and outputs the inversion of the latched logical state at the second output 438. In this embodiment, coupling the data input 434 to the second output 438 toggles the logical state at the first output 436 of the flip-flop 430 (and thus the output 324 of the toggle circuit 320) at the rising edge of the enable signal.

[0039] In another embodiment, the flip-flop 430 is negative edge-triggered. In this case, the flip-flop 430 latches the logical state at the data input 434 at the falling edge of the enable signal, outputs the latched logical state at the first output 436, and outputs the inversion of the latched logical state at the second output 438. In this embodiment, coupling the data input 434 to the second output 438 toggles the logical state at the first output 436 of the flip-flop 430 (and thus the output 324 of the toggle circuit 320) at the falling edge of the enable signal.

[0040] It should be understood that the toggle circuit 320 is not limited to the exemplary implementation shown in FIGS. 4A and 4B, and the toggle circuit 320 can be implemented using other types of toggle circuits.

[0041] Figure 5 shows an exemplary implementation of the gating circuit 120 according to a particular aspect. In this embodiment, the gating circuit 120 includes a latch 510 and a gate 520. The latch 510 has a first input 512, a second input 514, and an output 516. The first input 512 is coupled to the enable input 124 of the gating circuit 120 to receive an enable signal, and the second input 514 is coupled to the signal input 122 of the gating circuit 120 to receive a clock signal. In a particular aspect, the latch 510 is configured to latch the logical state of the enable signal at the falling edge of the clock signal and output the latched logical state of the enable signal at the output 516. In these aspects, the latch 510 can be implemented using a negative edge-triggered flip-flop or another type of latch.

[0042] The gate 520 has a first input 522, a second input 524, and an output 526. The first input 522 is coupled to the output 516 of the latch 510, the second input 524 is coupled to the signal input 122 of the gating circuit 120 to receive a clock signal, and the output 526 is coupled to the output 126 of the gating circuit 120. In the embodiment of Figure 5, the gate 520 includes an AND gate that can be implemented using a NAND gate and an inverter. However, it should be understood that the gate 520 is not limited to this embodiment.

[0043] In this embodiment, the first logical state of the above-described enable signal is 1 and the second logical state of the above-described enable signal is 0. When the enable signal is 1, the latch 510 latches 1 at the falling edge of the clock signal and outputs 1 to the first input 522 of the gate 520. The 1 at the first input 522 of the gate 520 causes the gate 520 to pass the clock signal at the second input 524 to the output 526 (and thus the output 126 of the gating circuit 120). Therefore, in this embodiment, the gating circuit 120 passes the clock signal when the enable signal is 1.

[0044] When the enable signal is 0, the latch 510 latches 0 at the falling edge of the clock signal and outputs 0 to the first input 522 of the gate 520. The 0 at the first input 522 of the gate 520 causes the gate 520 to output 0 at the output 526 (and thus at the output 126 of the gating circuit 120), regardless of the logical state of the clock signal at the second input 524 of the gate 520. This effectively blocks the clock signal from the output 526, thereby gating the clock signal. Therefore, in this embodiment, the gating circuit 120 gates the clock signal when the enable signal is 0. By latching the logical state of the enable signal at the falling edge of the clock signal, the latch 510 helps to ensure that the gate 520 starts gating the clock signal when the clock signal is low (i.e., 0), and to prevent glitches at the output 126 of the gating circuit 120.

[0045] It should be understood that the gating circuit 120 is not limited to the exemplary implementation shown in FIG. 5, and the gating circuit 120 can be implemented using various configurations of one or more logic gates and one or more latches.

[0046] In certain embodiments, one or more latches can be used to control the timing of the input of the enable signal to the selection input 338 of the multiplexer 330. In this regard, FIG. 6 shows an example of a second latch 610 coupled between the output 516 of the latch 510 in the gating circuit 120 and the selection input 338 of the multiplexer 330. In this example, the second latch 610 has a first input 612, a second input 614, and an output 616. The first input 612 is coupled to the output 516 of the latch 510 in the gating circuit 120, and thus receives the enable signal from the output 516 of the latch 510. The second input 614 is coupled to the clock source 115 (shown in FIG. 3) to receive a clock signal, and the output 616 is coupled to the selection input 338 of the multiplexer 330. In certain embodiments, the second latch 610 is configured to latch the logical state of the enable signal at the rising edge of the clock signal and output the latched logical state of the enable signal to the selection input 338 of the multiplexer 330 via the output 616. In these embodiments, the second latch 610 can be implemented using a positive edge-triggered flip-flop or another type of latch.

[0047] In this embodiment, the multiplexer 330 can be configured to select the first input 332 when the enable signal is 1 and to select the second input 334 when the enable signal is 0. Therefore, when the gating circuit 120 passes the clock signal in this embodiment, the multiplexer 330 selects the first input 332, and when the gating circuit 120 gates the clock signal, the multiplexer 330 selects the second input 334. As described above, the gating circuit 120 of this embodiment starts gating the clock signal when the enable signal transitions from 1 to 0. In this embodiment, the second latch 610 delays the transition of the enable signal from 1 to 0 until the half period of the clock signal with respect to the output 516 of the latch 510 in the gating circuit 120. As a result, when the gating circuit 120 starts gating the clock signal, the multiplexer 330 switches from the first input 332 to the second input 334 after a delay of approximately half a clock cycle. This helps to ensure that the multiplexer 330 does not switch from the first input 332 to the second input 334 before the clock signal is gated.

[0048] FIG. 7 is a timing diagram showing an example of toggling according to a particular aspect of the present disclosure. More particularly, FIG. 7 shows an example of an enable signal (labeled "Enable") and a signal at the output 336 of multiplexer 330 (labeled "Mux Out"). In the example of FIG. 7, when the enable signal is 1, the clock signal is un-gated, and when the enable signal is 0, the clock signal is gated. Therefore, in this example, the enable signal is 0 during the idle period. As shown in FIG. 7, the output 336 of multiplexer 330 toggles between 1 and 0 over the idle period due to the toggling of toggle circuit 320. In the example of FIG. 7, the output 336 of multiplexer 330 is 1 (i.e., high) during odd idle periods (e.g., t1, t3,....) and 0 (i.e., low) during even idle periods (e.g., t2, t4,....). However, it should be understood that the present disclosure is not limited to this example.

[0049] Assuming that the cumulative duration of the idle periods during which the input 132 of clock path 130 is 0 (i.e., held low) is approximately equal to the cumulative duration of the idle periods during which the input 132 of clock path 130 is 1 (i.e., held high), the input 132 of clock path 130 spends approximately equal amounts of time held low and held high in the idle mode, which balances the aging over time of the transistors within clock path 130. Balanced (i.e., symmetric) aging over time reduces duty cycle shift in clock path 130.

[0050] However, in some cases, the cumulative duration of the idle period during which the input 132 of the clock path 130 is 0 (i.e., held low) is not approximately equal to the cumulative duration of the idle period during which the input 132 of the clock path 130 is 1 (i.e., held high). This can lead to a duty cycle shift in the clock path 130 that drives the duty cycle of the clock signal at the output 134 of the clock path 130 outside the allowable range. The duty cycle shift in the clock path 130 may also be caused by environmental conditions and / or other factors.

[0051] To address this, the system may include circuitry configured to disable (i.e., override) toggling in the idle mode when the duty cycle shift in the clock path 130 drives the clock signal at the output 134 of the clock path 130 outside the allowable range. In this case, the circuitry can hold the input 132 of the clock path 130 high or low depending on whether the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is longer or shorter than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high. For example, if the duty cycle shift in the clock path 130 is caused by the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low being longer than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, the circuitry can hold the input 132 of the clock path 130 high in the idle mode to move the duty cycle shift in the opposite direction. When the duty cycle of the clock signal returns within the allowable range, the circuitry can enable toggling in the idle mode again.

[0052] In this regard, FIG. 8 shows an embodiment of a system 805 that includes the gating circuit 120, toggle circuit 320, multiplexer 330, and clock path 130 discussed above. The system 805 also includes, according to certain aspects, a duty cycle monitor 810 and a control circuit 820. Also, in this embodiment, the toggle circuit 320 also has a reset input 832 and a set input 834.

[0053] In one embodiment, the reset input 832 is asserted by inputting a 1 to the reset input 832, and the set input 834 is asserted by inputting a 1 to the set input 834. However, it should be understood that the present disclosure is not limited to this embodiment. When the reset input 832 is asserted, the toggle circuit 320 disables (i.e., overrides) toggling and outputs a 0 at output 324. When the set input 834 is asserted, the toggle circuit 320 disables (i.e., overrides) toggling and outputs a 1 at output 324. If neither the reset input 832 nor the set input 834 is asserted, the toggle circuit 320 enables toggling and operates in the manner described above with reference to FIG. 3.

[0054] The duty cycle monitor 810 has an input 812 and an output 814. The input 812 can be coupled to the output 134 of the clock path 130. In certain aspects, the duty cycle monitor 810 is configured to measure the duty cycle of the clock signal at the output 134 of the clock path 130 and output a measurement signal indicative of the measured duty cycle at the output 814. Since the duty cycle monitor 810 is coupled to the output 134 of the clock path 130 in this embodiment, the duty cycle monitor 810 can measure a shift in the duty cycle of the clock signal caused by the clock path 130.

[0055] The control circuit 820 has an input 822, a first output 824, and a second output 826. The input 822 is coupled to the output of the duty cycle monitor 810, the first output 824 is coupled to the reset input 832 of the toggle circuit 320, and the second output 826 is coupled to the set input 834 of the toggle circuit 320.

[0056] During operation, the control circuit 820 receives a measurement signal from the duty cycle monitor 810 via the input 822. The control circuit 820 can then determine whether the measurement signal is within an acceptable range. This acceptable range may correspond to a range of duty cycles that do not cause a timing violation in the circuit 140. In one embodiment, the acceptable range can be defined by a first threshold and a second threshold. In this embodiment, the control circuit 820 can determine that the measurement signal is within the acceptable range when the measurement signal is between the first threshold and the second threshold. When the measured value is between the first threshold and the second threshold, the control circuit 820 deasserts both the reset input 832 and the set input 834 of the toggle circuit 320. In this case, the toggle circuit 320 toggles the output 324 as described above with reference to FIG. 3.

[0057] In this embodiment, the first threshold value may define the upper limit of the allowable range. When the measurement signal exceeds the first threshold value, the duty cycle is considered to be too high. When the measurement signal exceeds the first threshold value, the control circuit 820 asserts one of the reset input 832 and the set input 834. For example, when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is longer than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, and the measurement signal exceeds the first threshold value, the control circuit 820 can hold the input 132 of the clock path 130 high by asserting the set input 834. On the other hand, when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is shorter than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, and the measurement signal exceeds the first threshold value, the control circuit 820 can hold the input 132 of the clock path 130 low by asserting the reset input 832. Whether the measurement signal exceeds the first threshold value when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is longer or shorter than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high may depend, for example, on the number of clock buffers in the clock path 130 and / or the implementation form of the clock buffers in the clock path 130.

[0058] In this embodiment, the second threshold value may define the lower limit of the allowable range. When the measurement signal falls below the second threshold value, the duty cycle of the clock signal is considered to be too low. When the measurement signal falls below the second threshold value, the control circuit 820 asserts one of the reset input 832 and the set input 834. For example, when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is longer than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, and the measurement signal falls below the second threshold value, the control circuit 820 can hold the input 132 of the clock path 130 high by asserting the set input 834. On the other hand, when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is shorter than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high, and the measurement signal falls below the second threshold value, the control circuit 820 can hold the input 132 of the clock path 130 low by asserting the reset input 832. Whether the measurement signal falls below the second threshold value when the cumulative duration of the idle period during which the input 132 of the clock path 130 is held low is longer or shorter than the cumulative duration of the idle period during which the input 132 of the clock path 130 is held high may depend on, for example, the number of clock buffers in the clock path 130 and / or the implementation form of the clock buffers in the clock path 130.

[0059] In this embodiment, the control circuit 820 asserts a different one of the reset input 832 and the set input 834 when the measurement signal exceeds the first threshold value and when the measurement signal falls below the second threshold value. For example, when the control circuit 820 asserts the reset input 832 when the measurement signal exceeds the first threshold value, the control circuit 820 asserts the set input 834 when the measurement signal falls below the second threshold value. On the other hand, when the control circuit 820 asserts the set input 834 when the measurement signal exceeds the first threshold value, the control circuit 820 asserts the reset input 832 when the measurement signal falls below the second threshold value.

[0060] FIG. 9 shows a method 900 for equalizing the aging over time in a clock path. This clock path may correspond to the clock path 130.

[0061] In block 910, an enable signal is received. For example, the enable signal can be received by the gating circuit 120, the toggle circuit 320, and / or the multiplexer 330.

[0062] In block 920, when the enable signal has a first logic state, the clock signal is passed to the clock path. The clock signal can be passed by the gating circuit 120 and / or the multiplexer 330.

[0063] In block 930, when the enable signal has a second logic state, the clock signal is gated. For example, the clock signal can be gated by the gating circuit 120. The first logic state can be 1, the second logic state can be 0, or vice versa.

[0064] In block 940, the logic state of the toggle circuit is toggled in response to an edge of the enable signal. For example, the logic state of the toggle circuit can be toggled by the toggle circuit 320. The edge of the enable signal can be a rising edge or a falling edge.

[0065] In block 950, when the clock signal is gated, the logic state of the toggle circuit is passed to the clock path. For example, the logic state of the toggle circuit can be passed to the clock path by the multiplexer 330.

[0066] The power management circuit 160 and the control circuit 620 can each be implemented using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (such as logic gates), or any combination thereof, designed to perform the functions described herein. The functions described herein can be performed by a processor executing software that includes code for performing those functions. This software can be stored on a computer-readable storage medium such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk.

[0067] In the following numbered clauses, implementation examples are described. 1. An apparatus comprising: A gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal; A toggle circuit having an output, configured to toggle a logical state at the output of the toggle circuit based on the enable signal; A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit, and the multiplexer is configured to select one of the first input and the second input based on the enable signal, and couple the selected one of the first input and the second input to the output of the multiplexer. 2. The apparatus of clause 1, wherein the signal input of the gating circuit is coupled to a clock source. 3. The apparatus of clause 2, wherein the output of the multiplexer is coupled to a clock path including clock buffers coupled in series. 4. The device according to any one of clauses 1 to 3, wherein the toggle circuit is configured to toggle the logical state at the output of the toggle circuit in response to an edge of the enable signal. 5. The gating circuit is configured to receive a clock signal at a signal input and pass the clock signal to the output of the gating circuit when the enable signal is high, and to gate the clock signal when the enable signal is low. The multiplexer is configured to select the first input when the enable signal is high and to select the second input when the enable signal is low. The device according to any one of clauses 1 to 4. 6. The gating circuit is configured to receive a clock signal at a signal input and pass the clock signal to the output of the gating circuit when the enable signal is low, and to gate the clock signal when the enable signal is high. The multiplexer is configured to select the first input when the enable signal is low and to select the second input when the enable signal is high. The device according to any one of clauses 1 to 4. 7. The toggle circuit is a flip-flop having a data input, a clock input, and an output, wherein the clock input of the flip-flop is configured to receive the enable signal, and the output of the flip-flop is coupled to the output of the toggle circuit, and an inverter coupled between the output of the flip-flop and the data input of the flip-flop, the device according to any one of clauses 1 to 6. 8. The toggle circuit is A flip-flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flip-flop is configured to receive an enable signal, the first output is coupled to the output of a toggle circuit, the second output is coupled to the data input, and the first output and the second output are complementary, the apparatus of any one of clauses 1 to 6. 9. A clock path coupled to the output of a multiplexer and including clock buffers coupled in series. A duty cycle monitor coupled to the clock path. Further comprising a control circuit coupled to the duty cycle monitor and coupled to at least one of a set input and a reset input of the toggle circuit, the apparatus of any one of clauses 1 to 8. The apparatus of any one of clauses 1 to 8. 10. The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit. The control circuit is configured to assert one of the set input and the reset input of the toggle circuit when the measurement signal exceeds a threshold. The apparatus of clause 9. 11. The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit. The control circuit is configured to assert one of the set input and the reset input of the toggle circuit when the measurement signal is below a threshold. The apparatus of clause 9. 12. The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit. The control circuit is configured to assert the reset input of the toggle circuit when the measurement signal exceeds a first threshold value, and to assert the set input of the toggle circuit when the measurement signal falls below a second threshold value. The apparatus of clause 9. 13. The duty cycle monitor is configured to measure the duty cycle of a clock signal on a clock path and output a measurement signal indicating the measured duty cycle to a control circuit. The control circuit is configured to assert the set input of the toggle circuit when the measurement signal exceeds a first threshold value, and to assert the reset input of the toggle circuit when the measurement signal falls below a second threshold value. The apparatus of clause 9. 14. The gating circuit is a latch having a first input, a second input, and an output, wherein the first input of the latch is coupled to the enable input of the gating circuit, and the second input of the latch is coupled to the signal input of the gating circuit, and a gate having a first input, a second input, and an output, wherein the first input of the gate is coupled to the output of the latch, the second input of the gate is coupled to the signal input of the gating circuit, and the output of the gate is coupled to the output of the gating circuit, the apparatus of any one of clauses 1 to 13. 15. The apparatus of clause 14, wherein the gate includes an AND gate. 16. A method for equalizing aging over time in a clock path, receiving an enable signal, passing a clock signal through the clock path when the enable signal has a first logic state, gating the clock signal when the enable signal has a second logic state, toggling the logic state of a toggle circuit in response to an edge of the enable signal, and passing the logic state of the toggle circuit through the clock path when the clock signal is gated. 17. The method of clause 16, wherein the first logical state is 1 and the second logical state is 0. 18. The method of clause 16, wherein the first logical state is 0 and the second logical state is 1. 19. The method according to any one of clauses 16 to 18, wherein the edge of the enable signal is a rising edge. 20. The method according to any one of clauses 16 to 18, wherein the edge of the enable signal is a falling edge.

[0068] Within the scope of the present disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as being more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation being discussed. The term "coupled" as used herein refers to a direct or indirect electrical coupling between two structures.

[0069] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal; A toggle circuit having an output, wherein the toggle circuit is configured to toggle a logic state at the output of the toggle circuit based on the enable signal; A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit, and the multiplexer is configured to: Select one of the first input and the second input based on the enable signal; Couple the selected one of the first input and the second input to the output of the multiplexer; A clock path coupled to the output of the multiplexer, the clock path including clock buffers coupled in series; A duty cycle monitor coupled to the clock path; A control circuit coupled to the duty cycle monitor and coupled to at least one of a set input and a reset input of the toggle circuit; The apparatus.

2. The apparatus of claim 1, wherein the signal input of the gating circuit is coupled to a clock source.

3. The apparatus of claim 2, wherein the output of the multiplexer is coupled to a clock path including clock buffers coupled in series.

4. The apparatus of claim 1, wherein the toggle circuit is configured to toggle the logic state at the output of the toggle circuit in response to an edge of the enable signal.

5. The gating circuit is configured to receive a clock signal at the signal input, pass the clock signal to the output of the gating circuit when the enable signal is high, and gate the clock signal when the enable signal is low. The multiplexer is configured to select the first input when the enable signal is high and to select the second input when the enable signal is low. The apparatus according to claim 1.

6. The gating circuit receives a clock signal at the signal input and is configured to pass the clock signal to the output of the gating circuit when the enable signal is low and to gate the clock signal when the enable signal is high. The multiplexer is configured to select the first input when the enable signal is low and to select the second input when the enable signal is high. The apparatus according to claim 1.

7. The toggle circuit is a flip-flop having a data input, a clock input, and an output, wherein the clock input of the flip-flop is configured to receive the enable signal, and the output of the flip-flop is coupled to the output of the toggle circuit. an inverter coupled between the output of the flip-flop and the data input of the flip-flop. The apparatus according to claim 1, comprising.

8. The toggle circuit is a flip-flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flip-flop is configured to receive the enable signal, the first output is coupled to the output of the toggle circuit, the second output is coupled to the data input, and the first output and the second output are complementary. The apparatus according to claim 1, comprising a flip-flop.

9. The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and to output a measurement signal indicative of the measured duty cycle to the control circuit. The control circuit is configured to assert one of the set input and the reset input of the toggle circuit when the measurement signal exceeds a threshold. The apparatus according to claim 1.

10. The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and to output a measurement signal indicative of the measured duty cycle to the control circuit. When the measurement signal is below the threshold value, the control circuit is configured to assert one of the set input and the reset input of the toggle circuit. The apparatus according to claim 1.

11. The duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit. When the measurement signal exceeds a first threshold value, the control circuit is configured to assert the reset input of the toggle circuit, and when the measurement signal is below a second threshold value, the control circuit is configured to assert the set input of the toggle circuit. The apparatus according to claim 1.

12. The duty cycle monitor is configured to measure a duty cycle of a clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit. When the measurement signal exceeds a first threshold value, the control circuit is configured to assert the set input of the toggle circuit, and when the measurement signal is below a second threshold value, the control circuit is configured to assert the reset input of the toggle circuit. The apparatus according to claim 1.

13. The gating circuit is a latch having a first input, a second input, and an output, wherein the first input of the latch is coupled to the enable input of the gating circuit, and the second input of the latch is coupled to the signal input of the gating circuit; is a gate having a first input, a second input, and an output, wherein the first input of the gate is coupled to the output of the latch, the second input of the gate is coupled to the signal input of the gating circuit, and the output of the gate is coupled to the output of the gating circuit; The apparatus according to claim 1, comprising:

14. The apparatus according to claim 13, wherein the gate includes an AND gate.

15. A method performed by the apparatus according to claim 1 for balancing aging over time in a clock path, the method comprising: receiving the enable signal at the multiplexer; When the enable signal has a first logic state by the multiplexer, passing a clock signal to the clock path; When the enable signal has a second logic state by the gating circuit, gating the clock signal; Toggling the logic state of the toggle circuit in response to an edge of the enable signal by the toggle circuit; When the clock signal is gated, passing the logic state of the toggle circuit to the clock path by the multiplexer; A method comprising the above. **Claim 16** The method according to claim 15, wherein the first logic state is 1 and the second logic state is 0. **Claim 17** The method according to claim 15, wherein the first logic state is 0 and the second logic state is 1. **Claim 18** The method according to claim 15, wherein the edge of the enable signal is a rising edge. **Claim 19** The method according to claim 15, wherein the edge of the enable signal is a falling edge.

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