Semiconductor device and inspection method for semiconductor device

Abstract

To provide a semiconductor device in which the physical damage due to a probe needle can be suppressed, and an inspecting method for the semiconductor device.SOLUTION: A gate pad 22 includes only a part of a first gate metal layer 12 that is exposed to an opening part 17b of a passivation film 17. The gate pad 22 includes only the first gate metal layer 12 formed of a material with high adhesion to a bonding wire. A Rg measurement pad 24 includes a part of a second gate metal layer 14 that is exposed to an opening part 17d of the passivation film 17 and a plating film 34 covering a surface of the first gate metal layer 12. In an inspection step, a probe needle, which is a metal contact, is in contact with the plating film 34 on the outermost surface of the Rg measurement pad 24. The plating film 34 on the outermost surface of the Rg measurement pad 24 is hard to such a degree that the metal contact does not penetrate. After the inspection step of a semiconductor chip 10, the bonding wire is bonded to the gate pad 22.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for inspecting a semiconductor device.

Background Art

[0002] Regarding the wiring structure of a conventional semiconductor device, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor having an insulated gate composed of a three-layer structure of metal - oxide film - semiconductor) will be described as an example. FIG. 19 is a plan view showing the layout of a conventional semiconductor device as viewed from the front side of a semiconductor chip (semiconductor substrate).

[0003] FIG. 20 is a cross-sectional view showing the cross-sectional structure at the cut line AA - AA' in FIG. 19. FIG. 23 is a cross-sectional view showing another example of the cross-sectional structure at the cut line AA - AA' in FIG. 19. FIGS. 21 and 24 are cross-sectional views showing the states during inspection of the semiconductor chips in FIGS. 20 and 23, respectively. FIGS. 22 and 25 are cross-sectional views showing the states after mounting of the semiconductor chips in FIGS. 20 and 23, respectively. The gate runner 214 is not shown in FIGS. 20 to 25.

[0004] The conventional semiconductor device 220 shown in FIG. 19 includes a source electrode 211, a gate metal layer 212, a source pad (electrode pad) 221 including a part of the source electrode 211 (shown by a thick solid line), and a gate pad (electrode pad) 222 including a part of the gate metal layer 212 (shown by a thick solid line) on the front surface of the semiconductor chip 210 in the active region 201. The source electrode 211 and the gate metal layer 212 are made of aluminum (Al).

[0005] The source electrode 211 and the gate metal layer 212 are covered with a polyimide layer (PI: polyimide) 213 (the hatched part of the dots). The part of the source electrode 211 exposed at the opening 213a (indicated by the thick dashed line) of the polyimide layer 213 is included in the source pad 221. The part of the gate metal layer 212 exposed at the opening 213b (indicated by the thick dashed line) of the polyimide layer 213 is included in the gate pad 222.

[0006] The source pad 221 and the gate pad 222 include plating films 231 and 232 on the outermost surface. The plating films 231 and 232 are formed by laminating a nickel (Ni) plating film and a gold (Au) plating film in sequence, and have a high hardness such that the probe needles 241 and 242 (see FIG. 21), which are metal contacts, cannot penetrate when pressed against them at a predetermined pressure during screening inspection.

[0007] Also, the materials of the plating films 231 and 232 have a lower contact resistance with the probe needles 241 and 242 compared to aluminum. For this reason, a high voltage can be applied to the semiconductor chip 210 from the source pad 221 and the gate pad 222 via the probe needles 241 and 242, or a large current can be passed through. Also, the plating films 231 and 232 with high solder wettability improve the adhesion between the electrode pads and the wiring members soldered to the electrode pads.

[0008] After the inspection process in the state of the semiconductor chip 210, the semiconductor chip 210 is mounted on the circuit pattern of a mounting substrate (not shown), and pin-shaped wiring members for external connection (hereinafter referred to as terminal pins) 235 and 236 are joined to the source pad 221 and the gate pad 222 via solder layers 233 and 234, respectively (FIG. 22).

[0009] The difference between the conventional semiconductor device 220’ shown in FIG. 23 and the conventional semiconductor device 220 shown in FIGS. 19 and 20 is that the source pad 221’ and the gate pad 222’ do not include a plating film. The outermost surfaces of the source pad 221’ and the gate pad 222’ are a source electrode 211 and a gate metal layer 212 made of Al, which has high adhesion to the Al bonding wires 235’, 236’ (see FIG. 25).

[0010] On the other hand, since the contact surfaces of the source pad 221’ and the gate pad 222’ with the probe needles 241’, 242’ (see FIG. 24) are not plating films, the contact resistance with the probe needles 241, 242 is high. Reference numeral 202 denotes an edge termination region.

[0011] As a wiring structure of such a conventional semiconductor device, a structure has been proposed in which a Ni plating film and an Au plating film are sequentially provided on the surface of an Al electrode, and a lead frame is joined to the Al electrode through these plating films (see, for example, Patent Document 1 below). In Patent Document 1 below, the Ni plating film and the Au plating film ensure the reliability of the joint between the Al electrode on the surface of the semiconductor chip and the lead frame.

[0012] Also, as another wiring structure of a conventional semiconductor device, a structure has been proposed in which a source pad made of Al as a metal material is divided into a plurality of parts, and one Al wire is bonded to the surface of each source pad (see, for example, Patent Document 2 below). In Patent Document 2 below, by measuring the resistance of the conventional semiconductor device after packaging, a bonding defect of the Al wire is detected.

[0013] Also, as another wiring structure of a conventional semiconductor device, a structure has been proposed in which an electrode pad for screening inspection is provided separately from the electrode pad for bonding (see, for example, Patent Document 3 below). In Patent Document 3 below, during the screening inspection, the screening inspection is performed using the electrode pad for screening inspection, thereby preventing damage to the surface of the electrode pad for bonding that is normally used as a terminal.

[0014] Also, as another wiring structure of a conventional semiconductor device, a structure has been proposed in which an electrode pad for gate resistance measurement is provided separately from the electrode pad for bonding (see, for example, Patent Document 4 below). Patent Document 4 below discloses the connection position between the electrode pad for gate resistance measurement and the gate runner that can accurately measure the overall gate resistance (the combined resistance of the built-in gate resistance of polysilicon and the parasitic gate resistance) of the semiconductor device.

Prior Art Documents

Patent Documents

[0015]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0016] In order to apply a high voltage or pass a large current to the semiconductor chip 210 in the inspection process, it is necessary to make the outermost surface of the electrode pad a plating film. However, a general discrete component (a semiconductor component with unified specifications) or a conventional semiconductor device 220' (see FIG. 23) using Al bonding wires 235', 236' as a wiring member for external connection does not form a plating film on the outermost surface of the electrode pad.

[0017] The reason is that the adhesion between the plating film and the Al bonding wires 235’, 236’ is low, and the bonding strength of the Al bonding wires 235’, 236’ becomes weak. Also, Al, which is the electrode material, is softer than Ni or Au, which are the materials of the plating film, and is easily damaged by the probe needle at the electrode pad. When the probe needle penetrates the electrode pad and reaches the interlayer insulating film under the electrode pad, there is a risk of cracks occurring in the electrode pad.

[0018] An object of the present invention is to provide a semiconductor device and an inspection method for a semiconductor device that can suppress physical damage caused by a probe needle in order to solve the problems of the prior art described above.

Means for Solving the Problems

[0019] In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. An element structure of a semiconductor element that performs a switching operation is provided on the front surface side of a semiconductor chip. A first electrode electrically connected to the gate or base of the element structure is provided on the front surface of the semiconductor chip. A second electrode having the same potential as the first electrode is provided on the front surface of the semiconductor chip, separated from the first electrode. A protective film covers the first electrode and the second electrode. A first electrode pad is provided in a first opening of the protective film. The first electrode pad includes a portion of the first electrode that faces the first opening in the depth direction. A second electrode pad is provided in a second opening of the protective film. The second electrode pad includes at least a portion of the second electrode that faces the second opening in the depth direction and is harder than the first electrode pad. A surface electrode is provided on the back surface of the semiconductor chip. The first electrode and the second electrode are electrically connected by a resistor. The resistor is a polysilicon layer. The second electrode pad The surface area is smaller than that of the first electrode pad, has a recess on the surface metal contact and is covered with an insulator.

[0020] Further, in the semiconductor device according to this invention, in the above-described invention, the first electrode pad includes only the first electrode. The second electrode pad includes the second electrode made of the same material as the first electrode and a high-hardness metal film harder than the first electrode. and the high-hardness metal film has the recess It is characterized by this.

[0021] Further, in the semiconductor device according to this invention, in the above-described invention, the high-hardness metal film is provided on the surface of the second electrode, which is characterized.

[0022] Further, in the semiconductor device according to this invention, in the above-described invention, the first electrode is a metal film containing aluminum. The high-hardness metal film is a metal film containing gold, silver, copper, nickel, cobalt, tungsten, molybdenum, titanium or platinum, or a metal alloy film or a metal laminated film containing these metals, which is characterized.

[0023] Further, in the semiconductor device according to this invention, in the above-described invention, the first electrode is a single aluminum film or an aluminum alloy film containing silicon or copper, which is characterized.

[0026] Further, in the semiconductor device according to this invention, in the above-described invention, the semiconductor element is an insulated-gate field-effect transistor or an insulated-gate bipolar transistor, which is characterized.

[0027] Further, in the semiconductor device according to this invention, in the above-described invention, the semiconductor element is a bipolar transistor, which is characterized.

[0028] Further, in the semiconductor device according to this invention, in the above-described invention, the semiconductor chip is made of silicon carbide, which is characterized.

[0029] Also, the semiconductor device according to this invention further includes a third electrode and a third electrode pad in the above-described invention. The third electrode is electrically connected to the source or emitter of the element structure and is covered with the protective film. The third electrode pad is provided in a third opening of the protective film and includes a portion of the third electrode that faces the third opening in the depth direction. The surface of the third electrode pad includes the third electrode made of the same material as the first electrode and provided on a part of the third electrode the high-hardness metal film, and is characterized by including these. Further, the semiconductor device according to the present invention further includes a third electrode and a third electrode pad in the above-described invention. The third electrode is electrically connected to the source or emitter of the element structure and is covered with the protective film. The third electrode pad is provided in a third opening of the protective film and includes a portion of the third electrode facing the third opening in the depth direction. The surface of the third electrode pad is characterized by being made of the high-hardness metal film provided on the third electrode.

[0030] Also, the semiconductor device according to this invention, in the above-described invention, the second electrode pad by the metal contact is the semiconductor chip to at a predetermined electric impression current application for pad portion, and is characterized by this.

[0031] Also, the semiconductor device according to this invention, in the above-described invention, the second electrode pad by the metal contact is the semiconductor chip to at a predetermined current for energization pad portion, and is characterized by this.

[0032] Also, the semiconductor device according to this invention, in the above-described invention, the first electrode pad is a single wire in the form of a thin wire containing aluminum or copper -connection bonded for pad portion, and is characterized by this.

[0033] Also, the semiconductor device according to this invention, in the above-described invention, the first electrode pad has a rectangular planar shape. The second electrode pad is characterized by having a square planar shape with a smaller surface area than the surface area of the first electrode pad.

[0034] Also, in order to solve the above-described problems and achieve the object of the present invention, a method for inspecting a semiconductor device according to this invention On the front side of the semiconductor chip, there is provided an element structure of a semiconductor element that performs a switching operation, a first electrode provided on the front surface of the semiconductor chip and electrically connected to the gate or base of the element structure, a second electrode provided on the front surface of the semiconductor chip, separated from the first electrode and having the same potential as the first electrode, a protective film covering the first electrode and the second electrode, a first electrode pad provided in a first opening of the protective film and including a portion of the first electrode facing the first opening in the depth direction, a second electrode pad provided in a second opening of the protective film and including at least a portion of the second electrode facing the second opening in the depth direction, and a surface electrode provided on the back surface of the semiconductor chip. is a method for inspecting a semiconductor device and has the following characteristics. The second electrode pad is harder than the first electrode pad. The first electrode and the second electrode are electrically connected by a resistor. The resistor is a polysilicon layer. A testing step of bringing a metal contact into contact with the second electrode pad for electrical connection and applying a voltage to the semiconductor chip or passing a current through the metal contact to inspect the electrical characteristics of the element structure; and a coating step of covering the second electrode pad with an insulator after the testing step.

[0035] Further, the method for inspecting a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the inspection step, a plurality of the metal contacts are brought into contact with the second electrode pad.

[0036] Further, the method for inspecting a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the inspection step, the metal contact is brought into contact with the second electrode pad a plurality of times.

[0037] Further, the method for inspecting a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the inspection step, a current of 300 A / cm 2 or more is passed through the semiconductor chip.

[0038] Further, the method for inspecting a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the inspection step, the voltage is applied to the gate of the element structure or the current is passed through the base of the element structure via the second electrode pad for 10 minutes or more.

[0039] Further, the method for inspecting a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the inspection step, the voltage is applied to the gate of the element structure or the current is passed through the base of the element structure via the second electrode pad.

[0040] Also, in order to solve the above-described problems and achieve the object of the present invention, a method for inspecting a semiconductor device according to the present invention is a method for inspecting a semiconductor device according to the above-described invention, and has the following features. A metal contact is brought into contact with and electrically connected to a portion of the third electrode pad including the high-hardness metal film, and the electrical characteristics of the element structure are inspected by passing a current through the pn diode of the element structure via the third electrode pad in a state where no voltage is applied to the second electrode pad and no current flows from the second electrode pad. and, after the inspection step, a coating step of covering the second electrode pad with an insulator including.

Effects of the Invention

[0041] According to the semiconductor device and the method for inspecting a semiconductor device according to the present invention, since the electrode pad to be brought into contact with the probe needle includes a metal film formed of a material harder than the surface electrode layer (first and second electrodes), it is possible to suppress physical damage to the electrode pad caused by the probe needle.

Brief Description of the Drawings

[0042]

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Figure 19

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Embodiments for Carrying Out the Invention

[0043] With reference to the accompanying drawings below, preferred embodiments of a semiconductor device and a method for inspecting a semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in layers or regions preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers or regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0044] (Embodiment 1) The structure of the semiconductor device according to Embodiment 1 will be described by taking a vertical MOSFET as an example. FIG. 1 is a plan view showing the layout of the semiconductor device according to Embodiment 1 as viewed from the front side of the semiconductor chip (semiconductor substrate). FIGS. 2 and 3 are cross-sectional views showing the cross-sectional structures at the cut lines A1 - A1' in FIG. 1 and the cut line A2 - A2' in FIG. 1, respectively. FIG. 4 is a plan view showing the state during inspection of the semiconductor chip in FIG. 1. FIG. 5 is a plan view showing the state after mounting of the semiconductor chip in FIG. 1. In FIGS. 1 to 5, the passivation film (protective film) 17 is shown by dot hatching, and the plating films 31 and 34 are shown by diagonal hatching.

[0045] In FIGS. 1, 4, and 5, the front surface (top surface) electrode layers (the first and second source electrodes 11 and 13 and the first and second gate metal layers (the first and second electrodes) 12 and 14) of the semiconductor chip 10 are shown by thick solid lines, and the openings 17a to 17d of the passivation film 17 are shown by thick dashed lines (the same applies to FIGS. 6 to 9, 11, and 13). In FIGS. 2 and 3, the internal element structure (MOS gate (insulated gate composed of metal - oxide - semiconductor)) of the semiconductor chip 10, the gate runner 15, and the interlayer insulating film provided between the semiconductor chip 10 and the front - surface electrode layer of the semiconductor chip 10 are not shown (the same applies to FIGS. 10, 12, and 14).

[0046] The semiconductor device 20 according to Embodiment 1 shown in FIGS. 1 to 3 includes a plurality of electrode pads on the front surface of the semiconductor chip 10 in the active region 1. The material of the semiconductor chip 10 is, for example, silicon (Si) or silicon carbide (SiC). The semiconductor chip 10 has, for example, a substantially rectangular planar shape. The active region 1 is a region where the main current (drift current) flows when the MOSFET is in the on state. The active region 1 has, for example, a substantially rectangular planar shape and is provided at the center of the semiconductor chip 10.

[0047] In the active region 1, a plurality of unit cells (constituent units of the element: not shown) of a vertical MOSFET through which a drift current flows from the back surface to the front surface of the semiconductor chip 10 are provided. On the front - surface side of the semiconductor chip 10, general MOS gates (not shown) of each unit cell of the MOSFET are provided. An interlayer insulating film (not shown) is provided to cover the gate electrodes constituting the MOS gate over the entire front surface of the semiconductor chip 10. A drain electrode (surface electrode) 18 that also serves as a drain pad is provided over the entire back surface of the semiconductor chip 10.

[0048] Between the active region 1 and the end of the semiconductor chip 10 is the edge termination region 2. The edge termination region 2 surrounds the periphery of the active region 1 in a substantially rectangular shape. The edge termination region 2 has a function of relaxing the electric field on the front surface side of the semiconductor chip 10. In the edge termination region 2, a predetermined breakdown voltage structure (not shown), such as a field limiting ring (FLR) or a junction termination extension (JTE) structure, is arranged. The breakdown voltage is the limit voltage at which the MOSFET does not malfunction or break down.

[0049] On the front surface of the semiconductor chip 10 between the active region 1 and the breakdown voltage structure, a gate runner 15 is provided via a field oxide film (not shown). The gate runner 15 has, for example, a two-layer structure in which a gate polysilicon (poly-Si) wiring layer and a gate metal wiring layer are laminated in order, and surrounds the periphery of the active region 1 in a substantially rectangular shape. The gate polysilicon wiring layer and the gate metal wiring layer of the gate runner 15 are in contact with the entire circumference of the gate runner 15 within a contact hole that penetrates the interlayer insulating film in the depth direction. All the gate electrodes of the unit cells of the MOSFETs arranged in the active region 1 are electrically connected to the gate runner 15.

[0050] On the front surface of the semiconductor chip 10 between the gate runner 15 and a gate pad (first electrode pad) 22 described later, a built-in gate resistor 16 is provided via a field oxide film. The built-in gate resistor 16 is, for example, a single-layer gate polysilicon wiring layer. The built-in gate resistor 16 electrically connects the gate runner 15 and the gate pad 22. By the gate runner 15, the built-in gate resistor Rg2 due to the built-in gate resistor 16 and the parasitic gate resistor Rg1 due to the gate electrode of the MOSFET are connected in series (see FIG. 18). The combined resistance of the built-in gate resistor Rg2 and the parasitic gate resistor Rg1 is the overall gate resistance Rg3 of the semiconductor chip 10.

[0051] The electrode pads on the front surface of the semiconductor chip 10 include, for example, a source pad (third electrode pad) 21 including a part of the first source electrode (third electrode) 11, an OC pad 23 including a part of the second source electrode 13, a gate pad 22 including a part of the first gate metal layer 12, and an Rg measurement pad (second electrode pad) 24 for gate resistance measurement including a part of the second gate metal layer 14. The first and second source electrodes 11 and 13 and the first and second gate metal layers 12 and 14 are provided separately from each other on the interlayer insulating film on the front surface of the semiconductor chip 10 in the active region 1.

[0052] The first source electrode 11 is electrically connected to the source region and the base region that constitute the MOS gate of the main semiconductor element (see, for example, the main semiconductor element 71 in FIG. 16) in the contact hole that penetrates the interlayer insulating film in the depth direction. The main semiconductor element includes most of the unit cells of the MOSFET arranged in the active region 1. The first source electrode 11 covers substantially the entire surface of the active region 1 except for the portions where the second source electrode 13 and the first and second gate metal layers 12 and 14 are arranged.

[0053] For example, the first source electrode 11 is recessed inward (toward the center of the semiconductor chip 10) to surround three sides of a substantially rectangular planar region where the first gate metal layer 12 is arranged, and is also recessed inward to surround two sides of a substantially rectangular planar region where the second source electrode 13 and the second gate metal layer 14 are arranged, having a substantially rectangular planar shape. The first and second gate metal layers 12 and 14 and the second source electrode 13 have, for example, a substantially rectangular planar shape. The first and second gate metal layers 12 and 14 and the second source electrode 13 are provided near the boundary between the active region 1 and the edge termination region 2.

[0054] The second source electrode 13 is electrically connected to the source region and the base region that constitute the MOS gate of the current sense portion (see, for example, the current sense portion 72 in FIG. 16) within the contact hole that penetrates the interlayer insulating film in the depth direction. The current sense portion is a circuit portion for protecting the main semiconductor element, operates under the same conditions as the main semiconductor element, and has a function of detecting an overcurrent (OC: Over Current) flowing through the main semiconductor element.

[0055] The current sense portion includes a smaller number of unit cells of a part of the MOSFET arranged in the active region 1 than the main semiconductor element, and the occupied area of the active region 1 is smaller than that of the main semiconductor element. The unit cell of the current sense portion is arranged directly below the second source electrode 13. The first gate metal layer 12 is electrically connected to the gate runner 15 via the built-in gate resistor 16. The second gate metal layer 14 is electrically connected to the gate runner 15.

[0056] The surface electrode layers on the front surface of the semiconductor chip 10, such as the first and second source electrodes 11 and 13, the first and second gate metal layers 12 and 14, and the gate metal wiring layer (gate runner 15 and built-in gate resistor 16), are formed of, for example, the same material and arranged in the same layer. These surface electrode layers are metal films containing aluminum (Al) (indicated as "Al" in FIGS. 2 and 3), and may be, for example, Al alloy films containing aluminum (Al) such as aluminum silicon (AlSi), aluminum silicon copper (AlSiCu), or aluminum copper (AlCu), or pure Al films with a purity of 99.9% or more.

[0057] The first and second source electrodes 11 and 13, the first and second gate metal layers 12 and 14, the gate runner 15, and the built-in gate resistor 16 are covered with a passivation film 17. The first source electrode 11, the second source electrode 13, the first and second gate metal layers 12 and 14, the gate runner 15, and the built-in gate resistor 16 are electrically insulated from each other by the passivation film 17. The material of the passivation film 17 may be, for example, polyimide (PI), silicon nitride (SiN), or silicon oxide (SiO2), and preferably SiN and SiO2 from the viewpoint of ease of the manufacturing process when forming the source pad 21.

[0058] Openings 17a to 17d penetrating the passivation film 17 in the depth direction are provided in the same number as the number of electrode pads (here, four) on the front surface of the semiconductor chip 10. Different surface electrode layers (specifically, the first source electrode 11, the first gate metal layer 12, the second source electrode 13, and the second gate metal layer 14, respectively) on the front surface of the semiconductor chip 10 are exposed in the openings 17a to 17d of the passivation film 17. The exposure in the openings 17a to 17d of the passivation film 17 means that a part of the surface electrode layer faces the openings 17a to 17d in the depth direction Z, respectively. The openings 17a to 17d of the passivation film 17 have, for example, a substantially rectangular planar shape (which may be a rectangular shape with rounded corners).

[0059] The portion of the first source electrode 11 exposed in the opening (third opening) 17a of the passivation film 17 becomes part of the source pad 21 of the main semiconductor element. The portion of the first gate metal layer 12 exposed in the opening (first opening) 17b of the passivation film 17 becomes the gate pad 22. The gate pad 22 is an electrode pad common to the main semiconductor element and the current sense section. The portion of the second source electrode 13 exposed in the opening 17c of the passivation film 17 becomes the electrode pad (hereinafter referred to as the OC pad) 23 of the current sense section. The portion of the second gate metal layer 14 exposed in the opening (second opening) 17d of the passivation film 17 becomes part of the electrode pad (hereinafter referred to as the Rg measurement pad) 24 for measuring the gate resistance of the main semiconductor element.

[0060] The source pad 21 includes a metal film (hereinafter referred to as a high-hardness metal film) formed of a material harder than the first and second source electrodes 11 and 13. Specifically, the source pad 21 has, as the high-hardness metal film, for example, a plating film 31 with high solder wettability on the outermost surface over the entire area of the opening 17a of the passivation film 17. A probe needle 41, which is a metal contact of an inspection device (not shown), contacts the plating film 31 of the source pad 21 during inspection of the main semiconductor element (FIG. 4). The source pad 21 may have, for example, a substantially rectangular planar shape with a smaller surface area than the first source electrode 11 and a larger surface area than the other electrode pads.

[0061] The gate pad 22 has a layer structure different from that of the source pad 21 and the Rg measurement pad 24. Specifically, the gate pad 22 includes only the first gate metal layer 12 formed of a material with high adhesion to the bonding wire 52, and does not include a metal film (high-hardness metal film) formed of a material harder than the first and second gate metal layers 12 and 14. The gate runner 15 is electrically connected to the gate pad 22 via the first gate metal layer 12 and the built-in gate resistor 16. Among the active regions 1, directly below the gate pad 22 is, for example, a region that does not function as a MOSFET (see the invalid region 1b in FIG. 18), and unit cells of the MOSFET are not arranged. The gate pad 22 has a planar shape, such as a substantially square shape or a substantially rectangular shape, that is smaller than the surface area of the first gate metal layer 12.

[0062] The OC pad 23 has a layer structure different from that of the source pad 21 and the Rg measurement pad 24. Specifically, the OC pad 23 includes only the second source electrode 13 formed of a material with high adhesion to the bonding wire 53, and does not include a metal film (high-hardness metal film) formed of a material harder than the first and second source electrodes 11 and 13. A part directly below the OC pad 23 is a sense active region (see reference numeral 72a in FIGS. 15 and 16) that functions as a MOSFET constituting a current sense section. The remaining part directly below the OC pad 23 is a sense inactive region (see reference numeral 72b in FIG. 15) that does not function as a current sense section, and unit cells of the MOSFET are not arranged. The OC pad 23 has a planar shape, such as a substantially square shape, that is smaller than the surface area of the second source electrode 13 and smaller than the surface area of the gate pad 22.

[0063] The pad 24 for Rg measurement includes a metal film (high-hardness metal film) formed of a material harder than the first and second gate metal layers 12 and 14. Specifically, the pad 24 for Rg measurement has, for example, a plating film 34 on its outermost surface as the high-hardness metal film. A probe needle 42, which is a metal contact of an inspection device (not shown), contacts the plating film 34 of the pad 24 for Rg measurement during inspection (Fig. 4). Since the pad 24 for Rg measurement is not used during product operation, it is covered with an insulator (not shown) after the inspection process of the semiconductor chip 10. Immediately below the pad 24 for Rg measurement is, for example, a region that does not function as a MOSFET (see the invalid region 1b in Fig. 18), where unit cells of the MOSFET are not arranged. The pad 24 for Rg measurement has a substantially square planar shape that is smaller than the surface area of the second gate metal layer 14 and also smaller than the surface area of the gate pad 22.

[0064] "Hardness" refers to the depth (indentation depth) or area of the dent formed in the electrode pad when the electrode pad is pressed against the probe needles 41 and 42 (or even when the probe needles 41 and 42 are pushed into the electrode pad), or the load when the electrode pad is pressed against the probe needles 41 and 42 until a predetermined indentation depth is reached, which is the "indentation hardness" expressed by, and represents the difficulty of dent formation and the small amount of damage to the underlying structure (interlayer insulating film, silicon part, etc.). Preferably, "hardness" is, for example, the "Vickers hardness" expressed as the quotient obtained by dividing the load by the surface area calculated based on the diagonal of the indentation formed by pressing a square pyramid diamond against the measurement target.

[0065] That is, the source pad 21 and the pad 24 for Rg measurement include high-hardness metal films (plated films 31, 34) that are harder than the OC pad 23 and the gate pad 22. The plated films 31, 34 may be, for example, metal films containing gold (Au), silver (Ag), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), or platinum (Pt), or metal alloy films or metal laminated films containing these metals. When the plated films 31, 34 are laminated films, for example, they may be laminated films in which a plated film of a metal that is difficult to oxidize (e.g., Au) is laminated on a Ni plated film.

[0066] One or more probe needles 41, 42 contact the plated films 31, 34 according to the inspection conditions in one inspection, and the probe needles 41, 42 contact the plated films 31, 34 every time there are multiple inspections. Dents (needle marks) are left on the plated films 31, 34 by the probe needles 41, 42 according to the number of probe needles 41, 42 that have contacted and the number of times the probe needles 41, 42 have contacted, but the plated films 31, 34 are hard enough that the probe needles 41, 42 do not penetrate. Therefore, it is possible to suppress cracks from occurring in the electrode pads in the lower layer of the plated films 31, 34. Instead of the plated films 31, 34, for example, deposited films by sputtering or chemical vapor deposition (CVD: Chemical Vapor Deposition) may be used.

[0067] The inspection process is performed with the semiconductor chip 10 placed on a conductive stage (not shown) of the inspection apparatus. The source pad 21 and the pad 24 for Rg measurement are each pressed against the probe needles 41, 42 with a predetermined pressure to make contact and be electrically connected. A high voltage (e.g., 15 V or more) equal to or higher than the rated voltage is applied for a short time (e.g., 10 seconds or less) or a long time (e.g., 10 minutes or more) at a high temperature (e.g., about 150 °C or more) between the pad 24 for Rg measurement and the source pad 21 (gate-source) via the probe needles 41, 42, and a high electric field is applied to the gate insulating film of the main semiconductor element to evaluate the reliability of the gate insulating film.

[0068] In the screening test, the source pad 21 is pressed against the probe needle 41 with a predetermined pressure to make contact and be electrically connected, and the drain electrode 18 is electrically connected to the stage on which the semiconductor chip 10 is placed. In a state where a voltage is applied to the Rg measurement pad 24 (an on state in which a gate voltage equal to or higher than the gate threshold voltage is applied to the main semiconductor element), or in a state where no voltage is applied (an off state in which no gate voltage is applied to the main semiconductor element), a high temperature (e.g., about 100 °C or higher) and a large current (e.g., about 50 A / cm 2 or more) are passed through between the source and the drain via the probe needle 41 and the stage for a short time (e.g., about 10 seconds or less) or a long time (e.g., about 10 minutes or more) to calculate the amount of change over time in various characteristics of the MOSFET (e.g., on-resistance, gate threshold voltage, leakage current, breakdown voltage).

[0069] Also, since the Rg measurement pad 24 is connected to the gate runner 15, a built-in gate resistance Rg2 due to the built-in gate resistor 16 is connected in series between the Rg measurement pad 24 and the gate pad 22. Therefore, by increasing the resistance value of the built-in gate resistance Rg2 due to the built-in gate resistor 16 to such an extent that the parasitic gate resistance Rg1 due to the gate electrode can be ignored, the resistance value of the built-in gate resistance Rg2 can be regarded as the resistance value of the overall gate resistance Rg3 of the main semiconductor element. Therefore, by measuring the resistance value of the built-in gate resistance Rg2 due to the built-in gate resistor 16, it becomes possible to select the semiconductor chip 10 in which the overall gate resistance Rg3 of the main semiconductor element has a predetermined resistance value.

[0070] In gate resistance measurement, the gate pad 22 and the pad 24 for Rg measurement are each pressed against a probe needle (not shown) with a predetermined pressure to make contact and are electrically connected. A voltage is applied to the gate polysilicon wiring layer (a part of the gate runner 15 and the built-in gate resistor 16) between the gate pad 22 and the pad 24 for Rg measurement via the probe needle. The resistance value of the built-in gate resistor Rg2 can be calculated from the applied voltage at this time and the current value flowing through the gate polysilicon wiring layer between the gate pad 22 and the pad 24 for Rg measurement. Since the gate resistance measurement is performed at room temperature (for example, about 25°C) with a low voltage and a small current, even if the gate pad 22 does not include a plating film, the adverse effect on the gate pad 22 due to contact with the probe is small.

[0071] Therefore, inspections such as gate resistance measurement that are at room temperature with a low voltage and a small current are performed using the gate pad 22. Inspections such as screening inspections that are at a high temperature with a high voltage and a large current, where the probe mark becomes large and the adverse effect on the gate pad 22 becomes large when the probe contacts the gate pad 22, are performed using the pad 24 for Rg measurement.

[0072] After the inspection process, the semiconductor chip 10 is mounted and sealed on the circuit pattern of a mounting substrate (not shown) by a general assembly process. As shown in FIGS. 5(b) and 5(c), on the plating film 31 on the outermost surface of the source pad 21 of the semiconductor chip 10, a lead (conductor) 51 or a terminal pin (not shown) wider than the bonding wire (fine metal wire) is soldered so as to contact substantially the entire surface of the plating film 31 (not shown in FIG. 5(a)). As shown in FIG. 5(a), a bonding wire 52 is wire-bonded (ultrasonic bonding) to the first gate metal layer 12 on the outermost surface of the gate pad 22 of the semiconductor chip 10, and a bonding wire 53 is wire-bonded to the second source electrode 13 on the outermost surface of the OC pad 23.

[0073] One bonding wire 52, 53 is respectively bonded to the gate pad 22 and the OC pad 23. The source pad 21, the gate pad 22, and the OC pad 23 are electrically connected to the circuit pattern of the mounting substrate through the leads 51 and the bonding wires 52, 53, respectively. The leads 51 and the bonding wires 52, 53 may contain, for example, an Al alloy or a Cu alloy such as AlSi, AlSiCu, or AlCu, or may contain pure Al or pure Cu with a purity of 99.9% or more. Further, the above-described inspection process may be performed in the state of the semiconductor wafer.

[0074] Another example of the semiconductor device according to Embodiment 1 will be described. FIGS. 6 to 8 are plan views showing the layout of another example of the semiconductor device according to Embodiment 1 as viewed from the front side of the semiconductor chip. In FIGS. 6 to 8, the passivation film 17 is indicated by dot hatching. In FIG. 6, the plating films 33, 34 are indicated by diagonal hatching. In FIG. 7, the plating films 31, 34 are indicated by diagonal hatching. In FIG. 8, the plating film 33 is indicated by diagonal hatching. Also in the semiconductor devices 20a to 20c according to Embodiment 1 shown in FIGS. 6 to 8, similar to the semiconductor device 20 according to Embodiment 1 shown in FIG. 1, the inspection process is performed by pressing the electrode pad including the plating film against the probe needle.

[0075] In the semiconductor device 20a according to Embodiment 1 shown in FIG. 6, the layer structures of the source pad 21' and the OC pad 23' are different from those of the semiconductor device 20 according to Embodiment 1 shown in FIG. 1. The source pad 21' includes only the first source electrode 11 and does not include a plating film. A bonding wire (not shown) is wire-bonded to the first source electrode 11 on the outermost surface of the source pad 21' after the inspection process of the semiconductor chip 10. Since the outermost surface of the source pad 21' does not include a plating film with low adhesion to the bonding wire, the adhesion between the source pad 21' and the bonding wire can be increased. The OC pad 23' includes a metal film formed of a material harder than the second source electrode 13.

[0076] Specifically, the OC pad 23' has, for example, a plating film 33 on its outermost surface as a metal film formed of a material harder than the second source electrode 13. By bringing a probe needle (not shown) into contact with the plating film 33 of the OC pad 23', screening inspection of the current sense section and gate resistance measurement can be performed. After the inspection process of the semiconductor chip 10, a bonding wire is joined to the plating film 33 on the outermost surface of the OC pad 23'. However, the surface area of the OC pad 23' is smaller than the surface area of the source pad 21. Therefore, the adverse effect on the reliability of the bonding between the plating film 33 and the bonding wire is limited compared to the adverse effect on the reliability of the bonding between the plating film and the bonding wire on the outermost surface of the source pad 21.

[0077] The difference between the semiconductor device 20b according to the first embodiment shown in FIG. 7 and the semiconductor device 20 according to the first embodiment shown in FIG. 1 is that the semiconductor device 20b does not include a current sense section. The semiconductor device 20b according to the first embodiment shown in FIG. 7 has plating films 31 and 34 on the outermost surfaces of the source pad 21 and the Rg measurement pad 24, respectively. Therefore, similar to the semiconductor device 20 according to the first embodiment shown in FIG. 1, inspection processes such as screening inspection of the main semiconductor element and gate resistance measurement can be performed. The semiconductor device 20b according to the first embodiment shown in FIG. 7 may increase the number of unit cells of the main semiconductor element and increase the surface area of the first source electrode 11' by the remaining area (surface area) due to not arranging the current sense section.

[0078] The difference between the semiconductor device 20c according to the first embodiment shown in FIG. 8 and the semiconductor device 20a according to the first embodiment shown in FIG. 6 is that the semiconductor device 20c does not include the Rg measurement pad 24. The semiconductor device 20c according to the first embodiment shown in FIG. 8 has a plating film 33 on the surface area of the OC pad 23'. Therefore, similar to the semiconductor device 20a according to the first embodiment shown in FIG. 6, screening inspection of the current sense section can be performed. The semiconductor device 20c according to the first embodiment shown in FIG. 8 may increase the surface area of the first source electrode 11' by the remaining area (surface area) due to not arranging the Rg measurement pad 24.

[0079] As described above, according to Embodiment 1, since the electrode pad brought into contact with the probe needle includes a metal film formed of a material harder than the surface electrode layer (the first and second source electrodes and the second gate metal layer), physical damage to the electrode pad by the probe needle can be suppressed. Thereby, it is possible to prevent the probe needle from piercing through the electrode pad and reaching the interlayer insulating film under the electrode pad, and it is possible to suppress the occurrence of cracks in the electrode pad.

[0080] Also, according to Embodiment 1, the plating film of the electrode pad in contact with the probe needle has a low contact resistance with the probe needle, and a large current can flow through the semiconductor chip during the inspection process. Therefore, it is possible to prevent defective chips from flowing out in products with a specification allowing a large current to flow. Further, according to Embodiment 1, since the gate pad to which the bonding wire is joined does not include a plating film, the reliability of the bonding between the gate pad and the bonding wire can be ensured.

[0081] (Embodiment 2) Next, the structure of the semiconductor device according to Embodiment 2 will be described. FIG. 9 is a plan view showing the layout of the semiconductor device according to Embodiment 2 as viewed from the front side of the semiconductor chip. FIG. 11 is a plan view showing the state of the semiconductor chip in FIG. 9 during the screening inspection. FIG. 13 is a plan view showing the state of the semiconductor chip in FIG. 9 after mounting. FIGS. 10, 12, and 14 are cross-sectional views showing the cross-sectional structures along the cutting lines A3 - A3', A4 - A4', and A5 - A5' of FIG. 9, FIG. 11, and FIG. 13, respectively. In FIGS. 9 to 14, the passivation film 17 is shown by dot hatching, and the plating films 62 and 34 are shown by diagonal hatching.

[0082] The semiconductor device 60 according to Embodiment 2 is different from the semiconductor device 20 (see FIGS. 1 to 5) according to Embodiment 1 in that a part (hereinafter referred to as the first part) 61a of the source pad (third electrode pad) 61 includes a metal film (high-hardness metal film) formed of a material harder than the first source electrode 11. Specifically, the first part 61a of the source pad 61 has, as a metal film formed of a material harder than the first source electrode 11, for example, a plating film 62 having the same configuration as the plating film 31 of Embodiment 1 on the entire outermost surface of the first part 61a. A probe needle 43, which is a metal contact of an inspection device, contacts the plating film 62 on the first part 61a of the source pad 61 (FIGS. 11 and 12).

[0083] A part (hereinafter referred to as the second part) 61b of the source pad 61 other than the first part 61a has a layer structure different from that of the first part 61a of the source pad 61. Specifically, the second part 61b of the source pad 61 includes only the first source electrode 11 formed of a material having high adhesion to the bonding wire 54, and does not include a metal film formed of a material harder than the first source electrode 11. The bonding wire 54 is wire-bonded to the second part 61b of the source pad 61 after the inspection process of the semiconductor chip 10 (FIGS. 13 and 14).

[0084] The first and second parts 61a and 61b of the source pad 61 are arranged adjacent to each other and electrically connected to each other through one opening 17e of the passivation film 17, and are not separated by the passivation film 17. That is, the source pad 61 has a structure in which two metal layers (first and second parts 61a and 61b) having different layer structures are adjacent to each other and electrically connected to each other in a direction parallel to the front surface of the semiconductor chip 10 (the second direction Y in FIG. 9) in one opening 17e of the passivation film 17.

[0085] The plating film 62 of the first portion 61a of the source pad 61 is preferably arranged symmetrically in at least one direction parallel to the front surface of the semiconductor chip 10 with respect to the center of the semiconductor chip 10 within one opening 17e of the passivation film 17 (symmetrically shown in the first direction X in FIG. 9). By arranging the plating film 62 symmetrically in at least one direction parallel to the front surface of the semiconductor chip 10, the imbalance of the current flowing in the plane of the semiconductor chip 10 can be eliminated, which is particularly useful when a large current flows through the semiconductor chip 10.

[0086] The source pad 61 only needs to satisfy the above conditions, and its planar shape (that is, the planar shape of the opening 17e of the passivation film 17) can be variously changed. FIG. 9 shows a source pad 61 having a substantially C-shaped planar shape formed by one first portion 61a extending in a direction (first direction X) parallel to the front surface of the semiconductor chip 10 and two second portions 61b respectively connected to both ends of the first portion 61a and extending in a direction parallel to the front surface of the semiconductor chip 10 and in a second direction Y orthogonal to the first direction X.

[0087] As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Further, according to the second embodiment, the source pad exposed in one opening of the passivation film has first and second portions having different layer structures configured according to the purpose. Therefore, one source pad can be used for two or more means with different purposes in an optimal state respectively.

[0088] (Embodiment 3) Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 15 is a plan view showing the layout of the semiconductor device according to the third embodiment as viewed from the front surface side of the semiconductor chip. FIG. 16 is a cross-sectional view showing the cross-sectional structure taken along the cutting line B - B' in FIG. 15. The difference between the semiconductor device 70 according to the third embodiment and the semiconductor device 20 (see FIG. 1) according to the first embodiment is that the same semiconductor chip 110 as the main semiconductor element 71 is provided with a plurality of circuit portions for protecting and controlling the main semiconductor element 71.

[0089] In Embodiment 3, for example, in the same semiconductor chip 110 as the main semiconductor element 71, as a circuit section for protecting and controlling the main semiconductor element 71, in addition to the current sense section 72, for example, a high - function section such as a temperature sense section (not shown), an over - voltage protection section (not shown), and an arithmetic circuit section (not shown) is provided. The main semiconductor element 71 is, for example, a vertical MOSFET having a trench - gate structure, and is composed of a plurality of unit cells arranged adjacent to each other and connected in parallel to perform a main operation.

[0090] The main semiconductor element 71 is disposed in the effective region (hereinafter referred to as the main effective region) 81a of the active region 81. The main effective region 81a is a region where the main current (drift current) of the main semiconductor element 71 flows in a direction from the back surface to the front surface of the semiconductor chip 110 (the direction opposite to the depth direction Z) when the main semiconductor element 71 is turned on. The main effective region 81a has, for example, a substantially rectangular planar shape and occupies most of the surface area of the active region 81. Three sides of the substantially rectangular planar main effective region 81a are adjacent to an edge termination region 82 described later.

[0091] The circuit section for protecting and controlling the main semiconductor element 71 is, for example, a high - function section such as a current sense section 72, a temperature sense section 73, an over - voltage protection section (not shown), and an arithmetic circuit section (not shown), and is disposed in the main ineffective region 81b of the active region 81. The main ineffective region 81b is a region where the unit cells of the main semiconductor element 71 are not disposed and does not function as the main semiconductor element 71. The main ineffective region 81b has, for example, a substantially rectangular planar shape and is disposed between the remaining one side of the substantially rectangular planar main effective region 81a and the edge termination region 82.

[0092] In the edge termination region 82, a gate runner (see reference numeral 15 in FIG. 1) and a breakdown voltage structure are arranged in the same manner as in the first embodiment. Further, in the edge termination region 82, between the region below the region where the gate runner is arranged (referred to as the gate ring region) 82a and the breakdown voltage structure, a Zener diode region 82b, a current sense source ring region 82c, and a main source ring region 82d may be provided. The Zener diode region 82b is provided adjacent to the outside of the gate ring region 82a (on the end portion (chip end portion) side of the semiconductor chip 110) and surrounds the periphery of the gate ring region 82a.

[0093] In the Zener diode region 82b, a Zener diode (not shown) made of, for example, polysilicon is arranged. The Zener diode in the Zener diode region 82b has a function of preventing an overvoltage from being applied between a third source electrode (not shown) of the current sense source ring region 82c described later and a second source electrode 127c of the current sense portion 72. The Zener diode in the Zener diode region 82b is electrically connected between the OC pad 93 and the gate pad 92 of the current sense portion 72 by a Zener diode wiring layer arranged in the short circuit regions 82e and 82f.

[0094] Further, the Zener diode in the Zener diode region 82b is electrically connected between the third source electrode of the current sense source ring region 82c and the second source electrode 127c of the current sense portion 72. The Zener diode in the Zener diode region 82b is electrically connected between the fourth source electrode of the main source ring region 82d and the first source electrode 127a of the main semiconductor element 71. Thereby, an overcurrent between the second source electrode 127c of the current sense portion 72 and the current sense source ring region 82c, and an overcurrent between the first source electrode 127a of the main semiconductor element 71 and the main source ring region 82d can be absorbed.

[0095] The current sense source ring region 82c is provided adjacent to the outside of the Zener diode region 82b and surrounds the periphery of the Zener diode region 82b. In the current sense source ring region 82c, a p-type base region (not shown) is provided in the surface region of the front surface of the semiconductor chip 110, and a third source electrode (not shown) electrically connected to the p-type base region is provided on the front surface of the semiconductor chip 110. The p-type base region of the current sense source ring region 82c is electrically connected to the p-type base region 104b of the current sense portion 72 by a Zener diode wiring layer disposed in the short circuit region 82g and is fixed to the potential (source potential) of the OC pad 93.

[0096] The main source ring region 82d is provided between the current sense source ring region 82c and the breakdown voltage structure and surrounds the periphery of the current sense source ring region 82c. In the current sense source ring region 82c, a p-type base region (not shown) is provided in the surface region of the front surface of the semiconductor chip 110, and a fourth source electrode (not shown) is provided on the front surface of the semiconductor chip 110. The p-type base region of the main source ring region 82d is electrically connected to the p-type base region 104a of the main semiconductor element 71 by a Zener diode wiring layer disposed in a short circuit region (not shown) and is fixed to the potential (source potential) of the source pad 91.

[0097] The source pad 91 of the main semiconductor element 71 is disposed on the front surface of the semiconductor chip 110 in the main active region 81a. The source pad 91 of the main semiconductor element 71 is disposed apart from the electrode pads other than the source pad 91. The source pad 91 of the main semiconductor element 71 has substantially the same planar shape as the main active region 81a and covers substantially the entire surface of the main active region 81a. The source pad 91 is composed of a part of the first source electrode 127a of the main semiconductor element 71 (the portion exposed in the opening 129a of the passivation film 129) and the outermost surface plating film 128a.

[0098] The electrode pads other than the source pad 91 are arranged apart from each other on the front surface of the semiconductor chip 110 in the main invalid region 81b. The electrode pads other than the source pad 91 are the gate pad 92 of the main semiconductor element 71, the OC pad 93 of the current sense section 72, the electrode pads (anode pad and cathode pad) 94a and 94b of the temperature sense section 73, the electrode pads of the overvoltage protection section (hereinafter referred to as OV pads: not shown), the electrode pads of the arithmetic circuit section (not shown), and the like. Similar to the first embodiment, an Rg measurement pad (see reference numeral 24 in FIG. 1) may be provided.

[0099] Similar to the first embodiment, the gate pad 92 of the main semiconductor element 71 includes only a part of the first gate metal layer 127b (the part exposed in the opening 129c of the passivation film). The OC pad 93 of the current sense section 72 includes only a part of the second source electrode 127c of the current sense section 72 (the part exposed in the opening 129b of the passivation film 129). Similar to the semiconductor device 20a according to the first embodiment shown in FIG. 6, instead of providing the plating film 128a on the source pad 91 of the main semiconductor element 71, a plating film may be provided on the outermost surface of the OC pad 93 of the current sense section 72.

[0100] The anode pad 94a and the cathode pad 94b of the temperature sense section 73 include parts of the anode electrode 127d and the cathode electrode 127e of the temperature sense section 73 (the parts exposed in the openings 129d and 129e of the passivation film), respectively. Plating films may be provided on the outermost surface of the anode pad 94a and the outermost surface of the cathode pad 94b of the temperature sense section 73, respectively. The configuration in which plating films are provided on the anode pad 94a and the cathode pad 94b of the temperature sense section 73 is useful when a high voltage is applied to the temperature sense section 73 or when a large current flows.

[0101] Regarding the OV pad of the overvoltage protection section and the electrode pad of the arithmetic circuit section, they each include only a part of the corresponding surface electrode layer containing Al (the part exposed in the opening where the passivation film is not shown). Or, the source pad 91 of the main semiconductor element 71 may not include the plating film 128a and may include only a part of the first source electrode 127a, and the OC pad 93 of the current sense section 72 may include a plating film on the outermost surface. Fig. 15 shows the source pad 91, gate pad 92, OC pad 93, anode pad 94a, and cathode pad 94b in a rectangular shape labeled as S, G, OC, A, and K respectively.

[0102] As described above, the current sense section 72 has a function of detecting an overcurrent (OC) flowing through the main semiconductor element 71. The current sense section 72 is arranged separately from the main semiconductor element 71. The unit cell of the current sense section 72 is arranged in a part of the region (hereinafter referred to as the sense effective region) 72a of the region of the semiconductor chip 110 covered by the OC pad 93. Also, among the regions of the semiconductor chip 110 covered by the OC pad 93, the region excluding the sense effective region 72a is a sense ineffective region 72b that does not function as the current sense section 72. No unit cell of the current sense section 72 is arranged in the sense ineffective region 72b.

[0103] The temperature sense section 73 has a function of detecting the temperature of the main semiconductor element 71 (semiconductor chip 110) by utilizing the temperature characteristics of the diode. The temperature sense section 73 is arranged directly below the anode pad 94a and the cathode pad 94b. The temperature sense section 73 may be, for example, a polysilicon diode (not shown) composed of a polysilicon layer provided on the interlayer insulating film 120 (see Fig. 16) on the front surface of the semiconductor chip 110, or a diffusion diode (not shown) formed by a pn junction between a p-type region and an n-type region formed inside the semiconductor chip 110.

[0104] The overvoltage protection section (not shown) is a diode that protects the main semiconductor element 71 from overvoltage (OV: Over Voltage) such as a surge. The current sense section 72, the temperature sense section 73, and the overvoltage protection section are controlled by the arithmetic circuit section. The arithmetic circuit section controls the main semiconductor element 71 based on the output signals of the current sense section 72, the temperature sense section 73, and the overvoltage protection section. The arithmetic circuit section is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit.

[0105] Next, the cross-sectional structures of the main semiconductor element 71 and the current sense section 72 will be described. The main semiconductor element 71 has a trench gate structure MOS gate composed of a p-type base region 104a, an n + -type source region 105a, a p ++ -type contact region 106a, a trench 107a, a gate insulating film 108a, and a gate electrode 109a on the front side of the semiconductor chip 110 in the main active region 81a. The semiconductor chip 110 has an n + -type starting substrate 111 made of silicon carbide, and an n - -type drift region 102 and each silicon carbide layer 112, 113 that will become the p-type base region 104a are sequentially epitaxially grown on the front surface of the starting substrate 111.

[0106] The n + -type starting substrate 111 is an n + -type drain region 101 common to the main semiconductor element 71 and the current sense section 72. The front main surface of the semiconductor chip 110 on the p-type silicon carbide layer 113 side is defined as the front surface, and the main surface on the n + -type starting substrate 111 side is defined as the back surface. Between the front surface of the semiconductor chip 110 and the p-type base region 104a, an n + -type source region 105a and a p ++ -type contact region 106a are selectively provided on the surface region of the front surface of the semiconductor chip 110. The trench 107a penetrates the n + -type source region 105a and the p-type base region 104a and reaches the n - -type drift region 102.

[0107] Inside the trench 107a, a gate electrode 109a is provided via a gate insulating film 108a. The gate electrodes 109a of all unit cells are electrically connected to the gate pad 92 (see FIG. 15). p ++ The p-type contact region 106a may not be provided. In this case, p ++ Instead of the p-type contact region 106a, a p-type base region 104a reaches the front surface of the semiconductor chip 110. Between the p-type base region 104a and the n - type drift region 102, the p-type base region 104a and the n - type drift region 102, an n-type current diffusion region 103a may be provided in contact therewith.

[0108] The n-type current diffusion region 103a is a so-called Current Spreading Layer (CSL) that reduces the spreading resistance of carriers. Also, inside the semiconductor chip 110, at a position closer to the n + type drain region 101 than the bottom surface of the trench 107a, first and second p + type high-concentration regions 114a, 115a may be selectively provided respectively. The first and second p + type high-concentration regions 114a, 115a have a function of relaxing the electric field applied to the bottom surface of the trench 107a. The interlayer insulating film 120 is provided on substantially the entire front surface of the semiconductor chip 110 and covers the gate electrode 109a in the main effective region 81a.

[0109] In the main effective region 81a, a first contact hole 120a that penetrates the interlayer insulating film 120 in the depth direction Z is provided in the interlayer insulating film 120, and the n + type source region 105a and the p ++ type contact region 106a are exposed. The ohmic electrode 121b makes ohmic contact with the semiconductor chip 110 inside the first contact hole 120a, and the n + type source region 105a, p ++It is electrically connected to the n-type contact region 106a and the p-type base region 104a. The ohmic electrode 121b is, for example, a nickel silicide (Ni_xSi_y, where x and y are integers) film.

[0110] The first source electrode 127a is composed of an ohmic electrode 121b and an Al alloy film 126a. The first source electrode 127a may have a first titanium nitride (TiN) film 122a, a first titanium (Ti) film 123a, a second TiN film 124a, a second Ti film 125a, and an Al alloy film 126a that function as a barrier metal between the ohmic electrode 121b and the Al alloy film 126a. The barrier metal has a function of preventing mutual reaction between each metal film of the barrier metal or between regions facing each other with the barrier metal interposed therebetween. The first TiN film 122a covers the entire surface of the interlayer insulating film 120.

[0111] The first Ti film 123a is provided on the entire surface of the first TiN film 122a and the surface of the ohmic electrode 121a. The second TiN film 124a is provided on the entire surface of the first Ti film 123a. The second Ti film 125a is provided on the entire surface of the second TiN film 124a. An Al alloy film 126a is provided on the entire surface of the second Ti film 125a. An Al film may be provided instead of the Al alloy film 126a. A plating film 128a is provided on the surface of the Al alloy film 126a. The passivation film 129 covers a portion of the first source electrode 127a other than the portion constituting the source pad 91.

[0112] The drain electrode 130 makes ohmic contact with the entire back surface (the back surface of the n-type starting substrate 111) of the semiconductor chip 110. On the drain electrode 130, for example, a drain pad (electrode pad: not shown) having a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order is provided. The drain pad is soldered to a metal base plate (not shown) formed of, for example, a copper (Cu) foil of an insulating substrate, and at least a part of the drain pad is in contact with the base portion of a cooling fin (not shown) via the metal base plate. +

[0113] ​The current sense section 72 includes a p-type base region 104b, an n + type source region 105b, a p ++ type contact region 106b, a trench 107b, a gate insulating film 108b, a gate electrode 109b, and an interlayer insulating film 120, having the same configuration as the corresponding parts of the main semiconductor element 71. Each part of the MOS gate of the current sense section 72 is provided in the sense active region 72a of the main inactive region 81b. The p-type base region 104b is separated from the p-type base region 104a of the main semiconductor element 71 by an n - type drift region 102 reaching the front surface of the semiconductor chip 110 by a pn junction.

[0114] The p-type base region 104b extends, for example, from the sense active region 72a to substantially the entire area of the main inactive region 81b. The current sense section 72 may have an n-type current diffusion region 103b and first and second p + type high-concentration regions 114b, 115b, similar to the main semiconductor element 71. The p ++ type contact region 106b may not be provided. In this case, similar to the main semiconductor element 71, instead of the p ++ type contact region 106b, the p-type base region 104b reaches the front surface of the semiconductor chip 110. The gate electrodes 109b of all unit cells are electrically connected to the gate pad 92 (see FIG. 15).

[0115] The interlayer insulating film 120 covers the gate electrode 109b. In the sense active region 72a, a second contact hole 120b penetrating the interlayer insulating film 120 in the depth direction Z is provided in the interlayer insulating film 120, and the n + type source region 105b and the p ++ type contact region 106b are exposed. A second source electrode 127c is provided with the same laminated structure as the first source electrode 127a of the main semiconductor element 71 so as to fill the second contact hole 120b. Reference numerals 121b to 126b are an ohmic electrode, a first TiN film, a first Ti film, a second TiN film, a second Ti film, and an Al alloy film constituting the second source electrode 127c, respectively.

[0116] The ohmic electrode 121b makes ohmic contact with the semiconductor chip 110 inside the second contact hole 120b, and is electrically connected to the n + -type source region 105b, p ++ -type contact region 106b and the p-type base region 104b. When the p ++ -type contact region 106b is not provided, instead of the p ++ -type contact region 106b, the p-type base region 104b is exposed to the second contact hole 120b and is electrically connected to the ohmic electrode 121b. Only the portion of the second source electrode 127c that is exposed to the opening 129c of the passivation film 129 constitutes the OC pad 93.

[0117] Although not shown in the figure, the p-type base region of the current sense source ring region 82c is separated from the p-type base regions 104a and 104b and is formed, for example, simultaneously with the p-type base regions 104a and 104b. The third source electrode of the current sense source ring region 82c has the same laminated structure as the first and second source electrodes 127a and 127c. The p-type base region of the main source ring region 82d is separated from the p-type base region of the current sense source ring region 82c and is formed, for example, simultaneously with the p-type base regions 104a and 104b. The fourth source electrode of the main source ring region 82d has the same laminated structure as the first and second source electrodes 127a and 127c.

[0118] As described above, according to the third embodiment, even when two or more semiconductor elements are provided on the same semiconductor chip as the main semiconductor element, the same effects as those of the first and second embodiments can be obtained.

[0119] (Embodiment 4) Next, as a semiconductor device according to Embodiment 4, the overall gate resistance Rg3 of the semiconductor device 20 according to Embodiment 1 will be described. FIG. 17 is a plan view showing the layout of the semiconductor device according to Embodiment 4 as viewed from the front side of the semiconductor chip. FIG. 18 is a cross-sectional view showing the cross-sectional structure along the cutting lines C1 - C2 - C3 in FIG. 17. The semiconductor device 80 according to Embodiment 4 is different from the semiconductor device 20 (see FIG. 1) according to Embodiment 1 in that it includes a plurality of Rg measurement pads 24 for measuring the gate resistance values at different locations of the gate runner 15. Although not shown in FIG. 17, a current sense portion may be provided as in Embodiment 1.

[0120] The plurality of Rg measurement pads 24 include, as in Embodiment 1, a portion of the second gate metal layer 14 exposed at the openings (17d, 17e) of the passivation film 17 and the outermost plating film 34. Here, the case where two Rg measurement pads 24 (hereinafter referred to as the first and second Rg measurement pads 24a and 24b) are arranged on the semiconductor chip 10 will be described as an example. In FIG. 17, each part (the second gate metal layer 14, the plating film 34) constituting the first and second Rg measurement pads 24a and 24b is shown with "a" and "b" appended to the end of the reference numeral. The reference numerals 17d and 17e are openings in the passivation film 17 that expose a part of the first and second gate metal layers 14a and 14b, respectively.

[0121] The first and second Rg measurement pads 24a and 24b are connected to different locations of the gate runner 15 while being separated from each other. The first Rg measurement pad 24a is connected between the connection point closest to the built-in gate resistor 16 among the connection points between the gate runner 15 and the gate electrode 133 and the connection point between the gate runner 15 and the built-in gate resistor 16. Therefore, between the first Rg measurement pad 24a and the gate pad 22, a built-in gate resistance Rg2 due to the built-in gate resistor 16 is connected in series, as in Embodiment 1. Therefore, as in Embodiment 1, by bringing the first Rg measurement pad 24a into contact with a probe needle during gate resistance measurement, the resistance value of the built-in gate resistance Rg2 can be measured.

[0122] The second Rg measurement pad 24b is connected to the gate runner 15 at a position farther from the built-in gate resistor 16 than the connection point among the connection points of the gate runner 15 and the gate electrode 133 that is farthest from the built-in gate resistor 16. Therefore, between the second Rg measurement pad 24b and the gate pad 22, the parasitic gate resistor Rg1 due to all the gate electrodes 133 and the built-in gate resistor Rg2 due to the built-in gate resistor 16 are connected in series. Therefore, by bringing the probe needle into contact with the second Rg measurement pad 24b during gate resistor measurement, the combined resistance of the built-in gate resistor Rg2 and the parasitic gate resistor Rg1 (the resistance value of the overall gate resistor Rg3 of the MOSFET) can be measured.

[0123] Specifically, the first and second Rg measurement pads 24a and 24b are arranged, for example, at different corner portions of the active region 1. The corner portions of the active region 1 are the respective vertices of the substantially rectangular planar active region 1. The first Rg measurement pad 24a is connected to the gate runner 15, for example, at the corner portion of the active region 1 closest to the built-in gate resistor 16. The second Rg measurement pad 24b is connected to the gate runner 15, for example, at the corner portion of the active region 1 farthest from the built-in gate resistor 16 and at the corner portion that shares one side with the corner portion to which the first Rg measurement pad 24a is connected. After the gate resistor measurement, the first and second Rg measurement pads 24a and 24b are covered with an insulator (not shown).

[0124] Next, the cross-sectional structure of the semiconductor device 80 according to Embodiment 4 will be described. As shown in FIG. 18, in the active region 1a of the active region 1, a MOS gate having a general trench gate structure of each unit cell of the MOSFET is provided on the front surface side of the semiconductor chip 10. The configuration of the MOS gate is the same as that of the main semiconductor element 71 (see FIG. 16) of Embodiment 3, for example. Reference numerals 131 to 134 denote a trench, a gate insulating film, a gate electrode, and an interlayer insulating film, respectively. The p-type base region, n + -type source region and p ++The illustration of the type contact region etc. is omitted. In the inactive region 1b of the active region 1, the front surface of the semiconductor chip 10 is covered with the field oxide film 135.

[0125] On the field oxide film 135, the gate electrode 133a extends from inside the trench 131a (131) arranged closest to the first Rg measurement pad 24a. The portion (hereinafter referred to as the extending portion) 133a' of this gate electrode 133a extending on the field oxide film 135 terminates at the inactive region 1b. Also, on the field oxide film 135, the built-in gate resistor 16 is provided at a distance from the extending portion 133a' of the gate electrode 133a. The built-in gate resistor 16 and the extending portion 133a' of the gate electrode 133a are covered with the interlayer insulating film 134. On the interlayer insulating film 134, the first source electrode 11 and the second gate metal layer 14a are provided.

[0126] The extending portion 133a' of the gate electrode 133a faces a part of the first source electrode 11 and a part of the second gate metal layer 14a with the interlayer insulating film 134 interposed therebetween in the depth direction. The extending portion 133a' of the gate electrode 133a is connected to the second gate metal layer 14a and fixed to the gate potential (FIG. 18), or is connected to the first source electrode 11 and fixed to the source potential. The built-in gate resistor 16 faces a part of the second gate metal layer 14a and the entire first gate metal layer 12 with the interlayer insulating film 134 interposed therebetween in the depth direction. The second gate metal layer 14a is electrically connected to the built-in gate resistor 16 in the contact hole of the interlayer insulating film 134 (FIG. 18), or is electrically connected to the built-in gate resistor 16 via the gate runner 15.

[0127] The first gate metal layer 12 is connected to the built-in gate resistor 16 within the contact hole of the interlayer insulating film 134 and is electrically connected to the second gate metal layer 14a via the built-in gate resistor 16. The gate pad 22 is formed by the portion of the first gate metal layer 12 exposed at the opening 17b of the passivation film 17. The first Rg measurement pad 24a is formed by the portion of the second gate metal layer 14a exposed at the opening 17d of the passivation film 17 and the plating film 34a on its surface. The source pad 21 is formed by the portion of the first source electrode 11 exposed at the opening 17a of the passivation film 17 and the plating film 31 on its surface.

[0128] The extending portion 133a' of the gate electrode 133a closest to the second gate metal layer 14b is also connected to the second gate metal layer 14b or the first source electrode 11 at the portion facing across the interlayer insulating film 134 in the depth direction, similar to the extending portion 133a' of the gate electrode 133a closest to the built-in gate resistor 16. The second gate metal layer 14b is electrically connected to the first gate metal layer 12 via the gate runner 15 and the built-in gate resistor 16. All the gate electrodes 133 are electrically connected to the gate runner 15 between the second gate metal layer 14b and the first gate metal layer 12. The second Rg measurement pad 24b is formed by the portion of the second gate metal layer 14b exposed at the opening 17e of the passivation film 17 and the plating film 34b on its surface.

[0129] A parasitic capacitance C1 is formed at the portion of the gate insulating film 132 along the sidewall of the trench 131 between the gate and the source of each unit cell of the MOSFET. A parasitic capacitance C2 is formed by the interlayer insulating film 134 between the extending portion 133a' of the gate electrode 133a and the source pad 21. A parasitic capacitance C3 is formed by the field oxide film 135 between the extending portion 133a' of the gate electrode 133a and the front surface of the semiconductor chip 10. A parasitic capacitance C4 is formed by the interlayer insulating film 134 and the field oxide film 135 between the first and second Rg measurement pads 24a and 24b and the front surface of the semiconductor chip 10. A parasitic capacitance C5 is formed by the field oxide film 135 between the built-in gate resistor 16 and the front surface of the semiconductor chip 10.

[0130] By adjusting the thicknesses of the interlayer insulating film 134 and the field oxide film 135, these parasitic capacitances C1 to C5 can be adjusted. By increasing the parasitic capacitances C3 and C4, the ESD (Electro Static Discharge) tolerance of the lower layer of the first and second Rg measurement pads 24a and 24b can be improved. By increasing the parasitic capacitance C5, the ESD tolerance of the lower layer of the gate pad 22 can be improved. Also, by fixing the polysilicon layer (the extending portion 133a' of the gate electrode 133a) of the lower layer of the first and second Rg measurement pads 24a and 24b to the gate potential or the source potential, the parasitic capacitances C3 and C4 can be increased. The parasitic capacitances C1 to C5 are connected in parallel between the gate pad 22 and the source pad 21. Therefore, by increasing any one of the parasitic capacitances C1 to C5, the overall parasitic capacitance formed by the interlayer insulating film 134 and the field oxide film 135 can be increased.

[0131] As described above, in the embodiment 4 according to the above, the same effects as those of the first and second embodiments can be obtained. Also, according to the embodiment 4 according to the above, between the second Rg measurement pad and the gate pad, the parasitic gate resistance due to the gate electrode and the built-in gate resistance due to the built-in gate resistor are connected in series. Therefore, by the second Rg measurement pad, the resistance value of the overall gate resistance, which is the combined resistance of the built-in gate resistance and the parasitic gate resistance, can be measured. Thereby, the accurate resistance value of the gate resistance between the gate pad and the gate electrode can be obtained, and based on the accurate resistance value of the gate resistance, the semiconductor chips can be sorted into a predetermined rank where the resistance values of the gate resistances are approximately the same. Therefore, when connecting a plurality of semiconductor chips in parallel, semiconductor chips with substantially the same switching timing can be selected and used, so that switching noise can be reduced.

[0132] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, even when a high-hardness metal film is included in the intermediate layer or the lowermost layer of the electrode pad instead of the plating film on the outermost surface of the electrode pad, the same effects as those of the present invention can be obtained. Further, instead of the MOSFET, the present invention can be applied to switching devices such as BJT (Bipolar Junction Transistor) and IGBT (Insulated Gate Bipolar Transistor). When the present invention is applied to an IGBT, the source and drain in each of the above-described embodiments may be read as the emitter and collector, respectively.

[0133] When the present invention is applied to a BJT, the source and drain in each of the above-described embodiments are read as the emitter and collector, respectively, and the gate pad (without a plating film) in each of the above-described embodiments is replaced with an electrode pad (base pad) electrically connected to the base of the BJT. In addition to this, an electrode pad having the same configuration as the Rg measurement pad (with a plating film) in each of the above-described embodiments is provided at the base potential, and a base current may be passed through the BJT by bringing a probe needle into contact with the electrode pad at the base potential. Further, as the semiconductor material of the semiconductor chip, not only Si and SiC but also a semiconductor having a wider bandgap than silicon (Si) other than SiC may be used. Further, the present invention also holds when the conductivity type (n-type, p-type) is reversed.

Industrial Applicability

[0134] As described above, the semiconductor device and the inspection method of the semiconductor device according to the present invention are useful for a switching device (a semiconductor element that performs a switching (on / off) operation) to which a high voltage is applied or a large current flows, and are particularly suitable for a semiconductor device using SIC as a semiconductor material.

Explanation of Reference Numerals

[0135] 1,81 Active region 1a Effective region of the active region 1b Inactive region of the active area 2,82 Edge termination region 10,110 Semiconductor chip 11,11',127a First source electrode 12,127b First gate metal layer 13,127c Second source electrode 14,14a,14b Second gate metal layer 15 Gate runner 16 Built-in gate resistor 17,129 Passivation film 17a~17e,129a~129e Openings in the passivation film 18,130 Drain electrode 20,20a~20c,60,70,80 Semiconductor device 21,21',61,91 Source pad 22,92 Gate pad 23,23',93 OC pad 24,24a,24b Pads for Rg measurement 31,33,34,34a,34b,62,128a Plating film 41~43 Probe needles 51 Lead 52~54 Bonding wires 61a First part of the source pad 61b Second part of the source pad 71 Main semiconductor element 72 Current sense section 72a Sense active region 72b Sense inactive region 73 Temperature sense section 81a Main active region 81b Main inactive region 82a Gate ring region 82b Zener diode region 82c Current sense source ring region 82d Main source ring region 82e~82g Short-circuit region 94a Anode pad 94b Cathode Pad 101 n + Type Drain Region 102 n - Type Drift Region 103a, 103b n-Type Current Diffusion Region 104a, 104b p-Type Base Region 105a, 105b n + Type Source Region 106a, 106b p ++ Type Contact Region 107a, 107b, 131, 131a Trench 108a, 108b, 132 Gate Insulating Film 109a, 109b, 133, 133a Gate Electrode 111 n + Type Starting Substrate 112 n - Type Silicon Carbide Layer 113 p-Type Silicon Carbide Layer 114a, 114b, 115a, 115b p + Type High-Concentration Region 120, 134 Interlayer Insulating Film 120a, 120b Contact Hole 121a, 121b Ohmic Electrode 122a, 122b First TiN Film 123a, 123b First Ti Film 124a, 124b Second TiN Film 125a, 125b Second Ti Film 126a, 126b Al Alloy Film 127d Anode Electrode 127e Cathode Electrode 133a' Extension of Gate Electrode 135 Field Oxide Film First Direction Parallel to Front Surface of X Semiconductor Chip Second Direction Parallel to Front Surface of Y Semiconductor Chip and Orthogonal to First Direction Z Depth Direction

Claims

1. The device structure of a semiconductor element that performs a switching operation, provided on the front surface side of a semiconductor chip, and a first electrode provided on the front surface of the semiconductor chip and electrically connected to the gate or base of the device structure; a second electrode provided on the front surface of the semiconductor chip, separated from the first electrode, and having the same potential as the first electrode; a protective film covering the first electrode and the second electrode; a first electrode pad provided in a first opening of the protective film and including a portion of the first electrode that faces the first opening in the depth direction; a second electrode pad provided in a second opening of the protective film, including at least a portion of the second electrode that faces the second opening in the depth direction, and being harder than the first electrode pad; a surface electrode provided on the back surface of the semiconductor chip; comprising: the first electrode and the second electrode are electrically connected by a resistor; the resistor is a polysilicon layer; the second electrode pad has a smaller surface area than the surface area of the first electrode pad, has a recess on the surface by a metal contact, and is covered with an insulator. A semiconductor device characterized by this.

2. The first electrode pad includes only the first electrode; The second electrode pad includes the second electrode made of the same material as the first electrode and a high-hardness metal film harder than the first electrode, and has the recess in the high-hardness metal film. The semiconductor device according to claim 1, characterized by this.

3. The semiconductor device according to claim 2, characterized in that the high-hardness metal film is provided on the surface of the second electrode.

4. The first electrode is a metal film containing aluminum; The high-hardness metal film is a metal film containing gold, silver, copper, nickel, cobalt, tungsten, molybdenum, titanium, or platinum, or a metal alloy film or a metal laminated film containing these metals. The semiconductor device according to claim 2 or 3, characterized by this.

5. The semiconductor device according to claim 4, characterized in that the first electrode is a single aluminum film or an aluminum alloy film containing silicon or copper.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that the semiconductor element is an insulated gate field effect transistor or an insulated gate bipolar transistor.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that the semiconductor element is a bipolar transistor. ​

8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor chip is made of silicon carbide.

9. A third electrode electrically connected to a source or an emitter of the element structure and covered with the protective film; A third electrode pad provided in a third opening of the protective film and including a portion of the third electrode facing the third opening in a depth direction; further comprising: The semiconductor device according to any one of claims 2 to 5, wherein a surface of the third electrode pad includes the third electrode made of the same material as the first electrode and the high-hardness metal film provided on a part of the third electrode.

10. A third electrode electrically connected to a source or an emitter of the element structure and covered with the protective film; A third electrode pad provided in a third opening of the protective film and including a portion of the third electrode facing the third opening in a depth direction; further comprising: The semiconductor device according to any one of claims 2 to 5, wherein a surface of the third electrode pad is made of the high-hardness metal film provided on the third electrode.

11. The semiconductor device according to claim 6, wherein the second electrode pad is a pad portion for applying a predetermined voltage to the semiconductor chip by the metal contact.

12. The semiconductor device according to claim 7, wherein the second electrode pad is a pad portion for passing a predetermined current through the semiconductor chip by the metal contact.

13. The semiconductor device according to any one of claims 1 to 12, wherein the first electrode pad is a pad portion for wire bonding of a single thin wire containing aluminum or copper.

14. The first electrode pad has a rectangular planar shape, The semiconductor device according to any one of claims 1 to 13, wherein the second electrode pad has a square planar shape with a smaller surface area than the surface area of the first electrode pad.

15. An element structure of a semiconductor element that performs a switching operation, provided on a front surface side of a semiconductor chip; A first electrode provided on the front surface of the semiconductor chip and electrically connected to a gate or a base of the element structure; A second electrode having the same potential as the first electrode, provided on the front surface of the semiconductor chip and separated from the first electrode; A protective film covering the first electrode and the second electrode; A first electrode pad provided in the first opening of the protective film and including a portion of the first electrode facing the first opening in the depth direction; A second electrode pad provided in the second opening of the protective film and including at least a portion of the second electrode facing the second opening in the depth direction; A surface electrode provided on the back surface of the semiconductor chip, and a method for inspecting a semiconductor device including the same, The second electrode pad is harder than the first electrode pad, The first electrode and the second electrode are electrically connected by a resistor, The resistor is a polysilicon layer, An inspection step of bringing a metal contact into contact with the second electrode pad for electrical connection and applying a voltage to the semiconductor chip or passing a current through the metal contact to inspect the electrical characteristics of the element structure; A covering step of covering the second electrode pad with an insulator after the inspection step; A method for inspecting a semiconductor device, comprising the steps of:

16. The method for inspecting a semiconductor device according to claim 15, wherein in the inspection step, a plurality of the metal contacts are brought into contact with the second electrode pad.

17. The method for inspecting a semiconductor device according to claim 15 or 16, wherein in the inspection step, the metal contact is brought into contact with the second electrode pad a plurality of times.

18. The method for inspecting a semiconductor device according to any one of claims 15 to 17, wherein in the inspection step, a current of 300 A / cm2 or more is passed through the semiconductor chip.

19. The method for inspecting a semiconductor device according to any one of claims 15 to 18, wherein in the inspection step, the voltage is applied to the semiconductor chip for 10 minutes or more, or the current is passed through the semiconductor chip for 10 minutes or more.

20. The method for inspecting a semiconductor device according to any one of claims 15 to 19, wherein in the inspection step, the voltage is applied to the gate of the element structure or the current is passed through the base of the element structure via the second electrode pad.

21. The method for inspecting a semiconductor device according to claim 9 or 10, A testing step of inspecting electrical characteristics of the element structure by passing a current through the pn diode of the element structure via the third electrode pad in a state where a metal contact is brought into contact with and electrically connected to a portion of the third electrode pad including the high-hardness metal film, no voltage is applied to the second electrode pad, and no current flows from the second electrode pad; A coating step of covering the second electrode pad with an insulator after the testing step; A method for inspecting a semiconductor device, comprising the above steps.

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