Method for manufacturing a semiconductor device and method for testing a semiconductor device

Abstract

To solve a problem in which a threshold voltage of a semiconductor device may deviate from a design value.SOLUTION: A semiconductor device manufacturing method includes an element forming step of forming a semiconductor element on a semiconductor substrate and forming a metal electrode on the semiconductor substrate, a plating step of plating the metal electrode, an annealing step of annealing the semiconductor substrate, a voltage applying step of applying a voltage corresponding to the thickness of a gate insulating film to the gate insulating film after the annealing step, and a determination step of measuring a threshold voltage of the semiconductor element after the voltage applying step and determining whether the semiconductor element is good or bad on the basis of the measurement result.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a method for testing a semiconductor device.

Background Art

[0002] Conventionally, a configuration for plating the surface of an electrode of a semiconductor device including a transistor has been known (see, for example, Patent Document 1). Patent Document 1 Japanese Unexamined Patent Application Publication No. 2017-157851

Summary of the Invention

Problems to be Solved by the Invention

[0003] When plating the electrode of a semiconductor device, sodium ions or the like may reach the gate insulating film, and the threshold voltage of the semiconductor device may deviate from the designed value.

Means for Solving the Problems

[0004] In a first aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include an element formation step of forming a semiconductor element including a gate insulating film on a semiconductor substrate and forming a metal electrode above the semiconductor substrate. The manufacturing method may include a plating step of plating the metal electrode. The manufacturing method may include an annealing step of annealing the semiconductor substrate. The manufacturing method may include a voltage application step of applying a voltage corresponding to the thickness of the gate insulating film to the gate insulating film after the annealing step. The manufacturing method may include a determination step of measuring the threshold voltage of the semiconductor element after the voltage application step and determining the quality of the semiconductor element based on the measurement result.

[0005] In the voltage application step, a voltage may be applied to the gate insulating film such that an electric field greater than 3.64 kV / μm is applied to the gate insulating film per unit thickness.

[0006] In the voltage application step, a voltage may be applied to the gate insulating film such that an electric field of 4.55 kV / μm or more is applied to the gate insulating film.

[0007] In the voltage application process, the voltage application time may be 10 seconds or less.

[0008] In the voltage application process, the voltage application time may be 1 second or less.

[0009] In the element formation process, a gate conductive part insulated from the semiconductor substrate by a gate insulating film may be formed, and an interlayer insulating film insulating the gate conductive part and the metal electrode may be formed. In the annealing process, the semiconductor substrate may be annealed so that the average diffusion distance of sodium in the interlayer insulating film is 70% or more of the thickness of the interlayer insulating film.

[0010] In the annealing process, the annealing temperature may be 240°C or higher and 300°C or lower.

[0011] The manufacturing method may include an assembling process of assembling a semiconductor package using a semiconductor element determined to be a good product by a determination process.

[0012] In a second aspect of the present invention, a method for testing a semiconductor device is provided. The semiconductor device may include a semiconductor substrate on which a semiconductor element including a gate insulating film is formed, and a metal electrode formed above the semiconductor substrate and having a plated upper surface. The test method may include an annealing process of annealing the semiconductor substrate in a chip or wafer state before being incorporated into a semiconductor package. The test method may include a voltage application process of applying a voltage corresponding to the thickness of the gate insulating film to the gate insulating film after the annealing process. The test method may include a determination process of measuring the threshold voltage of the semiconductor element after the voltage application process and determining the quality of the semiconductor element based on the measurement result.

[0013] The semiconductor substrate may include a gate conductive part insulated from the semiconductor substrate by a gate insulating film, and an interlayer insulating film insulating the gate conductive part and the metal electrode.

[0014] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

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Figure 8

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Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0016] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0017] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction during mounting of the semiconductor device.

[0018] In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0019] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. When described as P+-type or N+-type in this specification, it means that the doping concentration is higher than that of P-type or N-type, and when described as P--type or N--type, it means that the doping concentration is lower than that of P-type or N-type.

[0020] FIG. 1 is a cross-sectional view showing an example of the semiconductor device 100. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. In FIG. 1, only a partial region on the upper surface 21 side of the semiconductor device 100 is shown.

[0021] In the cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a metal electrode 52, and a plating layer 53. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. A contact hole 39 for exposing a part of the upper surface 21 of the semiconductor substrate 10 is provided in the interlayer insulating film 38.

[0022] The metal electrode 52 is provided above the interlayer insulating film 38. The metal electrode 52 may be formed of a metal or alloy such as aluminum. The metal electrode 52 may be formed to a thickness of 2.5 μm to 7.5 μm by a sputtering method. The metal electrode 52 is, for example, the emitter electrode in an IGBT (Insulated Gate Bipolar Transistor) or the source electrode in a MOSFET. The metal electrode 52 contacts the semiconductor substrate 10 through the contact hole 39 in the interlayer insulating film 38. A barrier metal layer such as titanium may be provided between the interlayer insulating film 38 and the semiconductor substrate 10 and the metal electrode 52. The barrier metal layer may be formed with a thickness thinner than that of the metal electrode 52. A plug electrode such as tungsten may be embedded in the contact hole 39 of the interlayer insulating film 38, and the metal electrode 52 may be provided thereon.

[0023] The semiconductor substrate 10 has an N-type emitter region 12, a P-type base region 14, and an N-type drift region 18 in order from the upper surface 21 side. The emitter region 12 and the base region 14 may be formed by locally implanting impurities into the semiconductor substrate 10. The semiconductor substrate 10 may have regions in which impurities are locally implanted in addition to these regions. Depending on the type of the semiconductor device 100, an N-type or P-type region is also provided below the drift region 18, but is omitted in FIG. 1.

[0024] One or more gate trench portions 40 are provided on the upper surface 21 of the semiconductor substrate 10. The gate trench portion 40 reaches the drift region 18 from the upper surface 21 of the semiconductor substrate 10. The emitter region 12 and the base region 14 are in contact with the side walls of the gate trench portion 40.

[0025] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of a trench (groove portion) provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench. The gate insulating film 42 in this example is a thermal oxide film obtained by oxidizing the trench inner wall. The gate conductive portion 44 is provided inside the gate insulating film 42 within the trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0026] In this example, let the thickness of the gate insulating film 42 be T1 (μm). The thickness T1 is the thickness of the gate insulating film 42 in a direction perpendicular to the inner wall of the trench. The thickness T1 may be the thickness of the gate insulating film 42 in a direction parallel to the upper surface 21 of the semiconductor substrate 10. The thickness T1 may use the average value of the thickness of the gate insulating film 42 at the portion in contact with the base region 14.

[0027] The gate conductive portion 44 is provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Thereby, the gate insulating film 42 and the gate conductive portion 44 of the gate trench portion 40 are insulated from the metal electrode 52. In this example, let the thickness of the interlayer insulating film 38 be T2 (μm). The thickness T2 is the thickness of the interlayer insulating film 38 in a direction perpendicular to the upper surface 21 of the semiconductor substrate 10. The thickness T2 may use the minimum value of the thickness of the interlayer insulating film 38 at the portion in contact with the gate insulating film 42.

[0028] The gate conductive portion 44 is electrically connected to a gate wiring (not shown) insulated from the metal electrode 52. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 in contact with the gate trench portion 40. Thereby, the semiconductor device 100 is in an on state in which current flows between the upper surface 21 and the lower surface of the semiconductor substrate 10. The gate voltage at which the semiconductor device 100 becomes an on state is referred to as a threshold voltage.

[0029] In the example of FIG. 1, a gate voltage is applied to all the gate trench portions 40. In other examples, some of the gate trench portions 40 may be connected to the metal electrode 52 without a gate voltage being applied. In this case, the gate trench portion 40 does not function as a gate for switching the transistor, but functions as a dummy gate. By arranging the dummy gate, the carrier concentration in the drift region 18 can be adjusted, and the on-resistance of the semiconductor device 100 can be adjusted.

[0030]

[0029] A plating layer 53 is provided on the metal electrode 52. The plating layer 53 is formed of a material such as gold, copper, nickel alloy, etc., and is formed of a single layer or a laminated layer. For example, when the metal electrode 52 is an alloy layer mainly composed of aluminum, first nickel alloy is plated on the metal electrode 52 with a thickness of 2.0 μm to 6.0 μm, and then gold is plated thereon with a thickness of 0.01 μm to 0.10 μm to form a laminated layer. A wiring (not shown) such as a lead frame may be soldered to the upper surface of the plating layer 53.

[0031] In the plating process for forming the plating layer 53, the upper surface of the metal electrode 52 may be immersed in a plating solution containing ions such as sodium. In the plating process, the ions contained in the plating solution may reach the semiconductor substrate 10. For example, in a process such as sputtering for forming the metal electrode 52, an unintentional through hole 37 may be formed in the metal electrode 52. If the interlayer insulating film 38 is exposed by the through hole 37, sodium ions or the like may reach the interlayer insulating film 38 through the through hole 37 and reach the semiconductor substrate 10 through the interlayer insulating film 38. Similarly, if the upper surface 21 of the semiconductor substrate 10 is exposed by the through hole 37, sodium ions or the like may reach the semiconductor substrate 10 through the through hole 37.

[0032] When sodium ions or the like that have reached the semiconductor substrate 10 are injected into the gate insulating film 42, the charged state of the gate insulating film 42 changes, so the threshold voltage may fluctuate. For example, when the semiconductor device 100 is placed in a high-temperature environment, there is a high possibility that sodium ions or the like will reach the gate insulating film 42, and the threshold voltage may fluctuate. Therefore, in the manufacturing process of the semiconductor device 100, it is preferable to screen in advance devices in which the threshold voltage is likely to fluctuate due to the influence of sodium ions or the like.

[0033] FIG. 2 is a diagram showing an outline of a manufacturing method of the semiconductor device 100. The manufacturing method may include only a part of the steps shown in FIG. 2. In this example, a plurality of semiconductor chips are formed using a semiconductor wafer. First, in an element formation step S202, a semiconductor element is formed on the semiconductor substrate 10, and a metal electrode 52 is formed above the semiconductor substrate 10. The semiconductor substrate 10 in the element formation step S202 is in a wafer form.

[0034] The semiconductor element is, for example, a MOSFET, an IGBT, or the like. In the example of FIG. 1, the semiconductor element has an emitter region 12, a base region 14, a drift region 18, and a gate trench portion 40. In the element formation step S202, the interlayer insulating film 38 shown in FIG. 1 may be formed. Also, in the element formation step S202, a metal electrode may be formed on the lower surface of the semiconductor substrate 10.

[0035] Next, in a plating step S204, the upper surface of the metal electrode 52 is plated to form a plating layer 53. In the plating step S204, the upper surface of the metal electrode 52 may be immersed in a plating solution containing ions such as sodium and a plating material such as gold, copper, or nickel alloy. In the plating step S204, the plating layer 53 may be formed by electroless plating or the like.

[0036] Next, in the dicing step S206, the semiconductor wafer is diced to cut out a plurality of semiconductor chips. The dicing step S206 may include a step of attaching a dicing tape to the semiconductor wafer before dicing so that the plurality of semiconductor chips do not become separated.

[0037] Next, in the test step S208, each chip-shaped semiconductor device 100 is tested. The test step S208 in this example tests the threshold voltage of the semiconductor device 100 by means of an annealing step S210, a voltage application step S212, and a determination step S214. The test step S208 may also test the semiconductor device 100 for items other than the threshold voltage test. In the test step S208, each semiconductor device 100 is sorted into good products and defective products.

[0038] In the annealing step S210, the semiconductor substrate 10 is annealed. In the annealing step S210, the semiconductor device 100 may be placed in an annealing furnace or the like to anneal the entire semiconductor device 100. In the annealing step S210, it is preferable to anneal the semiconductor device 100 under conditions such that at least a part of the sodium ions incorporated in the upper surface of the interlayer insulating film 38 can pass through the interlayer insulating film 38 in the thickness direction. As an example, the annealing temperature in the annealing step S210 is 240°C or higher and 300°C or lower.

[0039] Next, in the voltage application step S212, a predetermined voltage is applied to the gate insulating film 42. In the voltage application step S212, a predetermined voltage is applied to the gate conductive portion 44 via the gate wiring. The potential of the upper surface 21 of the semiconductor substrate 10 may be the same as the potential of the metal electrode 52. The potential of the metal electrode 52 may be, for example, the ground potential.

[0040] In the voltage application step S212, by applying a predetermined voltage to the gate insulating film 42, sodium ions and the like present in the vicinity of the gate insulating film 42 are attracted to the gate insulating film 42. The polarity of the voltage applied to the gate conductive portion 44 is opposite to the polarity of the ions attracted to the gate insulating film 42. In this example, since sodium ions, which are positive ions, are attracted, a negative voltage is applied to the gate conductive portion 44.

[0041] Also, in the voltage application step S212, it is preferable to apply a voltage corresponding to the film thickness T1 of the gate insulating film 42 to the gate insulating film 42 (or the gate conductive portion 44) so that sodium ions can be incorporated into the gate insulating film 42. In the voltage application step S212 of this example, a negative voltage such that an electric field greater than 3.64 kV / μm is applied to the gate conductive portion 44 with respect to the unit thickness of the gate insulating film 42. Thereby, the influence of the threshold voltage due to sodium ions and the like can be made apparent.

[0042] Next, in the determination step S214, the threshold voltage of the semiconductor element (in this example, the semiconductor device 100) is measured, and the quality of the semiconductor element is determined based on the measurement result. In the determination step S214, the quality of each semiconductor device 100 may be determined by comparing the measured threshold voltage with a preset reference value.

[0043] Next, in the assembly step S216, a semiconductor package is assembled using the semiconductor device 100 determined to be a good product. The semiconductor package may be a semiconductor module including a control circuit that controls the semiconductor device 100 in addition to the semiconductor device 100. The semiconductor module may include a resin case that houses the semiconductor device 100 and the control circuit.

[0044] Next, in the package test step S218, the semiconductor package is tested. The semiconductor package test step S218 may include items for testing the operation of the semiconductor device 100. According to this example, the semiconductor package is assembled using the semiconductor device 100 that passed the threshold voltage test. Therefore, the semiconductor packages determined to be defective in the package test step S218 can be reduced, and the overall manufacturing cost can be reduced.

[0045] In the manufacturing method of this example, before the package assembly step S216, the semiconductor device 100 is annealed and tested. The package test step S218 may not include a test item of heating the semiconductor package or the semiconductor device 100 to 100°C or higher. The semiconductor package may be a semiconductor discrete in addition to the semiconductor module.

[0046] FIG. 3 is a diagram showing an example of voltage-current characteristics measured in the determination step S214. In FIG. 3, the characteristics of one semiconductor device 100 are shown by one line. In the determination step S214, the gate voltage Vge applied to the gate conduction part 44 of the semiconductor device 100 is changed, and the main current Ic flowing through the semiconductor device 100 is measured. The main current Ic is, for example, the collector current of an IGBT or the drain current of a MOSFET.

[0047] The threshold voltage is the gate voltage Vge at which the main current Ic starts to flow. As shown in the defective product group in FIG. 3, when sodium ions are implanted into the gate insulating film 42, the main current Ic starts to flow at a low gate voltage Vge. In the determination step S214, the threshold voltage of each semiconductor device 100 may be calculated by measuring the voltage-current characteristics as shown in FIG. 3.

[0048] FIG. 4 is a diagram for explaining the conditions in the voltage application step S212. In this example, while a plurality of semiconductor devices 100 were at 175° C., an electric field was applied to the gate insulating film 42. Also, the applied electric field was changed, and an experiment was conducted to determine whether a defect could be detected in the determination step S214 when each electric field was applied. The conditions under which a defect could be detected in the determination step S214 when the application time of the electric field was 0.2 seconds are indicated by circles in the determination column. Also, under the conditions marked with a cross in the determination column, even when the application time of the electric field was 15 minutes, a defect could not be detected in the determination step S214.

[0049] As shown in FIG. 4, in the example where an electric field of 3.64 [kV / μm] was applied to the gate insulating film 42, the semiconductor device 100 could not be screened in the determination step S214. On the other hand, in the example where an electric field greater than 3.64 [kV / μm] was applied, the semiconductor device 100 could be screened in the determination step S214. In the voltage application step S212, it is preferable to apply a voltage to the gate insulating film 42 such that an electric field greater than 3.64 [kV / μm] is applied to the unit thickness of the gate insulating film 42. In the voltage application step S212, a voltage may be applied to the gate insulating film 42 such that an electric field of 4.55 [kV / μm] or more is applied to the unit thickness of the gate insulating film 42. As an example, when the thickness T1 of the gate insulating film 42 is 110 nm, the voltage Vge applied to the gate insulating film 42 may be -50 V or more.

[0050] In the voltage application step S212, the temperature of the semiconductor device 100 may be 100° C. or higher and 250° C. or lower. The temperature may be 150° C. or higher. The temperature may be 200° C. or lower. In the voltage application step S212, the higher the temperature, the smaller the applied electric field may be.

[0051] In the voltage application step S212, the application time of the voltage may be 10 seconds or less. As described above, by setting an appropriate electric field, the semiconductor device 100 can be screened with a short application time. Thereby, the manufacturing efficiency can be improved. The application time of the voltage may be 1 second or less. The application time of the voltage may be 0.1 second or more and may be 0.2 second or more.

[0052] Also, in the annealing step S210, the semiconductor substrate 10 may be annealed so that the average diffusion distance of sodium ions in the interlayer insulating film 38 is 70% or more of the thickness T2 of the interlayer insulating film 38. Thereby, it becomes easier to diffuse the sodium ions incorporated in the interlayer insulating film 38 to the semiconductor substrate 10. In the annealing step S210, the semiconductor substrate 10 may be annealed so that the average diffusion distance is 85% or more of the thickness T2 of the interlayer insulating film 38, or the semiconductor substrate 10 may be annealed so that the average diffusion distance is 100% or more.

[0053] FIG. 5 is a diagram showing the average diffusion distance of sodium ions in the interlayer insulating film 38. The average diffusion distance x ave [cm 2 is given by the following equation. x ave = 2×(Dt) 0.5 D = D0exp(-Q / kT) However, t is time [s], D is the diffusion coefficient [cm 2 / s], D0 is the diffusion constant [cm 2 / s], Q is the activation energy [eV], k is the Boltzmann constant, and T is the absolute temperature [K]. For the diffusion constant D0 and the activation energy Q, constants of the target ions are used. The target ions in this example are sodium ions, and D0 = 3.4×10 -2 cm 2 / s, Q = 1.22 eV.

[0054] In the example of FIG. 5, the thickness T2 of the interlayer insulating film 38 is 1 μm. In this case, the average diffusion distance x aveIt is preferable to adjust at least one of the annealing temperature and the annealing time of the semiconductor substrate 10 so that it becomes 0.7 μm or more. The annealing temperature may be 240°C or higher and 300°C or lower. Also, the annealing temperature may be 260°C or higher, or may be 280°C or higher. By increasing the annealing temperature, the annealing time can be shortened and the manufacturing efficiency can be improved. Also, by setting the annealing temperature to 300°C or lower, cracking of the metal electrode 52 or the like can be prevented. The annealing temperature may be 290°C or lower.

[0055] FIG. 6 is a diagram showing an example of annealing conditions in the annealing step S210. The thickness T2 of the interlayer insulating film 38 in this example is 1 μm. In the determination column in FIG. 6, a circle indicates the case where the semiconductor device 100 could be screened in the determination step S214, and a cross indicates the case where it could not be screened. In the determination step S214, the application time of the electric field was 0.2 seconds, and the electric field applied to the gate insulating film 42 was 4.55 [kV / μm].

[0056] As shown in FIG. 6, the boundary between the case where screening is possible and the case where it is not possible is the condition of an annealing temperature of 260°C and an annealing time of 4 h. Referring to FIG. 5, the average diffusion distance of sodium ions under this condition is about 70% of the thickness T2 of the interlayer insulating film 38. As described above, in the annealing step S210, the annealing conditions may be set so that the ratio of the average diffusion distance of sodium ions in the interlayer insulating film 38 to the thickness T2 of the interlayer insulating film 38 is 70% or more, the annealing conditions may be set so that the ratio is 85% or more, or the annealing conditions may be set so that the ratio is 100% or more.

[0057] FIG. 7 is a diagram showing an example of the gate voltage - main current characteristics of the semiconductor device 100. In FIG. 7, the characteristics of the non - defective semiconductor device 100 are shown. In the characteristics of the non - defective semiconductor device 100, the voltage at which a line obtained by extending the rising waveform of the current (the broken line in FIG. 7) intersects the horizontal axis (Vge) is defined as the reference threshold voltage Vth. The reference threshold voltage Vth may use a predetermined value such as the design value of the semiconductor device 100. The range from the reference threshold voltage Vth to 0 V is defined as the low - current range.

[0058] In the determination step S214, the gate voltage Vge may be changed within the low - current range to measure the threshold voltage of each semiconductor device 100. By the annealing step S210 and the voltage application step S212, the threshold voltage of the defective semiconductor device 100 changes within the low - current range. By measuring the threshold voltage within this range, threshold fluctuations due to sodium ions or the like can be efficiently detected.

[0059] FIG. 8 is a diagram showing another example of the manufacturing method of the semiconductor device 100. In the manufacturing method of this example, a test step S208 is performed after the plating step S204 and before the dicing step S206. That is, in the test step S208, the semiconductor device 100 in the wafer state is tested. The content of each step is the same as that in the example of FIG. 2.

[0060] In the test step S208, a plurality of semiconductor devices 100 in the semiconductor wafer may be tested in parallel. In the annealing step S210, by putting the semiconductor wafer into an annealing furnace, a plurality of semiconductor devices 100 can be annealed simultaneously.

[0061] In the voltage application step S212 and the determination step S214, electrical tests can be performed on a plurality of semiconductor devices 100 in parallel by bringing probe pins into contact with the respective semiconductor devices 100. In this example, since a plurality of semiconductor devices 100 can be processed in parallel, even if the voltage application time in the voltage application step S212 is lengthened, the test time will not become so long. The voltage application time in this example may be 20 minutes or less, may be 10 minutes or less, may be 5 minutes or less, or may be 1 minute or less. By lengthening the voltage application time, the influence on the threshold voltage such as sodium ions can be made apparent.

[0062] FIG. 9 is a circuit diagram showing an example of a circuit 200 provided in a resin case of a semiconductor module. The circuit 200 is a circuit that supplies power to a load such as a motor. The semiconductor module may include a plurality of circuits 200. For example, the semiconductor module may be a three-phase inverter including three sets of circuits 200.

[0063] The circuit 200 includes one or more of the semiconductor devices 100 described with reference to FIGS. 1 to 8. In the example of FIG. 9, the circuit 200 includes four semiconductor devices 100. As shown in FIG. 9, the semiconductor device 100-1 and the semiconductor device 100-2 are connected in parallel to form the upper arm of the inverter. The semiconductor device 100-3 and the semiconductor device 100-4 are connected in parallel to form the lower arm of the inverter. The upper arm and the lower arm are connected in series.

[0064] The circuit 200 may include a gate terminal G, a P terminal, an N terminal, and an output terminal. An external power supply is connected to the P terminal and the N terminal. A gate voltage for controlling each semiconductor device 100 is input to the gate terminal G. The output terminal is connected to a node between the upper arm and the lower arm. An external load is connected to the output terminal.

[0065] FIG. 10 is a top view showing an example of a semiconductor module 300. The semiconductor module 300 is a semiconductor package including a plurality of semiconductor devices 100. The semiconductor module 300 includes a housing 88 and a circuit 200. The housing 88 houses the circuit 200. The circuit 200 may be placed on the bottom surface 94 of the housing 88. The housing 88 is a resin case formed of, for example, resin. The housing 88 of this example houses three sets of the circuit 200 shown in FIG. 9. The semiconductor module 300 of this example functions as a three-phase inverter.

[0066] The housing 88 has a plurality of main terminals 86 and a plurality of control terminals 99. The main terminals 86 function as P terminals, N terminals, and output terminals in FIG. 9. The control terminals 99 function as gate terminals G in FIG. 9. The control terminals 99 may include terminals for detecting the current flowing through each semiconductor device 100, terminals for detecting the temperature of the semiconductor device 100, and the like.

[0067] A circuit board 162 is placed on the bottom surface 94 of the housing 88. A plurality of semiconductor devices 100 and wiring patterns are provided on the circuit board 162. The wiring patterns connect each terminal of the semiconductor device 100 and each node such as the main terminals 86 and the control terminals 99. Further, the housing 88 may be provided with wirings such as wires or lead frames connecting each node.

[0068] A cooling unit for cooling the semiconductor module 300 may be arranged below the housing 88. In FIG. 10, the cooling unit is omitted. The housing 88 may have through holes 84 for fixing the semiconductor module 300 to an external device.

[0069] FIG. 11 is a view showing an example of a cross section taken along D-D' in FIG. 10. The cross section taken along D-D' is a cross section passing through the semiconductor device 100-2 and the semiconductor device 100-4. As described above, a cooling unit 114 is provided below the housing 88. A refrigerant such as water flows inside the cooling unit 114. Cooling fins 95 for increasing the contact area with the refrigerant may be provided inside the cooling unit 114. The cooling fins 95 may be connected to the lower surface of the housing 88.

[0070] The housing 88 may have a recess 93 for accommodating the circuit 200. The inside of the recess 93 may be filled with a sealing material such as silicon gel for sealing the circuit 200.

[0071] FIG. 12 is a cross-sectional view showing an example of the semiconductor discrete 400. The semiconductor discrete 400 is a semiconductor package including one semiconductor device 100. The semiconductor discrete 400 of this example includes sealing portions 101, one or more terminals 102, connection portions 103, connection portions 105, connection portions 106, wirings 104, wirings 107, and a chip mounting portion 108.

[0072] The chip mounting portion 108 mounts the semiconductor device 100. The chip mounting portion 108 may be electrically connected to the electrodes formed on the lower surface of the semiconductor device 100 via the connection portion 103. The chip mounting portion 108 may be formed of a conductive member such as copper. The chip mounting portion 108 may function as a terminal for electrically connecting to an external circuit. Further, the chip mounting portion 108 may be fixed to an external cooling device. The connection portions 103, 105, and 106 are formed of a conductive material such as solder.

[0073] The terminals 102 are connected to the respective electrodes of the semiconductor device 100. For example, the semiconductor discrete 400 may include a terminal 102 connected to the main electrode formed on the upper surface of the semiconductor device 100 and a terminal 102 connected to the control electrode formed on the upper surface of the semiconductor device 100. The main electrode is, for example, the emitter electrode in an IGBT. The control electrode is, for example, the gate electrode in an IGBT.

[0074] Wiring 104 and wiring 107 electrically connect respective terminals 102 and semiconductor device 100. Wiring 104 and wiring 107 are, for example, linear wires or plate-shaped lead frames. In this example, wiring 104 is a lead frame and wiring 107 is a wire. Connection portion 103 connects wiring 104 and terminal 102. Connection portion 105 connects wiring 104 and an electrode of semiconductor device 100. Wiring 107 may be bonded to terminal 102 and an electrode of semiconductor device 100.

[0075] Sealing portion 101 seals semiconductor device 100 so that semiconductor device 100 is not exposed to the outside. Sealing portion 101 is formed of an insulating material. Sealing portion 101 may be a resin such as epoxy or a ceramic. Sealing portion 101 may seal wiring 104 and wiring 107 so that wiring 104 and wiring 107 are not exposed to the outside. Sealing portion 101 may seal respective terminals 102. However, the end portions of terminals 102 are exposed outside sealing portion 101. Sealing portion 101 may seal chip mounting portion 108. The lower surface of chip mounting portion 108 may be exposed outside sealing portion 101.

[0076] As described in FIG. 8, after testing semiconductor device 100 by test step S208, the good semiconductor devices are incorporated into semiconductor modules such as semiconductor module 300 or semiconductor discrete 400. For this reason, the defective rate in module test S218 can be reduced and the manufacturing cost can be reduced.

[0077] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0078] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "earlier than" or "preceding" etc. in particular, and it should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if explanations are made using "first," "next," etc. for convenience, it does not mean that it is essential to be implemented in this order.

Explanation of Reference Numerals

[0079] 10 ··· semiconductor substrate, 12 ··· emitter region, 14 ··· base region, 18 ··· drift region, 21 ··· upper surface, 37 ··· through hole, 38 ··· interlayer insulating film, 39 ··· contact hole, 40 ··· gate trench portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 52 ··· metal electrode, 53 ··· plating layer, 84 ··· through hole, 86 ··· main terminal, 88 ··· housing, 93 ··· recess, 94 ··· bottom surface, 95 ··· cooling fin, 99 ··· control terminal, 100 ··· semiconductor device, 101 ··· sealing portion, 102 ··· terminal, 103 ··· connection portion, 104 ··· wiring, 105 ··· connection portion, 106 ··· connection portion, 107 ··· wiring, 108 ··· chip mounting portion, 114 ··· cooling portion, 162 ··· circuit board, 200 ··· circuit, 300 ··· semiconductor module, 400 ··· semiconductor discrete

Claims

1. An element formation step of forming a semiconductor element including a gate insulating film on a semiconductor substrate and forming a metal electrode above the semiconductor substrate; A plating step of plating the metal electrode; An annealing step of annealing the semiconductor substrate; A voltage application step of applying a voltage corresponding to the thickness of the gate insulating film to the gate insulating film after the annealing step; A determination step of measuring the threshold voltage of the semiconductor element after the voltage application step and determining the quality of the semiconductor element based on the measurement result; A method for manufacturing a semiconductor device comprising the above steps.

2. In the voltage application step, a voltage is applied to the gate insulating film such that an electric field greater than 3.64 kV / μm is applied to the gate insulating film per unit thickness. The method for manufacturing a semiconductor device according to claim 1.

3. In the voltage application step, a voltage is applied to the gate insulating film such that an electric field of 4.55 kV / μm or more is applied. The method for manufacturing a semiconductor device according to claim 1.

4. In the voltage application step, the application time of the voltage is 10 seconds or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. In the voltage application step, the application time of the voltage is 1 second or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

6. In the element formation step, a gate conductive portion insulated from the semiconductor substrate by the gate insulating film is formed, and an interlayer insulating film for insulating the gate conductive portion and the metal electrode is formed. In the annealing step, the semiconductor substrate is annealed such that the average diffusion distance of sodium in the interlayer insulating film is 70% or more of the thickness of the interlayer insulating film. The method for manufacturing a semiconductor device according to any one of claims 1 to 5.

7. In the element formation step, the gate insulating film is formed to cover the inner wall of a trench provided on the upper surface of the semiconductor substrate, and the gate conductive portion is formed inside the trench and inside the gate insulating film. The method for manufacturing a semiconductor device according to claim 6.

8. In the annealing step, the annealing temperature is 240°C or more and 300°C or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. An assembly step of assembling a semiconductor package using the semiconductor element determined to be a good product by the determination step; Comprising; The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

10. The temperature of the semiconductor device in the voltage application step is lower than the annealing temperature in the annealing step. The method for manufacturing a semiconductor device according to any one of Claims 1 to 9.

11. In the voltage application step, the temperature of the semiconductor device is 100°C or higher and 250°C or lower. The method for manufacturing a semiconductor device according to any one of Claims 1 to 10.

12. A test method for testing a semiconductor device including a semiconductor substrate on which a semiconductor element including a gate insulating film is formed and a metal electrode formed above the semiconductor substrate and having a plated upper surface, an annealing step of annealing the semiconductor substrate in a chip or wafer state before being incorporated into a semiconductor package; a voltage application step of applying a voltage corresponding to the thickness of the gate insulating film to the gate insulating film after the annealing step; and a determination step of measuring the threshold voltage of the semiconductor element after the voltage application step and determining the quality of the semiconductor element based on the measurement result. The test method comprising the above steps.

13. The semiconductor substrate includes a gate conductive portion insulated from the semiconductor substrate by the gate insulating film and an interlayer insulating film that insulates the gate conductive portion from the metal electrode. The test method according to Claim 12.

14. In the annealing step, the semiconductor substrate is annealed such that the average diffusion distance of sodium in the interlayer insulating film is 70% or more of the thickness of the interlayer insulating film. The test method according to Claim 13.

15. In the annealing step, the annealing temperature is 240°C or higher and 300°C or lower. The test method according to any one of Claims 12 to 14.

16. The temperature of the semiconductor device in the voltage application step is lower than the annealing temperature in the annealing step. The test method according to any one of Claims 12 to 15.

17. In the voltage application step, the temperature of the semiconductor device is 100°C or higher and 250°C or lower. The test method according to any one of Claims 12 to 16.

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