Resistance change type nonvolatile memory device and its writing method

Abstract

This variable-resistance-type non-volatile storage device comprises a variable resistance element (RSE) capable of reversibly changing the state of resistance between a high resistance state and a low resistance state, and a current supply circuit (24) which passes, to the variable resistance element, a resistance-lowering current for changing the state of resistance from the high resistance state to the low resistance state, wherein: a current waveform of the resistance-lowering current includes, in a time axis, a first period and a second period subsequent to the first period; with the resistance-lowering current, a first current is applied to the variable resistance element in the first period, and a second current smaller than the first current is applied to the variable resistance element in the second period; and the first current at the end of the first period is not zero, and the second current at the start of the second period is not zero.

Description

Technical Field

[0001] The present disclosure relates to a resistive change type nonvolatile memory device composed of memory cells each including a resistive change type nonvolatile memory element whose resistance value changes reversibly based on an electrical signal, and a writing method thereof.

Background Art

[0002] In recent years, research and development of a resistive change type nonvolatile memory device having memory cells composed of resistive change type nonvolatile memory elements have been progressing. A resistive change type nonvolatile memory element has a property that its resistance value changes reversibly by an electrical signal or the like, and further, it can nonvolatilely store data corresponding to this resistance value. Examples of the resistive change type nonvolatile memory device include ReRAM based on a change in electrical resistance value due to a redox reaction, MRAM based on a change in magnetic resistance, and PCRAM based on a change in electrical resistance value due to a phase change.

[0003] It is known that in these resistive change type nonvolatile memory devices, control of the resistance value and stabilization of the operation can be achieved by controlling the current amount flowing through the resistive change type nonvolatile memory element and the voltage value applied thereto in the rewrite operation. Such a resistive change type nonvolatile memory device is disclosed in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a conventional resistance-change type nonvolatile memory device, for example, when reducing power consumption with the miniaturization of resistance-change elements, if the write current for changing the resistance-change element from a high-resistance state to a low-resistance state is reduced, there is a problem that an initial operation window cannot be secured sufficiently. Here, the operation window refers to the difference between the read current obtained in the high-resistance state and the read current obtained in the low-resistance state. If this difference is sufficiently large, a stable read operation is guaranteed. Conversely, the smaller this difference is, the greater the possibility of a read error occurring. Also, the operation window tends to deteriorate due to a high-cycling operation, that is, a rewrite operation performed a large number of times (for example, 100,000 times). Here, the initial operation window refers to the operation window during the initial (for example, from the first time to about several tens or several hundreds of times) rewrite operation immediately after manufacturing.

[0006] On the other hand, if the write current for reducing the resistance is increased, the initial operation window can be secured, but there is a problem that deterioration of the operation window due to a high-cycling operation becomes apparent.

[0007] Therefore, an object of the present disclosure is to provide a resistance-change type nonvolatile memory device and a writing method thereof that can expand an initial operation window and suppress deterioration of the operation window due to a large number of rewrite operations.

Means for Solving the Problems

[0008] A resistance-change type nonvolatile memory device according to an aspect of the present disclosure includes a resistance-change element capable of reversibly changing between a high-resistance state and a low-resistance state, and a current supply circuit that energizes the resistance-change element with a current for reducing the resistance for changing the element from the high-resistance state to the low-resistance state. The current for reducing the resistance has a downward staircase-shaped current waveform.

Effects of the Invention

[0009] According to the resistance-change type nonvolatile memory device of the present disclosure, it is possible to expand an initial operation window and suppress deterioration of the operation window due to a large number of rewrite operations.

Brief Description of the Drawings

[0010]

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[0011] (Knowledge underlying the present invention) The present inventor has found that the following problems occur in the resistive change type nonvolatile memory device described in the "Background Art" section.

[0012] In Patent Document 1, in a memory device including a 1T1R memory cell in which a resistive change type nonvolatile memory element and a transistor are connected, a drive circuit (pass transistor) and a drive method suitable for parallel driving of a low-resistance operation and a high-resistance operation are shown. The resistive change type nonvolatile memory element is composed of an insulator film such as SiN, SiO2, Gd2O3, and a conductor film such as a metal film, an alloy film, or a metal compound film containing a metal element such as Cu, Ag, Zr, or Al.

[0013] Here, the resistive change type nonvolatile memory element can be set to a desired low resistance value according to the current value to be driven. Further, by restricting the current to be driven so that an excessive current does not flow through the resistive change type nonvolatile memory element, deterioration of the resistive change type nonvolatile memory element can be suppressed.

[0014] By the way, research on resistive change type non-volatile memory devices such as ReRAM has been actively conducted in recent years because they can perform high-speed writing and reading operations compared to flash memory, which has been the mainstream of conventional non-volatile memory devices. Furthermore, although the number of rewrite cycles of flash memory used to be about 100,000 times, it has decreased to about several thousand times with the progress of miniaturization and large capacity. In this regard, ReRAM, which is said to have high rewrite performance, is expected to replace flash memory as a non-volatile memory device.

[0015] However, the disclosure regarding the conventional resistive change type non-volatile memory device suppresses the destruction and deterioration of the resistive change type non-volatile memory element by a method of setting the resistive change type non-volatile memory element to a desired resistance value and current-limiting so that excessive current is not applied by the rewrite operation of the resistive change type non-volatile memory element. Regarding the problem of achieving both an expanded operation window of the cell current between the low resistance state and the high resistance state for stable operation and a high number of rewrite cycles, it is not disclosed and has not been overcome.

[0016] Therefore, an object of the present disclosure is to provide a resistive change type non-volatile memory device and a writing method thereof that can expand an initial operation window and suppress deterioration of the operation window due to a large number of rewrite operations.

[0017] In order to solve the above problems, a resistive change type non-volatile memory device according to an aspect of the present disclosure includes a resistive change element that can reversibly change between a high resistance state and a low resistance state, and a current supply circuit that energizes a low resistance current for changing from the high resistance state to the low resistance state to the resistive change element. The low resistance current has a current waveform that has a first period and a second period following the first period on the time axis. The current supply circuit applies a first current to the resistive change element in the first period and applies a second current smaller than the first current to the resistive change element in the second period. The first current at the end of the first period is not zero, and the second current at the start of the second period is not zero.

[0018] According to this, it is possible to expand the initial operation window and suppress the deterioration of the operation window due to multiple rewrite operations.

[0019] (Embodiment) Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0020] Note that all of the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components not described in the independent claims showing the implementation forms according to one form of the present disclosure are described as optional components. The implementation forms of the present disclosure are not limited to the current independent claims and can also be expressed by other independent claims.

[0021] [1. Schematic Configuration Example] FIG. 1A is a diagram showing a configuration example of a main part of a resistive change type nonvolatile memory device 2 in an embodiment. This figure shows a circuit related to a low-resistance writing operation for changing a resistive change type nonvolatile memory element from a high-resistance state to a low-resistance state as a main configuration of the present disclosure. In addition, in this figure, a circuit related to a high-resistance writing operation, which is not a main part of the present disclosure, is omitted. The resistive change type nonvolatile memory device 2 shown in this figure includes a memory cell 3, an LR-converted BL selection switch 13, an LR-converted SL selection switch 14, and a current waveform control circuit 24.

[0022] The memory cell 3 has a resistive change type nonvolatile memory element RSE and a memory cell transistor 1 connected in series. Note that the memory cell 3 in this figure represents one memory cell in a memory array composed of a plurality of memory cells 3 arranged in a matrix. The resistive change type nonvolatile memory element RSE may hereinafter be simply referred to as a resistive change element RSE.

[0023] The resistance change element RSE is an element that can reversibly change between a high-resistance state and a low-resistance state, and functions as a readable and writable memory element by corresponding the high-resistance state and the low-resistance state to digital binary values. One end of the resistive change type non-volatile memory element RSE is connected to the source S of the memory cell transistor 1, and the other end is connected to the bit line BL.

[0024] The memory cell transistor 1 has a drain D, a source S, and a gate G. The drain D is connected to the source line SL. The gate G is connected to the memory cell gate terminal MG. The source S is connected to one end of the resistance change element RSE. Note that the drain and source of the transistor may be on either side with the gate in between, but in this specification, the side connected to the resistive change type non-volatile memory element RSE is defined as the source S.

[0025] During the low-resistance writing operation, the voltage VwL shown in the figure is applied to the memory cell gate MG. As a result, the memory cell transistor 1 becomes on.

[0026] The LR conversion BL selection switch 13 and the LR conversion SL selection switch 14 both become on during the low-resistance writing operation.

[0027] The current waveform control circuit 24 is a current supply circuit that energizes the resistance change element with a low-resistance current LRIcell for changing from a high-resistance state to a low-resistance state. The low-resistance current LRIcell has a downward staircase-shaped current waveform. The current waveform control circuit 24 performs a drive to reduce the constant current in the low-resistance writing operation in two steps by making the low-resistance current LRIcell have a downward staircase-shaped current waveform. This drive is called a constant current two-step reduction drive. According to this drive, in the writing operation of changing from a high-resistance state to a low-resistance state, degradation of the initial window can be suppressed, and degradation of the operation window during high cycling (for example, when rewriting 100,000 times) can be suppressed. For example, even when miniaturized, a highly reliable and stable rewriting operation can be realized over a long period.

[0028] Next, a specific example of the current waveform of the current for reducing resistance will be described.

[0029] FIG. 1B is a diagram showing an example of the current waveform of the current for reducing resistance. As shown in FIG. 1B, the downward staircase-shaped current waveform has a first period and a second period following the first period. The current supply circuit, that is, the current waveform control circuit 24, energizes the first constant current to the resistance change element RSE in the first period, and energizes the second constant current smaller than the first constant current to the resistance change element RSE in the second period.

[0030] Therefore, the current supply circuit, that is, the current waveform control circuit 24, includes an LR reduction current limiting element 26 as the first constant current source and an LR reduction current limiting element 27 as the second constant current source. The current waveform control circuit 24 generates the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source in the first period. Further, the current waveform control circuit 24 generates the second constant current as the constant current from either one of the first constant current source and the second constant current source in the second period.

[0031] Furthermore, the current supply circuit, that is, the current waveform control circuit 24, includes a first switch (that is, the constant current control switch 31) connected in series with the first constant current source and a second switch (that is, the constant current control switch 32) connected in series with the second constant current source. The current waveform control circuit 24 energizes the first constant current to the resistance change element RSE by turning on both the first switch and the second switch in the first period. Also, the current waveform control circuit 24 energizes the second constant current to the resistance change element RSE by turning one of the first switch and the second switch off and the other on in the second period.

[0032] According to this, since a current value higher than that in the second period is applied to the resistance change element RSE in the first period, a sufficient initial window can be secured. Since a current value lower than that in the first period is applied to the resistance change element in the second period, window degradation during high cycling can be suppressed. Also, a downward staircase-shaped current waveform can be easily generated by the operations of the first switch and the second switch.

[0033] Also, as shown in FIG. 1B, the first period is shorter than the second period. For example, the first period may be 10% or less of the second period. By doing so, the operation window can be expanded in the first period in which a relatively high first constant current is applied, and degradation of the operation window due to high cycling operation can be suppressed in the second period in which a relatively low second constant current is applied. Also, even if the first period is a transient period of 10% or less of the second period, the operation window can be sufficiently expanded. More specifically, the first period may be 5n seconds or less, and the second period may be 50n seconds or more. By doing so, the write operation to the low-resistance state can be performed at high speed.

[0034] Also, the second constant current may be 60% or less of the first constant current. By doing so, the write operation to the low-resistance state can be made low-power. More specifically, the first constant current may be 125 μA or more, and the second constant current may be 75 μA or less. By doing so, the write operation to the low-resistance state can be made low-power.

[0035] [1.1 Detailed Configuration Example] Next, a more detailed configuration example of the resistance change type nonvolatile memory device 2 will be described.

[0036] FIG. 2A is a diagram showing a detailed configuration example of the resistance change type nonvolatile memory device 2 in the embodiment.

[0037] In FIG. 2A, the circuit related to the high-resistance write operation omitted in FIG. 1A is also shown, and a specific example of the current waveform control circuit 24 and the circuits around it is shown.

[0038] The resistive change type nonvolatile memory device 2 shown in FIG. 2A includes a memory cell 3, a bit line drive circuit 22b, and a source line drive circuit 23.

[0039] Since the memory cell 3 is the same as that in FIG. 1A already described, the description thereof will not be repeated here.

[0040] The bit line drive circuit 22b includes a low resistance conversion BL selection switch 13 and a high resistance conversion BL selection switch 16, and is connected to the memory cell 3 via the bit line BL.

[0041] The low resistance conversion BL selection switch 13 is a switch that connects the ground and the bit line BL, and is turned on during the low resistance conversion operation.

[0042] The high resistance conversion BL selection switch 16 is a switch that connects the high resistance conversion power supply terminal 17 and the bit line BL, and is turned on during the high resistance conversion operation. That is, the high resistance conversion BL selection switch 16 is a switch for supplying a high resistance conversion current pulse for making the memory cell 3 into a high resistance state to the memory cell 3.

[0043] A voltage VdH for generating a pulse voltage for high resistance conversion is applied to the high resistance conversion power supply terminal 17.

[0044] The source line drive circuit 23 includes a low resistance conversion power supply terminal 11, a low resistance conversion SL selection switch 14, a high resistance conversion SL selection switch 18, a current waveform control circuit 24, and a write pulse width control terminal 33. This source line drive circuit 23 is a circuit for energizing a low resistance conversion current to the resistive change element RSE. The low resistance conversion current has a downward staircase-shaped current waveform instead of a single rectangular pulse waveform.

[0045] A voltage VdL for generating a pulse current for low resistance conversion is applied to the low resistance conversion power supply terminal 11.

[0046] The LR-mode SL selection switch 14 connects the source line SL to the current supply terminal of the current waveform control circuit 24 and is turned on during the low-resistance operation period. The current supply terminal of the current waveform control circuit 24 refers to the connection point with the constant current control switch 31 and the constant current control switch 32.

[0047] The HR-mode SL selection switch 18 is a switch that connects the ground and the source line SL and is turned on during the high-resistance operation period.

[0048] The current waveform control circuit 24 shows a more specific circuit example of the current supply circuit shown in Fig. 1A, that is, the current waveform control circuit 24. The current waveform control circuit 24 in Fig. 2A includes a constant current control circuit 25, an LR-mode current limiting element 26, and an LR-mode current limiting element 27. The current waveform control circuit 24 is composed of a constant current control circuit 25 and LR-mode current limiting elements 26 and 27 formed by PMOS transistors.

[0049] The constant current control circuit 25 is composed of a delay circuit 28 having a first delay time (for example, 5 ns), a NAND circuit 29, an inverter 30, and constant current control switches 31 and 32 formed by PMOS transistors.

[0050] The write pulse width control terminal 33 is connected to the input of the delay circuit 28, the input terminal of the inverter 30, and the gate terminal of the constant current control switch 32. One input terminal of the NAND circuit 29 is connected to the output terminal of the delay circuit 28. The other input terminal of the NAND circuit 29 is connected to the output of the inverter 30. The output terminal of the NAND circuit 29 is connected to the gate terminal of the constant current control switch 31. Also, for the LR-mode current limiting elements 26 and 27, the source terminals are both connected to the LR-mode power supply terminal 11, the drain terminals are respectively connected to the source terminals of the constant current control switches 31 and 32, and furthermore, the drain terminals of the constant current control switches 31 and 32 are both connected to the LR-mode SL selection switch 14.

[0051] The current limiting element 26 for LR conversion is composed of a PMOS transistor, and a clamping voltage Vc1 (<VdL) is applied to its gate terminal. Also, the current limiting element 27 for LR conversion is composed of a PMOS transistor, and a clamping voltage Vc2 (<VdL) is applied to its gate terminal. Therefore, the current limiting elements 26 and 27 for LR conversion become substantially constant current sources due to the current saturation region characteristics of each current limiting element 26 and 27 for LR conversion, and can limit the current to constant currents Iset1 (for example, 100 μA) and Iset2 (for example, 75 μA), respectively. That is, the transistor size and its gate voltage are set so that the output currents of the current limiting elements 26 and 27 for LR conversion can be limited to the constant currents Iset1 and Iset2. For example, the PMOS transistor lengths of the current limiting elements 26 and 27 for LR conversion are the same, and the ratio of the transistor widths of the current limiting element 26 for LR conversion to the current limiting element 27 for LR conversion is set to 4 to 3. In this way, when Vc1 = Vc2, Iset1 to Iset2 is 4 to 3.

[0052] The write pulse width control terminal 33 is a terminal for inputting a voltage Vi that specifies the timing and pulse width (that is, the LR write pulse width) of the low-resistance current for low resistance conversion.

[0053] The constant current control switch 31 is a first switch connected in series with the current limiting element 26 for LR conversion, that is, the first current source, and becomes on in the first period according to the pulse voltage Vc.

[0054] The constant current control switch 32 is a second switch connected in series with the current limiting element 27 for LR conversion, that is, the second current source, and becomes on in the second period according to the pulse voltage Vi.

[0055] The circuit composed of the delay circuit 28, the NAND circuit 29, and the inverter 30 is a control circuit that controls the conduction and non-conduction of the first switch, i.e., the constant current control switch 31. As shown in FIG. 2B, this circuit is a circuit for generating a negative logic pulse voltage Vc obtained by differentiating the leading edge of the negative logic pulse voltage Vi input from the write pulse width control terminal 33. The pulse width of the negative logic pulse voltage Vc determines the first period for turning on the constant current control switch 31. Also, the pulse width of the negative logic pulse voltage Vi determines the second period for turning on the constant current control switch 32.

[0056] When reducing the resistance of the memory cell 3, the LR BL selection switch 13 and the LR SL selection switch 14 are turned on for a predetermined period, and the HR BL selection switch 16 and the HR SL selection switch 18 are turned off. Then, when a negative logic voltage pulse Vi having a pulse width of a predetermined period (e.g., 100 ns) is applied to the write pulse width control terminal 33, as shown in FIG. 2B, the output voltage Va of the delay circuit 28 becomes a voltage pulse delayed by 5 ns from the voltage pulse Vi. Also, the output voltage Vb of the inverter 30 becomes a voltage pulse obtained by logically inverting the voltage pulse Vi. The output voltage Vc of the NAND circuit 29 is the NAND operation result of the output voltage Va and the output voltage Vb, and becomes a negative logic voltage pulse having a pulse width of the first delay time (e.g., 5 ns).

[0057] Therefore, at the start of the low-resistance conversion at time t1, the constant-current control switches 31 and 32 are both activated for 5 ns and turned on, and the LR write current is limited to the sum of the constant current Iset1 (100 μA) and the constant current Iset2 (75 μA) (e.g., 175 μA) by both the LR conversion current limiting elements 26 and 27. At time t2, the constant-current control switch 32 maintains the on state, and the constant-current control switch 31 turns off. After that, during the remaining 95 ns period (t2 to t3), only the constant-current control switch 31 is in the off state, and the LR write current is reduced to the constant current Iset2 (75 μA) by the LR conversion current limiting element 27. In this way, the LR write current is passed while being controlled to reduce the current in two steps from the source line SL side to the bit line BL side. In this way, the current waveform control circuit 24 energizes the resistance change element RSE with a low-resistance current having a descending staircase-shaped current waveform shown in FIG. 2B as the low-resistance conversion operation.

[0058] When high-resistance conversion is to be performed, the LR conversion BL selection switch 13 and the LR conversion SL selection switch 14 are turned off, the HR conversion BL selection switch 16 and the HR conversion SL selection switch 18 are turned on for a predetermined period, and current is passed from the bit line BL to the source line SL.

[0059] Next, a configuration example of the resistance change type nonvolatile memory element RSE will be described.

[0060] FIG. 3 is an explanatory diagram showing the circuit symbol and cross-sectional structure of the resistance change type nonvolatile memory element RSE in the embodiment.

[0061] As shown in FIG. 3(a), in the resistance change type nonvolatile memory element RSE indicated by the circuit symbol, the terminal connected to the source S of the memory cell transistor 1 is defined as terminal A, and the terminal connected to the bit line BL is defined as terminal B.

[0062] The resistance change type nonvolatile memory element 3000a shown in FIG. 3(b) shows the structure of the resistance change type nonvolatile memory element RSE after manufacturing and before forming.

[0063] The resistance change type nonvolatile memory element 3000a includes a first electrode 81 (lower electrode) corresponding to the terminal A side, a second electrode 84 (upper electrode) corresponding to the terminal B side, and a resistance change layer 85 composed of an oxygen-deficient transition metal oxide. The resistance change layer 85 is composed of a first transition metal oxide layer 82 made of an oxygen-deficient transition metal oxide and a second transition metal oxide layer 83 made of a transition metal oxide with a lower oxygen deficiency degree than the first transition metal oxide layer 82, which are laminated.

[0064] The resistance change type nonvolatile memory element RSE shown in Fig. 3(c) shows the structure after forming. By applying an electrical stress to the resistance change type nonvolatile memory element 3000a before forming, minute filaments 86 serving as conductive paths are formed in local regions of the second transition metal oxide layer 83. An oxidation-reduction reaction occurs in these minute filaments 86, and the resistance change phenomenon appears due to the change in its resistance value. Hereinafter, the resistance change operation described in this disclosure is based on the structure of the resistance change type nonvolatile memory element RSE after this forming.

[0065] In this embodiment, as an example, the same kind of transition metal is used for the first transition metal oxide layer 82 and the second transition metal oxide layer 83. The first transition metal oxide layer 82 is an oxygen-deficient first tantalum oxide layer (hereinafter, the first Ta oxide layer), and the second transition metal oxide layer 83 is a second tantalum oxide layer (hereinafter, the second Ta oxide layer), which are laminated. When the first Ta oxide layer is denoted as TaOx and the second Ta oxide layer is denoted as TaOy, x < y. The film thickness of the second Ta oxide layer is preferably 1 nm or more and 10 nm or less. Also, in this embodiment, the first electrode 81 is formed by laminating titanium nitride (TiN) and tantalum nitride (TaN), and the second electrode 84 is composed of a noble metal material, for example, iridium (Ir).

[0066] An oxygen-deficient transition metal oxide refers to an oxide having an oxygen content (atomic ratio: the ratio of oxygen atoms to the total number of atoms) less than that of an oxide having a stoichiometric composition. Usually, an oxide having a stoichiometric composition is an insulator or has a very high resistance value. For example, when the transition metal is Ta, the stoichiometric oxide composition is Ta2O5, and the atomic ratio of O to Ta (O / Ta) is 2.5. Therefore, in the oxygen-deficient Ta oxide, the atomic ratio of Ta to O is greater than 0 and less than 2.5.

[0067] Here, the oxygen content rate of the second Ta oxide layer as the second transition metal oxide layer 83 is higher than that of the first Ta oxide layer as the first transition metal oxide layer 82. In other words, the oxygen deficiency degree of the second Ta oxide layer is less than that of the first Ta oxide layer. The oxygen deficiency degree refers to the ratio of the oxygen that is lacking to the amount of oxygen that constitutes the oxide of the stoichiometric composition in each transition metal. For example, when the transition metal is tantalum (Ta), since the stoichiometric oxide composition is Ta2O5, it can be expressed as TaO2.5. The oxygen deficiency degree of TaO2.5 is 0%. For example, the oxygen deficiency degree of the oxygen-deficient tantalum oxide having a composition of TaO1.5 is oxygen deficiency degree = (2.5 - 1.5) / 2.5 = 40%. Also, the oxygen content rate is the ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide. The oxygen content rate of Ta2O5 is the ratio of the number of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, in the oxygen-deficient tantalum oxide, the oxygen content rate is greater than 0 and less than 71.4 atm%.

[0068] The metal constituting the resistance change layer 85 may be a transition metal other than tantalum or some metals. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), etc. can be used, and as the metal, aluminum (Al), etc. can be used. Since transition metals can take on multiple oxidation states, it is possible to realize different resistance states through oxidation-reduction reactions. For example, when using hafnium oxide, when the composition of the first hafnium oxide layer as the first transition metal oxide layer 82 is HfOx, x is 0.9 or more and 1.6 or less, and when the composition of the second hafnium oxide layer as the second transition metal oxide layer 83 is HfOy, y is larger than the value of x, it has been confirmed that the resistance value of the resistance change layer 85 can be stably and rapidly changed. In this case, the film thickness of the second hafnium oxide layer is preferably 3 nm or more and 4 nm or less. Also, when using zirconium oxide, when the composition of the first zirconium oxide layer as the first transition metal oxide layer 82 is ZrOx, x is 0.9 or more and 1.4 or less, and when the composition of the second zirconium oxide layer as the second transition metal oxide layer 83 is ZrOy, y is larger than the value of x, it has been confirmed that the resistance value of the resistance change layer 85 can be stably and rapidly changed. In this case, the film thickness of the second zirconium oxide layer is preferably 1 nm or more and 5 nm or less.

[0069] In the above-described example, the resistance change layer 85 has a two-layer stacked structure, but it may be composed of a single-layer resistance change layer with an oxygen-deficient transition metal oxide layer.

[0070] The second electrode 84 connected to the second transition metal oxide layer 83 with a smaller oxygen deficiency degree is made of a material with a higher standard electrode potential compared to the transition metal constituting the second transition metal oxide layer 83 and the material constituting the first electrode 81, such as platinum (Pt), iridium (Ir), palladium (Pd), etc. By adopting such a configuration, a selective oxidation-reduction reaction occurs in the second transition metal oxide layer 83 near the interface between the second electrode 84 and the second transition metal oxide layer 83, thereby realizing a stable resistance change phenomenon.

[0071] Further, as the resistance change layer 85, a laminated structure composed of a first transition metal oxide layer 82 made of a first transition metal and a second transition metal oxide layer 83 made of a second transition metal different from the first transition metal may be used. The oxygen deficiency degree of the second transition metal oxide layer is smaller than that of the first transition metal oxide layer. In other words, the resistance value of the second transition metal oxide layer 83 is higher than that of the first transition metal oxide layer 82.

[0072] Also, when using different materials for the first transition metal and the second transition metal, it is preferable that the standard electrode potential of the second transition metal is smaller than that of the first transition metal. For example, by using an oxygen-deficient tantalum oxide for the first transition metal oxide layer 82 and titanium oxide (TiO2) for the second transition metal oxide layer 83, a stable resistance change operation can be realized. Titanium (standard electrode potential = -1.63 eV) is a material with a lower standard electrode potential than tantalum (standard electrode potential = -0.6 eV). By disposing an oxide of a metal having a smaller standard electrode potential than the first transition metal oxide layer 82 in the second transition metal oxide layer 83, a redox reaction is more likely to occur in the second transition metal oxide layer 83.

[0073] In the structure as described above, when a positive voltage is applied to the second electrode 84 with reference to the first electrode 81, oxygen ions contained in the first transition metal oxide layer 82 move into the filament 86, causing an oxidation reaction. As a result, it is considered that the resistance of the filament 86 increases and enters a high-resistance state.

[0074] Conversely, when a negative voltage is applied to the second electrode 84 with reference to the first electrode 81, the oxygen ions in the filament 86 are pushed toward the first transition metal oxide layer 82 side, causing a reduction reaction in the filament 86. As a result, it is considered that the resistance of the minute filament 86 decreases and enters a low-resistance state.

[0075] Incidentally, the resistance value of the second transition metal oxide layer 83, which has a higher resistance value than the first transition metal oxide layer 82, is formed, for example, to be about several hundreds of MΩ to 1 GΩ. On the other hand, the resistance value of the filament 86 is about several hundreds of kΩ to several MΩ even when it becomes a high-resistance state due to the oxidation reaction.

[0076] Therefore, the voltage applied between the first electrode 81 and the second electrode 84 is divided by the first transition metal oxide layer 82 and the second transition metal oxide layer 83, and the voltage becomes higher for the second transition metal oxide layer 83 having a higher resistance value. However, the current path associated therewith is not uniform within the second transition metal oxide layer 83. The current concentrates in the region of the filament 86 having a lower resistance value within the second transition metal oxide layer 83. Therefore, control of the current and voltage that can stably and continuously perform the resistance change operation occurring in the filament 86 is important in the case of a resistance change type nonvolatile memory element operating in the filament model.

[0077] [2. Experimental Results for Evaluation] Next, the results of experiments conducted to evaluate the resistance change type nonvolatile memory device 2 of FIG. 2A will be described. In the experiment, in addition to the resistance change type nonvolatile memory device 2 of FIG. 2A, the resistance change type nonvolatile memory device shown in FIG. 13 was also used as an experimental subject as a comparative example.

[0078] First, the resistance change type nonvolatile memory device of the comparative example will be described.

[0079] FIG. 13 is a diagram showing the configuration of a resistance change type nonvolatile memory device as a comparative example. This comparative example is a circuit similar to the resistance change type nonvolatile memory device of Patent Document 1, and shows a 1T1R memory cell and its peripheral circuits. (a) of FIG. 13 shows a high-resistance operation. The thick downward arrow indicates the current HRIcell applied to the resistance change type nonvolatile memory element RSE. Further, (b) of FIG. 13 shows a low-resistance operation. The thick upward arrow indicates the current LRIcell applied to the resistance change type nonvolatile memory element RSE.

[0080] The resistive change type nonvolatile memory device of FIG. 13 mainly differs in that it includes a source line drive circuit 22a instead of the source line drive circuit 23 as compared with FIG. 2A.

[0081] The source line drive circuit 22a is a circuit that energizes the memory cell 3 with a single-shot constant current rectangular wave pulse in the low-resistance operation.

[0082] When increasing the resistance, the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be off, the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be on for a predetermined period, and a current HRIcell is passed through the memory cell 3 from the bit line BL to the source line SL.

[0083] When decreasing the resistance, the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be on for a predetermined period, the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be off, and a current LRIcell is passed through the memory cell 3 from the source line SL to the bit line BL.

[0084] This evaluation circuit can evaluate the memory cell 3 in units of 1 bit by applying a predetermined voltage to each terminal of the source line drive circuit 22a and the bit line drive circuit 22b. However, when configuring and evaluating a memory cell array, it is configured in a form that shares the source line drive circuit 22a and the bit line drive circuit 22b for a plurality of memory cells 3. In this evaluation, a plurality of memory cells can be selectively evaluated, and rewrite evaluation is possible in units of 1 bit or in units of a memory cell array of a plurality of bits.

[0085] Also, the LR BL selection switch 13, the LR SL selection switch 14, the HR BL selection switch 16, and the HR SL selection switch 18 are general selection circuits composed of transistors, but the voltage drops at these locations are minimized, and the transistor size, transistor configuration, and gate voltage are set so that the current is not rate-limited.

[0086] In common with both the high-resistance operation and the low-resistance operation, a voltage VdL is constantly applied to the power supply terminal 11 for LR conversion, a voltage Vclamp (<VdL) is applied to the clamp control terminal 12 for LR conversion, and a voltage VdH is applied to the power supply terminal 17 for HR conversion.

[0087] In the high-resistance operation, a voltage VwH is applied to the memory cell gate terminal MG of the memory cell transistor 1, and the HR conversion BL selection switch 16 and the HR conversion SL selection switch 18 perform on control for a period of 100 ns. At this time, the LR conversion BL selection switch 13 and the LR conversion SL selection switch 14 are set to off control. By performing such a high-resistance operation, a resistance change for high resistance is performed by flowing a current HRIcell from the bit line BL side to the source line SL side through the resistive change type nonvolatile memory element RSE.

[0088] In the low-resistance operation, in the 1T1R memory cell 3 composed of the resistive change type nonvolatile memory element RSE and the memory cell transistor 1, a voltage VwL is applied to the memory cell gate terminal MG of the memory cell transistor 1, and the LR conversion BL selection switch 13 and the LR conversion SL selection switch 14 perform on control for a period of 100 ns. At this time, the HR conversion BL selection switch 16 and the HR conversion SL selection switch 18 are set to off control. By performing such a low-resistance operation, a resistance change for low resistance is performed by flowing a current LRIcell from the source line SL side to the bit line BL side through the resistive change type nonvolatile memory element RSE. At this time, the constant current source composed of the PMOS transistor 10 can limit the current to the constant current Iset, and its gate voltage is applied so that the impedance of the memory cell transistor 1 operates with a sufficiently low value. Therefore, the current Imos flowing through the memory cell transistor 1 and the current LRIcell flowing through the resistive change type nonvolatile memory element RSE are limited to Iset.

[0089] Next, the rewriting operation for evaluation performed in the experiment will be described.

[0090] FIG. 4 is a diagram showing an experimental processing flow including a plurality of rewrite processes. The processing flow in this figure was performed for each of the resistive change type nonvolatile memory device of the comparative example in FIG. 13 and the resistive change type nonvolatile memory device 2 in FIG. 2A.

[0091] In FIG. 4, first, a low-resistance operation and cell current measurement of a plurality of bits to be evaluated (for example, about 1 kb) in the memory cell array are performed (S41, S42). Subsequently, a high-resistance operation and cell current measurement of the bits to be evaluated are performed (S43, S44). This resistance change operation is repeated 100,000 times and then ended (S45). The cell current measurement is to confirm whether the memory cell 3 has been brought into a desired resistance state by the resistance change operation, and a low voltage at which the resistive change type nonvolatile memory element RSE is not disturbed is applied to measure the current value. Figure 14 FIG. is a diagram showing drive conditions of the resistive change type nonvolatile memory device in the embodiment. These drive conditions were applied to the resistive change type nonvolatile memory device of the comparative example in FIG. 13 and the resistive change type nonvolatile memory device 2 in FIG. 2A.

[0092] In common for both the low-resistance operation and the high-resistance operation, a voltage VdL of 2.8 V is constantly applied to the voltage VdL of the power supply terminal 11 for low resistance conversion, an intermediate voltage of 1.73 V is applied to the voltage Vclamp of the clamp control terminal 12 for low resistance conversion, and a voltage VdH of 1.7 V is constantly applied to the voltage VdH of the power supply terminal 17 for high resistance conversion. Here, 1.73 V is applied to the voltage Vclamp to constitute a constant current source of 175 μA, but the set current value of the constant current source can be changed by changing the voltage Vclamp.

[0093] For example, when it is desired to constitute a constant current source of 75 μA in FIG. 13, 1.86 V may be applied to the voltage Vclamp. In the low-resistance operation, a voltage VwL of 3.0 V is applied to the memory cell gate terminal MG of the memory cell transistor 1, and the low-resistance conversion BL selection switch 13 and the low-resistance conversion SL selection switch 14 perform on control for a period of 100 ns. The high-resistance conversion BL selection switch 16 and the high-resistance conversion SL selection switch 18 are kept off.

[0094] In the high-resistance operation, the memory cell gate terminal MG of the memory cell transistor 1 is supplied with 1.8 V at voltage VwH, and the HR BL selection switch 16 and the HR SL selection switch 18 perform on control for a period of 100 ns. The LR BL selection switch 13 and the LR SL selection switch 14 are kept off.

[0095] Also, in the low-resistance operation in FIG. 2A, both Vc1 and Vc2 were supplied with 1.73 V. The PMOS transistor lengths of the current limiting elements 26 and 27 for LR conversion are the same, and the ratio of the transistor widths of the current limiting element 26 for LR conversion to the current limiting element 27 for LR conversion is set to 4:3. As a result, the current limiting element 26 for LR conversion generates a first constant current value of 100 μA, and the current limiting element 27 for LR conversion generates a second constant current value of 75 μA.

[0096] Next, the evaluation results will be described.

[0097] First, the trend will be explained using some measurement data of the initial and 100,000 resistance changes.

[0098] FIG. 5 is a normal expected value plot showing the cell current distribution of the 1T1R memory cell of the comparative example in FIG. 13 as an experimental result.

[0099] FIG. 5(a) is a cell current distribution (about 1 kb) with the normal expected values plotted for the high-resistance state (HR) and the low-resistance state (LR) in the initial state where the operation after forming is stable when the set current value of the constant current source is set to 75 μA. The white squares indicate the cell currents in the high-resistance state, and the white circles indicate the cell currents in the low-resistance state.

[0100] FIG. 5(b) is a cell current distribution (about 1 kb) with the normal expected values plotted for the high-resistance state (HR) and the low-resistance state (LR) in the initial state where the operation after forming is stable when the set current value of the constant current source is set to 175 μA. The white squares indicate the cell currents in the high-resistance state, and the white circles indicate the cell currents in the low-resistance state.

[0101] FIG. 5(c) shows the transition of the cell current distribution (about 1 kb) with the normal expected values of the high resistance state (HR) and the low resistance state (LR) plotted after forming and after 100,000 rewrites, when the set current value of the constant current source is set to 175 μA. The open squares represent the high resistance state in the initial state, the open circles represent the low resistance state in the initial state, the black diamonds represent the low resistance state after 100,000 times, and the black triangles represent the cell current of the high resistance state after 100,000 times.

[0102] In a memory device using a resistive change type nonvolatile memory element, the written low resistance state or high resistance state is read by a sense amplifier circuit, and a discrimination operation is performed to determine whether the data is "1" or "0". For this purpose, a difference (operation window) of a predetermined value or more is required between the minimum cell current value of the low resistance state and the maximum cell current value of the high resistance state.

[0103] As shown in FIG. 5(a), when the LR write current is set to a low current of 75 μA, the LR cell current decreases, the operation window becomes less than the predetermined value and is very small, and it becomes difficult to stably discriminate data in the sense amplifier circuit.

[0104] In FIG. 5(b), by increasing the LR write current to 175 μA, the LR cell current is increased, and as a result, a sufficient operation window can be secured.

[0105] However, as shown in FIG. 5(c), when the number of rewrites is increased up to 100,000 times, the deterioration of the resistance change operation due to rewriting (increase in the variation of the cell current distribution) becomes apparent, high resistance defective bits and current drop bits at the tail of the LR cell current distribution occur, and the operation window substantially disappears.

[0106] FIG. 6 is a normal expected value plot showing the cell current distribution of the 1T1R memory cell in FIG. 2A in the embodiment of the present disclosure. The transition of the normal expected value plot of the cell current distribution (about 1 kb) of the high resistance state (HR) and the low resistance state (LR) in the initial state and after 100,000 rewrites when LR writing is performed by reducing the set current value of the constant current source from a total of 175 μA (current application time 5 ns) to 75 μA (current application time 95 ns). The white squares indicate the high resistance state in the initial state, the white circles indicate the low resistance state in the initial state, the black diamonds indicate the low resistance state after 100,000 times, and the black triangles indicate the cell current of the high resistance state after 100,000 times.

[0107] Due to the high current short pulse (constant current 175 μA, 5 ns) in the first period, the pulse width is shorter than that of the conventional write current pulse (constant current 175 μA, pulse width 100 ns), so the movement of oxygen ions from within the filament 86 to the first Ta oxide layer as the first transition metal oxide layer 82, that is, the reduction reaction becomes insufficient, and the median value of the LR cell current decreases, but the initial window can be secured. In the subsequent second period, due to the low current pulse (constant current 75 μA, 95 ns), the filament 86 is annealed with a low current application, and the voids (defects) formed by the movement of oxygen ions in the filament 86 are made uniform and stabilized, and the deterioration of the resistance change operation due to an increase in the number of rewrites (an increase in the variation of the cell current distribution) can be significantly reduced, enabling a stable and sustainable rewrite operation.

[0108] As described above, by performing the constant current two-step reduction writing of the present disclosure, it is possible to achieve both securing the initial window by the high current short pulse and suppressing and stabilizing the rewrite deterioration by the low current pulse.

[0109] [3. Configuration example including a memory array of a resistive change type nonvolatile memory device] Next, as an embodiment of the present disclosure, the overall configuration of a resistive change type nonvolatile memory device in which the resistive change element RSE described above and the 1T1R memory cells using the constant current two-step reduction drive of the present disclosure are arranged in a matrix will be described.

[0110] (Embodiment 1) FIG. 7 is a block diagram showing a configuration example of a resistive change type nonvolatile memory device according to an embodiment of the present disclosure.

[0111] The resistive change type nonvolatile memory device 4000 according to the present embodiment includes a memory main body 300 on a semiconductor substrate. The memory main body 300 includes a memory array 301, a column selection circuit 302, a row selection circuit 303, a write circuit 304 for writing data, and a read circuit 305 that detects the current flowing through the selected bit line and determines whether the stored data is "1" or "0".

[0112] The peripheral circuit unit 306 includes a voltage generation circuit 308, a word line voltage switching circuit 316, an address input circuit 317, and an input / output circuit 318, and includes a control circuit 307 that controls the operations of the memory main body 300 and the peripheral circuit unit 306 based on a control signal input from the outside.

[0113] The voltage generation circuit 308 includes a word line power supply 309 for low resistance, a word line power supply 310 for high resistance, a word line power supply 311 for reading, a clamp power supply 312 for low resistance, a pulse power supply 313 for low resistance, a pulse power supply 314 for high resistance, and a precharge power supply 315.

[0114] These power supplies take the external power supply VDD as an input and Figure 14 generate a predetermined set voltage value shown in. The values shown here are based on the voltage values in the constant current two-step reduction type drive for low resistance described in FIG. 1A.

[0115] Furthermore, the output VwL of the word line power supply 309 for low resistance, the output VwH of the word line power supply 310 for high resistance, and the output Vr of the word line power supply 311 for reading are supplied to the word line voltage switching circuit 316. Either the output VwL by the low resistance write instruction signal WEL, the output VwH by the high resistance write instruction signal WEH, or the output Vr by the read instruction signal RE is selected and supplied to the row selection circuit 303 as the output VRD of the word line voltage switching circuit 316.

[0116] The outputs Vc1 / Vc2 of the low-resistance clamp power supply 312, the output VdL of the low-resistance pulse power supply 313, and the output VdH of the high-resistance pulse power supply 314 are supplied to the writing circuit 304. The output VPR of the precharge power supply 315 is supplied to the column selection circuit 302 and the writing circuit 304. Each power supply circuit is composed of a general step-down circuit that steps down the external power supply VDD to generate a predetermined voltage, and a detailed description thereof is omitted. Further, each power supply circuit has a generally used trimming function so that the output voltage value can be finely adjusted to reflect manufacturing variations, etc. or to set the optimal operating point.

[0117] Note that depending on the voltage value of the external power supply VDD, any one or all of these power supply circuits may be configured to be generated by boosting from the external power supply VDD.

[0118] Also, any one or all of these power supply circuits do not necessarily have to be provided inside the resistance change type nonvolatile memory device 4000, and may be configured to provide a predetermined voltage as an external power supply.

[0119] The address input circuit 317 receives an address signal input from the outside and instructs the designated memory cell 3 of the memory array 301.

[0120] The input / output circuit 318 receives the data input signal Din input to the DQ terminal from the outside, supplies it to the memory main body 300 as a write signal, or receives the read output signal from the memory main body 300 and outputs the output signal Dout to the outside via the DQ terminal.

[0121] In the memory array 301, the memory cells 3 described above as the basic data of the present disclosure are arranged in an m-row and n-column matrix. Here, M11 is the upper left, and the memory cells are represented as M11, M21, ···, Mm1 in the row direction and M11, M12, ···, M1n in the column direction, respectively.

[0122] A plurality of word lines WL1, WL2, ···, WLm output in the row direction from the row selection circuit 303 are connected to the memory cell gate terminals MG of the respective memory cells 3.

[0123] A plurality of bit lines BL1, BL2, ···, BLn and a plurality of source lines SL1, SL2, ···, SLn output in the column direction from the column selection circuit 302 are alternately arranged in parallel and are connected to the bit lines BL and the source lines SL of the respective memory cells 3.

[0124] The column selection circuit 302 and the write circuit 304 are arranged on the upper side and the lower side of the memory array 301, and are configured to control writing from both ends of the bit lines BL1, BL2, ···, BLn and the source lines SL1, SL2, ···, SLn.

[0125] This is arranged on both sides for the purpose of reducing the influence of IR drop caused by the wiring resistance of the bit lines and the source lines. However, when the influence of IR drop is small depending on the number of memory cells 3 arranged and the wiring resistance value of the manufacturing process applied, for example, it may be arranged on only the lower side.

[0126] The writing operation to the memory cell 3 is the same as in the case of the description of the basic data of the present disclosure. When the bit line BL is set to a low potential and the source line SL is set to a high potential, the resistance is reduced. When the bit line BL is set to a high potential and the source line SL is set to a low potential, the resistance is increased.

[0127] FIG. 8 is a diagram showing a circuit example of the write circuit 304.

[0128] It includes a source line write circuit 330 and a bit line write circuit 336.

[0129] The source line writing circuit 330 is connected to the source line input terminal SLin via a PMOS transistor 333 whose gate input is the output of an inverter 332 that takes the low-resistance write instruction signal WEL as an input, and whose drain terminal is commonly connected to the drain terminals of the constant current control switches 31 and 32 inside the current waveform control circuit 24, to which the output VdL of the low-resistance pulse power supply 313 is connected to the LR conversion power supply terminal 11, the outputs Vc1 / Vc2 of the low-resistance clamp power supply 312 are connected to the gate terminals of the LR conversion current limiting elements 26 and 27, and the voltage pulse Vi for low-resistance writing output from the control circuit 307 is input to the write pulse width control terminal 33. Further, the source line input terminal SLin is connected to an NMOS transistor 334 whose gate input is the high-resistance write instruction signal WEH and whose source is grounded, a PMOS transistor 335 whose source input is the output VPR of the precharge power supply 315 and whose gate input is the precharge instruction signal NPR, and an NMOS transistor 342 whose gate input is the read instruction signal RE and whose source is grounded.

[0130] The bit line writing circuit 336 is composed of a PMOS transistor 338 whose source input is the output VdH of the high-resistance pulse power supply 314, whose gate input is the output of an inverter 337 that takes the high-resistance write instruction signal WEH as an input, and whose drain is connected to the bit line input terminal BLin, an NMOS transistor 339 whose drain input is the bit line input terminal BLin, whose gate input is the low-resistance write instruction signal WEL, and whose source is grounded, a PMOS transistor 340 whose gate input is the precharge instruction signal NPR, whose source input is the output VPR of the precharge power supply 315, and whose drain input is connected to the bit line input terminal BLin, and an NMOS transistor 341 whose gate input is the read instruction signal RE, whose drain input is the bit line input terminal BLin, and whose source is connected to the bit line output signal BLout.

[0131] The bit line output signal BLout is connected to the read circuit 305.

[0132] In the resistive change type nonvolatile memory device of FIG. 1A, the LR conversion SL selection switch 14 corresponds to the PMOS transistor 333, the LR conversion BL selection switch 13 corresponds to the NMOS transistor 339, the HR conversion BL selection switch 16 corresponds to the PMOS transistor 338, and the HR conversion SL selection switch 18 corresponds to the NMOS transistor 334.

[0133] FIG. 9 shows a circuit example of the column selection circuit 302.

[0134] The bit line selection circuit 350 includes an NMOS transistor 351 having one of the source and drain connected to the bit line BLi (i = 1 to n) and the other connected to the bit line input terminal BLin, and a PMOS transistor 352 having one of the source and drain also connected to the bit line BLi (i = 1 to n) and the other connected to the output VPR of the precharge power supply 315. The gates of both transistors are connected to the same column selection signal CLi (i = 1 to n).

[0135] The source line selection circuit 353 includes an NMOS transistor 354 having one of the source and drain connected to the source line SLi (i = 1 to n) paired with the bit line BLi and the other connected to the source line input terminal SLin, and a PMOS transistor 355 having one of the source and drain also connected to the source line SLi (i = 1 to n) and the other connected to the output VPR of the precharge power supply 315. The gates of both transistors are connected to the same column selection signal CLi (i = 1 to n).

[0136] The bit line selection circuit 350 and the source line selection circuit 353 are arranged alternately.

[0137] Only one of the n column selection signals CLi (i = 1 to n) is set to the high level, and the others are set to the low level. Only a pair of the selected bit line BLi and source line SLi are connected to the bit line input terminal BLin and the source line input terminal SLin, and the remaining non-selected bit lines BLi and source lines SLi are precharged to VPR.

[0138] Also, although the high level of the column selection signal CLi (i = 1 to n) is the external power supply VDD, a voltage higher than only the output of this signal may be applied, or a configuration paired with a PMOS transistor may be used so that the influence of the threshold voltages of the NMOS transistors 351 and 354 does not appear.

[0139] FIG. 10 is a diagram showing a circuit example of the row selection circuit 303.

[0140] The row selection circuit 303 includes a decoding circuit 370 that generates a decoding signal for designating a selected row based on the address selection instruction signal generated by the address input circuit 317, and a word line driver 371 connected to the decoding signal. The word line driver 371 has another input as the output VRD of the word line voltage switching circuit 316 and has a number corresponding to the number of word lines (m lines). Then, for the word lines WLj (j = 1 to m) corresponding to the selected row, the voltage VwL is output for a specified period during low-resistance writing, the voltage VwH is output during high-resistance writing, and the voltage Vr is output during a read operation.

[0141] The operation of the resistive change type nonvolatile memory device 4000 configured as described above will be described with reference to the timing chart shown in FIG. 11.

[0142] Here, it is defined that when the resistive change type nonvolatile memory element is in a high-resistance state, it is assigned to data "0", and when it is in a low-resistance state, it is assigned to data "1". Also, for the amplitude levels of the control signals, those without a voltage symbol have a high level of the external power supply VDD and a low level of 0V.

[0143] The explanation will be given for four cycles. Cycle T1 shows an operation example of low-resistance writing to the memory cell M11, cycle T2 shows high-resistance writing to the memory cell M12, cycle T3 shows reading of the low-resistance state of the memory cell M11, and cycle T4 shows reading of the high-resistance state of the memory cell M12.

[0144] First, the low-resistance writing operation to the memory cell M11 in cycle T1 will be described.

[0145] Initially, all word lines WLj (j = 1 to m) and column select signals CLi (i = 1 to n) are at 0V, and all memory cells are in an unselected state.

[0146] On the other hand, the precharge instruction signal NPR is a negative logic signal, and precharge is being performed at 0V. As a result, all bit lines BLi, source lines SLi (i = 1 to n), and bit line input terminals BLin, source line input terminals SLin are precharged to the voltage VPR.

[0147] And the input / output DQ terminal is set to a high level for writing the data "1".

[0148] Next, the precharge instruction signal NPR is set to a high level, and the precharged states of the bit line input terminal BLin and the source line input terminal SLin are released.

[0149] Next, upon receiving the selection instruction from the address input circuit 317, the selected word line WL1 and the selected column, i.e., the column select signal CL1, are set to a high level. At this time, the voltage of the word line WL1 becomes VwL for low-resistance writing. Also, the selected bit line BL1 and source line SL1 of the selected column have their precharge released and are connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the non-selected bit lines and non-selected source lines other than these maintain their precharge.

[0150] Next, corresponding to the write instruction of the data "1" to the input / output DQ terminal, the low-resistance write instruction signal WEL is set to a high level, and a negative logic voltage pulse Vi is set to a low level for a period of 100 ns. In response to this, the source line input terminal SLin is driven to the high potential side, and the bit line input terminal BLin is driven to the low potential side, and the selected memory cell M11 performs the constant current two-step reduction low-resistance writing operation described in detail as the basic data of the present disclosure.

[0151] Next, upon receiving the end of the low-resistance write instruction, the selected word line WL1 and the selected column selection signal CL1 are set to 0V, the memory cell M11 becomes unselected, and the precharge of the bit line BL1 and the source line SL1 is started.

[0152] Finally, the precharge instruction signal NPR is set to 0V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the low-resistance write cycle ends.

[0153] Next, the high-resistance write operation to the memory cell M12 in cycle T2 will be described.

[0154] First, all word lines WLj (j = 1 to m) and column selection signals CLi (i = 1 to n) are at 0V, and none of the memory cells are selected.

[0155] On the other hand, the precharge instruction signal NPR is at 0V and precharge is performed, and the bit lines BLi, source lines SLi (i = 1 to n), and the bit line input terminal BLin and source line input terminal SLin are precharged to the voltage VPR.

[0156] And the input / output DQ terminal is set to a low level for writing the data "0".

[0157] Next, the precharge instruction signal NPR is set to a high level, and the precharged state of the bit line input terminal BLin and the source line input terminal SLin is released.

[0158] Next, upon receiving the selection instruction from the address input circuit 317, the selected word line WL1 and the selected column selection signal CL2, which is the selected column, are set to a high level. At this time, the voltage of the word line WL1 becomes VwH for high-resistance writing. Also, the bit line BL2 and the source line SL2, which are the selected columns, have their precharge released and are connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the precharge of the other non-selected bit lines and non-selected source lines is maintained.

[0159] Next, in response to the data “0” write instruction for the input / output DQ terminal, a high-impedance write instruction signal WEH is set to the high level for a period of 100 ns. In response to this, the source line input terminal SLin is driven to the low potential side and the bit line input terminal BLin is driven to the high potential side, and the high-impedance write operation described in detail as the basic data of the present disclosure is performed on the selected memory cell M12.

[0160] Note that the cell current in this timing chart indicates its absolute value, and the flowing direction is opposite to that of cycle T1.

[0161] Next, upon receiving the end of the high-impedance write instruction, the selected word line WL1 and the selected column selection signal CL2 are set to 0 V, the memory cell M12 becomes unselected, and the precharge of the bit line BL2 and the source line SL2 is started.

[0162] Finally, the precharge instruction signal NPR is set to 0 V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the high-impedance write cycle ends.

[0163] Next, the read operation of the memory cell M11 in the low-impedance state in cycle T3 will be described.

[0164] First, all word lines WLj (j = 1 to m) and column selection signals CLi (i = 1 to n) are 0 V, and none of the memory cells are selected.

[0165] On the other hand, the precharge instruction signal NPR is 0 V and precharge instruction is performed, and the bit lines BLi, source lines SLi (i = 1 to n), and the bit line input terminal BLin and the source line input terminal SLin are precharged to the voltage VPR.

[0166] Next, the precharge instruction signal NPR is set to the high level, and the precharged states of the bit line input terminal BLin and the source line input terminal SLin are released.

[0167] Next, in response to the selection instruction of the address input circuit 317, the selection word line WL1 and the column selection signal CL1, which is the selection column, are set to the high level. At this time, the voltage of the word line WL1 becomes Vr for reading. Also, the pre-charging of the bit line BL1 and the source line SL1, which are the selected columns, is released and they are connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the pre-charging of the other non-selected bit lines and non-selected source lines is maintained.

[0168] Next, the read instruction signal RE is set to the high level during the period of the read operation (set to 150 ns here), the NMOS transistor 342 is turned on, and the selected source line SL1 is driven to the low potential side via the source line input terminal SLin. At the same time, the NMOS transistor 341 is turned on, and the selected bit line BL1 is connected to the bit line output signal BLout via the bit line input terminal BLin. The bit line output signal BLout is connected to the read circuit 305 and discriminates data "1" or data "0" based on the magnitude of the current flowing from the bit line BL side to the source line SL side. The memory cell M11 is written in the low resistance state, and more current flows compared to the case of the high resistance state. The read circuit 305 determines it as data "1", and a high level is output from the input / output DQ terminal.

[0169] Next, upon receiving the end of the read instruction, the selected word line WL1 and the selected column selection signal CL1 are set to 0V, the memory cell M11 becomes unselected, and the pre-charging of the bit line BL1 and the source line SL1 is started.

[0170] Finally, the pre-charge instruction signal NPR is set to 0V, the pre-charging of the bit line input terminal BLin and the source line input terminal SLin is started, and the read operation cycle ends.

[0171] The read operation of the memory cell M12 in the high-resistance state during cycle T4 is the same as that in cycle T3 except that the selection column is different, the selected memory cell M12 is written in the high-resistance state, and the current is less than that in the low-resistance state. The read circuit 305 determines the data as "0" and outputs a low level from the input / output DQ terminal, so detailed description is omitted.

[0172] The above is the description of the operation of the resistive change type non-volatile memory device 4000. Regarding the precharging of the unselected bit line and the unselected source line to a predetermined voltage VPR, the effect will be described with reference to FIG. 12.

[0173] FIG. 12 is a bias diagram of the memory cell of the resistive change type non-volatile memory device in the embodiment.

[0174] The memory cell state shown in FIG. 12(a) schematically illustrates in a cross-sectional view the state of the selected memory cell that has performed the low-resistance writing described as an example in this embodiment, and corresponds to the state of the selected memory cell M11 in cycle T1 described in FIG. 11.

[0175] The memory cell transistor 402 is composed of a gate electrode 404 which is also a word line, a gate oxide film 405, a drain 406 of an N-type diffusion layer connected to the source line SL, and a source 407 of an N-type diffusion layer on the semiconductor substrate 401. The source 407 is connected to the lower electrode of the resistive change type non-volatile memory element RSE, and the upper electrode is connected to the bit line BL.

[0176] For low-resistance writing, the source line SL is set to approximately the voltage VdL-α (α represents the voltage drop due to the current limiting elements 26 and 27 for LR conversion), the bit line is set to a low voltage of 0V, and the word line is given the voltage VwL. The memory cell transistor 402 is turned on, a channel 408 is formed, and current flows from the drain 406 to the source 407.

[0177] Generally, as the manufacturing process is miniaturized, the memory cells are also miniaturized, enabling higher integration. In that case, the planar size of the memory cell transistor 402 is reduced, and the gate oxide film 405 is also thinned. Therefore, the maximum voltage that can be applied to the gate electrode 404 decreases as miniaturization progresses.

[0178] Therefore, for the high reliability of the memory cell, control to relax the electric field applied to the gate oxide film 405 is important.

[0179] In this embodiment, since the channel 408 is formed in the selected memory cell 400, substantially the electric field between the gate electrode 404 and the channel 408 is applied to the gate oxide film 405. In the case of low-resistance writing, the electric field applied to the gate oxide film 405 is highest in the channel 408 near the source 407 with a lower voltage. Although the bit line BL is 0V, a current flows through the resistive change type nonvolatile memory element RSE. Therefore, the potential of the source 407 increases by the voltage between the terminals of the resistive change type nonvolatile memory element RSE (about 1 to 1.2V), and substantially the potential difference between the gate electrode 404 and the channel 408 can be relaxed to about 1.8V to 2.0V.

[0180] The memory cell state shown in Fig. 12(b) schematically illustrates in a cross-sectional view the states of non-selected memory cells in the same row as the selected memory cell in which the low-resistance writing described in this embodiment is being performed. The states of non-selected memory cells M12, etc. in cycle T1 described in Fig. 11 correspond to this. The source line SL and the bit line BL of the non-selected column are pre-charged to the voltage VPR (1.1V). Since the resistive change type non-volatile memory element RSE has conductivity, the voltage of the source 407 of the N-type diffusion layer also becomes VPR together with the drain 406 of the N-type diffusion layer. For the selected row, the gate electrode 404 has the voltage VwL, and both the gate-source potential and the gate-drain potential are equal to or higher than the threshold voltage of the memory cell transistor 402, so that the memory cell transistor 402 turns on and the channel 411 is formed. The voltage of this channel 411 becomes the same VPR as the bit line BL and the source line SL. Therefore, the potential difference between the gate electrode 404 and the channel 411 can be relaxed to 1.9V.

[0181] On the other hand, the memory cell state shown in Fig. 12(c) illustrates the case where the bit line BL and the source line SL of the non-selected memory cell in the same row as the selected memory cell in which low-resistance writing is being performed are pre-charged to 0V, which is generally performed conventionally. In this case, the voltage of the channel 421 becomes the same 0V as the bit line BL and the source line SL. The potential difference between the gate electrode 404 and the channel 421 becomes 3.0V, which is 1V or more higher than the memory cell state in Fig. 12(b), and is not very desirable when applying a finer process.

[0182] The memory cell state in Fig. 12(d) illustrates the state when the bit line BL and the source line SL of the non - selected memory cells in the same row as the selected memory cell where low - resistance writing is being performed are pre - charged to the same voltage as the voltage VwL of the gate electrode 404, which is the opposite of the memory cell state in Fig. 12(c). In this case, the memory cell transistor 402 is off and no channel is formed. Therefore, an electric field is applied across the gate oxide film 405 between the gate electrode 404 and the semiconductor substrate 401. Since the semiconductor substrate 401 is generally set to 0V, substantially, in terms of the electric field of the gate oxide film 405 in the memory cell state of Fig. 12(c), it is also 3.0V, which is not very desirable when applying a finer process.

[0183] From the above, the pre - charge voltage VPR of the source line SL and the bit line BL of the memory cells in the non - selected column is set to be lower than the voltage obtained by subtracting the threshold voltage Vtns of the memory cell transistor 402 from the voltage VwL of the selected word line and higher than 0V so that a channel is formed, and it can be applied to a finer process. That is, the pre - charge voltage VPR may be set as follows.

[0184] 0V < VPR < VwL - Vtns

[0185] In this case, the pre - charge voltage VPR is desirably set to a voltage less than VwL - Vtns and higher in terms of reducing the electric field of the gate oxide film 405. On the other hand, pre - charging all non - selected bit lines and non - selected source lines to a predetermined voltage also leads to the contradictory problem of increased power consumption.

[0186] Considering the balance between the two, for example, it may be set to the optimal pre - charge voltage VPR such as VPR=(VwL - Vtns) / 2.

[0187] Also, in this embodiment, in order to reduce the low - resistance writing current in two steps of constant current, the current waveform control circuit 24 is provided on the side of the LR - conversion power supply terminal 11. Needless to say, a current waveform control circuit having a similar function may be provided on the GND terminal side.

[0188] Furthermore, in this embodiment, the memory cell transistor is used as the switching element, but a bidirectional diode may be used to reduce the cell area.

[0189] Also, in this embodiment, tantalum oxide is used as the resistance change layer 85, but the same effect can be achieved by using tantalum-aluminum oxide (TaAlO) obtained by adding aluminum (Al) to tantalum oxide.

[0190] [3. Modified Example] Next, a modified example of the main part of the resistive change type nonvolatile memory device in the embodiment will be described.

[0191] Figure 15 FIG. is a diagram showing a modified example of the main part of the resistive change type nonvolatile memory device in the embodiment. The resistive change type nonvolatile memory device 2 in this figure is different in that it includes a current waveform control circuit 24a instead of the current waveform control circuit 24 as compared with FIG. 1A. Hereinafter, the same points will be omitted from the description to avoid duplication, and the different points will be mainly described.

[0192] The current waveform control circuit 24a includes a waveform generation unit 35, a DAC 36, and a transistor 37.

[0193] The waveform generation unit 35 generates waveform data Ctl, which is a digital signal indicating the current waveform of the low-resistance current. The waveform generation unit 35 is composed of, for example, a ROM that stores time-series sample values indicating the waveform data Ctl, or a dedicated circuit.

[0194] The DAC 36 is a digital-to-analog conversion circuit that converts the waveform data Ctl from the waveform generation unit 35 into an analog signal. The DAC 36 supplies the converted analog signal to the gate of the transistor 37 as the gate voltage Vgp.

[0195] The transistor 37 is a pMOS transistor that serves as a current source for supplying a current with a waveform corresponding to the gate voltage Vgp to the memory cell 3 via the LR-improved SL selection switch 14.

[0196] Figure 16 is a diagram showing a modified example of the current waveform of the current with reduced resistance in the embodiment. (a) of the figure shows the gate voltage Vgp output from the DAC 36 to the gate of the transistor 37. The current in (b) of the figure shows the current with reduced resistance output from the transistor 37. Since the transistor 37 is a pMOS transistor, the current with reduced resistance has a waveform inverted with respect to the change in the gate voltage Vgp.

[0197] The current waveform of the current with reduced resistance has one first period and a second period following the first period on the time axis. The portion corresponding to the first period in the current with reduced resistance is called the first current. The portion corresponding to the second period in the current with reduced resistance is called the second current. In (b) of the figure, the first current is a triangular wave and has a first peak current Ip1. The second current is a substantially constant current and has a current value Ip2 smaller than the first peak current Ip1. Also, the first current at the time t2 at the end of the first period is not 0, and the second current Ip2 at the time t2 at the start of the second period is not 0. That is, the first current does not drop from the peak to 0 within the first period, and the second current is a value not equal to 0 at the start of the second period.

[0198] Even if the current waveform of the current with reduced resistance is Figure 16 a waveform like that in (b) of, the same effect as that of FIG. 1B can be obtained.

[0199] Furthermore, another modified example of the current waveform of the current with reduced resistance will be described.

[0200] Figure 17 is a diagram showing another modified example of the current waveform of the current with reduced resistance in a modified example of the embodiment.

[0201] In the example of (a) in the figure, the current for reducing resistance has a current waveform with a sawtooth shape having a steep fall in the first period. The time width of the first period, the time width of the second period, the peak value Ip1 of the first current, and the second current Ip2 may be the same as those in FIG. 1B.

[0202] In the example of (b) in the figure, the current for reducing resistance has a current waveform with a sawtooth shape having a steep rise in the first period.

[0203] The example of (c) in the figure is Figure 16 the same as (b) of

[0204] In the example of (d) in the figure, the current for reducing resistance has a triangular current shape in the first period and a current waveform in which the second current decreases stepwise in the second period.

[0205] In the example of (e) in the figure, the current for reducing resistance has two or more sets of the first period and the second period as in (c) of the figure. The time width of the first period, the time width of the second period, the peak value Ip1 of the first current, and the second current Ip2 do not have to be the same as those in FIG. 1B.

[0206] As described above, the resistance change type nonvolatile memory device 2 according to one aspect of the embodiment includes a resistance change element (RSE) capable of reversibly changing between a high resistance state and a low resistance state, and a current waveform control circuit 24a as a current supply circuit that supplies a current for changing from the high resistance state to the low resistance state to the resistance change element. The current waveform of the current for reducing resistance has a first period and a second period following the first period on the time axis. The current supply circuit 24a applies a first current to the resistance change element in the first period and applies a second current smaller than the first current to the resistance change element in the second period. The first current at the end of the first period is not zero, and the second current at the start of the second period is not zero.

[0207] According to this, in the writing for changing from the high-resistance state to the low-resistance state, deterioration of the initial window can be suppressed, and deterioration of the operation window during high cycling (for example, during 100,000 rewritings) can be suppressed. For example, even when miniaturized, a highly reliable and stable rewriting operation can be realized over a long period of time.

[0208] Here, the first current may be a constant current.

[0209] According to this, it is possible to use a constant current source as the current waveform control circuit 24a.

[0210] Here, the first current may have a peak value larger than that of the second current.

[0211] According to this, the current waveform control circuit 24a can use a waveform that is not a constant current as the first current.

[0212] Here, the current for reducing the resistance may also have a downward staircase-shaped current waveform.

[0213] According to this, the current waveform control circuit 24a generates the first current and the second current as a downward staircase-shaped current waveform. Also by this, the above-mentioned deterioration of the initial window can be suppressed, and deterioration of the operation window during high cycling (for example, during 100,000 rewritings) can be suppressed.

[0214] Here, the current waveform control circuit 24a as the current supply circuit may energize the first constant current to the resistance change element in the first period, and energize a second constant current smaller than the first constant current to the resistance change element in the second period.

[0215] According to this, in the writing for changing from the high resistance state to the low resistance state, driving is performed to reduce the constant current in two steps. This driving is called constant current two-step reduction driving. This driving is suitable for generating the downward staircase-shaped current waveform described above. Note that the energization period is not limited to having only the first period and the second period, and may separately have third, fourth, ··· n periods.

[0216] Here, the current waveform control circuit 24 as the current supply circuit includes an LR conversion current limiting element 26 as a first constant current source and an LR conversion current limiting element 27 as a second constant current source. The current supply circuit may generate the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source in the first period, and generate the second constant current as the constant current from either the first constant current source or the second constant current source in the second period.

[0217] According to this, since a higher current value than in the second period is applied to the resistance change element in the first period, an initial window can be sufficiently secured. Since a lower current value than in the first period is applied to the resistance change element in the second period, window deterioration during high cycling can be suppressed.

[0218] Here, the current waveform control circuit 24 as the current supply circuit further includes a constant current control switch 31 as a first switch connected in series with the first constant current source and a constant current control switch 32 as a second switch connected in series with the second constant current source. The current supply circuit may energize the first constant current to the resistance change element by turning on both the first switch and the second switch in the first period, and energize the second constant current to the resistance change element by turning one of the first switch and the second switch off and the other on in the second period.

[0219] According to this, a downward staircase-shaped current waveform can be easily generated by the operations of the first switch and the second switch.

[0220] Here, the first period may be shorter than the second period.

[0221] According to this, it is possible to expand the operation window in the first period in which a relatively high first constant current is applied, and suppress the deterioration of the operation window due to high-cycling operation in the second period in which a relatively low second constant current is applied.

[0222] Here, the first period may be 10% or less of the second period.

[0223] According to this, it is possible to expand the operation window in the first period which is 10% or less of the second period.

[0224] Here, the first period may be 5n seconds or less, and the second period may be 50n seconds or more.

[0225] According to this, it is possible to perform the writing operation to the low-resistance state at high speed.

[0226] Here, the second constant current may be 60% or less of the first constant current.

[0227] According to this, it is possible to reduce the power consumption of the writing operation to the low-resistance state.

[0228] Here, the first constant current may be 125 μA or more, and the second constant current may be 75 μA or less.

[0229] According to this, it is possible to reduce the power consumption of the writing operation to the low-resistance state.

[0230] Here, the resistance change element RSE includes a first electrode 81, a second electrode 84 formed to face the first electrode, and a resistance change layer 85 interposed between the first electrode 81 and the second electrode 84, and the resistance change layer 85 may have a configuration including a transition metal oxide.

[0231] Here, the transition metal oxide may contain at least one oxide of tantalum or hafnium.

[0232] Here, the resistance change element is formed on a semiconductor substrate, and the second electrode 84 may be formed farther from the semiconductor substrate than the first electrode 81.

[0233] Here, the resistance change type nonvolatile memory device may include a plurality of memory cells arranged in a matrix, and the memory cell may include a switch element and the resistance change element connected in series with the switch element.

[0234] Here, the switch element may be an NMOS transistor or a bidirectional diode.

[0235] Further, a writing method of a resistance change type nonvolatile memory device according to an embodiment is a writing method for changing a resistance change element RSE, which can reversibly change between a high resistance state and a low resistance state, from the high resistance state to the low resistance state in a resistance change type nonvolatile memory device having the resistance change element as a memory cell, and includes passing a first constant current through the resistance change element in a first period, and passing a second constant current smaller than the first constant current through the resistance change element in a second period following the first period.

[0236] According to this, in rewriting from the high resistance state to the low resistance state, deterioration of the initial window can be suppressed, and deterioration of the operation window during high cycling can be suppressed. Therefore, it is suitable for miniaturization.

[0237] Note that, without departing from the gist of the present disclosure, a resistance change type nonvolatile memory device realized by making various modifications conceived by those skilled in the art or arbitrarily combining the components in the embodiment, and a writing method thereof are also included in the present disclosure.

Industrial Applicability

[0238] As described above, in the resistive change type nonvolatile memory device having a memory cell composed of a resistive change element whose resistance value changes reversibly based on an electrical signal and a switch element such as a transistor, the practical write control method can improve the number of rewritable times in a simple manner with a circuit area without significantly increasing the array area, and thus is useful for realizing a highly reliable memory.

Explanation of Signs

[0239] 1, 402 Memory cell transistor 2 Resistive change type nonvolatile memory device 3 Memory cell 10, 333, 335, 338, 340, 352, 355 PMOS transistor 11 Power supply terminal for LR conversion 12 Clamp control terminal for LR conversion 13 BL selection switch for LR conversion 14 SL selection switch for LR conversion 16 BL selection switch for HR conversion 17 Power supply terminal for HR conversion 18 SL selection switch for HR conversion 22a, 23 Source line drive circuit 22b Bit line drive circuit 24, 24a Current waveform control circuit (current supply circuit) 25 Constant current control circuit 26 Current limiting element for LR conversion (first constant current source) 27 Current limiting element for LR conversion (second constant current source) 28 Delay circuit 29 NAND circuit 30, 332, 337 Inverter 31 Constant current control switch (first switch) 32 Constant current control switch (second switch) 33 Write pulse width control terminal 35 Waveform generation unit 36 DAC 37 Transistor 81 First electrode (lower electrode) 82 First transition metal oxide layer 83 Second transition metal oxide layer 84 Second electrode (upper electrode) 85 Resistance change layer 86 Filament 300 Memory main body 301 Memory array 302 Column selection circuit 303 Row selection circuit 304 Writing circuit 305 Reading circuit 306 Peripheral circuit section 307 Control circuit 308 Voltage generation circuit 309 Word line power supply for low resistance conversion 310 Word line power supply for high resistance conversion 311 Word line power supply for reading 312 Low resistance clamping power supply 313 Pulse power supply for low resistance conversion 314 Pulse power supply for high resistance conversion 315 Precharge power supply 316 Word line voltage switching circuit 317 Address input circuit 318 Input / output circuit 330 Source line writing circuit 334, 342, 339, 341, 351, 354 NMOS transistor 336 Bit line writing circuit 350 Bit line selection circuit 353 Source line selection circuit 370 Decoding circuit 371 Word line driver 400 Selected memory cell 401 Semiconductor substrate 404 Gate electrode 405 Gate oxide film 406 Drain 407 Source 408, 411, 421 Channel 520 Ultra-high resistance state 3000a Resistance change type non-volatile memory element 4000 Resistance-change type nonvolatile memory device RSE Resistance-change type nonvolatile memory element

Claims

1. A resistive change element capable of reversibly changing between a high-resistance state and a low-resistance state, and a current supply circuit that supplies a current for changing the resistance from the high-resistance state to the low-resistance state to the resistive change element, wherein the current waveform of the current for reducing the resistance has, on the time axis, a first period rising from a current of 0 and a second period following the first period and falling to a current of 0, the current supply circuit applies a first current, which is a constant current, to the resistive change element in the first period, applies a second current, which is a constant current smaller than the first current, to the resistive change element in the second period, the first current at the end of the first period is not 0, and the second current at the start of the second period is not 0 A resistive change type nonvolatile memory device.

2. The current for reducing the resistance has a downward staircase-shaped current waveform The resistive change type nonvolatile memory device according to claim 1.

3. The current supply circuit applies a first constant current to the resistive change element in the first period, and applies a second constant current smaller than the first constant current to the resistive change element in the second period The resistive change type nonvolatile memory device according to claim 1 or 2.

4. The current supply circuit includes a first constant current source, and a second constant current source, the current supply circuit generates the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source in the first period, and generates, as the second constant current, the constant current from either the first constant current source or the second constant current source in the second period The resistive change type nonvolatile memory device according to claim 3.

5. The current supply circuit includes a first switch connected to the first constant current source, and a second switch connected to the second constant current source, the current supply circuit applies the first constant current to the resistive change element by turning on both the first switch and the second switch in the first period, and applies the second constant current to the resistive change element by turning off one of the first switch and the second switch and turning on the other in the second period The resistive change type nonvolatile memory device according to claim 4.

6. The first period is shorter than the second period The resistive change type nonvolatile memory device according to any one of claims 1 to 5.

7. The first period is 10% or less of the second period The resistive change type nonvolatile memory device according to any one of claims 1 to 6.

8. The first period is 5 ns or less, The second period is 50 ns or more The resistive change type nonvolatile memory device according to any one of claims 1 to 6.

9. The second constant current is 60% or less of the first constant current The resistive change type nonvolatile memory device according to any one of claims 3 to 5.

10. The first constant current is 125 μA or more, The second constant current is 75 μA or less The resistive change type nonvolatile memory device according to any one of claims 3 to 5.

11. The resistive change element, A first electrode, A second electrode formed to face the first electrode, A resistive change layer interposed between the first electrode and the second electrode, and has, The resistive change layer contains a transition metal oxide The resistive change type nonvolatile memory device according to any one of claims 1 to 10.

12. The transition metal oxide contains at least one oxide of tantalum and hafnium The resistive change type nonvolatile memory device according to claim 11.

13. The resistive change element is formed on a semiconductor substrate, The second electrode is formed farther from the semiconductor substrate than the first electrode The resistive change type nonvolatile memory device according to claim 11 or 12.

14. The resistive change type nonvolatile memory device includes a plurality of memory cells arranged in a matrix, The memory cell has a switch element and the resistive change element connected in series with the switch element The resistive change type nonvolatile memory device according to any one of claims 1 to 13.

15. The switch element is an NMOS transistor or a bidirectional diode The resistive change type nonvolatile memory device according to claim 14.

16. In a resistive change type nonvolatile memory device having a resistive change element that can reversibly change between a high resistance state and a low resistance state as a memory cell, a writing method for changing the resistive change element from the high resistance state to the low resistance state, Applying a first current, which is a constant current, to the resistive change element in a first period rising from a current of 0, Applying a second current, which is a constant current smaller than the first current, to the resistive change element in a second period following the first period and falling to a current of 0, The first current at the end of the first period is not 0, The second current at the start of the second period is not 0 A writing method for a resistive change type nonvolatile memory device.

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