Semiconductor integrated circuit device

Abstract

This semiconductor integrated circuit device (1) is provided with a ring oscillator (5) of plural stages having delay circuits (10). In each delay circuit (10), when the signal at the input terminal (IN) makes a first transition, the signal at the output terminal (OUT) transitions by the action of a first transistor (N1), which corresponds to the transistor within an SRAM cell (20). When the signal at the input terminal (IN) makes a second transition, the first transistor (N1) is electrically isolated from the output terminal (OUT), and the signal at the output terminal (OUT) transitions by the action of a second transistor (P2).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit device having a configuration for measuring the delay characteristics of transistors.

Background Art

[0002] In a semiconductor integrated circuit equipped with SRAM (Static Random Access Memory), there is a technique for measuring the delay characteristics of transistors constituting the SRAM using a ring oscillator in order to measure the influence of manufacturing variations of the SRAM.

[0003] Patent Document 1 discloses a technique for independently measuring the rise / fall characteristics of transistors constituting SRAM by incorporating the transistors constituting the SRAM into a delay circuit constituting a ring oscillator and measuring the oscillation frequency of the ring oscillator.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technique of Patent Document 1, the accuracy of measuring the delay characteristics of the transistors to be evaluated is low. Specifically, in one cycle of the oscillation operation of the ring oscillator, the signal path includes four transistors, and the transistor to be evaluated is one of them. Therefore, in the delay operation for oscillation, the proportion of the delay due to the transistor to be evaluated is low. Also, if the load connected to the output of the transistor to be evaluated is increased in order to increase the delay due to the transistor to be evaluated, the load of the other transistors also increases, so the proportion of the delay due to the transistor to be evaluated in the delay operation does not increase much.

[0006] This disclosure aims to improve the accuracy of measuring the delay characteristics of transistors to be evaluated in a semiconductor integrated circuit device.

Means for Solving the Problem

[0007] In an aspect of this disclosure, a semiconductor integrated circuit device includes an SRAM circuit block including SRAM cells and a ring oscillator having a plurality of stages of delay circuits. Each of the delay circuits corresponds to a transistor in the SRAM cell and includes a first transistor of a first conductivity type having a gate connected to the input terminal, a source connected to a first power supply; a second transistor of a second conductivity type having a gate connected to the input terminal, a source connected to a second power supply, and a drain connected to the output terminal; and a third transistor of the first conductivity type having a gate connected to the input terminal, a source connected to the drain of the first transistor, and a drain connected to the output terminal. When a signal applied to the input terminal makes a first transition, the first and third transistors conduct, the second transistor does not conduct, and the drain of the first transistor is electrically connected to the output terminal due to the conduction of the third transistor, and the signal at the output terminal transitions due to the operation of the first transistor. When the signal applied to the input terminal makes a second transition opposite to the first transition, the first and third transistors do not conduct, the second transistor conducts, the drain of the first transistor is electrically separated from the output terminal due to the non-conduction of the third transistor, and the signal at the output terminal transitions due to the operation of the second transistor.

[0008] According to this aspect, the semiconductor integrated circuit device includes a ring oscillator having a plurality of stages of delay circuits. In each delay circuit, when the signal applied to the input terminal makes a first transition, the signal at the output terminal transitions due to the operation of the first transistor corresponding to the transistor in the SRAM cell. Also, when the signal applied to the input terminal makes a second transition, the first transistor corresponding to the transistor in the SRAM cell is electrically separated from the output terminal, and the signal at the output terminal transitions due to the operation of the second transistor. Therefore, by increasing the load capacitance connected to the output of the first transistor, the ratio of the delay caused by the first transistor in the oscillation period of the ring oscillator can be increased. Thus, the measurement accuracy of the delay characteristics of the first transistor can be improved.

Effect of the Invention

[0009] According to the semiconductor integrated circuit device according to the present disclosure, the accuracy of measuring the delay characteristics of the transistor to be evaluated can be increased.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, "IN" and "OUT" are used as both the symbols for the terminal names and the signal names. Also, the high level and low level of the signal may be simply referred to as "high" and "low".

[0012] FIG. 1 is a plan view schematically showing the overall configuration of a semiconductor integrated circuit device according to an embodiment. In the semiconductor integrated circuit device 1 of FIG. 1, a plurality of SRAM (Static Random Access Memory) circuit blocks 2 and a plurality of characteristic measurement circuits 3 are provided on a semiconductor substrate.

[0013] FIG. 2 is an example of the circuit configuration of an SRAM cell. The SRAM cell 20 shown in FIG. 2 includes P-type load transistors LD1 and LD2, N-type drive transistors DV1 and DV2, and N-type access transistors XF1 and XF2. By applying a high level to the word line WL, data can be read from the bit line pair BL and / BL, and data can be written to the bit line pair BL and / BL. The SRAM circuit block 2 includes a plurality of SRAM cells 20.

[0014] The characteristic measurement circuit 3 includes a ring oscillator described later. By measuring the oscillation frequency of the ring oscillator, the delay characteristics of the transistors of the SRAM cell 20 can be measured. In FIG. 1, five characteristic measurement circuits 3 are provided in the central part and the vicinity of the four corners of the semiconductor integrated circuit device 1, but the number and arrangement position of the characteristic measurement circuits 3 are not limited to those shown here. By providing a plurality of characteristic measurement circuits 3, the within-chip variation in the delay characteristics of the transistors can be measured.

[0015] FIG. 3 is an example of the configuration of a ring oscillator included in the characteristic measurement circuit. The ring oscillator 5 shown in FIG. 3 includes 2N (N is a natural number) stages of delay circuits 10 connected in series and a NAND circuit 15. The value of N is, for example, 100 or more. In each delay circuit 10, the logic of the signal is inverted. The NAND circuit 15 takes an enable signal EN and the output OUT of the last stage delay circuit 10 as inputs. The output of the NAND circuit 15 is given to the input IN of the first stage delay circuit 10. The output signal OUT of the last stage delay circuit 10 is output as the output signal OUT of the ring oscillator 5.

[0016] When the enable signal EN is low, the output of the NAND circuit 15 goes high. The outputs OUT of the respective delay circuits 10 alternate between low and high, and the output signal OUT of the ring oscillator 5 goes high. By setting the enable signal EN high, the oscillation operation of the ring oscillator 5 is started, and an oscillation signal is output as the output signal OUT. By measuring the oscillation frequency of the output signal OUT, the delay characteristics of the transistor can be measured.

[0017] <First Example> FIG. 4 shows a first example of the circuit configuration of the delay circuit. The delay circuit 10 shown in FIG. 4 includes P-type transistors P1 and P2 and N-type transistors N1 and N2. In the delay circuit 10 shown in FIG. 4, the delay characteristics of the transistor N1 corresponding to the N-type transistor of the SRAM cell can be measured.

[0018] The transistors P1 and N1 are connected in series between VDD as the high-voltage side power supply and VSS as the low-voltage side power supply, and their gates are connected to each other. That is, the transistors P1 and N1 form an inverter 11. The gates of the transistors P1 and N1 are connected to the input terminal IN. The transistors P1 and N1 respectively correspond to the transistors LD2 and DV2 in the SRAM cell 20 shown in FIG. 2. That is, the transistors P1 and N1 have the same size as the transistors LD2 and DV2, respectively.

[0019] The transistor P2 (pull-up transistor) has its gate connected to the input terminal IN, its source connected to VDD, and its drain connected to the output terminal OUT. When the input signal IN is low, the transistor P2 electrically connects VDD and the output terminal OUT.

[0020] The transistor N2 (load separation transistor) has its gate connected to the input terminal IN and its drain connected to the output terminal OUT. Also, its source is connected to the drains of the transistors P1 and N, that is, to the output of the inverter 11. When the input signal IN is low, the transistor N2 electrically separates the output of the inverter 11 and the output terminal OUT.

[0021] A large load capacitance LD is provided at the output node of the inverter 11. The load capacitance LD is realized by wiring, capacitance, etc. such that the load is larger than the load capacitance connected to the output terminal OUT. For example, the load capacitance LD is realized by wiring with a long wiring length, dummy gates, etc.

[0022] The delay circuit 10 shown in FIG. 4 operates as follows. When the signal IN transitions from low to high, the transistor N2 turns on and the output of the inverter 11 is electrically connected to the output terminal OUT. Also, the transistor P2 turns off. Then, when the transistor N1 turns on, the output signal OUT goes from high to low with a delay T_fN1. The delay T_fN1 is the delay when the output of the transistor N1 rises.

[0023] When the signal IN transitions from high to low, the transistor N2 turns off and the output of the inverter 11 and the output terminal OUT are electrically separated. Then, when the transistor P2 turns on, the output signal OUT goes from low to high with a delay T_rP2. The delay T_rP2 is the delay when the output of the transistor P2 rises.

[0024] And the load capacitance LD is connected to the output terminal OUT when the signal IN transitions from low to high, but is not connected to the output terminal OUT when the signal IN transitions from high to low. Therefore, the relationship between the delay T_fN1 and the delay T_rP2 is T_fN1 > T_rP2 as follows.

[0025] When measuring the delay characteristics of transistor N1, the ring oscillator 5 in FIG. 3 operates as follows. Set the enable signal EN high. When the input of the NAND circuit 15 transitions from low to high, the output of the NAND circuit 15 transitions from high to low. Let the delay at this time be T_fNAND. Since the input IN of the first-stage delay circuit 10 transitions from high to low, the output OUT transitions from low to high with a delay of T_rP2. Since the input IN of the second-stage delay circuit 10 transitions from low to high, the output OUT transitions from high to low with a delay of T_fN1. Since the subsequent delay circuits 10 from the third stage onward perform the same operation, the output signal OUT transitions from high to low with a delay of N(T_fN1 + T_rP2) in the entire 2N-stage delay circuit 10.

[0026] This output signal is fed back to the NAND circuit 15, and the output of the NAND circuit 15 transitions from low to high. Let the delay at this time be T_rNAND. Since the input IN of the first-stage delay circuit 10 transitions from low to high, the output OUT transitions from high to low with a delay of T_fN1. Since the input IN of the second-stage delay circuit 10 transitions from high to low, the output OUT transitions from low to high with a delay of T_rP2. Since the subsequent delay circuits 10 from the third stage onward perform the same operation, the output signal OUT transitions from low to high with a delay of N(T_fN1 + T_rP2) in the entire 2N-stage delay circuit 10.

[0027] The above-described operation constitutes one cycle of the oscillation operation of the ring oscillator 5. Therefore, the period T_cycle1 of the oscillation operation is T_cycle1 = T_fNAND + T_rNAND + 2N(T_fN1 + T_rP2) That is.

[0028] Thus, by increasing the value of N and increasing the load capacitance LD in FIG. 4, the ratio of the delay T_fN1 to the period T_cycle1 of the oscillation operation can be increased. Therefore, the accuracy of measuring the delay characteristics of transistor N1 can be improved.

[0029] <Second Example> FIG. 5 shows a second example of the circuit configuration of the delay circuit. The delay circuit 10 shown in FIG. 5 includes P-type transistors P1 and P3 and N-type transistors N1 and N3. In the delay circuit 10 shown in FIG. 5, the delay characteristics of the transistor P1 corresponding to the P-type transistor of the SRAM cell can be measured. Note that the description of the components common to FIG. 4 may be omitted.

[0030] The transistor N3 (pull-down transistor) has its gate connected to the input terminal IN, its source connected to VSS, and its drain connected to the output terminal OUT. When the input signal IN is high, the transistor N3 electrically connects VSS and the output terminal OUT.

[0031] The transistor P3 (load separation transistor) has its gate connected to the input terminal IN and its drain connected to the output terminal OUT. Also, its source is connected to the drains of the transistors P1 and N1, that is, the output of the inverter 11. When the input signal IN is high, the transistor P3 electrically separates the output of the inverter 11 and the output terminal OUT.

[0032] The delay circuit 10 shown in FIG. 5 operates as follows. When the signal IN transitions from high to low, the transistor P3 turns on, and the output of the inverter 11 is electrically connected to the output terminal OUT. Also, the transistor N3 turns off. Then, when the transistor P1 turns on, the output signal OUT goes from low to high with a delay T_rP1. The delay T_rP1 is the delay when the output of the transistor P1 rise rises.

[0033] When the signal IN transitions from low to high, the transistor P3 turns off, and the output of the inverter 11 and the output terminal OUT are electrically separated. Then, when the transistor N3 turns on, the output signal OUT goes from high to low with a delay T_fN3. The delay T_fN3 is the delay when the output of the transistor N3 falls.

[0034] And when the load capacitance LD is connected to the output terminal OUT when the signal IN transitions from high to low, it is not connected to the output terminal OUT when the signal IN transitions from low to high. Therefore, the relationship between the delay TrP1 and the delay TfN3 is TrP1 > TfN3 which holds.

[0035] When measuring the delay characteristics of the transistor P1, the ring oscillator 5 in FIG. 3 operates as follows. The enable signal EN is set high. When the input of the NAND circuit 15 transitions from low to high, the output of the NAND circuit 15 transitions from high to low with a delay TfNAND. Since the input IN of the first-stage delay circuit 10 transitions from high to low, the output OUT transitions from low to high with a delay TrP1. Since the input IN of the second-stage delay circuit 10 transitions from low to high, the output OUT transitions from high to low with a delay TfN3. Since the subsequent delay circuits 10 from the third stage onward perform the same operation, the output signal OUT transitions from high to low with a delay of N(TrP1 + TfN3) in the entire 2N-stage delay circuit 10.

[0036] This output signal is fed back to the NAND circuit 15, and the output of the NAND circuit 15 transitions from low to high with a delay TrNAND. Since the input IN of the first-stage delay circuit 10 transitions from low to high, the output OUT transitions from high to low with a delay TfN3. Since the input IN of the second-stage delay circuit 10 transitions from high to low, the output OUT transitions from low to high with a delay TrP1. Since the subsequent delay circuits 10 from the third stage onward perform the same operation, the output signal OUT transitions from low to high with a delay of N(TrP1 + TfN3) in the entire 2N-stage delay circuit 10.

[0037] The above-described operation constitutes one cycle of the oscillation operation of the ring oscillator 5. Therefore, the period Tcycle2 of the oscillation operation is Tcycle2 = TfNAND + TrNAND + 2N(TrP1 + TfN3) It becomes

[0038] By doing so, while increasing the value of N and increasing the load capacitance LD in FIG. 5, the ratio of the delay TrP1 to the oscillation period T_cycle2 of the oscillation operation can be increased. Therefore, the accuracy of measuring the delay characteristics of the transistor P1 can be improved.

[0039] As described above, according to the present embodiment, the semiconductor integrated circuit device 1 includes a ring oscillator 5 having a plurality of stages of delay circuits 10. In each delay circuit 10, when the signal applied to the input terminal IN makes a first transition, the signal at the output terminal OUT transitions due to the operation of the first transistor (N1 in FIG. 4, P1 in FIG. 5) corresponding to the transistor in the SRAM cell 20. Also, when the signal applied to the input terminal IN makes a second transition, the first transistor corresponding to the transistor in the SRAM cell 20 is electrically separated from the output terminal OUT, and the signal at the output terminal OUT transitions due to the operation of the second transistor (P2 in FIG. 4, N3 in FIG. 5). For this reason, by increasing the load capacitance LD connected to the output of the first transistor, the ratio of the delay by the first transistor to the oscillation period of the ring oscillator 5 can be increased. Therefore, the accuracy of the delay characteristics of the first transistor can be improved.

[0040] (Other embodiments) (Part 1) The above-described first example and second example may be implemented independently or both may be implemented. That is, the semiconductor integrated circuit device according to the present disclosure may include a first ring oscillator having a delay circuit according to the first example and a second ring oscillator having a delay circuit according to the second example.

[0041] (Part 2) In the above-described embodiment, the semiconductor integrated circuit device is provided with an SRAM circuit block. However, the semiconductor integrated circuit device according to the present disclosure is not limited thereto. For example, the semiconductor integrated circuit device according to the present disclosure may be provided with a logic circuit, and a characteristic measurement circuit for evaluating the characteristics of transistors corresponding to the transistors in the logic circuit may include a ring oscillator having the delay circuit shown in the present disclosure.

Industrial Applicability

[0042] According to the present disclosure, the accuracy of measuring the delay characteristics of the transistors to be evaluated can be improved. Therefore, for example, it is useful for improving the performance of LSIs.

Explanation of Signs

[0043] 1 Semiconductor integrated circuit device 2 SRAM circuit block 3 Characteristic evaluation circuit 5 Ring oscillator 10 Delay circuit 11 Inverter 20 SRAM cell IN Input terminal OUT Output terminal P1, P2, P3, N1, N2, N3 Transistors

Claims

1. An SRAM circuit block including SRAM cells, and a ring oscillator having a plurality of stages of delay circuits, wherein each of the delay circuits has an input terminal, an output terminal, a first transistor of a first conductivity type corresponding to a transistor in the SRAM cell, having a gate connected to the input terminal and a source connected to a first power supply, a second transistor of a second conductivity type having a gate connected to the input terminal, a source connected to a second power supply, and a drain connected to the output terminal, and a third transistor of the first conductivity type having a gate connected to the input terminal, a source connected to the drain of the first transistor, and a drain connected to the output terminal, when a signal applied to the input terminal makes a first transition, the first and third transistors conduct, the second transistor does not conduct, the drain of the first transistor is electrically connected to the output terminal by conduction of the third transistor, and the signal at the output terminal transitions by operation of the first transistor, when the signal applied to the input terminal makes a second transition opposite to the first transition, the first and third transistors do not conduct, the second transistor conducts, the drain of the first transistor is electrically separated from the output terminal by non-conduction of the third transistor, and the signal at the output terminal transitions by operation of the second transistor a semiconductor integrated circuit device.

2. In the semiconductor integrated circuit device according to claim 1, the first conductivity type is N-type, the second conductivity type is P-type, the first power supply is a low-voltage-side power supply, the second power supply is a high-voltage-side power supply, the first transition is a transition from a low level to a high level, and the second transition is a transition from a high level to a low level a semiconductor integrated circuit device.

3. In the semiconductor integrated circuit device according to claim 1, the first conductivity type is P-type, the second conductivity type is N-type, the first power supply is a high-voltage-side power supply, the second power supply is a low-voltage-side power supply, the first transition is a transition from a high level to a low level, and the second transition is a transition from a low level to a high level a semiconductor integrated circuit device.

4. In the semiconductor integrated circuit device according to claim 1, the first transistor has the same size as the transistor in the SRAM cell a semiconductor integrated circuit device.

5. A ring oscillator having a plurality of stages of delay circuits, wherein each of the delay circuits has an input terminal, an output terminal, a first transistor of a first conductivity type having a gate connected to the input terminal and a source connected to a first power supply, a second transistor of a second conductivity type having a gate connected to the input terminal, a source connected to a second power supply, and a drain connected to the output terminal, and a third transistor of the first conductivity type having a gate connected to the input terminal, a source connected to the drain of the first transistor, and a drain connected to the output terminal, when a signal applied to the input terminal makes a first transition, the first and third transistors conduct, the second transistor does not conduct, the drain of the first transistor is electrically connected to the output terminal by the conduction of the third transistor, and the signal at the output terminal transitions by the operation of the first transistor, when the signal applied to the input terminal makes a second transition opposite to the first transition, the first and third transistors do not conduct, the second transistor conducts, the drain of the first transistor is electrically separated from the output terminal by the non - conduction of the third transistor, and the signal at the output terminal transitions by the operation of the second transistor a semiconductor integrated circuit device. **Claim 6**: The semiconductor integrated circuit device according to claim 5, wherein the first conductivity type is N - type, the second conductivity type is P - type, the first power supply is a low - voltage - side power supply, the second power supply is a high - voltage - side power supply, the first transition is a transition from a low level to a high level, and the second transition is a transition from a high level to a low level a semiconductor integrated circuit device. **Claim 7**: The semiconductor integrated circuit device according to claim 5, wherein the first conductivity type is P - type, the second conductivity type is N - type, the first power supply is a high - voltage - side power supply, the second power supply is a low - voltage - side power supply, the first transition is a transition from a high level to a low level, and the second transition is a transition from a low level to a high level a semiconductor integrated circuit device. **Claim 8** a first ring oscillator having a plurality of stages of first delay circuits, and a second ring oscillator having a plurality of stages of second delay circuits, wherein each of the first delay circuits has a first input terminal, a first output terminal, a first transistor of a first conductivity type having a gate connected to the first input terminal and a source connected to a first power supply, A second transistor of a second conductivity type, having a gate connected to the first input terminal, a source connected to a second power supply, and a drain connected to the first output terminal; A third transistor of the first conductivity type, having a gate connected to the first input terminal, a source connected to the drain of the first transistor, and a drain connected to the first output terminal; When the signal applied to the first input terminal makes a first transition; The first and third transistors conduct, the second transistor does not conduct, the drain of the first transistor is electrically connected to the first output terminal by the conduction of the third transistor, and the signal at the first output terminal transitions by the operation of the first transistor; When the signal applied to the first input terminal makes a second transition opposite to the first transition; The first and third transistors do not conduct, the second transistor conducts, the drain of the first transistor is electrically separated from the first output terminal by the non-conduction of the third transistor, and the signal at the first output terminal transitions by the operation of the second transistor; Each of the second delay circuits includes: A second input terminal; A second output terminal; A fourth transistor of the second conductivity type, having a gate connected to the second input terminal and a source connected to the second power supply; A fifth transistor of the first conductivity type, having a gate connected to the second input terminal, a source connected to the first power supply, and a drain connected to the second output terminal; A sixth transistor of the second conductivity type, having a gate connected to the second input terminal, a source connected to the drain of the fourth transistor, and a drain connected to the second output terminal; When the signal applied to the second input terminal makes the second transition; The fourth and sixth transistors conduct, the fifth transistor does not conduct, the drain of the fourth transistor is electrically connected to the second output terminal by the conduction of the sixth transistor, and the signal at the second output terminal transitions by the operation of the fourth transistor; When the signal applied to the second input terminal makes the first transition; The fourth and sixth transistors are non-conductive, the fifth transistor is conductive, the drain of the fourth transistor is electrically separated from the second output terminal due to the non-conduction of the sixth transistor, and the signal of the second output terminal transitions by the operation of the fifth transistor. Semiconductor integrated circuit device.

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