Solid imaging device, method for driving the solid imaging device, and electronic apparatus

Abstract

To provide a solid-state imaging apparatus, a method for driving the solid-state imaging apparatus, and an electronic apparatus, capable of suppressing the reduction of an SNR at the coupling point of signals different in conversion gain, without being affected by an optical specification.SOLUTION: In a pixel 200, a floating diffusion FD11 and a first capacitor CS11 are selectively connected through a first connection element LG11-Tr, so that the capacitance of the FD11 is changed to a first capacitance or a second capacitance, to switch the conversion gain to a first conversion gain (HCG) decided by the first capacitance or a second conversion gain (MCG) decided by the second capacitance and the FD11 and a second capacitor CS12 are connected through a second connection element SG11-Tr, so that the capacitance of the FD11 is changed to a third capacitance, to switch the conversion gain of an SF11-Tr to a third conversion gain (LCG) decided by the third capacitance.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device.

Background Art

[0002] As a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates electric charges, a CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put into practical use. CMOS image sensors are widely applied as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), in-vehicle cameras, and mobile devices such as mobile phones.

[0003] A CMOS image sensor has a FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and its reading is mainly of a column parallel output type in which one row in the pixel array is selected and they are simultaneously read in the column (column) output direction.

[0004] Generally, each pixel of a CMOS image sensor includes, for example, four elements of a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element (amplification element), and a selection transistor as a selection element as active elements.

[0005] By the way, various methods have been proposed to realize a high-quality CMOS image sensor having a high dynamic range (HDR) for improving characteristics (see, for example, Patent Documents 1, 2, and 3).

[0006] The CMOS image sensor that realizes a high dynamic range described in Patent Document 1 includes a photodiode PD in a pixel that generates charge in response to incident light. The charge from the photodiode PD is coupled to a voltage source and can be discharged or transferred to a charge storage region such as a storage diode. When the charge generated in the charge storage region exceeds the first charge level, the charge may overflow through the first transistor to the first storage capacitor. When the generated charge exceeds a second charge level higher than the first charge level, the charge may overflow through the second transistor. The charge that overflows through the second transistor can be discharged or transferred to the second storage capacitor for subsequent reading.

[0007] Patent Document 2 describes a solid-state image pickup device, its control method, and an electronic device aimed at suppressing the influence of PLS while realizing a wide dynamic range. The solid-state image pickup device includes a pixel array unit in which a plurality of pixels are arranged. A part of the pixels in the pixel array unit are unit pixels having at least one photoelectric conversion element and an overflow storage capacitor (LOFIC). Further, the solid-state image pickup device includes one AD converter for one or more unit pixels in the pixel array unit.

[0008] Patent Document 3 describes a CMOS image sensor that can realize a wide dynamic range while maintaining high sensitivity with a high S / N ratio. The pixel array has a structure in which each pixel includes a photodiode PD for receiving light and generating and storing a photoelectric charge, and a storage capacitor CS coupled to the photodiode PD via a transfer transistor Tr1 for storing the photoelectric charge that overflows from the photodiode PD. The storage capacitor CS is configured to store the photoelectric charge that overflows from the photodiode PD.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0010] As described above, a CMOS image sensor (CIS) can be configured by adopting various characteristic structures for improving the dynamic range of pixels.

[0011] As one of the approaches for achieving a high dynamic range, the configuration of a lateral overflow integration capacitor (LOFIC) can be mentioned. However, LOFIC has an important problem of a decrease in SNR at the coupling (junction) point of a high conversion gain (HCG) signal and a low conversion gain (LCG) signal. That is, with only the LOFIC configuration, the kTC noise of the LCG signal cannot be removed, so the SNR at the coupling point of the HCG signal and the LCG signal decreases.

[0012] One of the methods for achieving the minimum SNR reduction is the dual conversion gain (gain) readout, and the triple conversion gain readout technology with LOFIC and split pixels.

[0013] However, this type of pixel structure (split pixel type) has several problems in optical specifications. These problems include, for example, the optical structure between a large photodiode PD and a small photodiode PD, different angular responses and different quantum efficiencies (Q.E.), or the responsivity between a large photodiode PD and a small photodiode PD.

[0014] An object of the present invention is to provide a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus capable of suppressing a decrease in SNR at a coupling point between signals having different conversion gains without being affected by optical specifications.

Means for Solving the Problems

[0015] The solid-state imaging device according to the first aspect of the present invention has pixels capable of performing photoelectric conversion and reading out signals corresponding to at least three conversion gains. The pixels include a floating diffusion that holds the transferred charge and converts it into a voltage corresponding to the capacitance in order to read out the voltage as a signal, a photoelectric conversion element that accumulates charge corresponding to the incident light amount during the exposure period, a transfer element that is held in a non-conductive state during the exposure period and in a conductive state during the transfer period to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion, a reset element capable of performing a reset process for discharging at least the accumulated charge of the floating diffusion, a first capacitive element controlled to be connected or disconnected to the floating diffusion according to the conversion gain, a first connection element that selectively connects the floating diffusion and the first capacitive element, a second capacitive element capable of accumulating overflow charge overflowing from the photoelectric conversion element, a second connection element that selectively connects the floating diffusion and the second capacitive element, an overflow path capable of overflowing the charge overflowing from the photoelectric conversion element in the direction of the formation region of the second capacitive element, an overflow gate element formed on the overflow path for controlling the conduction of the overflow path, and a source follower element that amplifies and outputs the voltage signal converted by the floating diffusion.

[0016] A second aspect of the present invention has a pixel capable of performing photoelectric conversion and reading out signals corresponding to at least three conversion gains. The pixel includes a floating diffusion that holds the transferred charge and converts it into a voltage corresponding to the capacitance in order to read it out as a voltage signal, a photoelectric conversion element that accumulates charges corresponding to the incident light amount during the exposure period, a transfer element that is kept in a non-conductive state during the exposure period and in a conductive state during the transfer period to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion, a reset element capable of performing a reset process for discharging at least the accumulated charge in the floating diffusion, a first capacitive element controlled to be in a connected state or a non-connected state with the floating diffusion according to the conversion gain, a first connection element that selectively connects the floating diffusion and the first capacitive element, a second capacitive element capable of accumulating overflow charges that overflow from the photoelectric conversion element, a second connection element that selectively connects the floating diffusion and the second capacitive element, an overflow path capable of overflowing the charges that overflow from the photoelectric conversion element in the direction of the formation region of the second capacitive element, an overflow gate element formed on the overflow path for controlling the conduction of the overflow path, and a source follower element that amplifies and outputs the voltage signal converted by the floating diffusion. A driving method of a solid-state imaging device includes selectively connecting the floating diffusion and the first capacitive element through the first connection element to change the capacitance of the floating diffusion to a first capacitance or a second capacitance, and switching the conversion gain to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance; connecting the floating diffusion and the first capacitive element through the first connection element, and connecting the floating diffusion, the first capacitive element, and the second capacitive element through the second connection element to change the capacitance of the floating diffusion to a third capacitance and switching the conversion gain of the floating diffusion to a third conversion gain determined by the third capacitance.

[0017] An electronic device according to a third aspect of the present invention includes a solid-state imaging device and an optical system that forms a subject image on the solid-state imaging device. The solid-state imaging device has pixels that perform photoelectric conversion and can read out signals corresponding to at least three conversion gains. Each pixel includes a floating diffusion that holds the transferred charge and converts it into a voltage corresponding to the capacitance in order to read out the charge as a voltage signal, a photoelectric conversion element that accumulates charge corresponding to the incident light amount during an exposure period, a transfer element that is held in a non-conductive state during the exposure period and in a conductive state during a transfer period to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion, a reset element capable of performing a reset process for discharging at least the accumulated charge in the floating diffusion, a first capacitance element controlled to be connected or disconnected to the floating diffusion according to the conversion gain, a first connection element that selectively connects the floating diffusion and the first capacitance element, a second capacitance element capable of accumulating overflow charge that overflows from the photoelectric conversion element, a second connection element that selectively connects the floating diffusion and the second capacitance element, an overflow path capable of overflowing the charge that overflows from the photoelectric conversion element in the direction of the formation region of the second capacitance element, an overflow gate element formed on the overflow path for controlling conduction of the overflow path, and a source follower element that amplifies and outputs the voltage signal converted by the floating diffusion.

Advantages of the Invention

[0018] According to the present invention, it is possible to suppress a decrease in SNR at the coupling point between signals with different conversion gains without being affected by optical specifications.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in association with the drawings.

[0021] (First Embodiment) FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a pixel in a solid-state imaging device according to a first embodiment of the present invention. FIGS. 3(A) and (B) are diagrams for explaining conversion gain and capacitance related to triple conversion gain read in a solid-state imaging device according to a first embodiment of the present invention. In the present embodiment, the solid-state imaging device 10 is constituted by, for example, a CMOS image sensor.

[0022] As shown in FIG. 1, this solid-state imaging device 10 mainly includes a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a read circuit (column read circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60 as main components. Among these components, for example, a pixel signal reading unit 70 is constituted by a vertical scanning circuit 30, a reading circuit 40, a horizontal scanning circuit 50, and a timing control circuit 60.

[0023] In the first embodiment, in the solid-state imaging device 10, as will be described in detail later, the pixels 200 arranged in a matrix in the pixel unit 20 basically have a configuration as shown in FIG. 2. That is, the pixel 200 includes a floating diffusion FD (Floating Diffusion) 11 that holds the charge to be transferred as a voltage signal for reading, a photodiode PD11 as a photoelectric conversion element that accumulates charge according to the incident light amount during the exposure period PEXP, a transfer transistor TG11-Tr as a transfer element that is held in a non-conductive state during the exposure period PEXP and in a conductive state during the transfer period and transfers the charge accumulated in the photodiode PD11 as a photoelectric conversion element to the floating diffusion FD11, and a reset transistor RST11-Tr as a reset element capable of performing a reset process for discharging the accumulated charge of the floating diffusion FD11.

[0024] Furthermore, the pixel 200 includes a first capacitor CS11 as a first capacitive element that is controlled to be in a connected state or a non-connected state with the floating diffusion FD11 according to the conversion gain, a first switching transistor LG11-Tr as a first connection element that selectively connects the floating diffusion FD11 and the first capacitor CS11 as a first capacitive element, a second capacitor CS12 as a second capacitive element that can accumulate overflow charge overflowing from the photodiode PD11 as a photoelectric conversion element, and a second switching transistor SG11-Tr as a second connection element that selectively connects the floating diffusion FD11 and the second capacitor CS12 as a second capacitive element.

[0025] Furthermore, the pixel 200 includes an overflow path OVFP that can overflow the charge overflowing from the photodiode PD11 as a photoelectric conversion element in the direction of the formation region of the second capacitor CS2 as a second capacitive element, an overflow path transistor LO11-Tr as an overflow gate element formed on the overflow path OVFP for controlling the conduction of the overflow path OVFP, a source follower transistor SF11-Tr as a source follower element that outputs a voltage signal converted by the floating diffusion FD11, and a selection transistor SEL11-Tr as a selection element.

[0026] The pixel 200 according to this embodiment can change the capacitance of the floating diffusion FD11 to a first capacitance or a second capacitance under the control of the reading unit 70, and by selectively connecting the floating diffusion FD11 and the first capacitor CS11 as a first capacitive element through the first switching transistor LG11-Tr as a first connection element, switch to a first conversion gain (e.g., high conversion gain: HCG: High Conversion Gain) determined by the first capacitance or a second conversion gain (e.g., middle conversion gain: MCG: Middle Conversion Gain) determined by the second capacitance. Furthermore, the pixel 200 can change the capacitance of the floating diffusion FD11 to a third capacitance under the control of the reading unit 70, and by connecting the floating diffusion FD11 and the second capacitor CS12 as a second capacitive element through the second switching transistor SG11-Tr as a second connection element, switch to a third conversion gain (e.g., low conversion gain: LCG: Low Conversion Gain) determined by the third capacitance.

[0027] Under the control of the reading unit 70, as shown in FIG. 3, the pixel 200 performs first conversion gain mode reading for reading a pixel signal with a first conversion gain (high conversion gain: HCG) corresponding to a first capacitance during a specified dual conversion gain reading mode period, and second conversion gain mode reading for reading a pixel signal with a second conversion gain (medium conversion gain: MCG) corresponding to a second capacitance (different from the first capacitance). It is configured to be able to perform the above. Furthermore, under the control of the reading unit 70, the pixel 200 is configured to be able to perform third conversion gain mode reading for reading a pixel signal with a third conversion gain (low conversion gain: LCG) corresponding to a third capacitance during an overflow reading mode (LOFIC) reading mode period specified subsequent to the dual conversion gain reading mode.

[0028] The pixel 200 is provided with, for example, a horizontal overflow integration capacitance (hereinafter referred to as "L0FIC (Lateral Overflow Integration Capacitor)"). Under the control of the reading unit 70, in low illumination conditions, it performs a dual sampling reading mode (LOFIC mode) operation using the third conversion gain (single gain) related to the accumulated charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element.

[0029] Thus, in this first embodiment, without providing divided pixels, in order to achieve the minimum SNR reduction, as shown in FIG. 3, the pixel 200 performs first conversion gain mode reading for reading a pixel signal with a first conversion gain (for example, high conversion gain: HCG) corresponding to a first capacitance, second conversion gain mode reading for reading a pixel signal with a second conversion gain (for example, medium conversion gain: MCG) corresponding to a second capacitance (different from the first capacitance), and third conversion gain mode reading for reading a pixel signal with a third conversion gain (for example, low conversion gain: LCG) corresponding to a third capacitance. Triple conversion gain reading is performed.

[0030] (Specific Circuit Configuration of Pixel 200) Here, the specific circuit configuration of pixel 200 in FIG. 2 will be described. Here, a configuration example of pixel 200 having a LOFIC structure will be described.

[0031] The pixel section 20 includes readout pixels 200 each including a photodiode (photoelectric conversion element) and an in-pixel amplifier, which are arranged in a two-dimensional matrix (matrix) of N rows × M columns.

[0032] As shown in FIG. 2, for example, this pixel 200 includes a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a transfer element, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, a first switching transistor LG11-Tr as a first connection element, a second switching transistor SG11-Tr as a second connection element, an overflow pass transistor LO11-Tr as an overflow gate element, a first capacitor CS11 as a first capacitive element, a second capacitor CS12 as a second capacitive element, a floating diffusion FD11, a first node ND11 connected to the floating diffusion FD11, a second node ND12, and a third node ND13 connected to the second capacitor CS12.

[0033] In the present first embodiment, the photodiode PD11 of pixel 200 is formed by a high-capacity photodiode. Also, in pixel 200, the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 have their capacitances set as follows (see also FIG. 3(B)). The capacitance CFD of the floating diffusion FD11 is formed to be a very small capacitance for high gain and low noise. The capacitance CS1 of the first capacitor CS11 is set to a medium capacitance that is larger than the high-capacity photodiode PD11 in order to minimize the reduction in SNR. The capacitance CS2 of the second capacitor CS12 is set to a very large capacitance (capacitance) for high FWC (Full Well Capacity). The capacitance CS2 of the second capacitor CS12 is larger than the capacitance CS1 of the first capacitor CS11 and the capacitance CFD of the floating diffusion FD11. For a medium conversion gain, the capacitance CS1 of the first capacitor CS11 is mainly used, and for a low conversion gain, the capacitance CS2 of the second capacitor CS12 is also used.

[0034] The high-capacity photodiode PD11 generates and accumulates a signal charge (here, electrons) in an amount corresponding to the incident light amount. Hereinafter, the signal charge is an electron, and the case where each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.

[0035] In each pixel 200, an embedded photodiode (PPD) is used as the photodiode (PD). Since there are interface levels due to defects such as dangling bonds on the substrate surface forming the photodiode (PD), a large amount of charge (dark current) is generated by thermal energy, and there is a risk that a correct signal cannot be read out. In the embedded photodiode (PPD), by embedding the charge accumulation part of the photodiode (PD) in the substrate, it is possible to reduce the mixing of the dark current into the signal.

[0036] The transfer transistor TG11-Tr is connected between the photodiode PD11 and the floating diffusion FD11 (and the first node ND11) and is controlled through the control signal TG. Transfer transistor TG11-Tr is selected and turned on during the period when the control signal TG is at the high level (H), and transfers the charge (electrons) photoelectrically converted by the photodiode PD11 and accumulated in the accumulation node to the floating diffusion FD11.

[0037] In the example of FIG. 2, the reset transistor RST11-Tr is connected between the power supply potential VAAPIX and a first switching transistor LG11-Tr connected to the floating diffusion FD11 via a first node ND11 and a second switching transistor SG11-Tr connected via a second node ND12, and is controlled through the control signal RST. Reset transistor RST11-Tr is selected and turned on during the period when the control signal RST is at the H level, and resets at least the floating diffusion FD11 to the power supply potential VAAPIX.

[0038] Also, in the first embodiment, the reset transistor RST11-Tr and the transfer transistor TG11-Tr are held in the conductive state to reset the floating diffusion FD11 and the photodiode PD11.

[0039] The first switching transistor LG11-Tr is connected between the floating diffusion FD11 and the first capacitor CS11 via the first node ND11. The first switching transistor LG11-Tr is controlled by a control signal LG applied to the gate through a control line. The first switching transistor LG11-Tr is selected and turned on during the period when the control signal LG is at the H level, and connects the floating diffusion FD11 and the first capacitor CS11. In the first embodiment, the reset transistor RST11-Tr and the first switching transistor LG11-Tr are held in the conductive state to reset the floating diffusion FD11 and the first capacitor CS11.

[0040] The second switching transistor SG11-Tr is connected between the floating diffusion FD11 (and the reset transistor RST11-Tr) and the second capacitor CS12 via the second node ND12. The second switching transistor SG11-Tr is controlled by a control signal SG applied to the gate through a control line. The second switching transistor SG11-Tr is selected and turned on during the period when the control signal SG is at the H level, connecting the floating diffusion FD11 (and the reset transistor RST11-Tr) and the second capacitor CS12. In this first embodiment, the reset transistor RST11-Tr and the second switching transistor SG11-Tr are held in the conductive state to reset the floating diffusion FD11 and the second capacitor CS12.

[0041] The overflow pass transistor LO11-Tr is connected between the charge storage node of the photodiode PD11 and the second capacitor CS12 via the third node ND13. The overflow pass transistor LO11-Tr is controlled by a control signal LO applied to the gate through a control line. The overflow pass transistor LO11-Tr is selected and turned on during the period when the control signal LO is at the H level, connecting the charge storage node of the photodiode PD11 and the second capacitor CS12.

[0042] In the first embodiment, as shown in FIG. 2, the overflow path OVFP is formed as a path through which the overflow charge of the photodiode PD11 can overflow to the second capacitor CS12 via the overflow path transistor LO11-Tr and the third node ND13 (solid arrow), and a path through which the overflow charge of the second capacitor CS12 can be discarded to the power supply potential VAAPIX via the second switching transistor SG11-Tr, the second node ND12, and the reset transistor RST11-Tr is formed (dashed arrow).

[0043] The source follower transistor SF11-Tr and the selection transistor SEL11-Tr are connected in series between the power supply potential VAAPIX and the vertical signal line LSGN11. A floating diffusion FD11 is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled by a control signal SEL applied to the gate through a control line. The selection transistor SEL11-Tr is selected and turned on during the selection period when the control signal SEL is at the H level. As a result, the source follower transistor SF11-Tr outputs the voltage signals (VRST1, VSIG1) converted by the floating diffusion FD11 to the vertical signal line LSGN11.

[0044] Since the pixel circuits 200 are arranged in N rows × M columns in the pixel section 20, there are N control lines and M vertical signal lines respectively. In FIG. 1, each control line is represented as a single horizontal scanning control line.

[0045] The vertical scanning circuit 30 drives the pixels through the horizontal scanning control lines in the shutter row and the readout row in accordance with the control of the timing control circuit 60. Further, the vertical scanning circuit 30 outputs a row selection signal of the row address of the read row for reading signals and the shutter row for resetting the charges accumulated in the photodiode PD11 according to the address signal.

[0046] The readout circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured such that column-parallel processing can be performed by the plurality of column signal processing circuits.

[0047] The horizontal scanning circuit 50 scans the signals processed by the plurality of column signal processing circuits of the readout circuit 40, transfers them in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0048] The timing control circuit 60 generates timing signals necessary for signal processing of the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, etc.

[0049] When the dual conversion gain readout mode MDCG is specified, the readout section 70 performs a second conversion gain reset readout process MCGRRD, a first conversion gain reset readout process HCGRRD, a first conversion gain readout process HCGSRD, and a second conversion gain readout process MCGSRD. When the overflow readout mode MOVF (MLOFIC) regarding overflow charge is specified, the readout section 70 performs a third conversion gain readout process LCGSRD and a third conversion gain reset readout process LCGRRD.

[0050] In the present first embodiment, after starting the exposure period PEXP, the readout section 70 performs readout sequence control so as to perform the readout process of the dual conversion gain readout mode MDCG as a readout mode process, and subsequently perform the overflow readout mode MOVF (MLOFIC).

[0051] For example, the readout unit 70 holds the reset transistor RST11-Tr, the first switching transistor LG11-Tr, the second switching transistor SG11-Tr, and the transfer transistor TG11-Tr in the conductive state for a predetermined period to reset the photodiode PD11, the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12, performs shutter processing, turns the transfer transistor TG11-Tr off, and starts the exposure period PEXP. After starting the exposure period PEXP, the readout unit 70 sequentially performs, as the processing of the dual conversion gain readout mode DMCG, the second conversion gain reset readout process MCGRRD, the first conversion gain reset readout process HCGRRD, the first conversion gain signal readout process HCGSRD, and the second conversion gain signal readout process MCGSRD. Next, the readout unit 70 performs the third conversion gain signal readout process LCGSRD as the overflow readout mode process for the overflow charge. Subsequently, after the readout unit 70 holds the reset transistor RST11-Tr, the first switching transistor LG11-Tr, and the second switching transistor SG11-Tr in the conductive state for a predetermined period to discard all the charges of the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 to the power supply potential VAAPIX and performs shutter processing, the third conversion gain reset readout process LCGRRD is sequentially performed.

[0052] Here, an example of the readout sequence for the pixel 200 in the solid-state imaging device according to the first embodiment will be described.

[0053] FIGS. 4(A) to (E) are timing charts for explaining an example of the readout sequence in the dual conversion gain readout mode and the overflow readout mode for the pixel of the solid-state imaging device according to the first embodiment of the present invention. Figs. 5(A) to 5(H) are diagrams showing an operation sequence and potential transitions for explaining operations in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to the first embodiment of the present invention under low illuminance conditions. Figs. 6(A) to 6(H) are diagrams showing an operation sequence and potential transitions for explaining operations in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to the first embodiment of the present invention under medium illuminance conditions. Figs. 7(A) to 7(H) are diagrams showing an operation sequence and potential transitions for explaining operations in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to the first embodiment of the present invention under high illuminance conditions.

[0054] Fig. 4(A) shows the control signal RST of the reset transistor RST11-Tr, Fig. 4(B) shows the control signal SG of the second switching transistor SG11-Tr, Fig. 4(C) shows the control signal LG of the first switching transistor LG11-Tr, Fig. 4(D) shows the control signal TG of the transfer transistor TG11-Tr, and Fig. 4(E) shows the control signal LO of the overflow pass transistor LO11-Tr.

[0055] Note that the readout sequences in the dual conversion gain readout mode and the overflow readout mode for pixels are basically performed in the same manner under low illuminance conditions, medium illuminance conditions, and high illuminance conditions as described below.

[0056] Before the processing of the dual conversion gain readout mode MDCG is started, the control signals RST, SG, LG, TG, and LO are set to a high level for a predetermined period, and the reset transistor RST11-Tr, the second switching transistor SG11-Tr, the first switching transistor LG11-Tr, the transfer transistor TG11-Tr, and the overflow pass transistor LO11-Tr are held in a conductive state for a predetermined period. As a result, the photodiode PD11, the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 are reset to the fixed potential VAAPIX. That is, the shutter operation is performed (Figs. 4(A) to (E)).

[0057] Then, the exposure time PEXP starts at the timing when the transfer transistor TG11-Tr is switched from the conductive state to the non-conductive state (Fig. 4(D)). After the exposure period PEXP ends, at the beginning of the readout period, the control signal RST and the control signal LG are switched to the high level, and the reset transistor RST11-Tr and the first switching transistor LG11-Tr are switched to the conductive state. As a result, the floating diffusion FD11 and the first capacitor CS11 are reset. Here, after a predetermined period has elapsed since the control signal RST and the control signal LG are switched to the high level, only the control signal RST is switched to the low level and the reset transistor RST11-Tr is switched to the non-conductive state, entering the first reset signal readout period. At this time, since the control signal LG is held at the high level and the first switching transistor LG11-Tr is in the conductive state, the charge of the floating diffusion FD11 and the charge of the first capacitor CS11 are shared, and the gain of the floating diffusion FD11 is switched to the second conversion gain MCG determined by the second capacitance including the capacitance CFD of the floating diffusion FD11 and the capacitance CS1 of the first capacitor CS1.

[0058] Then, during the first reset signal readout period after the reset process, the second readout reset signal MCGRST(ADC) converted with the second conversion gain MCG determined by the second capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr, and the second conversion gain reset readout process MCGRRD that performs a predetermined process on this second readout reset signal MCGRST(ADC) is performed.

[0059] Next, after the first reset signal read period has elapsed, the control signal LG is switched to the low level, the first switching transistor LG11-Tr is switched to the non-conducting state, and the second reset signal read period begins. At this time, the first capacitor CS11 is disconnected from the floating diffusion FD11, the charges of the floating diffusion FD11 and the first capacitor CS11 are separated, and the gain of the floating diffusion FD11 (source follower transistor SF11-Tr) is switched to the first conversion gain HCG determined by the first capacitance CFD of the floating diffusion FD11.

[0060] Then, during the second reset signal read period, the first read reset signal HCGRST(ADC) converted by the first conversion gain HCG determined by the first capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr is read, and the first conversion gain reset read process HCGRRD that performs a predetermined process on this first read reset signal HCGRST(ADC) is performed.

[0061] Next, during the first transfer period after the second reset signal read period, the control signal TG is switched to the high level and the transfer transistor TG11-Tr is held in the conducting state, and the accumulated charge of the photodiode PD11 is transferred to the floating diffusion FD11. After the first transfer period, the control signal TG is switched to the low level, and the transfer transistor TG11-Tr is switched to the non-conducting state.

[0062] Next, during the first signal read period following the first transfer period, the first read signal HCGSIG(ADC) converted by the first conversion gain determined by the first capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr is read, and the first conversion gain signal read process HCGSRD that performs a predetermined process on this first read signal HCGSIG(ADC) is performed.

[0063] Then, either the reset level HCGRSTADC and the signal level HCGSIGADC are held, or a CDS operation is performed based on the difference between the reset level and the signal level.

[0064] Next, after the first conversion gain readout process HCGSRD, the control signal LG is switched from a low level to a high level, the first switching transistor LG11-Tr is switched to a conductive state, and the first capacitor CS11 is connected to the floating diffusion FD11. As a result, the charge of the floating diffusion FD11 and the charge of the first capacitor CS11 are shared, and the gain of the floating diffusion FD11 is switched to the second conversion gain MCG determined by the second capacitance.

[0065] Next, during the second transfer period after the first signal readout period, the control signal TG is switched to a high level, the transfer transistor TG11-Tr is held in a conductive state, and the stored charge of the photodiode PD11 is transferred to the floating diffusion FD11. After the second transfer period, the control signal TG is switched to a low level, and the transfer transistor TG11-Tr is switched to a non-conductive state. Then, during the second signal readout period following the second transfer period after the first signal readout period, the second readout signal MCGSIG(ADC) converted with the second conversion gain MCG determined by the second capacitance of the floating diffusion FD11 from the source follower transistor SF11-Tr is read out, and a second conversion gain signal readout process MCGSRD for performing a predetermined process on this second readout signal MCGSIG(ADC) is performed.

[0066] Then, either the reset level MCGRSTADC and the signal level MCGSIGADC are held, or a CDS operation is performed based on the difference between the reset level MCGRSTADC and the signal level MCGSIGADC.

[0067] Here, the readout mode switches from the dual conversion gain readout mode to the LOFIC readout mode. Note that the dual conversion gain readout process is only to read the stored charge of the photodiode PD11 using two gains. In contrast, during LOFIC readout, the charge that has overflowed and been stored in the second capacitor CS12 beyond the saturation of the photodiode PD11 is also read out.

[0068] After the above-described second conversion gain readout process MCGSRD, the control signal SG is switched from a low level to a high level, and the second switching transistor SG11-Tr is switched to a conducting state, connecting the second capacitor CS12 to the floating diffusion FD11. As a result, the charge FDC of the floating diffusion FD11, the charge of the first capacitor CS11, and the charge of the second capacitor CS12 are shared, and the gain of the floating diffusion FD11 is switched to the third conversion gain LCG determined by the third capacitance.

[0069] Then, during the third signal readout period after the second signal readout period, the third readout signal LCG(LOFIC)SIG(ADC) converted with the third conversion gain LCG determined by the third capacitance of the floating diffusion FD11 is read out from the source follower transistor SF11-Tr (Fig. 4(B)), and the third conversion gain signal readout process LCGSRD that performs a predetermined process on this third readout signal LCGSIG(ADC) is performed.

[0070] Next, during the second reset process period after the third signal readout period, the control signal RST is switched to a high level, and the reset transistor RST11-Tr is switched to a conducting state. As a result, the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12 are reset. Here, after a predetermined period has elapsed since the control signal RST was switched to a high level, the control signal RST is switched to a low level, and the reset transistor RST11-Tr is switched to a non-conducting state, resulting in the third reset signal readout period. At this time, since the control signals LG and SG are held at a high level and the first switching transistor LG11-Tr and the second switching transistor SG11-Tr are in a conductive state, the charge of the floating diffusion FD11, the charge of the first capacitor CS11, and the second capacitor CS12 are shared, and the gain of the floating diffusion FD11 is maintained at a third conversion gain LCG determined by a third capacitance including the capacitance CFD of the floating diffusion FD11, the capacitance CS1 of the first capacitor CS11, and the capacitance CS2 of the second capacitor CS12.

[0071] Then, during the third reset signal read period after the reset process, a third read reset signal LOFIC(LCG)RST(ADC) converted by the third conversion gain LCG determined by the third capacitance of the floating diffusion FD11 is read from the source follower transistor SF11-Tr (FIGS. 4(B) and (C)), and a third conversion gain reset read process LCGRRD that performs a predetermined process on this third read reset signal LOFIC(LCG)RST(ADC) is performed.

[0072] Then, the reset level LCGRSTADC and the signal level LCGSIGADC are held, or a CDS operation is performed based on the difference between the reset level LCGRSTADC and the signal level LCGSIGADC.

[0073] As described above, in the solid-state imaging device 10 of the first embodiment, as shown in FIG. 5(A), since the reset process of the floating diffusion FD11 is performed before the first read reset signal HCGRST is read, the FD dark current charged in the floating diffusion FD11 is removed (the FD dark current does not exist). Also, in the solid-state imaging device 10 of the first embodiment, as shown in FIG. 6(C), before the readout of the second read reset signal MCGRST, the reset process of the floating diffusion FD11 and the first capacitor CS11 is performed. Therefore, there is no FD / CS dark current charged in the floating diffusion FD11 and the first capacitor CS11. However, since the second capacitor CS12 as the second capacitive element becomes a node that accumulates charges during the accumulation period, it is not possible to remove the dark current.

[0074] As described above, according to the first embodiment, the pixel 200 includes a floating diffusion FD11 that holds the transferred charge as a voltage signal for readout, a photodiode PD11 that accumulates charges corresponding to the incident light amount during the exposure period PEXP, a transfer transistor TG11-Tr that is held in a non-conductive state during the exposure period PEXP and in a conductive state during the transfer period to transfer the charges accumulated in the photodiode PD11 to the floating diffusion FD11, and a reset transistor RST11-Tr capable of performing a reset process for discharging the accumulated charge of the floating diffusion FD11. Furthermore, the pixel 200 includes a first capacitor CS11 that is controlled to be in a connected state or a non-connected state with the floating diffusion FD11 according to the conversion gain, a first switching transistor LG11-Tr that selectively connects the floating diffusion FD11 and the first capacitor CS11, a second capacitor CS12 capable of accumulating overflow charges that overflow from the photodiode PD11, and a second switching transistor SG11-Tr that selectively connects the floating diffusion FD11 and the second capacitor CS12. Furthermore, the pixel 200 includes an overflow path OVFP that can overflow the charge overflowing from the photodiode PD11 in the direction of the formation region of the second capacitor CS12, an overflow gate element LO11-Tr formed on the overflow path OVFP for controlling the conduction of the overflow path OVFP, and a source follower transistor SF11-Tr that amplifies and outputs the voltage signal converted by the floating diffusion FD11.

[0075] The pixel 200 according to the first embodiment selectively connects the floating diffusion FD11 and the first capacitor CS11 through the first switching transistor LG11-Tr under the control of the reading unit 70, thereby changing the capacitance of the floating diffusion FD11 to the first capacitance or the second capacitance and changing the conversion gain of the floating diffusion FD11 to the first conversion gain (high conversion gain: HCG) determined by the first capacitance or the second conversion gain (medium conversion gain: MCG) determined by the second capacitance. It is switchable. Furthermore, the pixel 200 connects the floating diffusion FD11 and the second capacitor CS12 through the second switching transistor SG11-Tr under the control of the reading unit 70, thereby changing the capacitance of the floating diffusion FD11 to the third capacitance and changing the conversion gain to the third conversion gain (low conversion gain: LCG) determined by the third capacitance. It is switchable.

[0076] Thus, in the first embodiment, the pixel 200 performs first conversion gain mode reading for reading the pixel signal with the first conversion gain (for example, high conversion gain: HCG) corresponding to the first capacitance, and the second capacitance (different from the first capacitance). Second conversion gain mode reading for reading the pixel signal with the second conversion gain (for example, medium conversion gain: MCG) corresponding to the above, and third conversion gain mode reading for reading the pixel signal with the third conversion gain (for example, low conversion gain: LCG) corresponding to the third capacitance. Since triple conversion gain reading is performed, it is possible to realize the minimum SNR reduction at the mode connection point without providing a split pixel. In other words, according to the first embodiment, it is possible to suppress a decrease in SNR at the connection point between signals with different conversion gains without being affected by the optical specifications.

[0077] Also, according to the first embodiment, it is possible to expand the dynamic range with a small pixel size in a predetermined readout mode. According to the first embodiment, it is possible to substantially realize a high dynamic range and a high frame rate. Furthermore, according to the first embodiment, a high dynamic range signal can be read with a linear response as shown in FIGS. 8(A) to 8(C), and a high-sensitivity / low-noise signal can be read with HCG readout. And it is possible to prevent variations in the pixel connection point signal due to saturation variations.

[0078] (Second Embodiment) FIG. 9 is a circuit diagram showing a configuration example of readout pixels in a solid-state imaging device according to the second embodiment of the present invention.

[0079] FIGS. 10(A) to 10(F) are timing charts for explaining an example of a readout sequence in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to the second embodiment of the present invention. FIGS. 11(A) to 11(H) are diagrams showing an operation sequence and potential transitions for explaining the operation of pixels of a solid-state imaging device according to the second embodiment of the present invention in a dual conversion gain readout mode and an overflow readout mode under low illuminance. FIGS. 12(A) to 12(H) are diagrams showing an operation sequence and potential transitions for explaining the operation of pixels of a solid-state imaging device according to the second embodiment of the present invention in a dual conversion gain readout mode and an overflow readout mode under medium illuminance. Figs. 13(A) to (H) are diagrams showing an operation sequence and potential transitions for explaining operations in a high illuminance condition in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to a second embodiment of the present invention.

[0080] Fig. 9(A) shows the control signal RST of the reset transistor RST11-Tr, Fig. 9(B) shows the control signal R_RD of the third switching transistor R_RD11-Tr, Fig. 9(C) shows the control signal SG of the second switching transistor SG11-Tr, Fig. 9(D) shows the control signal LG of the first switching transistor LG11-Tr, Fig. 9(E) shows the control signal TG of the transfer transistor TG11-Tr, and Fig. 9(F) shows the control signal LO of the overflow pass transistor LO11-Tr.

[0081] The difference between the pixel 200A of the solid-state imaging device 10A according to the second embodiment and the pixel 200 of the solid-state imaging device 10 according to the first embodiment described above is as follows.

[0082] In the pixel 200A of the solid-state imaging device 10A according to the second embodiment, a third switching transistor R_RD11-Tr as a third connection element whose conduction state and non-conduction state are selectively controlled by a control signal R_RD is connected between a connection node (second node) ND12 between the reset transistor RST11-Tr and the second switching transistor SG11-Tr and the floating diffusion FD11.

[0083] As shown in Figs. 10(A) to (B), the third switching transistor R_RD11-Tr is switched to a high level during the same period as the control signal RST of the reset transistor RST11-Tr in the first reset period and is held in a conduction state during this period. Also, as shown in FIGS. 10(A) to 10(C), when the third switching transistor R_RD11-Tr switches from the dual conversion gain readout mode to the LOFIC readout mode, it is switched to a high level at the same timing as the control signal SG of the second switching transistor SG11-Tr and is held in the conducting state.

[0084] Except for this configuration, in the solid-state imaging device 10A according to the second embodiment, the readout sequences in the dual conversion gain readout mode and the overflow readout mode for the pixels are performed in the same manner as in the solid-state imaging device of the first embodiment described above. Therefore, the detailed description thereof is omitted here.

[0085] Other configurations are the same as those of the first embodiment described above. According to the second embodiment, not only can the same effects as those of the first embodiment described above be obtained, but also the following effects can be obtained.

[0086] That is, according to the second embodiment, it becomes possible to connect the floating diffusion FD11 only during the setting period of the third conversion gain LCG to the second capacitor CS12 side. When the capacitance of the second capacitor CS12 is not required, it is possible to prevent unnecessary charges from flowing into the floating diffusion FD11 and charge mixing (resulting in false signals) from occurring. As a result, the number of adjacent transistors that determine the conversion gain of the floating diffusion FD11 can be reduced, and the conversion gain can be set with high accuracy.

[0087] (Third Embodiment) FIG. 14 is a circuit diagram showing a configuration example of readout pixels in a solid-state imaging device according to the third embodiment of the present invention.

[0088] FIGS. 15(A) to 15(D) are timing charts for explaining an example of a readout sequence in a dual conversion gain readout mode and an overflow readout mode for pixels of a solid-state imaging device according to the third embodiment of the present invention. FIGS. 16(A) to 16(H) are diagrams showing an operation sequence and potential transitions for explaining the operation of pixels of a solid-state imaging device according to the third embodiment of the present invention in a dual conversion gain readout mode and an overflow readout mode under low illuminance. FIGS. 17(A) to 17(H) are diagrams showing an operation sequence and potential transitions for explaining the operation of pixels of a solid-state imaging device according to the third embodiment of the present invention in a dual conversion gain readout mode and an overflow readout mode under medium illuminance. FIGS. 18(A) to 18(H) are diagrams showing an operation sequence and potential transitions for explaining the operation of pixels of a solid-state imaging device according to the third embodiment of the present invention in a dual conversion gain readout mode and an overflow readout mode under high illuminance.

[0089] FIG. 14(A) shows the control signal RST of the reset transistor RST11-Tr, FIG. 14(B) shows the control signal SG of the second switching transistor SG11-Tr, FIG. 14(C) shows the control signal LG of the first switching transistor LG11-Tr, and FIG. 14(D) shows the control signal TG of the transfer transistor TG11-Tr.

[0090] The difference between the pixel 200B of the solid-state imaging device 10B according to the third embodiment and the pixel circuit 200 of the solid-state imaging device 10 according to the first embodiment described above is as follows.

[0091] In the pixel 200B of the solid-state imaging device 10B according to the third embodiment, an overflow pass transistor LO11-Tr as an overflow gate element is shared with a second switching transistor SG11-Tr as a second connection element. Also, a third node ND13 is shared with a second node ND12. And the second switching transistor SG11-Tr as the shared second connection element is connected between the floating diffusion FD11 and the reset transistor RST11-Tr as the reset element, and a second node ND12 is formed by the connection node. And the second capacitor CS12 as the second capacitive element is connected to the second node ND12 which is the connection node between the second switching transistor SG11-Tr as the second connection element and the reset transistor RST11-Tr as the reset element. Also, the first switching transistor LO11-Tr as the first connection element and the first capacitor CS11 as the first capacitive element are connected in series between the floating diffusion FD11 connected to the first node ND11 and the reference potential VSS.

[0092] In the solid-state imaging device 10B of the third embodiment, as shown in FIG. 15(A), since the reset process of the floating diffusion FD11 is not performed before the reading of the first read reset signal HCGRST, the FD dark current charged in the floating diffusion FD11 is not completely removed (the FD dark current exists). Thus, although some FD dark current exists in the reading phase of the first read reset signal HCGRST, it can be removed by the CDS process.

[0093] Except for this configuration, in the solid-state imaging device 10B according to the third embodiment, the readout sequence in the dual conversion gain readout mode and the overflow readout mode for the pixels is basically performed in the same manner as the solid-state imaging device of the first embodiment described above. Therefore, the detailed description thereof is omitted here.

[0094] Other configurations are the same as those of the first embodiment described above. According to the third embodiment, not only can the same effects as those of the first embodiment described above be obtained, but also the circuit configuration can be simplified.

[0095] (Fourth Embodiment) FIG. 19 is a circuit diagram showing a configuration example of a read pixel in a solid-state imaging device according to the fourth embodiment of the present invention.

[0096] FIGS. 20(A) to (D) are timing charts for explaining an example of a read sequence in a dual conversion gain read mode and an overflow read mode for a pixel of a solid-state imaging device according to the fourth embodiment of the present invention. FIGS. 21(A) to (X) are diagrams showing an operation sequence and potential transitions for explaining the operations in a dual conversion gain read mode and an overflow read mode for a pixel of a solid-state imaging device according to the fourth embodiment of the present invention.

[0097] FIG. 20(A) shows the control signal RST of the reset transistor RST11-Tr, FIG. 20(B) shows the control signal SG of the second switching transistor SG11-Tr, FIG. 20(C) shows the control signal LG of the first switching transistor LG11-Tr, and FIG. 20(D) shows the control signal TG of the transfer transistor TG11-Tr, respectively.

[0098] The difference between the pixel 200C of the solid-state imaging device 10C according to the fourth embodiment and the pixel circuit 200B of the solid-state imaging device 10B according to the third embodiment described above is as follows.

[0099] In the pixel 200C of the solid-state imaging device 10C according to the fourth embodiment, a first switching transistor LG11-Tr as a first connection element is connected in series between a floating diffusion FD11 and a second switching transistor SG11-Tr as a second connection element. Further, a fourth node ND14 is formed by a connection node between the first switching transistor LG11-Tr as the first connection element and the second switching transistor SG11-Tr as the second connection element. And the second switching transistor SG11-Tr as a second connection element that is shared is connected between the second switching transistor SG11-Tr as the second connection element and a reset transistor RST11-Tr as a reset element, and a second node ND12 is formed by the connection node. And a first capacitor CS11 as a first capacitive element is connected to a fourth node ND14 that is a connection node between the first switching transistor LG11-Tr and the second switching transistor SG11-Tr. Also, a second capacitor CS12 as a second capacitive element is connected to a second node ND12 that is a connection node between the second switching transistor SG11-Tr and the reset transistor RST11-Tr as a reset element.

[0100] Also in the solid-state imaging device 10C of the fourth embodiment, as shown in Fig. 20(A), since the reset process of the floating diffusion FD11 is not performed before the reading of the first read reset signal HCGRST, the FD dark current charged in the floating diffusion FD11 is not completely removed (the FD dark current exists). Thus, although some FD dark current exists in the reading phase of the first read reset signal HCGRST, it can be removed by the CDS process.

[0101] Except for this configuration, in the solid-state imaging device 10C according to the fourth embodiment, the readout sequence in the dual conversion gain readout mode and the overflow readout mode for pixels is basically the same as that of the solid-state imaging device of the first embodiment described above. Therefore, a detailed description thereof will be omitted here.

[0102] Other configurations are the same as those of the third embodiment described above. According to the fourth embodiment, not only can the same effects as those of the third embodiment described above be obtained, but also further simplification of the circuit configuration can be achieved.

[0103] (Fifth Embodiment) FIG. 22 is a circuit diagram showing a configuration example of a pixel circuit of a solid-state imaging device 10D according to the fifth embodiment of the present invention.

[0104] The pixel 200D of the solid-state imaging device 10D according to the fifth embodiment is different from the pixel 200 of the solid-state imaging device 10 according to the first embodiment described above as follows.

[0105] The solid-state imaging device 10D according to the fifth embodiment has a pixel sharing structure in which a plurality (two in this embodiment) of adjacent pixels 200-1 and 200-2 share a floating diffusion FD11. The solid-state imaging device 10D according to the fifth embodiment shares a first switching transistor LG11-Tr as a first connection element and a first capacitor CS11 as a first capacitive element between adjacent pixels 200-1 and 200-2. In addition, in the pixel sharing structure of this example, a source follower transistor SF11-Tr and a selection transistor SEL11-Tr are shared.

[0106] Other configurations are the same as those of the first embodiment described above. According to the fifth embodiment, not only can the same effects as those of the first embodiment described above be obtained, but also the pixel size can be reduced, and further simplification of the circuit configuration becomes possible.

[0107] (Application examples to electronic devices) Furthermore, the solid-state imaging devices 10, 10A, 10B, 10C, and 10D described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0108] FIG. 23 shows a camera system to which the solid-state imaging device according to an embodiment of the present invention is applied. It is a diagram showing an example of the configuration of an electronic device equipped with the same.

[0109] As shown in FIG. 23, this electronic device 300 has a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A, 10B, 10C, and 10D according to this embodiment can be applied. Furthermore, the electronic device 300 has an optical system (such as a lens) 420 that guides incident light (forms a subject image) to the pixel region of this CMOS image sensor 310. The electronic device 300 has a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

[0110] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310. The image signal processed by the signal processing circuit 330 can be projected as a moving image on a monitor composed of a liquid crystal display or the like, or output to a printer, and various modes are possible, such as directly recording on a recording medium such as a memory card.

[0111] As described above, by mounting the solid-state imaging devices 10, 10A, 10B, 10C, and 10D described above as the CMOS image sensor 310, it becomes possible to provide a high-performance, small-sized, and low-cost camera system. Moreover, it is possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where there are restrictions on the installation requirements of the camera, such as the implementation size, the number of connectable cables, the cable length, and the installation height.

Description of Reference Numerals

[0112] 10, 10A, 10B, 10C, 10D ··· Solid-state imaging device, 20 ··· Pixel section, 200, 200A to 200D, 200-1, 200-2 ··· Pixels, PD11 ··· Photodiode, FD11 ··· Floating diffusion, TG11-Tr ··· Transfer transistor, RST11-Tr ··· Reset transistor, SF11-Tr ··· Source follower transistor, LG11-Tr ··· First switching transistor, SG11-Tr ··· Second switching transistor, CS11 ··· First capacitor, CS12 ··· Second capacitor, LO11-Tr ··· Overflow pass transistor, 300 ··· Electronic device, 310 ··· CMOS image sensor, 320 ··· Optical system, 330 ··· Signal processing circuit (PRC).

Claims

1. A solid-state imaging device having pixels capable of performing photoelectric conversion and reading out signals corresponding to at least three conversion gains, wherein each pixel includes: a floating diffusion that holds charges to be transferred and converts them into a voltage corresponding to the capacitance in order to read out the transferred charges as a voltage signal; a photoelectric conversion element that accumulates charges corresponding to the amount of incident light during an exposure period; a transfer element that is held in a non-conductive state during the exposure period and in a conductive state during a transfer period to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion; a reset element capable of performing a reset process for discharging at least the accumulated charges in the floating diffusion; a first capacitive element controlled to be connected or disconnected to the floating diffusion according to the conversion gain; a first connection element that selectively connects the floating diffusion and the first capacitive element; a second capacitive element capable of accumulating overflow charges that overflow from the photoelectric conversion element; a second connection element that selectively connects the floating diffusion and the second capacitive element; an overflow path capable of overflowing the charges that overflow from the photoelectric conversion element in the direction of the formation region of the second capacitive element; an overflow gate element formed on the overflow path for controlling the conductivity of the overflow path; a source follower element that amplifies and outputs the voltage signal converted by the floating diffusion; and includes a solid-state imaging device.

2. The pixel of claim 1, further comprising a third connection element that selectively connects the second connection element and the floating diffusion. The solid-state imaging device according to claim 1.

3. The overflow gate element is shared with the second connection element, the shared second connection element is connected between the floating diffusion and the reset element, the second capacitive element is connected to a connection node between the second connection element and the reset element, and the first connection element and the first capacitive element are connected in series between the floating diffusion and a reference potential. The solid-state imaging device according to claim 1.

4. The overflow gate element is shared with the second connection element, The first connection element and the shared second connection element are connected in series between the floating diffusion and the reset element, The first capacitive element is connected to a connection node between the first connection element and the second connection element, The second capacitive element is connected to a connection node between the second connection element and the reset element The solid-state imaging device according to claim 1.

5. It has a pixel section in which a plurality of the pixels are arranged, The pixel section, has a pixel sharing structure in which at least two adjacent pixels share the floating diffusion The solid-state imaging device according to claim 1.

6. The pixel section, shares the reset element with at least two adjacent pixels The solid-state imaging device according to claim 5.

7. The pixel section, shares the first capacitive element and the first connection element with at least two adjacent pixels The solid-state imaging device according to claim 5 or 6.

8. a pixel section in which the pixels are arranged, and a reading section that reads out pixel signals from the pixels in the pixel section, The reading section, by selectively connecting the floating diffusion and the first capacitive element through the first connection element, the capacitance of the floating diffusion can be changed to a first capacitance or a second capacitance, and the conversion gain can be switched to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance, by connecting the floating diffusion and the second capacitive element through the second connection element, the capacitance of the floating diffusion can be changed to a third capacitance, and the conversion gain can be switched to a third conversion gain determined by the third capacitance The solid-state imaging device according to any one of claims 1 to 7.

9. The reading section, in the dual conversion gain reading mode, sequentially performs a second conversion gain reset reading process, a first conversion gain reset reading process, a first conversion gain signal reading process, and a second conversion gain signal reading process, in the overflow reading mode for overflow charge, sequentially performs a third conversion gain signal reading process and a third conversion gain reset reading process The solid-state imaging device according to claim 8.

10. The reading section, The reset element, the first connection element, the second connection element, and the transfer element are kept in a conductive state for a predetermined period to reset the photoelectric conversion element, the floating diffusion, the first capacitance element, and the second capacitance element. After the transfer element is turned off to start the exposure period, As processing in the dual conversion gain readout mode, second conversion gain reset readout processing, first conversion gain reset readout processing, the first conversion gain signal readout processing, and second conversion gain signal readout processing are sequentially performed. Subsequently, as processing in the overflow readout mode for overflow charge, third conversion gain signal readout processing and third conversion gain reset readout processing are sequentially performed. The solid-state imaging device according to claim 9.

11. The readout unit In the dual conversion gain readout mode, before the first conversion gain reset readout processing, the reset element performs reset processing of the floating diffusion. The solid-state imaging device according to claim 10.

12. The readout unit After a predetermined period has elapsed since the start of the exposure period, The first connection element is switched to a conductive state for a predetermined period to connect the first capacitance element to the floating diffusion, and the charge of the floating diffusion and the charge of the first capacitance element are shared to switch the gain of the floating diffusion to a second conversion gain determined by the second capacitance. In a first reset readout period, a second readout reset signal converted with a second conversion gain determined by the second capacitance of the floating diffusion is read out from the source follower element, and second conversion gain reset readout processing for performing predetermined processing on the second readout reset signal. The first connection element is switched to a non-conductive state to disconnect the first capacitance element from the floating diffusion, and the charge of the floating diffusion and the charge of the first capacitance element are separated to switch the gain of the floating diffusion to a first conversion gain determined by the first capacitance. During a second reset read period following the first reset read period, a first read reset signal converted with a first conversion gain determined by the first capacitance of the floating diffusion from the source follower element is read, and a first conversion gain reset read process for performing a predetermined process on the first read reset signal is performed. During a first read period following a first transfer period after the second reset read period, a first read signal converted with a first conversion gain determined by the first capacitance of the floating diffusion from the source follower element is read, and a first conversion gain signal read process for performing a predetermined process on the first read signal is performed. After the first conversion gain signal read process, the first connection element is switched to a conductive state to connect the first capacitive element to the floating diffusion, and the charge of the floating diffusion and the charge of the first capacitive element are shared to switch the gain of the floating diffusion to a second conversion gain determined by the second capacitance. During a second read period following a second transfer period after the first read period, a second read signal converted with a second conversion gain determined by the second capacitance of the floating diffusion from the source follower element is read, and a second conversion gain signal read process for performing a predetermined process on the second read signal is performed. After the second conversion gain signal read process, the second connection element is switched to a conductive state to connect the second capacitive element to the floating diffusion, and the charge of the floating diffusion and the charges of the first capacitive element and the second capacitive element are shared to switch the gain of the floating diffusion to a third conversion gain determined by the third capacitance. During a third read period following the second read period, a third read signal converted with a third conversion gain determined by the third capacitance of the floating diffusion from the source follower element is read, and a third conversion gain signal read process for performing a predetermined process on the third read signal is performed. After resetting the floating diffusion by the reset element, a third read reset signal converted by the source follower element with a third conversion gain determined by the third capacitance of the floating diffusion is read out, and a third conversion gain reset readout process for performing predetermined processing on the third read reset signal is performed. The solid-state imaging device according to claim 10.

13. The readout unit After a predetermined period has elapsed since the start of the exposure period The first connection element is switched to a conductive state for a predetermined period to connect the first capacitive element to the floating diffusion, and the charges of the floating diffusion and the first capacitive element are shared to switch the gain of the floating diffusion to a second conversion gain determined by the second capacitance. After resetting the floating diffusion by the reset element, in a first reset readout period, a second read reset signal converted by the source follower element with a second conversion gain determined by the second capacitance of the floating diffusion is read out, and a second conversion gain reset readout process for performing predetermined processing on the second read reset signal is performed. The first connection element is switched to a non-conductive state to disconnect the first capacitive element from the floating diffusion, and the charges of the floating diffusion and the first capacitive element are separated to switch the gain of the floating diffusion to a first conversion gain determined by the first capacitance. In a second reset readout period following the first reset readout period after the reset process, a first read reset signal converted by the source follower element with a first conversion gain determined by the first capacitance of the floating diffusion is read out, and a first conversion gain reset readout process for performing predetermined processing on the first read reset signal is performed. In a first readout period following the first transfer period after the second reset readout period, a first readout signal converted by the source follower element with a first conversion gain determined by the first capacitance of the floating diffusion is read out, and a first conversion gain signal readout process for performing predetermined processing on the first readout signal is performed. After the first conversion gain signal readout process, switch the first connection element to a conductive state to connect the first capacitive element to the floating diffusion, share the charge of the floating diffusion and the charge of the first capacitive element, and switch the gain of the floating diffusion to a second conversion gain determined by the second capacitance. In a second read period following the second transfer period after the first read period, read out a second read signal converted from the source follower element with a second conversion gain determined by the second capacitance of the floating diffusion, and perform a second conversion gain signal readout process for performing a predetermined process on the second read signal. After the second conversion gain signal readout process, switch the second connection element to a conductive state to connect the second capacitive element to the floating diffusion, share the charge of the floating diffusion and the charges of the first capacitive element and the second capacitive element, and switch the gain of the floating diffusion to a third conversion gain determined by the third capacitance. In a third read period following the second read period, read out a third read signal converted from the source follower element with a third conversion gain determined by the third capacitance of the floating diffusion, and perform a third conversion gain signal readout process for performing a predetermined process on the third read signal. After resetting the floating diffusion by the reset element, read out a third read reset signal converted from the source follower element with a third conversion gain determined by the second capacitance of the floating diffusion, and perform a third conversion gain reset readout process for performing a predetermined process on the third read reset signal. The solid-state imaging device according to claim 11.

14. The readout unit Performs the second conversion gain reset readout process and the first conversion gain reset readout process during the exposure period. The solid-state imaging device according to claim 12 or 13.

15. Has a pixel capable of performing photoelectric conversion and reading out signals corresponding to at least three conversion gains. The pixel A floating diffusion that holds the transferred charge as a voltage signal and converts it to a voltage corresponding to the capacitance. A photoelectric conversion element that accumulates charges corresponding to the incident light amount during the exposure period. During the exposure period, it is held in a non-conductive state, and during the transfer period, it is held in a conductive state to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion, a transfer element; A reset element capable of performing at least a reset process for discharging the accumulated charge of the floating diffusion; A first capacitive element controlled to be in a connected state or a non-connected state with the floating diffusion according to the conversion gain; A first connection element that selectively connects the floating diffusion and the first capacitive element; A second capacitive element capable of accumulating overflow charges overflowing from the photoelectric conversion element; A second connection element that selectively connects the floating diffusion and the second capacitive element; An overflow path capable of overflowing the charges overflowing from the photoelectric conversion element in the direction of the formation region of the second capacitive element; An overflow gate element formed on the overflow path for controlling the conduction of the overflow path; A source follower element that amplifies and outputs the voltage signal converted by the floating diffusion; Including A driving method for a solid-state imaging device, By selectively connecting the floating diffusion and the first capacitive element through the first connection element, The capacitance of the floating diffusion is changed to a first capacitance or a second capacitance, and the conversion gain is switched to a first conversion gain determined by the first capacitance or a second conversion gain determined by the second capacitance, Connecting the floating diffusion and the second capacitive element through the second connection element, and connecting the floating diffusion and the second capacitive element through the second connection element, Changing the capacitance of the floating diffusion to a third capacitance and switching the conversion gain of the floating diffusion to a third conversion gain determined by the third capacitance A driving method for a solid-state imaging device.

16. A solid-state imaging device, An optical system that forms a subject image on the solid-state imaging device, and has The solid-state imaging device Performs photoelectric conversion and has pixels capable of reading out signals corresponding to at least three conversion gains, The pixel A floating diffusion that holds the transferred charge as a voltage signal and converts it into a voltage corresponding to the capacitance; A photoelectric conversion element that accumulates charges corresponding to the incident light amount during the exposure period; A transfer element that is kept in a non-conductive state during the exposure period and is kept in a conductive state during the transfer period to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion; A reset element capable of performing at least a reset process for discharging the stored charge in the floating diffusion; A first capacitive element controlled to be in a connected state or a non-connected state with the floating diffusion according to a conversion gain; A first connection element that selectively connects the floating diffusion and the first capacitive element; A second capacitive element capable of storing overflow charge overflowing from the photoelectric conversion element; A second connection element that selectively connects the floating diffusion and the second capacitive element; An overflow path capable of overflowing the charge overflowing from the photoelectric conversion element in the direction of the formation region of the second capacitive element; An overflow gate element formed on the overflow path for controlling the conduction of the overflow path; A source follower element that amplifies and outputs the voltage signal converted by the floating diffusion; including an electronic device.

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