Semiconductor device, and electronic apparatus

Abstract

Provided is a semiconductor device whereby long data retention time is achieved. The present invention pertains to a semiconductor device including a first transistor, a second transistor, a ferroelectric capacitor, a first capacitance, and a memory cell. Further, the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor, and a first terminal of the second transistor. In addition, a second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor, and a first terminal of the first capacitance. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the configuration described above, by applying a negative potential to the first terminal of the first transistor, a threshold voltage of the third transistor can be made high.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification or the like relates to an object, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

Background Art

[0003] Metal oxides have attracted attention as semiconductors applicable to transistors. In particular, In-Ga-Zn oxide is a typical multi-component metal oxide. In the research on In-Ga-Zn oxide, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystals nor amorphous, have been found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has been reported to have an extremely small off-current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process of the OS transistor can be incorporated into the CMOS process with conventional Si transistors, and the OS transistor can be stacked on the Si transistor. For example, Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having OS transistors are stacked on a substrate provided with Si transistors.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0008] As described above, since the off-current flowing through the OS transistor is extremely small, for example, by applying the OS transistor to a writing transistor included in a memory cell of a memory device, etc., a memory cell with a small leak due to the off-current can be configured.

[0009] By the way, in recent years, the amount of data handled in electronic devices and the like has been increasing, and in order to increase the storage capacity, attempts have been made to miniaturize memory devices, particularly memory cells. As for the miniaturization of memory cells, when reducing the size of the writing transistor (for example, channel length, channel width, etc.), variations are likely to occur in the electrical characteristics of the writing transistors included in each of the plurality of memory cells. In particular, when variations occur in the threshold voltage of each writing transistor, the off-current may increase in some writing transistors, and the data retention time of the memory cell including the writing transistor may be shortened. Therefore, as the writing transistor, in order to increase the threshold voltage, it is preferable to adopt a transistor configuration capable of controlling the threshold voltage. Further, it is preferable that an external circuit for controlling the threshold voltage of the transistor is provided in the memory device.

[0010] One aspect of the present invention is to provide a semiconductor device having a circuit for controlling the threshold voltage of a transistor. Or, one aspect of the present invention is to provide a semiconductor device having a memory cell with a long data retention time. Or, one aspect of the present invention is to provide a semiconductor device capable of reducing the number of refresh times of data held in a memory cell. Or, one aspect of the present invention is to provide a novel semiconductor device. Or, one aspect of the present invention is to provide an electronic device having the semiconductor device.

[0011] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are problems not mentioned in this item as described below. Problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not necessarily solve all of the problems listed above and other problems.

Means for Solving the Problems

[0012] (1) One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a ferroelectric capacitor, and a first capacitor. The first gate of the first transistor is electrically connected to the first terminal of the ferroelectric capacitor, and the first terminal of the first transistor is electrically connected to the second gate of the first transistor and the first terminal of the second transistor. Further, the second terminal of the second transistor is electrically connected to the second terminal of the ferroelectric capacitor and the first terminal of the first capacitor.

[0013] (2) Or, in the above (1), one aspect of the present invention may be configured such that the ferroelectric capacitor has a dielectric, and the dielectric has an oxide containing one or both of hafnium and zirconium.

[0014] (3) Alternatively, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor. A first gate of the first transistor is electrically connected to a first terminal of the first ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. Further, a second terminal of the second transistor is electrically connected to a second terminal of the first ferroelectric capacitor and a first terminal of the second ferroelectric capacitor.

[0015] (4) Alternatively, in the above (3), each of the first ferroelectric capacitor and the second ferroelectric capacitor may have a configuration in which the dielectric has an oxide containing one or both of hafnium and zirconium.

[0016] (5) Alternatively, one aspect of the present invention may have a configuration having a second capacitance in any one of the above (1) to (4). In particular, it is preferable that a first terminal of the second capacitance is electrically connected to a first terminal of the first transistor and a first terminal of the second transistor.

[0017] (6) Alternatively, one aspect of the present invention may have a configuration in which a second gate of the second transistor is electrically connected to a first gate of the second transistor in any one of the above (1) to (5).

[0018] (7) Alternatively, one aspect of the present invention may have a configuration including a memory cell including a third transistor in any one of the above (1) to (6). In particular, it is preferable that one of a first gate and a second gate of the third transistor is electrically connected to a first terminal of the first transistor.

[0019] (8) Alternatively, one aspect of the present invention is an electronic device having any one of the semiconductor devices (1) to (7) described above and a housing.

[0020] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device may be a semiconductor device itself or may have a semiconductor device.

[0021] In this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected, as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. It is assumed that X and Y are objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0022] As an example of the case where X and Y are electrically connected, one or more elements (such as a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable electrical connection between X and Y can be connected between X and Y. Note that a switch has a function of controlling on / off. That is, a switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0023] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (such as inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (such as digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (such as power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0024] Note that when it is explicitly described that X and Y are electrically connected, it shall include the case where X and Y are electrically connected (that is, connected with another element or another circuit sandwiched between X and Y) and the case where X and Y are directly connected (that is, connected without another element or another circuit sandwiched between X and Y).

[0025] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By stipulating the connection order in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0026] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of a plurality of components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component. Therefore, the electrically connected in this specification includes such a case where one conductive film has the functions of a plurality of components within its scope.

[0027] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" may sometimes be replaced with terms such as "resistance", "load", "region having a resistance value". Conversely, the terms "resistance", "load", "region having a resistance value" may sometimes be replaced with terms such as "resistive element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0028] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, parasitic capacitance, the gate capacitance of a transistor, and the like. Therefore, in this specification and the like, the "capacitive element" includes a circuit element including a pair of electrodes and a dielectric contained between the electrodes. Also, the terms "capacitive element", "parasitic capacitance", "gate capacitance", etc. may sometimes be replaced with terms such as "capacitance". Conversely, the term "capacitance" may sometimes be replaced with terms such as "capacitive element", "parasitic capacitance", "gate capacitance". Also, the term "pair of electrodes" of "capacitance" can be replaced with "pair of conductors", "pair of conductive regions", "pair of regions", etc. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less.

[0029] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain may be interchangeable with each other. Further, in this specification and the like, when explaining the connection relationship of the transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, it may have a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0030] For example, in this specification and the like, as an example of a transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used. When a multi-gate structure is adopted, since the channel formation regions are connected in series, it has a structure in which a plurality of transistors are connected in series. Therefore, with the multi-gate structure, it is possible to reduce the off-current and improve the breakdown voltage (reliability) of the transistor. Alternatively, with the multi-gate structure, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and voltage-current characteristics with a flat slope can be obtained. Utilizing the voltage-current characteristics with a flat slope, an ideal current source circuit or an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0031] Also, on a circuit diagram, even when a single circuit element is illustrated, the circuit element may have a plurality of circuit elements. For example, when one resistor is described on the circuit diagram, it shall include the case where two or more resistors are electrically connected in series. Also, for example, when one capacitor is described on the circuit diagram, it shall include the case where two or more capacitors are electrically connected in parallel. Also, for example, when one transistor is described on the circuit diagram, it shall include the case where two or more transistors are electrically connected in series and the gates of the respective transistors are electrically connected to each other. Similarly, for example, when one switch is described on the circuit diagram, the switch has two or more transistors, and the two or more transistors are electrically connected in series or in parallel, and the gates of the respective transistors are electrically connected to each other.

[0032] Also, in this specification and the like, a node can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., according to the circuit configuration, device structure, etc. Also, it is possible to rephrase a terminal, wiring, etc. as a node.

[0033] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to a wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc., also change.

[0034] Also, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, in two wirings, if both are described as "functioning as a wiring that supplies a high-level potential", the respective high-level potentials provided by the two wirings do not necessarily have to be equal to each other. Similarly, in two wirings, if both are described as "functioning as a wiring that supplies a low-level potential", the respective low-level potentials provided by the two wirings do not necessarily have to be equal to each other.

[0035] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers, unless otherwise specified. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring, etc., is defined as the direction in which the carrier that becomes a positive charge moves, and is described with a positive current amount. In other words, the direction in which the carrier that becomes a negative charge moves is the opposite direction to the direction of current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0036] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0037] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and the like, and can be appropriately rephrased according to the situation. For example, in the expression "insulator located on the upper surface of the conductor", by rotating the orientation of the shown drawing by 180 degrees, it can be rephrased as "insulator located on the lower surface of the conductor".

[0038] Also, the terms "above" or "below" do not limit the positional relationship of components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly in contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0039] In addition, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other according to the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or according to the situation, it is possible to replace the terms such as "film" and "layer" with other terms without using them. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0040] In addition, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the term "electrode" or "wiring" also includes cases where a plurality of "electrodes" or / and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced by terms such as "region" in some cases.

[0041] In addition, in this specification and the like, terms such as "wiring", "signal line", "power supply line", etc. can be interchanged with each other depending on the case or the situation. For example, the term "wiring" may be changed to the term "signal line" in some cases. Also, for example, the term "wiring" may be changed to terms such as "power supply line" in some cases. Also, vice versa, terms such as "signal line" and "power supply line" may be changed to the term "wiring" in some cases. Terms such as "power supply line" may be changed to terms such as "signal line" in some cases. Also, vice versa, terms such as "signal line" may be changed to terms such as "power supply line" in some cases. Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or the situation in some cases. Also, vice versa, terms such as "signal" may be changed to the term "potential" in some cases.

[0042] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic% are impurities. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, etc. (however, oxygen and hydrogen are not included).

[0043] In this specification and the like, a switch refers to something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not an electric current flows. Or, a switch refers to something that has a function of selecting and switching the path through which an electric current flows. Therefore, a switch may have two or three or more terminals through which an electric current flows, in addition to the control terminal. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, a switch only needs to be able to control an electric current and is not limited to a specific one.

[0044] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When using a transistor as a switch, the "conducting state" of the transistor means, for example, a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited, a state where a current can flow between the source electrode and the drain electrode, etc. Also, the "non-conducting state" of the transistor means a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically interrupted. When operating a transistor simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0045] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation.

[0046] In this specification, "parallel" means a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" or "approximately parallel" means a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" or "approximately perpendicular" means a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0047] According to one aspect of the present invention, a semiconductor device having a circuit for controlling the threshold voltage of a transistor can be provided. Or, according to one aspect of the present invention, a semiconductor device having a memory cell with a long data retention time can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of reducing the number of refresh times of data held in a memory cell can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, an electronic device having the semiconductor device can be provided.

[0048] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are the effects not mentioned in this item described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of the Drawings

[0049] FIG. 1A and FIG. 1B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 2A and FIG. 2B are timing charts showing an operation example of a semiconductor device. FIG. 3A and FIG. 3B are timing charts showing an operation example of a semiconductor device. FIG. 4A and FIG. 4B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 5A and FIG. 5B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 8A and FIG. 8B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 9 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 10A and FIG. 10B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 11A and FIG. 11B are circuit diagrams showing a configuration example of a circuit included in a semiconductor device. FIG. 12 is a block diagram showing a configuration example of a storage device including a semiconductor device. FIG. 13 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIGS. 14A to 14C are schematic cross-sectional views showing a configuration example of a transistor. FIG. 15A is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIGS. 16A and 16B are schematic cross-sectional views showing a configuration example of a transistor. FIG. 17 is a schematic cross-sectional view showing a configuration example of a transistor. FIGS. 18A to 18C are schematic cross-sectional views showing a configuration example of a transistor. FIG. 19 is a schematic cross-sectional view showing a configuration example of a transistor. FIGS. 20A and 20B are schematic cross-sectional views showing a configuration example of a transistor. FIGS. 21A and 21B are schematic cross-sectional views showing a configuration example of a transistor. FIG. 22 is a schematic cross-sectional view showing a configuration example of a transistor. FIG. 23 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 25A is a diagram for explaining the classification of crystal structures, FIG. 25B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 25C is a diagram for explaining the selected area electron diffraction pattern of crystalline IGZO. FIG. 26A is a perspective view showing an example of a semiconductor wafer, FIG. 26B is a perspective view showing an example of a chip, and FIGS. 26C and 26D are perspective views showing an example of an electronic component. FIG. 27 is a block diagram for explaining a CPU. FIGS. 28A to 28(J) are perspective views or schematic diagrams for explaining an example of a product. FIGS. 29A to 29E are perspective views or schematic diagrams for explaining an example of a product.

DETAILED DESCRIPTION OF THE INVENTION

[0050] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is included in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute the channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Further, when referring to an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0051] Also, in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0052] Also, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0053] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with at least one of the content described in another content (even a part of the content) described in the same embodiment and the content (even a part of the content) described in one or more other embodiments.

[0054] Note that the content described in the embodiments refers to the content described using various figures or the text described in the specification in each embodiment.

[0055] Note that the figure (which may be a part) described in one embodiment can be combined with another part of that figure, another figure (which may be a part) described in that embodiment, and at least one figure described in one or more other embodiments to form more figures.

[0056] The embodiments described in this specification are being explained with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways and that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the content described in the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used between different drawings for the same part or parts having similar functions, and the repeated description may be omitted. Also, in perspective views and the like, for the sake of clarity of the drawings, the description of some components may be omitted.

[0057] In this specification and the like, when the same reference numerals are used for a plurality of elements, particularly when it is necessary to distinguish them, a distinguishing reference numeral such as "_1", "[n]", "[m,n]" may be appended to the reference numeral for description. Also, in the drawings and the like, when a distinguishing reference numeral such as "_1", "[n]", "[m,n]" is appended to the reference numeral, the distinguishing reference numeral may not be described when it is not necessary to distinguish them in this specification and the like.

[0058] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0059] (Embodiment 1) In this embodiment, the circuit configuration of a semiconductor device according to one aspect of the present invention will be described.

[0060] <Configuration Example 1> FIG. 1A shows, as an example, a holding circuit for holding the potential of the back gate of transistor ME. Circuit HC, which is a holding circuit, includes transistor M1, transistor M2, capacitor C1, and capacitor FEC1.

[0061] Each of transistor M1 and transistor M2 is preferably an OS transistor. In addition, it is more preferable that the channel formation regions of each of transistor M1 and transistor M2 contain an oxide containing at least one of indium, gallium, and zinc. Alternatively, the channel formation regions of transistor M1 and transistor M2 may be an oxide containing at least one of indium, element M (element M includes, for example, one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc. Further, it is more preferable that transistor M1 and transistor M2 have the structure of the transistor described in Embodiment 3.

[0062] In addition, unless otherwise specified, transistors M1 and M2 shall include those that function as switching elements. That is, the gates, sources, and drains of transistors M1 and M2 shall include cases where voltages within the range in which each of transistors M1 and M2 operates as a switching element are appropriately input.

[0063] The capacitor FEC1 is a capacitor having a material that can have ferroelectricity as a dielectric. In this specification and the like, a capacitor using a material that can have ferroelectricity as a dielectric is referred to as a ferroelectric capacitor.

[0064] Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (where X is a real number greater than 0), a material obtained by adding element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, a material obtained by adding element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like. Further, as materials that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as PbTiO X , barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. In addition, as materials that can have ferroelectricity, for example, they can be a mixture or compound selected from the materials listed above. Or, as materials that can have ferroelectricity, they can be a laminated structure composed of a plurality of materials selected from the materials listed above. By the way, hafnium oxide, zirconium oxide, HfZrO XMaterials such as hafnium oxide with element J1 added thereto may have their crystal structures (properties) changed not only by film formation conditions but also by various processes. Therefore, in this specification and the like, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that may have ferroelectricity or materials that can be made to have ferroelectricity are also referred to as such.

[0065] Materials that may have ferroelectricity are insulators. When an electric field is applied from the outside, polarization occurs inside, and the polarization remains even when the electric field is set to zero. Therefore, they can be applied as non-volatile memory elements. Thus, by using such a material as a dielectric sandwiched between a pair of electrodes of a capacitor, the capacitor can be referred to as a "capacitor that may have ferroelectricity" or a "ferroelectric capacitor". Also, in this specification and the like, there are cases where a material that may have ferroelectricity is said to be between the first terminal and the second terminal of the capacitor. Note that a memory circuit using a capacitor that may have ferroelectricity may be called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like.

[0066] In this specification and the like, the circuit symbol of a ferroelectric capacitor (for example, capacitor FEC1) is, as shown in Fig. 1A, the circuit symbol of a capacitor with diagonal lines added. As another circuit symbol, as shown in Fig. 1B, it may be the circuit symbol of a capacitor with a plurality of diagonal lines added between two lines that are parallel to each other.

[0067] The transistor M1, transistor M2, and transistor ME illustrated in FIG. 1 are, as an example, n-channel transistors having a structure with gates above and below the channel, and each of the transistor M1, transistor M2, and transistor ME has a first gate and a second gate. For convenience, as an example, the first gate is described as the gate (which may be referred to as the front gate), and the second gate is described as the back gate. However, the first gate and the second gate can be interchanged with each other. Therefore, in this specification and the like, the term "gate" can be described by interchanging with the term "back gate". Similarly, the term "back gate" can be described by interchanging with the term "gate". As a specific example, the connection configuration of "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration of "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring".

[0068] The first terminal of the transistor M1 is electrically connected to the wiring VIL, the second terminal of the transistor M1 is electrically connected to the back gate of the transistor M1 and the first terminal of the transistor M2, and the gate of the transistor M1 is electrically connected to the first terminal of the capacitor FEC1. Also, the second terminal of the transistor M2 is electrically connected to the second terminal of the capacitor FEC1 and the first terminal of the capacitor C1, and the gate of the transistor M2 is electrically connected to the wiring VGL. Also, the second terminal of the capacitor C1 is electrically connected to the wiring VCL.

[0069] In particular, each of the second terminal of the transistor M1, the back gate of the transistor M1, and the first terminal of the transistor M2 is assumed to be electrically connected to the back gate of the transistor ME. Note that depending on the circuit configuration, each of the second terminal of the transistor M1, the back gate of the transistor M1, and the first terminal of the transistor M2 may be electrically connected to the gate instead of the back gate of the transistor ME.

[0070] Also, in this specification and the like, the electrical connection point between the gate of transistor M1 and the first terminal of capacitor FEC1 is referred to as node N1. Also, the electrical connection point between the second terminal of capacitor FEC1, the first terminal of capacitor C1, and the second terminal of transistor M2 is referred to as node N2. Also, the electrical connection point between the second terminal of transistor M1, the back gate of transistor M1, and the first terminal of transistor M2 is referred to as node NBG. That is, the potential applied to the back gate of transistor ME can be the potential of node NBG.

[0071] Note that since node N1 is not electrically connected to circuit elements, terminals, wirings, etc. other than the gate of transistor M1 and the first terminal of capacitor FEC1, no voltage is directly input to node N1 from a voltage source or the like. Therefore, in the circuit configuration of FIG. 1, node N1 is in a floating state. Also, for this reason, the initial potential of node N1 can be determined at the time of manufacturing the semiconductor device (specifically, for example, at the time of forming circuit HC).

[0072] Wiring VIL functions as a wiring for applying a constant voltage. As the constant voltage, for example, when shifting the threshold voltage of transistor ME to the positive side, it can be a low-level potential, a ground potential, a negative potential, etc. Also, for example, when shifting the threshold voltage of transistor ME to the negative side, it can be a high-level potential, a positive potential, etc.

[0073] Wiring VCL functions as a wiring for applying a voltage for polarizing a ferroelectric material that may be included in capacitor FEC1. For example, when the voltage is a positive potential and the material is polarized, the direction of the electric field generated in the material is from the first terminal of capacitor FEC1 to the second terminal. Also, for example, when the voltage is a negative potential and the material is polarized, the direction of the electric field generated in the material is from the second terminal of capacitor FEC1 to the first terminal. Also, wiring VCL may supply a voltage that does not polarize the ferroelectric material that may be included in capacitor FEC1.

[0074] The wiring VGL functions as a wiring for supplying a signal (voltage) for controlling the switching between the on-state and the off-state of the transistor M2. For example, by setting the voltage provided by the wiring VGL to a high-level potential, the transistor M2 can be turned on, and by setting the voltage provided by the wiring VGL to a low-level potential, the transistor M2 can be turned off.

[0075] <Operation Example> Next, an operation example of the circuit HC in FIG. 1A will be described.

[0076] <<Operation Example of Writing Potential to the Capacitor FEC1>> FIG. 2A is a timing chart showing an operation example of the circuit HC. The timing chart in FIG. 2A shows the changes in the respective potentials of the wiring VCL, the wiring VGL, the wiring VIL, the node N1, the node N2, and the node NBG during the period from time T11 to time T16 and at times in the vicinity thereof. In particular, FIG. 2A shows an operation example of writing a potential to the capacitor FEC1. Also, in FIG. 2A, the high-level potential is denoted as "high" and the low-level potential is denoted as "low".

[0077] Between time T11 and time T12, potentials in the initial state are applied to each of the wiring VCL, the wiring VGL, and the wiring VIL that are electrically connected to the circuit HC. Specifically, for example, a potential V FC1 is applied to the wiring VCL, a high-level potential is applied to the wiring VGL, and a potential V IN1 is applied to the wiring VIL. Note that V FC1 can be, for example, a positive potential, a high-level potential, a ground potential, etc., and V IN1 can be, for example, a positive potential, a high-level potential, a ground potential, etc.

[0078] Also, let the potential of the node N1 be V 11 and the potential of the node N2 be V 12 Note that the potential V 11 of the node N1 is the potential V 21Set it to a lower potential. Also, the voltage between the first terminal and the second terminal of the capacitor FEC1 is |V 11 -V 21 |. At this voltage, it is assumed that no polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1. Also, between time T11 and time T12, as long as no polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1, the potential V 11 of node N1 is not lower than the potential V 21 of node N2, but may be equal to the potential V 21 or higher than the potential V 21 .

[0079] Since a high-level potential from the wiring VGL is applied to the gate of the transistor M2, the transistor M2 is in an on state. Therefore, the connection between node N2 and node NBG becomes conductive, and the potential V BG1 of node NBG becomes almost equal to the potential V 21 of node N2.

[0080] Between time T12 and time T13, a low-level potential is applied to the wiring VGL. As a result, a low-level potential from the wiring VGL is applied to the gate of the transistor M2, so the transistor M2 is in an off state.

[0081] Also, when the transistor M2 is turned off, node N2 becomes a floating state.

[0082] Between time T13 and time T14, the potential V FC1 applied by the wiring VCL changes to the potential V FC2 . The potential V FC2 is a potential lower than V FC1 and is a potential at which polarization occurs in the dielectric that may have ferroelectricity included in the capacitor FEC1.

[0083] Since node N2 is in a floating state, as the potential applied by the wiring VCL changes from V FC1 to V FC2By changing to, due to the capacitive coupling in capacitor C1, the potential of node N2 changes in response to the voltage change. In this operation example, between time T13 and time T14, the potential of node N2 changes from V 21 to V 22 . Note that since the potential V FC2 is lower than V FC1 , the potential V 22 is lower than V 21 .

[0084] Also, since node N1 is also in a floating state, when the potential of node N2 changes from V 21 to V 22 , due to the capacitive coupling in capacitor FEC1, the potential of node N1 changes in response to the voltage change. However, there is a gate capacitance between the gate and the first terminal of transistor M1 between node N1 and wiring VIL, and there is a gate capacitance between the gate and the second terminal of transistor M1 between node N1 and node NBG. Therefore, the voltage change at node N1 may be smaller than the voltage change V 21 -V 22 at node N2. At this time, assume that the potential of node N1 changes from V 11 to V 12 .

[0085] At this time, the voltage between the first terminal and the second terminal of capacitor FEC1 is |V 12 -V 22 |, and in capacitor FEC1, assume that polarization occurs in the dielectric that may have ferroelectricity contained in capacitor FEC1. That is, assume that the write operation to capacitor FEC1 is performed at this timing.

[0086] Also, by setting the potential V IN1 given by wiring VIL as a positive potential, a high-level potential, etc., and applying the potential V IN1 from wiring VIL to transistor M1, it may be possible to boost the potential of node N1 through the gate - first terminal of transistor M1. As a result, the voltage |V12 -V 22 | can be increased, and when it can be easily polarized in the dielectric that may have ferroelectricity included in the capacitance FEC1.

[0087] During the period from time T14 to time T15, the potential V provided by the wiring VCL FC2 is V FC1 changes. That is, the potential provided by the wiring VCL during the period from time T14 to time T15 is assumed to be equal to the potential provided by the wiring VCL at a time before time T13.

[0088] Since the node N2 is in a floating state after time T12, when the potential V provided by the wiring VCL FC2 is V FC1 changes, the potential of the node N2 returns from V 22 to V 21 .

[0089] When the potential of the node N2 changes from V 22 to V 21 , the potential V of the node N1 also changes due to the capacitive coupling of the capacitance FEC1. Since polarization has occurred in the dielectric that may have ferroelectricity included in the capacitance FEC1 during the operation from time T13 to time T14, the potential of the node N1 does not return to the original potential V 12 , but becomes a potential higher than the potential V 11 and smaller than the potential V 12 . Specifically, in this operation example, during the period from time T14 to time T15, the potential of the node N1 is assumed to change from the potential V 11 to the potential V 12 to the potential V 13 .

[0090] Note that the potential V 13 is lower than the potential V 21 and the potential V IN1 . Here, the gate-source voltage V 13 -V IN1It is assumed to be lower than the threshold voltage of transistor M1, and transistor M1 is turned off.

[0091] Between time T15 and time T16, a high-level potential is applied to wiring VGL. As a result, since the high-level potential from wiring VGL is applied to the gate of transistor M2, transistor M2 is turned on.

[0092] By the above operation, the potential can be written into capacitor FEC1.

[0093] <<Example of potential writing operation to the back gate of transistor ME>> Figure 2B is a timing chart showing an operation example of circuit HC. The timing chart of Figure 2B shows the potential changes of each of wiring VCL, wiring VGL, wiring VIL, node N1, node N2, and node NBG between time T21 and time T24 and at times in the vicinity thereof. In particular, Figure 2B shows an operation example of writing the potential to the back gate of transistor ME. Also, in Figure 2B, the high-level potential is denoted as "high" and the low-level potential is denoted as "low".

[0094] Time T21 is a time after time T16 in the timing chart of Figure 2A. Therefore, between time T21 and time T22, potential V FC1 is applied to wiring VCL, a high-level potential is applied to wiring VGL, and potential V IN1 is applied to wiring VIL. Also, the potential of node N1 is V 13 and the potential of node N2 is V 21 and node NBG is V BG1 (=V 21 ).

[0095] Between time T22 and time T23, the potential V IN1 applied by wiring VIL changes to potential V IN2 . Note that potential V IN2 is V IN1is at a lower potential. Also, the potential V IN2 can be, for example, a negative potential or the like.

[0096] Since the potential V is applied to the first terminal of the transistor M1 from the wiring VIL, the gate-source voltage of the transistor M1 is V IN2 - V 13 - V IN2 becomes. Here, V 13 - V IN2 is set to a voltage higher than the threshold voltage of the transistor M1.

[0097] V 13 - V IN2 By setting V - V to a voltage higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. Also, since a high-level potential is applied to the wiring VGL and the transistor M2 is also turned on, the potential from the wiring VIL is supplied to the node N2 via the transistor M1, the node NBG, and the transistor M2.

[0098] Specifically, the potentials of the node N2 and the node NBG each decrease from V 21 In this operation example, between time T22 and time T23, the potentials of the node N2 and the node NBG each decrease by the voltage ΔV 21 - ΔV BG It is assumed that. Also, the potentials of the node N2 and the node NBG each decrease by ΔV BG and become V BG2 .

[0099] Also, as the potential of the node N2 decreases from V 21 to V BG2 , the potential V 13 of the node N1 also decreases due to the capacitive coupling of the capacitor FEC1. In this operation example, between time T22 and time T23, the potential of the node N1 is assumed to be V 13 - αΔV BG . Here, α is the capacitive coupling coefficient in the capacitor FEC1.

[0100] Between time T23 and time T24, the potential V provided by wiring VIL IN2 becomes V IN1 changes. That is, it is assumed that the potential provided by wiring VIL between time T23 and time T24 is equal to the potential provided by wiring VIL at a time before time T22.

[0101] At this time, since the potential V IN1 from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V 13 -αΔV BG -V IN1 Note that V 13 -αΔV BG is a potential lower than V 13 and V 13 is a potential lower than V IN1 Also, since V 13 -V IN1 is lower than the threshold voltage of transistor M1, V 13 -αΔV BG -V IN1 is also lower than the threshold voltage of transistor M1. As a result, between time T23 and time T24, transistor M1 is in an off state.

[0102] By the above operation, a voltage V BG2 can be written to node NBG of circuit HC. In particular, by setting V IN2 to a negative potential, V BG2 can be set to a negative potential, and the negative potential V BG2 can be written to node NBG of circuit HC. Also, since the gate-source voltage of transistor M1 can be made lower than the threshold voltage to turn transistor M1 off, the negative potential V BG2 of node NBG can be held for a long time. As a result, a negative potential V BG2 is applied to the back gate of transistor ME for a long time.can be given. Also, depending on the situation, a similar operation may be performed to refresh the negative potential held in the node NBG.

[0103] [[Operation of rewriting the potential applied to node NBG]] Next, an operation example of rewriting the potential of node NBG after time T24 in the operation example of FIG. 2B will be described.

[0104] [[When lowering the potential of node NBG]] When it is desired to lower the potential of node NBG, for example, the circuit HC may be operated as shown in the timing chart of FIG. 3A. The timing chart of FIG. 3A shows the changes in the potentials of the wiring VCL, wiring VGL, wiring VIL, node N1, node N2, and node NBG from time T31 to time T34 and at times in the vicinity thereof. Also, in FIG. 3A, the high-level potential is denoted as "high" and the low-level potential is denoted as "low".

[0105] Time T31 is a time after time T24 in the timing chart of FIG. 2B. Therefore, between time T31 and time T32, the potential V FC1 is applied to the wiring VCL, a high-level potential is applied to the wiring VGL, and the potential V IN1 is applied to the wiring VIL. Also, the potential of node N1 is V 13 -αΔV BG , the potential of node N2 is V BG2 , and node NBG is V BG2 .

[0106] Between time T32 and time T33, the potential V IN1 applied by the wiring VIL changes to the potential V IN3 . Note that the potential V IN3 is a potential lower than V IN2 . Also, the potential V IN3 can be, for example, a negative potential lower than V IN2 .

[0107] Since the potential V is applied to the first terminal of the transistor M1 from the wiring VIL, the gate-source voltage of the transistor M1 is V IN3 - αΔV 13 - V BG - V IN3 - αΔV 13 - V BG - V IN3 shall be a voltage higher than the threshold voltage of the transistor M1.

[0108] V 13 - αΔV BG - V IN3 is higher than the threshold voltage of the transistor M1, so the transistor M1 is in the on state. Also, since a high-level potential is applied to the wiring VGL and the transistor M2 is also in the on state, the potential from the wiring VIL is supplied to the node N2 through the transistor M1, the node NBG, and the transistor M2.

[0109] Specifically, the potentials of the node N2 and the node NBG each decrease from V BG2 In this operation example, during the period from time T32 to time T33, the potentials of the node N2 and the node NBG each decrease by the voltage ΔV BG2 from V BGN . Also, the potentials of the node N2 and the node NBG each decrease by ΔV BGN and become the potential V BG3 .

[0110] Also, as the potential of the node N2 decreases from V BG2 to V BG3 , the potential of the node N1 also decreases from V 13 - αΔV BG due to the capacitive coupling of the capacitor FEC1. In this operation example, during the period from time T32 to time T33, the potential of the node N1 is V 13 - α(ΔV BG + ΔV BGN ).

[0111] Between time T33 and time T34, the potential V provided by wiring VIL IN3 changes to V IN1 . That is, the potential provided by wiring VCL between time T33 and time T34 is assumed to be equal to the potential provided by wiring VIL at a time before time T32.

[0112] At this time, since the potential V from wiring VIL is applied to the first terminal of transistor M1 IN1 , the gate-source voltage of transistor M1 is V 13 - α(ΔV BG + ΔV BGN ) - V IN1 . Note that V 13 - α(ΔV BG + ΔV BGN ) is a potential lower than V 13 , and V 13 is a potential lower than V IN1 . Also, since V 13 - V IN1 is lower than the threshold voltage of transistor M1, V 13 - α(ΔV BG + ΔV BGN ) - V IN1 is also lower than the threshold voltage of transistor M1. As a result, between time T33 and time T34, transistor M1 is in the off state.

[0113] By causing the circuit HC to perform the operation example of FIG. 3B, the voltage written to node NBG in the operation example of FIG. 2B can be rewritten to a smaller voltage.

[0114] [When increasing the potential of node NBG] When it is desired to increase the potential of node NBG, for example, as shown in the timing chart of FIG. 3B, the circuit HC may be operated. The timing chart of FIG. 3B shows the changes in the respective potentials of the wiring VCL, wiring VGL, wiring VIL, node N1, node N2, and node NBG from time T41 to time T44 and at times in the vicinity thereof. Also, in FIG. 3B, the high-level potential is denoted as "high" and the low-level potential is denoted as "low".

[0115] Time T41 is set to be a time after time T24 in the timing chart of FIG. 2B. Therefore, between time T41 and time T42, potential V is applied to the wiring VCL, a high-level potential is applied to the wiring VGL, and potential V is applied to the wiring VIL. FC1 is applied, a high-level potential is applied to the wiring VGL, and potential V is applied to the wiring VIL. IN1 is applied. Also, the potential of node N1 is V 13 -αΔV BG and the potential of node N2 is V BG2 and node NBG is V BG2 .

[0116] Between time T42 and time T43, the potential V applied by the wiring VCL changes to potential V FC1 to potential V FC3 . Note that potential V FC3 is a potential higher than V FC1 .

[0117] When nodes N2 and NBG are in a floating state, as the potential applied by the wiring VCL changes from V FC1 to V FC3 , due to capacitive coupling in capacitor C1, the potentials of nodes N2 and NBG also change in response to the voltage change. In this operation example, between time T42 and time T43, the respective potentials of nodes N2 and NBG are assumed to increase by voltage ΔV BG2 from V BGP . Also, the respective potentials of nodes N2 and NBG are assumed to increase by ΔV BGP and become potential V BG4 .

[0118] Also, since node N1 is also in a floating state, as the potential of node N2 changes from V BG2 to V BG4 , due to capacitive coupling in capacitor FEC1, the potential of node N1 also changes in response to that voltage change. In this operation example, the potential of node N1 changes from V 13 -αΔV BG to V 13 -α(ΔV BG -ΔV BGP ).

[0119] Note that between time T42 and time T43, it is assumed that the voltage between node N1 and node N2 does not cause polarization reversal in the dielectric that may have ferroelectricity included in capacitor FEC1. In other words, the voltage that changes from potential V FC1 to potential V FC3 applied from wiring VCL is a voltage such that polarization reversal does not occur in the said dielectric.

[0120] Since the potential V IN1 from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V 13 -α(ΔV BG -ΔV BGP )-V IN1 . Between time T41 and time T42, the gate-source voltage of transistor M1 is V 13 -αΔV BG -V IN1 , so due to the operation from time T42 to time T43 (the change in the potential applied by wiring VCL from V FC1 to V FC3 ), the gate-source voltage of transistor M1 has increased by ΔV BGP .

[0121] Here, V 13 -α(ΔV BG -ΔV BGP )-V IN1Assuming that it is smaller than the threshold voltage of transistor M1, transistor M1 is turned off.

[0122] Between time T43 and time T44, the potential V provided by wiring VIL IN1 changes to potential V IN4 . Note that potential V IN4 is a potential lower than V IN1 and higher than potential V IN2 . Also, potential V IN4 can be, for example, a negative potential lower than V IN1 and higher than V IN2 .

[0123] Since the potential V from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V IN4 -α(ΔV 13 -ΔV BG -ΔV BGP )-V IN4 . Here, V 13 -α(ΔV BG -ΔV BGP )-V IN4 is a voltage higher than the threshold voltage of transistor M1.

[0124] By setting V 13 -α(ΔV BG -ΔV BGP )-V IN4 to be a voltage higher than the threshold voltage of transistor M1, transistor M1 is turned on. Also, since a high-level potential is applied to wiring VGL and transistor M2 is also turned on, the potential from wiring VIL is supplied from wiring VIL to node N2 through transistor M1, node NBG, and transistor M2.

[0125] Specifically, the potentials of node N2 and node NBG each decrease from V BG4 . In this operation example, between time T43 and time T44, the potentials of node N2 and node NBG each are V BG4from voltage ΔV BGQ shall only decrease. Also, the potential of each of node N2 and node NBG shall decrease by ΔV BGQ and become potential V BG5 .

[0126] Also, as the potential of node N2 decreases from V BG4 to V BG5 , due to the capacitive coupling of capacitor FEC1, the potential V 13 -α(ΔV BGN -ΔV BGP ) of node N1 also decreases. In this operation example, between time T43 and time T44, the potential of node N1 shall be V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ).

[0127] Between time T44 and time T45, the potential V IN4 provided by wiring VIL changes to V IN1 . That is, the potential provided by wiring VIL between time T44 and time T45 shall be equal to the potential provided by wiring VIL at a time before time T43.

[0128] At this time, since the potential V IN1 from wiring VIL is applied to the first terminal of transistor M1, the gate-source voltage of transistor M1 is V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ )-V IN1 . Note that V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ) is a potential lower than V 13 , and V 13 is a potential lower than V IN1 . Also, since V 13 -V IN1 is lower than the threshold voltage of transistor M1, V 13 -α(ΔV BGN -ΔVBGP +ΔV BGQ ) - V IN1 It also becomes lower than the threshold voltage of the transistor M1. As a result, between time T44 and time T45, the transistor M1 is turned off.

[0129] By the above operation, a voltage V higher than the voltage V is written to the node NBG of the circuit HC. BG2 higher voltage V BG5 can be written. Also, since the transistor M1 is in the off state, the negative potential V of the node NBG can be held for a long time. As a result, a negative potential V can be applied to the back gate of the transistor ME for a long time. BG5 to the back gate of the transistor ME for a long time. BG5 can be applied.

[0130] By the operations of the timing charts of FIGS. 3A and 3B, the voltage V written to the node NBG of the circuit HC can be rewritten to another potential. BG2 can be rewritten to another potential.

[0131] <Configuration Example 2> Next, a modified example of the circuit HC in FIG. 1 according to a semiconductor device of an aspect of the present invention will be described.

[0132] In FIG. 1, the connection configuration of the back gate of the transistor M2 is not shown, but the connection destination of the back gate of the transistor M2 can be determined at the design stage.

[0133] For example, in the case of the transistor M2, if it is desired to increase the on-current, the gate and the back gate of the transistor M2 may be electrically connected. Specifically, as shown in the circuit HC of FIG. 4A, the back gate of the transistor M2 may be electrically connected to the gate of the transistor M2.

[0134] Also, for example, in transistor M2, in order to vary the threshold voltage of the transistor or to reduce the off-current of transistor M2, a wiring electrically connected to an external circuit or the like may be provided, and a fixed potential or a variable potential may be applied to the back gate of the transistor by the external circuit or the like. Specifically, for example, as shown in the circuit HC of FIG. 4B, the back gate of transistor M2 may be electrically connected to wiring VBL. In the configuration of FIG. 4B, by applying a low-level potential, a ground potential, a negative potential, or the like to wiring VBL, the threshold voltage of transistor M2 can be increased, so that the off-current of transistor M2 can be reduced. On the other hand, when it is desired to increase the on-current of transistor M2, a high-level potential, a positive potential, or the like may be applied to wiring VBL to lower the threshold voltage of transistor M2.

[0135] Also, in the above example, the connection destination of the back gate of transistor M2 was described, but transistor M2 may be configured not to have a back gate.

[0136] Note that in FIGS. 4A and 4B, a modified example of the connection destination of the back gate of transistor M2 in FIG. 1 was described, but the connection destination of the back gate of each transistor described in other parts of this specification, such as other transistors shown in other drawings, can also be determined at the design stage in the same manner. Also, the presence or absence of the back gate of transistors described in other parts of this specification, such as other transistors shown in other drawings, can be determined at the design stage in the same manner.

[0137] For example, a modified example of the connection destination of the back gate of transistor M1 in the circuit HC of FIG. 1 will be described. As an example, as a semiconductor device according to an aspect of the present invention, as shown in FIG. 5A, in the circuit HC of FIG. 1, the back gate of transistor M1 may be connected to the gate of transistor M1 without being electrically connected to the second terminal of transistor M1, the first terminal of transistor M2, and the back gate of transistor ME.

[0138] As shown in FIG. 5A, by electrically connecting the gate and the back gate of the transistor M1, the on-current of the transistor M1 can be increased.

[0139] Also, as an example, as a semiconductor device according to an aspect of the present invention, as shown in FIG. 5B, in the circuit HC of FIG. 1, the gate and the back gate of the transistor M1 may be interchanged.

[0140] <Configuration Example 3> Next, a semiconductor device according to an aspect of the present invention, in which the circuit HC is different from the circuit configurations of FIGS. 1, 4A, 4B, 5A, and 5B, will be described.

[0141] The circuit HC shown in FIG. 6 is a modified example of the circuit HC of FIG. 1 and is different from the circuit HC of FIG. 1 in that it has a capacitor C2. In the circuit HC of FIG. 6, the first terminal of the capacitor C2 is electrically connected to the second terminal of the transistor M1, the back gate of the transistor M1, the first terminal of the transistor M2, and the back gate of the transistor ME. Also, the second terminal of the capacitor C2 is electrically connected to the second terminal of the capacitor FEC1 and the gate of the transistor M1. That is, the circuit HC of FIG. 6 has a configuration in which a capacitor C2 is provided between the node N1 and the node NBG.

[0142] By providing the capacitor C2 between the node N1 and the node NBG, the voltage between the gate and the second terminal of the transistor M1 can be held. Thereby, for example, between the time T13 and the time T14 of the timing chart of FIG. 2A, when the potential of the node N2 changes from V 21 to V 22 the voltage change at the node N1 can be made smaller than the voltage change V 21 -V 22 of the node N2. Therefore, by providing the capacitor C2 between the node N1 and the node NBG, for example, in the operation between the time T13 and the time T14 of the timing chart of FIG. 2A, the dielectric included in the ferroelectric capacitor FEC1 may be easily polarized.

[0143] <Constitution Example 4> Next, a semiconductor device according to an aspect of the present invention, which has a circuit configuration different from that of the circuit HC in FIGS. 1, 4A to 6, will be described.

[0144] The circuit HC shown in FIG. 7 is a modified example of the circuit HC in FIG. 1, and has a transistor M2B, a capacitor C1B, and a ferroelectric capacitor FEC1B. The back gate of the transistor M1 is electrically connected to the first terminal of the capacitor FEC1B, rather than the second terminal of the transistor M1, the first terminal of the transistor M2, and the back gate of the transistor ME. This is different from the circuit HC in FIG. 1.

[0145] As the transistor M2B, for example, a transistor applicable to the transistor M2 can be used. As the ferroelectric capacitor FEC1B, for example, a ferroelectric capacitor applicable to the ferroelectric capacitor FEC1 can be used. As the capacitor C1B, for example, a capacitor applicable to the capacitor C1 can be used.

[0146] The first terminal of the transistor M2B is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M2, and the back gate of the transistor ME. The second terminal of the transistor M2B is electrically connected to the first terminal of the capacitor C1B and the second terminal of the ferroelectric capacitor FEC1B. The gate of the transistor M2B is electrically connected to the wiring VGLB. The second terminal of the capacitor C1B is electrically connected to the wiring VCLB.

[0147] Also, in FIG. 7, the electrical connection point between the back gate of transistor M1 and the first terminal of capacitor FEC1B is referred to as node N1B. Also, the electrical connection point between the second terminal of capacitor FEC1B, the first terminal of capacitor C1B, and the second terminal of transistor M2B is referred to as node N2B. Also, the electrical connection point between the second terminal of transistor M1, the first terminal of transistor M2, and the first terminal of transistor M2B is referred to as node NBG. That is, the potential applied to the back gate of transistor ME can be the potential of node NBG.

[0148] Wiring VCLB functions as a wiring for applying a voltage for polarizing a ferroelectric material that may be included in capacitor FEC1B. For example, when the direction of the electric field generated in the material due to the polarization of the material is from the first terminal to the second terminal of capacitor FEC1B, the voltage may be a positive potential or the like. Also, for example, when the direction of the electric field generated in the material due to the polarization of the material is from the second terminal to the first terminal of capacitor FEC1B, the voltage may be a negative potential or the like. Also, wiring VCLB may supply a voltage that does not polarize the ferroelectric material that may be included in capacitor FEC1B.

[0149] Wiring VGLB functions as a wiring for supplying a signal (voltage) for controlling the switching between the on state and the off state of transistor M2B. For example, by setting the voltage applied by wiring VGLB to a high-level potential, transistor M2B can be turned on, and by setting the voltage applied by wiring VGLB to a low-level potential, transistor M2 can be turned off.

[0150] The circuit HC in FIG. 1 is configured to hold the potential of the gate of transistor M1 with capacitor FEC1, while the circuit HC shown in FIG. 7 is configured to hold the potential of the gate of transistor M1 with capacitor FEC1 and also hold the potential of the back gate of transistor M1 with capacitor FEC1B. Since the circuit HC in FIG. 7 is configured to be able to apply a potential to the back gate of transistor M1 as well, in some cases, the off-current of transistor M1 in the circuit HC of FIG. 7 can be made lower than that of transistor M1 in the circuit HC of FIG. 1.

[0151] Note that as a method of writing a potential to the back gate of transistor M1 (writing a potential to capacitor FEC1B), in the timing charts of FIGS. 2A, 2B, 3A, and 3B, by replacing wiring VCL with wiring VCLB, wiring VGL with wiring VGLB, node N1 with node N1B, and node N2 with node N2B, it can be performed in the same manner as the method of writing a potential to the gate of transistor M1 (writing a potential to capacitor FEC1).

[0152] Also, wiring VCL and wiring VCLB may be combined into a single wiring VCL, and wiring VGL and wiring VGLB may be combined into a single wiring VGLB (not shown). By adopting such a configuration, by performing the operation examples of the timing charts of FIGS. 2A, 2B, 3A, and 3B, polarization can be simultaneously caused in the dielectrics included in each of capacitor FEC1 and capacitor FEC1B. Also, the potential of the gate of transistor M1 and the potential of the back gate can be simultaneously held.

[0153] <Configuration Example 5> Next, a semiconductor device according to one aspect of the present invention, which has a circuit configuration different from that of the circuits HC in FIGS. 1, 4A to 7, will be described.

[0154] The circuit HC shown in FIG. 8A is a modified example of the circuit HC in FIG. 1, and has a configuration in which capacitor C1 included in the circuit HC in FIG. 1 is replaced with capacitor FEC2 containing a dielectric that can have ferroelectricity.

[0155] In the circuit HC of FIG. 1, even if the capacitor C1 is replaced with the capacitor FEC2 which is a ferroelectric capacitor, there may be a case where the operation examples of the timing charts shown in FIGS. 2A, 2B, 3(A), and 3(B) can be performed.

[0156] Also, by making the materials constituting each of the capacitors FEC1 and FEC2 equal, the capacitors FEC1 and FEC2 can be formed simultaneously in the manufacturing process of the circuit HC, so there may be a case where the time required for manufacturing the circuit HC can be shortened.

[0157] Also, the circuit HC shown in FIG. 8B is a modified example of the circuit HC of FIG. 1, and has a configuration in which the transistor M1 and the capacitor FEC1 included in the circuit HC of FIG. 1 are replaced with a FeFET (Ferroelectric FET).

[0158] The circuit HC of FIG. 8B has a transistor FEM as the FeFET, and the gate of the transistor FEM is electrically connected to the first terminal of the capacitor C1 and the second terminal of the transistor M2. Also, the electrical connection destinations of the first terminal, the second terminal, and the back gate of the transistor FEM correspond to the connection destinations of the first terminal, the second terminal, and the back gate of the transistor M1 included in the circuit HC of FIG. 1, respectively.

[0159] In the circuit HC of FIG. 1, even if the transistor M1 and the capacitor FEC1 are replaced with the transistor FEM which is a FeFET, the operation examples of the timing charts shown in FIGS. 2A, 2B, 3(A), and 3(B) can be performed.

[0160] As described above, as the semiconductor device according to one aspect of the present invention, by using FIGS. 1 to 8B, the potential input to the transistor ME can be held for a long time. Further, when the potential is a negative potential, the threshold voltage of the transistor ME can be increased. In particular, as the transistor ME, for example, by using a write transistor included in a memory cell or the like, the off-current of the write transistor can be reduced, and the memory cell can hold data for a long time.

[0161] <Configuration Example 6> Next, a semiconductor device according to one aspect of the present invention, in which the circuit HC has a circuit configuration different from that of FIGS. 1, 4A to 8, will be described.

[0162] The circuit HC shown in FIG. 9 has a configuration including a circuit HC1 and a circuit HC2 having the same circuit configuration as the circuit HC in FIG. 1. In the circuit HC1, the first terminal of the transistor M1 is electrically connected to the wiring VIL, the second terminal of the capacitor C1 is electrically connected to the wiring VCL1, and the gate of the transistor M2 is electrically connected to the wiring VGL1. In the circuit HC2, the second terminal of the capacitor C1 is electrically connected to the wiring VCL2, the gate of the transistor M2 is electrically connected to the wiring VGL2, and the second terminal of the transistor M1, the back gate of the transistor M1, and the first terminal of the transistor M2 are electrically connected to the back gate of the transistor ME.

[0163] The circuit HC1 and the circuit HC2 are electrically connected in series. Specifically, the node NBG of the circuit HC1 is electrically connected to the first terminal of the transistor M1 of the circuit HC2.

[0164] In FIG. 9, the wirings VCL1 and VCL2 correspond to the wiring VCL in FIG. 1, and the wirings VGL1 and VGL2 correspond to the wiring VGL in FIG. 1.

[0165] As shown in FIG. 9, by electrically connecting in series circuit HC1 and circuit HC2, which have the same circuit configuration as circuit HC in FIG. 1, the source-drain voltage per transistor of transistor M1 in circuit HC1 and transistor M1 in circuit HC2 can be made lower than the source-drain voltage of transistor M1 in circuit HC of FIG. 1. Therefore, in the circuit HC of FIG. 9, the drain current flowing through each of transistor M1 in circuit HC1 and transistor M1 in circuit HC2 can be reduced. That is, by adopting the configuration of the circuit HC in FIG. 9, the withstand voltage between wiring VIL and transistor ME can be increased compared to the circuit HC in FIG. 1.

[0166] In FIG. 9, a configuration in which two circuit configurations the same as circuit HC in FIG. 1 are connected in series is shown. However, the semiconductor device according to one aspect of the present invention may have a configuration in which three or more circuit configurations the same as circuit HC are connected in series.

[0167] By using circuit HC described in Configuration Examples 1 to 6 above, the negative potential applied to the back gate of transistor ME can be held for a long time.

[0168] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0169] (Embodiment 2) In this embodiment, a memory device to which circuit HC described in Embodiment 1 is applied will be described.

[0170] FIG. 10A shows, as an example, a circuit configuration in which circuit HC in FIG. 1 is applied to a memory device. In FIG. 10A, the memory device has a memory cell array MCA, and the memory cell array MCA has a plurality of memory cells MC. Each of the plurality of memory cells MC has a transistor ME. Note that the transistor ME can be, for example, a write transistor in the memory cell MC (or a write / read transistor depending on the configuration of the memory cell MC).

[0171] Also, in FIG. 10A, the back gate of each transistor ME included in the plurality of memory cells MC is electrically connected to the wiring BGL. Also, the wiring BGL is electrically connected to the second terminal of the transistor M1, the back gate of the transistor M1, and the first terminal of the transistor M2.

[0172] Also, in FIG. 10A, the wiring VCL is electrically connected to the circuit CP. Also, the wiring VIL is electrically connected to the negative voltage generation circuit NGE.

[0173] The circuit CP has a function as a voltage generation circuit. For example, the voltage generated by the circuit CP can be a high level potential, a low level potential, a positive potential, a negative potential, etc. The voltage generated by the circuit CP is input to the second terminal of the capacitor C1 of the circuit HC via the wiring VCL.

[0174] The negative voltage generation circuit NGE has a function of generating a negative voltage. Also, the negative voltage generation circuit NGE generates a negative potential and supplies the negative potential to the first terminal of the transistor M1 of the circuit HC via the wiring VIL.

[0175] One or both of the circuit CP and the negative voltage generation circuit NGE may have, as an example, a charge pump circuit capable of generating a negative potential.

[0176] Note that in FIG. 10A, the memory cell MC electrically connected to the wiring BGL is taken as the memory cell MC located in one row of the memory cell array MCA, but the configuration of the semiconductor device according to an aspect of the present invention is not limited to this. For example, as shown in FIG. 10B, the wiring BGL is extended so as to be divided into a plurality of rows of the memory cell array MCA, and the wiring BGL is electrically connected to the back gate of each transistor ME of the plurality of memory cells MC arranged in a matrix. By adopting the configuration shown in FIG. 10B, it is not necessary to provide the circuit HC for each row, so that the circuit area of the semiconductor device can be reduced.

[0177] Next, a configuration example of the memory cell applicable to the memory cell MC will be described.

[0178] FIG. 11A shows a configuration example of the memory cell MC applicable to the memory cells MC of FIGS. 10A and 10B. The memory cell MC in FIG. 11A is an example of a memory cell called DRAM (Dynamic Random Access Memory), and includes a transistor ME and a capacitor CA. In particular, in this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell may be referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark).

[0179] The first terminal of the transistor ME is electrically connected to the first terminal of the capacitor CA, the second terminal of the transistor ME is electrically connected to the wiring BL, the gate of the transistor M1 is electrically connected to the wiring WL, and the back gate of the transistor ME is electrically connected to the wiring BGL. The second terminal of the capacitor CA is electrically connected to the wiring CL.

[0180] The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CL functions as a wiring for applying a fixed potential to the second terminal of the capacitor CA. As the potential, for example, a high level potential, a low level potential, a ground potential, etc. can be used. The wiring BGL functions as a wiring for applying a fixed potential to the back gate of the transistor ME. In particular, by using the circuit HC shown in FIGS. 10A and 10B, a negative potential can be applied to the back gate of the transistor ME, the threshold voltage of the transistor ME can be increased, and the transistor ME can be operated in a normally-off state.

[0181] In this specification and the like, "normally-on" refers to a state in which a channel exists even without applying a voltage to the gate, and current flows through the transistor. Also, "normally-off" means that when no potential is applied to the gate or a ground potential is applied to the gate, the current per 1 μm channel width flowing through the transistor is 1 × 10 -20 A or less, 1 × 10 at 85 °C -18 A or less, or 1 × 10 at 125 °C -16 A or less.

[0182] Also, when the potential provided by wiring CL is equal to the potential provided by wiring BGL, wiring CL may be a wiring electrically connected to wiring BGL.

[0183] Note that the directions in which the respective wirings of wiring BL and wiring WL extend are not limited to the circuit diagram shown in Fig. 11A. For example, wiring BL may extend in the left-right direction on the drawing, and wiring WL may extend in the up-down direction on the drawing.

[0184] Also, a configuration example of memory cell MC applicable to the memory cells MC in Figs. 10A and 10B, which is different from Fig. 11A, is shown in Fig. 11B. The memory cell MC shown in Fig. 11B is a gain cell type memory cell using an OS transistor for transistor M3. The memory cell MC in Fig. 11B includes transistor ME, transistor M3, and capacitor CB. Also, in this specification and the like, a storage device having such a memory cell may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) (registered trademark).

[0185] Note that as the transistor M3, a transistor including silicon in the channel formation region (hereinafter referred to as an Si transistor) instead of an OS transistor can be used. As the silicon, for example, amorphous silicon (which may be called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used. Further, as the transistor M3, in addition to the OS transistor and the Si transistor, a transistor including Ge or the like in the channel formation region, a transistor including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, SiGe in the channel formation region, a transistor including a carbon nanotube in the channel formation region, a transistor including an organic semiconductor in the channel formation region, etc. can be used.

[0186] The first terminal of the transistor ME is electrically connected to the first terminal of the capacitor CB and the gate of the transistor M3, the second terminal of the transistor ME is electrically connected to the wiring WBL, the gate of the transistor ME is electrically connected to the wiring WWL, and the back gate of the transistor ME is electrically connected to the wiring BGL. The second terminal of the capacitor CB is electrically connected to the wiring RWL. The first terminal of the transistor M3 is electrically connected to the wiring RBL, and the second terminal of the transistor M3 is electrically connected to the wiring SL.

[0187] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, the wiring WWL functions as a write word line, and the wiring RWL functions as a read word line. Also, the wiring SL functions as a wiring for applying a predetermined potential to the second terminal of the transistor M3. As the potential, for example, a low-level potential, a ground potential, etc. can be used. Also, in some cases, the potential may be a high-level potential. When performing a write operation, as an example, after setting the wiring RWL to a high-level potential and the wiring WWL to a high-level potential, data for writing is sent from the wiring WBL, and thus the data can be written to the first terminal of the capacitor CB. Also, thereafter, by setting the wiring WWL to a low-level potential, the data can be held at the first terminal of the capacitor CB. Also, it is preferable to set the wiring RWL to a low-level potential after setting the wiring WWL to a low-level potential. Also, when performing a read operation, as an example, the wiring RBL is precharged to a high-level potential, and then by setting the wiring RWL to a high-level potential, the data held at the first terminal of the capacitor CB can be read. At this time, the potential of the wiring RBL is determined according to the data.

[0188] The descriptions of the above-mentioned wirings are examples, and the functions of the respective wirings can be changed as appropriate. For example, the wiring RWL may be a wiring to which a fixed potential is applied, and the wiring SL may be a wiring that functions as a read word line. At this time, when performing a write operation, as an example, data for writing is sent from the wiring WBL, and thus the data can be written to the first terminal of the capacitor CB. Also, thereafter, by setting the wiring WWL to a low-level potential, the data can be held at the first terminal of the capacitor CB. Also, when performing a read operation, as an example, each of the wiring RBL and the wiring SL is set to a high-level potential, and the wiring RBL is electrically floated. Thereafter, by setting the wiring SL to a low-level potential, the data held at the first terminal of the capacitor CB can be read. At this time, the potential of the wiring RBL is determined according to the data.

[0189] Further, for example, a wiring WBL that functions as a write bit line and a wiring RBL that functions as a read bit line may be combined into one wiring.

[0190] Note that the directions in which the wirings WBL, RBL, WWL, RWL, and SL extend are not limited to the circuit diagram shown in FIG. 11B. For example, at least one of the wirings WBL, RBL, and SL may extend in the left - right direction on the drawing, and the wiring WWL and / or the wiring RWL may extend in the up - down direction on the drawing.

[0191] <Memory device> Next, a memory device capable of including each of the memory cells in FIGS. 11A and 11B will be described.

[0192] FIG. 12 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device. The semiconductor device 200 has a peripheral circuit 280 and a memory cell array MCA. The peripheral circuit 280 has a control logic circuit 261, a row drive circuit 262, a column drive circuit 263, and an output circuit 264.

[0193] In the memory cell array MCA, a plurality of memory cells MC are arranged in a matrix. The row drive circuit 262 has a row decoder 271 and a word line driver circuit 272. The column drive circuit 263 has a column decoder 281, a precharge circuit 282, an amplifier circuit 283, and a write circuit 284.

[0194] Also, in the memory cell array MCA, a wiring 251 extends in the row direction and a wiring 252 extends in the column direction. In FIG. 12, only one wiring 251 and one wiring 252 are shown, but the wiring 251 may extend in the row direction of the memory cell array MCA as a plurality of wirings, and the wiring 252 may extend in the column direction of the memory cell array MCA as a plurality of wirings.

[0195] Also, when the memory cell MC in FIG. 12 is the memory cell MC shown in FIG. 11A, the wiring 251 can be, for example, the wiring WL, and the wiring 252 can be, for example, the wiring BL.

[0196] Also, when the memory cell MC in FIG. 12 is the memory cell MC shown in FIG. 11B, the wiring 251 can be, for example, a collection of wirings including the wiring WWL and the wiring RWL, and the wiring 252 can be, for example, a collection of wirings including the wiring WBL and the wiring RBL.

[0197] In FIGS. 11A and 11B, although the wiring BGL is shown as extending in the row direction, the wiring BGL may be included in the wiring 251 or may be included in the wiring 252. That is, circuits HC, circuit CP, negative voltage generation circuit NGE, etc. that are electrically connected to the wiring BGL as shown in FIGS. 10A and 10B can be provided in either the row drive circuit 262 or the column drive circuit 263 shown in FIG. 12.

[0198] The precharge circuit 282 has a function of precharging, for example, the above-described wiring BL, wiring RBL, etc. Also, the precharge circuit 282 may have the circuits HC, circuit CP, and negative voltage generation circuit NGE shown in FIGS. 10A and 10B. The amplification circuit 283 has a function of amplifying data signals read from, for example, the wiring BL, wiring RBL, etc. The amplified data signal is output to the outside of the semiconductor device 200 as a digital data signal RDATA via the output circuit 264.

[0199] A low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 280, and a high power supply voltage (VIL) for the memory cell array MCA are supplied to the semiconductor device 200.

[0200] In addition, control signals (CE, WE, RE), address signals ADDR, and data signals WDATA are input to the semiconductor device 200 from the outside. The address signal ADDR is input to the row decoder 271 and the column decoder 281, and the WDATA is input to the write circuit 284.

[0201] The control logic circuit 261 processes the input signals (CE, WE, RE) from the outside and generates control signals for the row decoder 271 and the column decoder 281. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 261 are not limited to these, and other control signals may be input as necessary. For example, a control signal for determining defective bits may be input, and the data signal read from the address of a specific memory cell may be specified as a defective bit.

[0202] Note that each of the above circuits or signals can be appropriately selected or discarded as necessary.

[0203] In the above-described memory device, by using the circuits HC of Configuration Examples 1 to 6 described in Embodiment 1, the negative potential applied to the back gate of the transistor ME provided in the memory cell MC can be held for a long time. Also, for this reason, the threshold voltage of the transistor ME can be increased, so that the off-current of the transistor ME can be decreased. Further, since the off-current of the transistor ME is decreased, the number of refresh times of the data held in the memory cell MC can be reduced.

[0204] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0205] (Embodiment 3) In this embodiment, a configuration example of the semiconductor device described in the above embodiment and a configuration example of the transistor applicable to the semiconductor device described in the above embodiment will be described.

[0206] <Configuration Example 1 of Semiconductor Device> FIG. 13 shows, as an example, the semiconductor device described in the above embodiment. The semiconductor device includes a transistor 300, a transistor 500, and a capacitor element 600. FIG. 14A shows a cross-sectional view of the transistor 500 in the channel length direction, FIG. 14B shows a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 14C shows a cross-sectional view of the transistor 300 in the channel width direction.

[0207] The transistor 500 is a transistor (OS transistor) having a metal oxide in the channel formation region. The transistor 500 has characteristics of a small off-current and a low change in the field-effect mobility even at high temperatures. By applying the transistor 500 to a semiconductor device, for example, the transistors M1 and M2 included in the circuit HC, the transistor ME included in the memory cell MC in FIGS. 11A and 11B, the transistor M3 included in the memory cell MC in FIG. 11B, etc., described in the above embodiment, a semiconductor device with a low degradation in operating ability even at high temperatures can be realized. In particular, by utilizing the characteristic of a small off-current and applying the transistor 500 to, for example, the transistor ME, the potential written in the capacitance of the memory cell MC (capacitance CA in FIG. 11A and capacitance CB in FIG. 11B) can be held for a long time.

[0208] The transistor 500 is provided, for example, above the transistor 300, and the capacitor element 600 is provided, for example, above the transistor 300 and the transistor 500. Note that the capacitor element 600 can be the capacitor C1, capacitor C2, capacitor CA, capacitor CB, etc. described in the above embodiment. Depending on the circuit configuration, the capacitor element 600 shown in FIG. 13 may not necessarily be provided.

[0209] The transistor 300 is provided on a substrate 310 and has an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 310, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. Note that the transistor 300 can be applied to, for example, the transistor M3 described in the above embodiment. In FIG. 13, a configuration is shown in which the gate of the transistor 300 is electrically connected to one of the source or drain of the transistor 500. However, depending on the configuration of the semiconductor device according to an aspect of the present invention, one of the source or drain of the transistor 300 can be electrically connected to one of the source or drain of the transistor 500, and one of the source or drain of the transistor 300 can be electrically connected to the gate of the transistor 500. Also, each terminal of the transistor 300 can be configured not to be electrically connected to each terminal of the transistor 500 and each terminal of the capacitor element 600.

[0210] Further, as the substrate 310, it is preferable to use a semiconductor substrate (for example, a single-crystal substrate or a silicon substrate).

[0211] As shown in FIG. 14C, in the transistor 300, the upper surface and the side surface in the channel width direction of the semiconductor region 313 are covered with the conductor 316 via the insulator 315. In this way, by forming the transistor 300 into a Fin type, the effective channel width is increased, so that the on characteristics of the transistor 300 can be improved. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0212] Note that the transistor 300 can be either a p-channel type or an n-channel type.

[0213] In regions where the channel of the semiconductor region 313 is formed, regions in the vicinity thereof, source regions, or drain regions, such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, etc., the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0214] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0215] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0216] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0217] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, the mesa isolation method, or the like.

[0218] Note that the transistor 300 shown in FIG. 13 is an example and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration, driving method, and the like. For example, the transistor 300 may have a planar structure instead of the FIN type shown in FIG. 14C. Further, for example, when the semiconductor device is a unipolar circuit including only OS transistors, as shown in FIG. 15, the configuration of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor. Details of the transistor 500 will be described later. Note that, in this specification and the like, a unipolar circuit refers to a circuit including transistors of only one polarity, either n-channel type transistors or p-channel type transistors.

[0219] Note that in FIG. 15, the transistor 300 is provided on the substrate 310A. In this case, as the substrate 310A, a semiconductor substrate may be used in the same manner as the substrate 310 of the semiconductor device in FIG. 13. Further, as the substrate 310A, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film can be used. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the bonded film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Or, as an example, there is a synthetic resin such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or papers.

[0220] In the transistor 300 shown in FIG. 13, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated and provided in this order from the substrate 310 side.

[0221] As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride may be used.

[0222] In addition, in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0223] The insulator 322 may function as a planarization film that planarizes steps generated by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0224] In addition, for the insulator 324, it is preferable to use a film having a barrier property that prevents hydrogen, impurities, etc. from diffusing from the substrate 310 or the transistor 300 into the region where the transistor 500 is provided.

[0225] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film with a small amount of hydrogen desorption.

[0226] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 324, in TDS analysis, when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of the insulator 324, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm2 The following may be sufficient.

[0227] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0228] Also, a capacitor element 600, or conductors 328 and 330 connected to the transistor 500, etc. are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductors 328 and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0229] As materials for each plug and wiring (conductors 328, 330, etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in layers. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0230] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 13, the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked and provided above the insulator 326 and the conductor 330. Further, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

[0231] Note that, for example, as the insulator 350, it is preferable to use an insulator having a barrier property against impurities such as hydrogen and water, similar to the insulator 324. Further, as the insulator 352 and the insulator 354, it is preferable to use an insulator having a relatively low dielectric constant in order to reduce the parasitic capacitance generated between wirings, similar to the insulator 326. Further, the conductor 356 preferably includes a conductor having a barrier property against impurities such as hydrogen and water. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0232] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0233] Further, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked on the insulator 354 and the conductor 356.

[0234] The insulator 360 is preferably an insulator having a barrier property against impurities such as water and hydrogen, similar to the insulator 324 and the like. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 and the like can be used.

[0235] The insulators 362 and 364 have functions as an interlayer insulating film and a planarization film. Also, the insulators 362 and 364 are preferably insulators having a barrier property against impurities such as water and hydrogen, similar to the insulator 324. For this reason, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.

[0236] Also, openings are formed in regions of the insulators 360, 362, and 364 that overlap with some of the conductors 356, and the conductor 366 is provided so as to fill the openings. Further, the conductor 366 is also formed on the insulator 362. The conductor 366 has, as an example, a function as a plug connected to the transistor 300 or a wiring. Note that the conductor 366 can be provided using the same material as the conductors 328 and 330.

[0237] On the insulator 364 and the conductor 366, the insulators 510, 512, 514, and 516 are sequentially stacked and provided. Any of the insulators 510, 512, 514, and 516 is preferably a material having a barrier property against oxygen and hydrogen.

[0238] For example, for the insulators 510 and 514, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from, for example, the region where the substrate 310 or the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, a material similar to the insulator 324 can be used.

[0239] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as transistor 500, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between transistor 500 and transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0240] Also, as a film having a barrier property against hydrogen, for example, for insulator 510 and insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0241] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxide constituting transistor 500. Therefore, it is suitable for use as a protective film for transistor 500.

[0242] Also, for example, for insulator 512 and insulator 516, the same materials as those of insulator 320 can be used. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as insulator 512 and insulator 516, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0243] In addition, conductors such as conductor 518 and the conductors (for example, conductor 503 shown in FIGS. 14A and 14B) constituting transistor 500 are embedded in insulator 510, insulator 512, insulator 514, and insulator 516. Note that conductor 518 functions as a plug connected to capacitor element 600 or transistor 300, or a wiring. Conductor 518 can be provided using the same material as conductor 328 and conductor 330.

[0244] In particular, conductor 518 in the region in contact with insulator 510 and insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0245] A transistor 500 is provided above insulator 516.

[0246] As shown in FIGS. 14A and 14B, transistor 500 includes insulator 516 on insulator 514, conductor 503 (conductor 503a and conductor 503b) disposed to be embedded in insulator 514 or insulator 516, insulator 522 on insulator 516 and on conductor 503, insulator 524 on insulator 522, oxide 530a on insulator 524, oxide 530b on oxide 530a, conductor 542a on oxide 530b, insulator 571a on conductor 542a, conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping a part of oxide 530b, and insulator 544 disposed on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. Further, insulator 580 is located on insulator 544. Here, as shown in FIGS. 14A and 14B, insulator 552 is in contact with the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side and upper surfaces of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Also, the upper surface of conductor 560 is disposed so as to be substantially flush with the upper part of insulator 554, the upper part of insulator 550, the upper part of insulator 552, and the upper surface of insulator 580. Further, insulator 574 is in contact with at least a part of the upper surface of conductor 560, the upper part of insulator 552, the upper part of insulator 550, the upper part of insulator 554, and the upper surface of insulator 580. Also, insulator 576 is located on at least one of the upper and side surfaces of insulator 574, the side surface of insulator 580, the side surface of insulator 544, the side surface of insulator 522, the side surface of insulator 516, the side surface of insulator 514, and the upper surface. Further, insulator 581 is located on the upper surface of insulator 576.

[0247] Insulators 580 and 544 are provided with openings reaching the oxide 530b. Inside the openings, insulators 552, 550, 554, and conductor 560 are arranged. Also, in the channel length direction of the transistor 500, conductors 560, insulators 552, 550, and 554 are provided between insulator 571a and conductor 542a, and insulator 571b and conductor 542b. Insulator 554 has a region in contact with the side surface of conductor 560 and a region in contact with the bottom surface of conductor 560.

[0248] The oxide 530 preferably has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By having the oxide 530a under the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0249] Note that in the transistor 500, the oxide 530 is shown as a structure in which two layers of the oxide 530a and the oxide 530b are stacked, but the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Or, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0250] Conductor 560 functions as a first gate (also referred to as a top gate) electrode, and conductor 503 functions as a second gate (also referred to as a back gate) electrode. Also, insulators 552, 550, and 554 function as a first gate insulator, and insulators 522 and 524 function as a second gate insulator. Note that the gate insulator may also be referred to as a gate insulating layer or a gate insulating film. Also, conductor 542a functions as one of the source or drain, and conductor 542b functions as the other of the source or drain. Also, at least a part of the region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0251] Here, an enlarged view of the vicinity of the channel formation region in FIG. 14A is shown in FIG. 16A. By supplying oxygen to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 16A, the oxide 530b has a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich the region 530bc and function as a source region or a drain region. At least a part of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is provided in the region between the conductor 542a and the conductor 542b. The region 530ba is provided so as to overlap with the conductor 542a, and the region 530bb is provided so as to overlap with the conductor 542b.

[0252] The region 530bc that functions as a channel formation region has less oxygen deficiency (in this specification, the oxygen deficiency in a metal oxide may be referred to as V O (oxygen vacancy).) or a lower impurity concentration than the regions 530ba and 530bb, and thus is a high-resistance region with a low carrier concentration. Therefore, the region 530bc can be said to be of the i-type (intrinsic) or substantially of the i-type.

[0253] In a transistor using a metal oxide, if impurities or oxygen deficiency (V O ) are present in the region where the channel in the metal oxide is formed, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, hydrogen near the oxygen deficiency (V O ) may form a defect (hereinafter, may be referred to as V O H) in which hydrogen enters the oxygen deficiency (V O ) and generate electrons that become carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen deficiency, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and a current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, impurities, oxygen deficiency, and V OH is preferably reduced as much as possible.

[0254] Also, regions 530ba and 530bb that function as the source region or the drain region have a high oxygen deficiency (V O ), or a high impurity concentration such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and a low-resistance region. That is, regions 530ba and 530bb are n-type regions with a high carrier concentration and low resistance compared to region 530bc.

[0255] Here, the carrier concentration of region 530bc that functions as the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 less, even more preferably less than 1×10 16 cm -3 less, even more preferably less than 1×10 13 cm -3 less, even more preferably less than 1×10 12 cm -3 less, and even more preferably less than 1×10 -9 cm -3 The lower limit of the carrier concentration of region 530bc that functions as the channel formation region is not particularly limited, but can be, for example, 1×10

[0256] Also, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than the carrier concentrations of regions 530ba and 530bb and equal to or higher than the carrier concentration of region 530bc. That is, the said region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in the said junction region may be equal to or lower than the hydrogen concentrations of regions 530ba and 530bb and equal to or higher than the hydrogen concentration of region 530bc. Also, the oxygen deficiency in the said junction region may be equal to or less than the oxygen deficiencies of regions 530ba and 530bb and equal to or more than the oxygen deficiency of region 530bc.

[0257] In addition, in Fig. 16A, an example where regions 530ba, 530bb, and 530bc are formed in oxide 530b is shown, but the present invention is not limited thereto. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0258] Also, in oxide 530, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region are not limited to stepwise changes from region to region, and may also change continuously within each region. That is, the closer the region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, may be.

[0259] For transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for oxide 530 (oxide 530a and oxide 530b) including the channel formation region.

[0260] In addition, as the metal oxide functioning as a semiconductor, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0261] As the oxide 530, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Also, as the oxide 530, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0262] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide 530b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0263] In this way, by disposing the oxide 530a under the oxide 530b, the diffusion of impurities and oxygen from the structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0264] In addition, since the oxide 530a and the oxide 530b have a common element (as the main component) other than oxygen, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Since the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered, the influence on carrier conduction due to interface scattering is small, and a high on-current can be obtained.

[0265] The oxide 530b preferably has crystallinity. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0266] CAAC-OS has a highly crystalline and dense structure and is a metal oxide with few impurities and defects (e.g., oxygen vacancies (V O such as)). In particular, by heat-treating the metal oxide at a temperature (e.g., 400 °C or higher and 600 °C or lower) such that the metal oxide does not polycrystallize after the formation of the metal oxide, CAAC-OS can be made to have a more highly crystalline and dense structure. In this way, by increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0267] On the other hand, since it is difficult to confirm distinct grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0268] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, hydrogen near an oxygen vacancy may form a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H).) and may generate electrons serving as carriers. For this reason, if an oxygen vacancy is included in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, in the region where a channel is formed in the oxide semiconductor, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible. In other words, in the region where a channel is formed in the oxide semiconductor, it is preferable that the carrier concentration is reduced and it is i-type (intrinsic) or substantially i-type.

[0269] On the other hand, by providing an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiency and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, it may cause a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility. Further, if the oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0270] Therefore, in the oxide semiconductor, the region 530bc that functions as the channel formation region preferably has a reduced carrier concentration and is of i-type or substantially i-type, while the regions 530ba and 530bb that function as the source region or the drain region preferably have a high carrier concentration and are of n-type. That is, it is preferable to reduce the oxygen deficiency and V O H in the region 530bc of the oxide semiconductor and not supply an excessive amount of oxygen to the regions 530ba and 530bb.

[0271] Therefore, in the present embodiment, while the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to reduce the oxygen deficiency and V O H in the region 530bc. Here, the microwave treatment refers to a treatment using, for example, a device having a power source for generating high-density plasma using microwaves.

[0272] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be made into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high-frequency waves such as RF can also be irradiated to the region 530bc. Due to the action of plasma, microwaves, etc., the V O H in the region 530bc is broken, hydrogen H is removed from the region 530bc, and the oxygen deficiency V Ocan be replenished with oxygen. That is, in region 530bc, the reaction "V O H → H + V O " occurs, and the hydrogen concentration in region 530bc can be reduced. Therefore, the oxygen deficiency and V O H in region 530bc can be reduced, and the carrier concentration can be decreased.

[0273] Also, when performing microwave treatment in an oxygen-containing atmosphere, the actions of microwaves, high frequencies such as RF, and oxygen plasma are shielded by the conductors 542a and 542b and do not reach regions 530ba and 530bb. Furthermore, the action of oxygen plasma can be reduced by the insulators 571 and 580 provided to cover the oxide 530b and the conductor 542. As a result, during microwave treatment, in regions 530ba and 530bb, the reduction of V O H and the supply of an excessive amount of oxygen do not occur, so a decrease in the carrier concentration can be prevented.

[0274] Also, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this way, oxygen can be efficiently injected into region 530bc. Also, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of region 530bc, the injection of more oxygen than necessary into region 530bc can be suppressed, and the oxidation of the side surface of the conductor 542 can be suppressed. Also, the oxidation of the side surface of the conductor 542 can be suppressed when forming the insulating film that becomes the insulator 550.

[0275] In addition, the oxygen injected into region 530bc exists in various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (also referred to as O radicals, atoms, molecules, or ions having unpaired electrons). Note that the oxygen injected into region 530bc is preferably in any one or more of the above-described forms, and particularly preferably an oxygen radical. Also, since the film quality of insulator 552 and insulator 550 can be improved, the reliability of transistor 500 is improved.

[0276] In this way, oxygen deficiency and V O H can be selectively removed in region 530bc of the oxide semiconductor, and region 530bc can be made into an i-type or substantially i-type. Further, the supply of excessive oxygen to regions 530ba and 530bb that function as a source region or a drain region can be suppressed, and the n-type can be maintained. Thereby, the variation in the electrical characteristics of transistor 500 can be suppressed, and the variation in the electrical characteristics of transistor 500 within the substrate surface can be reduced.

[0277] By adopting the above configuration, a semiconductor device with little variation in transistor characteristics can be provided. Also, a semiconductor device with good reliability can be provided. Also, a semiconductor device having good electrical characteristics can be provided.

[0278] Also, as shown in FIG. 14B, in a cross-sectional view in the channel width direction of transistor 500, a curved surface may be provided between the side surface and the upper surface of oxide 530b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as round).

[0279] The radius of curvature of the above-mentioned curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half of the length of the region without the above-mentioned curved surface. Specifically, the radius of curvature of the above-mentioned curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 552, the insulator 550, the insulator 554, and the conductor 560 on the oxide 530b can be enhanced.

[0280] The oxide 530 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0281] Also, the oxide 530b is preferably an oxide having crystallinity such as CAAC-OS. Oxides having crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, so that the transistor 500 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0282] Here, at the junction of the oxide 530a and the oxide 530b, the lower end of the conduction band changes smoothly. In other words, it can be said that the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is preferable to reduce the density of defect levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0283] Specifically, since the oxide 530a and the oxide 530b have a common element other than oxygen as a main component, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 530b is an In-M-Zn oxide, as the oxide 530a, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In-Zn oxide, an indium oxide, etc. may be used.

[0284] Specifically, as the oxide 530a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Also, as the oxide 530b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof may be used. Note that the vicinity of the composition includes a range of ±30% of the desired atomic ratio. Also, as the element M, it is preferable to use gallium.

[0285] In addition, when forming a film of a metal oxide by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide.

[0286] Also, as shown in FIG. 14A and the like, by providing an insulator 552 formed of aluminum oxide or the like in contact with the upper surface and side surfaces of the oxide 530, indium contained in the oxide 530 may be unevenly distributed at the interface between the oxide 530 and the insulator 552 and in the vicinity thereof. As a result, the vicinity of the surface of the oxide 530 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In-Zn oxide. By increasing the atomic ratio of indium in the vicinity of the surface of the oxide 530, particularly the oxide 530b, in this way, the field-effect mobility of the transistor 500 can be improved.

[0287] By configuring the oxide 530a and the oxide 530b as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 500 can obtain a large on-current and high-frequency characteristics.

[0288] At least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities (difficult for the above impurities to permeate) such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms for at least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (difficult for the above oxygen to permeate).

[0289] In this specification, the barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier property means a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it means a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0290] As the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as the insulators 512, 544, and 576, it is preferable to use silicon nitride or the like having higher hydrogen barrier properties. Further, for example, as the insulators 514, 571, 574, and 581, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 581 to the transistor 500 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 524 or the like to the substrate side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 580 or the like above the transistor 500 through the insulator 574 or the like. In this way, it is preferable to adopt a structure in which the transistor 500 is surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0291] Here, as the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581, it is preferable to use an oxide having an amorphous structure. For example, AlO x (where x is any number greater than 0), or MgO y (where y is any number greater than 0), etc., are preferably used as metal oxides. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen existing around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a transistor 500 and a semiconductor device having good characteristics and high reliability can be fabricated.

[0292] Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 preferably have an amorphous structure, but a region with a polycrystalline structure may be formed in part. Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 may have a multilayer structure in which a layer with an amorphous structure and a layer with a polycrystalline structure are laminated. For example, a laminated structure in which a layer with a polycrystalline structure is formed on a layer with an amorphous structure may also be used.

[0293] The film formation of the insulators 512, 514, 544, 571, 574, 576, and 581 may be performed, for example, using a sputtering method. Since the sputtering method does not need to use a molecule containing hydrogen as a film formation gas, the hydrogen concentration of the insulators 512, 514, 544, 571, 574, 576, and 581 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. may be appropriately used.

[0294] Also, in some cases, it is preferable to lower the resistivity of the insulators 512, 544, and 576. For example, by setting the resistivity of the insulators 512, 544, and 576 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, the insulators 512, 544, and 576 may be able to relax the charge-up of the conductors 503, 542, 560, etc. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0295] Also, the insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 516, 580, and 581, silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. may be appropriately used.

[0296] Further, as an example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarization film, or the like.

[0297] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. Further, a part of the conductor 503 may be embedded in the insulator 514.

[0298] The conductor 503 has a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and the side wall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the upper part of the conductor 503b is substantially the same as the height of the upper part of the conductor 503a and the height of the upper part of the insulator 516.

[0299] Here, for the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0300] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 through the insulator 524 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, as the conductor 503a, the above conductive material may be a single layer or a laminate. For example, the conductor 503a may use titanium nitride.

[0301] In addition, the conductor 503b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 503b.

[0302] The conductor 503 may function as a second gate electrode. In that case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, it is possible to increase the Vth of the transistor 500 and reduce the off-current. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0 V than when no negative potential is applied.

[0303] Also, the electrical resistivity of the conductor 503 is designed in consideration of the potential applied to the above-mentioned conductor 503, and the film thickness of the conductor 503 is set according to the electrical resistivity. Also, the film thickness of the insulator 516 is made substantially the same as that of the conductor 503. Here, it is preferable to reduce the film thicknesses of the conductor 503 and the insulator 516 within the range allowed by the design of the conductor 503. By reducing the film thickness of the insulator 516, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, so that the diffusion of the impurities into the oxide 530 can be reduced.

[0304] Note that the conductor 503 may be provided to be larger than the size of the region that does not overlap with the conductors 542a and 542b of the oxide 530 when viewed from above. In particular, as shown in FIG. 14B, the conductor 503 preferably extends also in a region outside the end portions in the channel width direction of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, it is preferable that the conductor 503 and the conductor 560 overlap with each other via an insulator. By having such a configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 503 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0305] Note that in this specification and the like, an S-channel structure transistor refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Also, the S-channel structure disclosed in this specification and the like is different from a Fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to increase the resistance to the short channel effect, in other words, to make a transistor in which the short channel effect hardly occurs.

[0306] Also, as shown in FIG. 14B, the conductor 503 is extended to function also as a wiring. However, it is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 503. Also, the conductor 503 does not necessarily have to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 503 is shared by a plurality of transistors.

[0307] Note that, in the transistor 500, although the conductor 503 is shown in a configuration where the conductor 503a and the conductor 503b are laminated, the present invention is not limited to this. For example, the conductor 503 may be provided in a single-layer or a laminated structure of three or more layers.

[0308] The insulators 522 and 524 function as gate insulators.

[0309] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Further, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0310] As the insulator 522, an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and suppress the generation of oxygen vacancies in the oxide 530. In addition, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 or the oxide 530.

[0311] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Further, the insulator 522 may be used by laminating silicon oxide, silicon oxynitride or silicon nitride on these insulators.

[0312] Further, the insulator 522 may be used in a single layer or in a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, as the insulator 522, a substance with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. may be used in some cases.

[0313] As the insulator 524 in contact with the oxide 530, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used.

[0314] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 530 to create oxygen vacancies (V OReduction of can be achieved. Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then, in order to supplement the desorbed oxygen, in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Alternatively, after the heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0315] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen. In other words, the reaction of "V O + O → null" can be promoted. Further, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 530 can be prevented from recombining with the oxygen deficiency to form V O H.

[0316] Note that the insulator 522 and the insulator 524 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. Further, the insulator 524 may be formed in an island shape so as to overlap with the oxide 530a. In this case, the insulator 544 is configured to be in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.

[0317] The conductor 542a and the conductor 542b are provided in contact with the upper surface of the oxide 530b. The conductor 542a and the conductor 542b each function as a source electrode or a drain electrode of the transistor 500.

[0318] As the conductor 542 (conductor 542a and conductor 542b), for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Also, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0319] Note that hydrogen contained in the oxide 530b or the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductor 542a and the conductor 542b, hydrogen contained in the oxide 530b or the like easily diffuses into the conductor 542a or the conductor 542b, and the diffused hydrogen may combine with nitrogen possessed by the conductor 542a or the conductor 542b. That is, hydrogen contained in the oxide 530b or the like may be absorbed by the conductor 542a or the conductor 542b.

[0320] Also, it is preferable that a curved surface is not formed between the side surface and the upper surface of the conductor 542. By making the conductor 542 without the formation of the curved surface, the cross-sectional area of the conductor 542 in the cross-section in the channel width direction can be increased. Thereby, the conductivity of the conductor 542 can be increased, and the on-current of the transistor 500 can be increased.

[0321] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. The insulator 571 preferably functions as at least a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 571 preferably has a function of suppressing the diffusion of oxygen more than the insulator 580. As the insulator 571, for example, a nitride containing silicon such as silicon nitride may be used. Further, the insulator 571 preferably has a function of capturing impurities such as hydrogen. In that case, as the insulator 571, an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide, may be used. In particular, using aluminum oxide having an amorphous structure or aluminum oxide with an amorphous structure as the insulator 571 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 500 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0322] The insulator 544 is provided so as to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 544 preferably contains silicon nitride or an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide. Further, for example, as the insulator 544, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.

[0323] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be wrapped with an insulator having barrier properties against oxygen. That is, it is possible to prevent oxygen contained in the insulator 524 and the insulator 580 from diffusing into the conductor 542. Thereby, it is possible to suppress the direct oxidation of the conductor 542 by oxygen contained in the insulator 524 and the insulator 580, an increase in resistivity, and a reduction in on-current.

[0324] The insulator 552 functions as part of the gate insulator. It is preferable to use a barrier insulating film against oxygen for the insulator 552. As the insulator 552, an insulator that can be used for the above-described insulator 574 may be used. For example, as the insulator 552, an insulator containing one or both of aluminum oxide and hafnium oxide may be used. Examples of such an insulator include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In the present embodiment, it is assumed that aluminum oxide is used for the insulator 552. In this case, the insulator 552 is an insulator having at least oxygen and aluminum.

[0325] As shown in FIG. 14B, the insulator 552 is provided in contact with the upper surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the upper surface of the insulator 522. That is, the region where the conductors 560 of the oxide 530a, the oxide 530b, and the insulator 524 overlap is covered with the insulator 552 in the cross section in the channel width direction. Thereby, when heat treatment or the like is performed, the desorption of oxygen by the oxides 530a and 530b can be blocked by the insulator 552 having barrier properties against oxygen. Therefore, the formation of oxygen vacancies (Vo) in the oxides 530a and 530b can be reduced. Thereby, the oxygen vacancies (Vo) and V O H formed in the region 530bc can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be enhanced.

[0326] Conversely, even if an excessive amount of oxygen is contained in the insulator 580 and the insulator 550, etc., it is possible to suppress the excessive supply of the oxygen to the oxide 530a and the oxide 530b. Therefore, via the region 530bc, it is possible to suppress the excessive oxidation of the regions 530ba and 530bb and to prevent a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0327] Also, as shown in FIG. 14A, the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580, respectively. Therefore, it is possible to reduce the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. Thereby, it is possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0328] Also, the insulator 552 needs to be provided in an opening formed in the insulator 580, together with the insulator 554, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 552 is thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and is preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 552 only needs to have a region with the above-described film thickness at least in part. Also, it is preferable that the film thickness of the insulator 552 is thinner than the film thickness of the insulator 550. In this case, the insulator 552 only needs to have a region with a film thickness thinner than that of the insulator 550 at least in part.

[0329] To form the insulator 552 with a reduced film thickness as described above, it is preferable to use the ALD method for film formation. The ALD method includes a Thermal ALD method in which the reaction of a precursor and a reactant is carried out using only thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like. In the PEALD method, film formation at a lower temperature may be possible by utilizing plasma, which is preferable in some cases.

[0330] The ALD method utilizes the self-control property of atoms and can deposit atoms one by one, enabling extremely thin film formation, film formation on a structure with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperature. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of openings formed in the insulator 580 or the like with the above-described thin film thickness.

[0331] Note that some precursors used in the ALD method contain carbon or the like. For this reason, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film formation methods. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0332] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, and the like. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 550 is an insulator having at least oxygen and silicon.

[0333] Similar to the insulator 524, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 550 may have a region with a film thickness as described above at least partially.

[0334] In FIGS. 14A and 14B etc., a configuration in which the insulator 550 is a single layer is shown, but the present invention is not limited thereto, and a laminated structure of two or more layers may be used. For example, as shown in FIG. 16B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0335] As shown in FIG. 16B, when the insulator 550 has a two-layer laminated structure, the lower-layer insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper-layer insulator 550b is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the oxygen contained in the insulator 550a from diffusing into the conductor 560. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. In addition, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be provided using a material that can be used for the above-described insulator 550, and the insulator 550b may preferably use an insulator containing one or both of aluminum oxide and hafnium oxide. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In the present embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b becomes an insulator having at least oxygen and hafnium. Further, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and is preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit value and upper limit value can be combined with each other. In this case, the insulator 550b only needs to have a region with the above-described film thickness in at least a part thereof.

[0336] Note that when silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may use an insulating material that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a laminated structure of the insulator 550a and the insulator 550b, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator. Thus, the breakdown voltage of the insulator 550 can be increased.

[0337] The insulator 554 functions as part of the gate insulator. As the insulator 554, it is preferable to use a barrier insulating film against hydrogen. Thereby, impurities such as hydrogen contained in the conductor 560 can be prevented from diffusing into the insulator 550 and the oxide 530b. As the insulator 554, an insulator that can be used for the above-described insulator 576 may be used. For example, silicon nitride formed by the PEALD method may be used as the insulator 554. In this case, the insulator 554 becomes an insulator having at least nitrogen and silicon.

[0338] Also, the insulator 554 may further have a barrier property against oxygen. Thereby, diffusion of oxygen contained in the insulator 550 into the conductor 560 can be suppressed.

[0339] Also, the insulator 554 needs to be provided in an opening formed in the insulator 580 or the like together with the insulator 552, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 554 is thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and is preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 554 may have a region with a film thickness as described above at least in part. Also, it is preferable that the film thickness of the insulator 554 is thinner than the film thickness of the insulator 550. In this case, the insulator 554 may have a region with a film thickness thinner than that of the insulator 550 at least in part.

[0340] The conductor 560 functions as the first gate electrode of the transistor 500. The conductor 560 preferably has a conductor 560a and a conductor 560b disposed on the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. Also, as shown in FIGS. 14A and 14B, the height position of the upper part of the conductor 560 is substantially the same as the height position of the upper part of the insulator 550. Note that in FIGS. 14A and 14B, the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b, but the conductor 560 can have a single-layer structure or a laminated structure of three or more layers other than the two-layer structure.

[0341] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0342] In addition, since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0343] In addition, since the conductor 560 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, for the conductor 560b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b can have a laminated structure of titanium, titanium nitride, or the above conductive material.

[0344] Also, in the transistor 500, the conductor 560 is self-alignedly formed so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, it is possible to surely arrange the conductor 560 in the region between the conductor 542a and the conductor 542b without alignment.

[0345] Also, as shown in FIG. 14B, in the channel width direction of the transistor 500, when the bottom surface of the insulator 522 is used as a reference, the height of the bottom surface of the region where the conductor 560 and the oxide 530b do not overlap of the conductor 560 is preferably lower than the height of the bottom surface of the oxide 530b. By configuring the conductor 560 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can easily act on the entire channel formation region of the oxide 530b. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 560 in the region where the oxide 530a and the oxide 530b and the conductor 560 do not overlap and the height of the bottom surface of the oxide 530b, when the bottom surface of the insulator 522 is used as a reference, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other.

[0346] The insulator 580 is provided on the insulator 544, and an opening is formed in the region where the insulator 550 and the conductor 560 are provided. Also, the upper surface of the insulator 580 may be planarized.

[0347] The insulator 580 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 580 is preferably provided using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because regions containing oxygen that desorb upon heating can be easily formed.

[0348] Preferably, the impurity concentrations such as water and hydrogen in the insulator 580 are reduced. For example, as the insulator 580, oxides containing silicon such as silicon oxide and silicon oxynitride may be appropriately used.

[0349] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an insulator having an amorphous structure, for example, an insulator such as aluminum oxide may be used. In this case, the insulator 574 becomes an insulator having at least oxygen and aluminum. By providing the insulator 574 having a function of capturing impurities such as hydrogen in contact with the insulator 580 within the region sandwiched between the insulator 512 and the insulator 581, impurities such as hydrogen contained in the insulator 580 and the like can be captured, and the amount of hydrogen in the region can be set to a constant value. In particular, using amorphous aluminum oxide as the insulator 574 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 500 having good characteristics and a highly reliable semiconductor device can be fabricated.

[0350] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 580. The insulator 576 is disposed on the insulator 574. As the insulator 576, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 576. By forming the insulator 576 by a sputtering method, a silicon nitride film with high density can be formed. Further, as the insulator 576, silicon nitride formed by a PEALD method or a CVD method may be laminated on the silicon nitride formed by a sputtering method.

[0351] Also, one of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540a that functions as a plug, and the other of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540b. In this specification etc., the conductor 540a and the conductor 540b are collectively referred to as the conductor 540.

[0352] The conductor 540a is provided, as an example, in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 14A, and further in the insulator 582 and the insulator 586 shown in FIG. 13, and the conductor 540a is provided inside the opening. Also, the conductor 540b is provided, as an example, in a region that overlaps with the conductor 542b. Specifically, in the region that overlaps with the conductor 542b, openings are formed in the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 14A, and further in the insulator 582 and the insulator 586 shown in FIG. 13, and the conductor 540b is provided inside the opening. Note that the insulator 582 and the insulator 586 will be described later.

[0353] Furthermore, as shown in FIG. 14A, an insulator 541a may be provided between the side surface of the opening of the region overlapping with the conductor 542a and the conductor 540a as an insulator having a barrier property against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening of the region overlapping with the conductor 542b and the conductor 540b as an insulator having a barrier property against impurities. In this specification and the like, the insulator 541a and the insulator 541b are collectively referred to as the insulator 541.

[0354] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 540a and the conductor 540b. Also, the conductor 540a and the conductor 540b may have a laminated structure.

[0355] Also, when the conductor 540 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor disposed in the vicinity of the insulator 574, the insulator 576, the insulator 581, the insulator 580, the insulator 544, and the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. Further, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 576 from mixing into the oxide 530 through the conductor 540a and the conductor 540b.

[0356] As the insulators 541a and 541b, a barrier insulating film that can be used for the insulator 544 or the like may be used. For example, as the insulators 541a and 541b, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulators 541a and 541b are provided in contact with the insulator 574, the insulator 576, and the insulator 571, it is possible to suppress impurities such as water and hydrogen contained in the insulator 580 from mixing into the oxide 530 through the conductors 540a and 540b. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 580 from being absorbed by the conductors 540a and 540b.

[0357] When the insulators 541a and 541b are formed in a laminated structure as shown in FIG. 14A, it is preferable to use a combination of a first insulator in contact with the inner wall of the opening of the insulator 580 or the like and a second insulator inside thereof, which are a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0358] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. By adopting such a configuration, oxidation of the conductor 540 can be suppressed, and further, the entry of hydrogen into the conductor 540 can be reduced.

[0359] Note that in the transistor 500, a configuration in which the first insulator and the second conductor of the insulator 541 are laminated is shown, but the present invention is not limited to this. For example, the insulator 541 may be provided in a single-layer or a laminated structure of three or more layers. Further, in the transistor 500, a configuration in which the first conductor and the second conductor of the conductor 540 are laminated is shown, but the present invention is not limited to this. For example, the conductor 540 may be provided in a single-layer or a laminated structure of three or more layers.

[0360] Also, as shown in FIG. 13, conductors 610, 612, etc. that function as wiring may be arranged in contact with the upper part of conductor 540a and the upper part of conductor 540b. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for conductors 610 and 612. Also, the conductor can have a laminated structure. Specifically, for example, the conductor may be a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed to be embedded in an opening provided in an insulator.

[0361] Note that the structure of the transistor included in a semiconductor device of the present invention is not limited to transistor 500 shown in FIGS. 13, 14A, 14B, and 15. The structure of the transistor included in a semiconductor device of the present invention may be changed according to the situation.

[0362] For example, transistor 500 shown in FIGS. 13, 14A, 14B, and 15 may have the configuration shown in FIG. 17. The transistor in FIG. 17 is different from transistor 500 shown in FIGS. 13, 14A, 14B, and 15 in that it has oxides 543a and 543b. In this specification, etc., oxides 543a and 543b are collectively referred to as oxide 543. Also, the configuration of the cross-section in the channel width direction of the transistor in FIG. 17 can be the same as the cross-section of transistor 500 shown in FIG. 14B.

[0363] Oxide 543a is provided between oxide 530b and conductor 542a, and oxide 543b is provided between oxide 530b and conductor 542b. Here, it is preferable that oxide 543a is in contact with the upper surface of oxide 530b and the lower surface of conductor 542a. Also, it is preferable that oxide 543b is in contact with the upper surface of oxide 530b and the lower surface of conductor 542b.

[0364] The oxide 543 preferably has a function of suppressing oxygen permeation. By disposing an oxide 543 having a function of suppressing oxygen permeation between the conductor 542 functioning as a source electrode or a drain electrode and the oxide 530b, the electric resistance between the conductor 542 and the oxide 530b is reduced, which is preferable. With such a configuration, the electrical characteristics, field-effect mobility, and reliability of the transistor 500 may be improved.

[0365] Further, as the oxide 543, a metal oxide containing an element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. Also, the oxide 543 preferably has a higher concentration of the element M than the oxide 530b. Further, gallium oxide may be used as the oxide 543. Further, a metal oxide such as an In-M-Zn oxide may be used as the oxide 543. Specifically, in the metal oxide used for the oxide, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, the film thickness of the oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. Also, the oxide 543 preferably has crystallinity. When the oxide 543 has crystallinity, the release of oxygen in the oxide 530 can be preferably suppressed. For example, if the oxide 543 has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 530 may be suppressed.

[0366] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0367] The insulator 582 is preferably made of a material that is barrier against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 582.

[0368] Also, the insulator 586 can use the same material as the insulator 320. Further, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0369] Subsequently, the capacitor element 600, and the wirings or plugs around it included in the semiconductor device shown in FIGS. 13 and 15 will be described. Note that above the transistor 500 shown in FIGS. 13 and 15, a capacitor element 600, wirings, and / or plugs are provided.

[0370] The capacitor element 600 has, as an example, a conductor 610, a conductor 620, and an insulator 630.

[0371] On one of the conductor 540a or the conductor 540b, the conductor 546, and the insulator 586, the conductor 610 is provided. The conductor 610 functions as one of a pair of electrodes of the capacitor element 600.

[0372] Also, on the other of the conductor 540a or the conductor 540b, and the insulator 586, the conductor 612 is provided. The conductor 612 functions as a plug, wiring, terminal, etc. that electrically connects the transistor 500 and circuit elements, wirings, etc. arranged above.

[0373] Note that the conductor 612 and the conductor 610 may be formed simultaneously.

[0374] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0375] In FIG. 13, the conductor 612 and the conductor 610 are shown in a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property, and a conductor having high adhesiveness to the conductor having a barrier property and the conductor having high conductivity may be formed between the conductor having a barrier property and the conductor having high conductivity.

[0376] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitor element 600.

[0377] As the insulator 630, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, etc. can be used. Further, the insulator 630 can be provided as a laminate or a single layer using the above-described materials.

[0378] Further, for example, the insulator 630 may use a laminated structure of a material having a large dielectric breakdown strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this configuration, the capacitor element 600 can secure a sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric breakdown strength by having an insulator having a large dielectric breakdown strength, thereby suppressing the electrostatic breakdown of the capacitor element 600.

[0379] As for the insulator of a high dielectric constant (high-k) material (material with a high relative dielectric constant), there are, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, a nitrogen oxide having aluminum and hafnium, an oxide having silicon and hafnium, a nitrogen oxide having silicon and hafnium, or a nitride having silicon and hafnium.

[0380] Alternatively, the insulator 630 may use, for example, a single layer or a laminate of an insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). Also, a compound containing hafnium and zirconium may be used for the insulator 630. As the miniaturization and high integration of semiconductor devices progress, problems such as leakage current in transistors and capacitor elements may occur due to the thinning of the gate insulator and the dielectric used in capacitor elements. By using a high-k material for the gate insulator and the insulator that functions as the dielectric used in capacitor elements, it becomes possible to reduce the gate potential during transistor operation and ensure the capacitance of capacitor elements while maintaining the physical film thickness.

[0381] A conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630. The conductor 610 functions as one of a pair of electrodes of the capacitor element 600.

[0382] Note that as the conductor 620, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Also, when forming simultaneously with other structures such as the conductor, Cu (copper), Al (aluminum), etc., which are low resistance metal materials, can be used. Further, for example, as the conductor 620, a material applicable to the conductor 610 can be used. Also, the conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.

[0383] An insulator 640 is provided on the conductor 620 and the insulator 630. As the insulator 640, for example, it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse into the region where the transistor 500 is provided. Therefore, the same material as the insulator 324 can be used.

[0384] An insulator 650 is provided on the insulator 640. The insulator 650 can be provided using the same material as the insulator 320. Also, the insulator 650 may function as a planarization film covering the uneven shape below it. Therefore, as the insulator 650, for example, a material applicable to the insulator 324 can be used.

[0385] Incidentally, although the capacitor element 600 shown in FIGS. 13 and 15 is of a planar type, the shape of the capacitor element is not limited to this. The capacitor element 600 may be, for example, of a cylinder type instead of a planar type.

[0386] Also, a wiring layer may be provided above the capacitor element 600. For example, in FIG. 13, insulators 411, 412, 413, and 414 are sequentially provided above the insulator 650. Also, a configuration is shown in which a conductor 416 that functions as a plug or a wiring is provided in the insulators 411, 412, and 413. Also, as an example, the conductor 416 can be provided in a region that overlaps with a conductor 660 described later.

[0387] In addition, openings are provided in regions of the insulators 630, 640, and 650 that overlap with the conductor 612, and a conductor 660 is provided so as to fill the openings. The conductor 660 functions as a plug and a wiring that is electrically connected to the conductor 416 included in the wiring layer described above.

[0388] For the insulators 411 and 414, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similar to the insulator 324, for example. Therefore, as the insulators 411 and 414, materials applicable to the insulator 324, for example, can be used.

[0389] For the insulators 412 and 413, it is preferable to use an insulator having a relatively low dielectric constant in order to reduce the parasitic capacitance generated between wirings, similar to the insulator 326, for example.

[0390] In addition, the conductor 612 and the conductor 416 can be provided using the same materials as the conductor 328 and the conductor 330, for example.

[0391] <Configuration Example of Transistor and Ferroelectric Capacitor> Next, a configuration will be described in which a dielectric that can have ferroelectricity is provided inside and around the transistor 500 in which a metal oxide is included in the channel formation region.

[0392] FIG. 18A shows an example of the configuration of a transistor in which a dielectric that can have ferroelectricity is provided in the configuration of the transistor 500 shown in FIGS. 13 and 14A.

[0393] The transistor shown in FIG. 18A has a configuration in which an insulator 522 that functions as a second gate insulator is replaced with an insulator 520. As an example, the insulator 520 can use a dielectric that can have ferroelectricity.

[0394] Therefore, a ferroelectric capacitor can be provided between a conductor 503 that functions as a second gate electrode and an oxide 530 in the transistor of FIG. 18A. In other words, the transistor of FIG. 18A can be an FeFET (Ferroelectric FET) provided with a dielectric that can have ferroelectricity in a part of the second gate insulator.

[0395] Note that materials that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (where X is a real number greater than 0), a material obtained by adding an element J1 (here, the element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, a material obtained by adding an element J2 (here, the element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like. Also, as materials that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as PbTiO X , barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. Further, as a material that can have ferroelectricity, for example, it can be a mixture or compound selected from the materials listed above. Or, as a material that can have ferroelectricity, it can be a laminated structure composed of a plurality of materials selected from the materials listed above. By the way, hafnium oxide, zirconium oxide, HfZrO X , and a material obtained by adding an element J1 to hafnium oxide, etc. may change in crystal structure (characteristics) not only depending on film formation conditions but also by various processes, etc. Therefore, in this specification, etc., a material that exhibits ferroelectricity is not only called a ferroelectric, but also a material that can have ferroelectricity or a material that is made to have ferroelectricity.

[0396] Among them, as a material that can have ferroelectricity, hafnium oxide or a material having hafnium oxide and zirconium oxide can have ferroelectricity even when processed into a thin film of several nm, which is preferable. Here, the film thickness of the insulator 520 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less. By using the thinned ferroelectric layer, a ferroelectric capacitor can be combined with the miniaturized transistor 500 to form a semiconductor device.

[0397] Also, in FIG. 18A, the insulator 520 is shown as a single layer, but the insulator 520 may be two or more insulating films including a dielectric that can have ferroelectricity. A specific example of the transistor is shown in FIG. 18B. In FIG. 18B, for example, the insulator 520 has an insulator 520a and an insulator 520b. The insulator 520a is provided on the upper surfaces of the insulator 516 and the conductor 503, respectively, and the insulator 520b is provided on the upper surface of the insulator 520a.

[0398] As the insulator 520a, for example, a dielectric that can have ferroelectricity can be used. As the insulator 520b, for example, silicon oxide or the like can be used. Also, for example, conversely, silicon oxide can be used for the insulator 520a and a dielectric that can have ferroelectricity can be used for the insulator 520b.

[0399] As shown in FIG. 18B, by providing the insulator 520 as two layers, with a dielectric that can have ferroelectricity provided in one layer and silicon oxide provided in the other layer, the current leakage flowing between the conductor 503 functioning as a gate electrode and the oxide 530 can be suppressed.

[0400] FIG. 18C also shows a configuration example of a transistor in which the insulator 520 has three layers. In FIG. 18C, the insulator 520 has, for example, an insulator 520a, an insulator 520b, and an insulator 520c. The insulator 520c is provided on the upper surfaces of the insulator 516 and the conductor 503, the insulator 520a is provided on the upper surface of the insulator 520c, and the insulator 520b is provided on the upper surface of the insulator 520a.

[0401] As the insulator 520a, for example, a dielectric that can have ferroelectricity can be used. As the insulator 520b and the insulator 520c, for example, silicon oxide or the like can be used.

[0402] The configurations of the transistor and the ferroelectric capacitor shown in FIGS. 18A to 18C can be applied to, for example, the transistor M1 and the capacitor FEC1 shown in FIGS. 1A and 1B described in Embodiment 1. Further, any of the transistors in FIGS. 18A to 18C may be applied as a FeFET to the transistor FEM in FIG. 8B.

[0403] FIG. 19 shows an example of a configuration of a transistor in which a dielectric that can have ferroelectricity is provided in the configuration of the transistor 500 such as FIGS. 13 and 14A, which is different from each of the transistors in FIGS. 18A to 18C.

[0404] The transistor shown in FIG. 19 shows an example of a configuration of a transistor in which a dielectric that can have ferroelectricity is provided above the insulator 552, the insulator 550, and the insulator 554 that function as a first gate insulator, the conductor 560 that functions as a first gate electrode, and a partial region of the insulator 580.

[0405] Specifically, an insulator 561 is provided so as to be in contact with the insulator 552, the insulator 550, the insulator 554, the conductor 560, and a partial region of the insulator 580. As an example, the insulator 561 can use a dielectric that can have ferroelectricity and can be applied to the insulator 520 in FIG. 18A.

[0406] Further, a conductor 562 is provided in contact with the upper portion of the insulator 561. As the conductor 562, for example, the same materials as those of the conductor 328 and the conductor 330 can be used.

[0407] Therefore, a ferroelectric capacitor can be provided between the conductor 503 that functions as the first gate electrode and the conductor 562 according to the configuration of the transistor in FIG. 19.

[0408] Note that the insulator 561 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0409] In addition, each configuration of the transistor and the ferroelectric capacitor shown in FIG. 19 can be applied to the transistor M1 and the capacitor FEC1 shown in FIGS. 1A and 1B, etc., described in Embodiment 1, for example.

[0410] FIG. 20A shows an example of the configuration of a transistor in which a dielectric having ferroelectricity is provided in the configuration of the transistor 500 in FIGS. 13 and 14A, etc., which is different from each of the transistors in FIGS. 18A to 18C and FIG. 19.

[0411] In the transistor shown in FIG. 20A, an insulator 602 is provided in an opening provided in the insulators 544, 571b, 580, 574, 576, and 581 in a region overlapping the conductor 542b. Specifically, in the opening, an insulator 541b is provided on the side surface of the opening, a conductor 540b is provided on the insulator 541b and on the conductor 542b which is the bottom of the opening, the insulator 602 is provided in a partial region of the insulator 581 and on the conductor 540b, and a conductor 613 is provided on the insulator 602 so as to fill the remaining opening.

[0412] As another specific configuration example, within the opening, an insulator 541b is provided on the side surface of the opening, a conductor 540b is provided on the insulator 541b, and an insulator 602 is provided on a partial region of the insulator 581, on the conductor 540b, and on a conductor 542b which is the bottom of the opening. An conductor 613 may be provided on the insulator 602 so as to fill the remaining opening.

[0413] As an example, the insulator 602 can be a dielectric having ferroelectricity, which can be applied to the insulator 520 in Fig. 18A.

[0414] The conductor 613 can be provided using, for example, the same materials as the conductor 328 and the conductor 330.

[0415] Therefore, with the configuration of the transistor in Fig. 20A, a ferroelectric capacitor can be provided between the conductor 540b and the conductor 613 within the opening included in the region overlapping the conductor 542b.

[0416] Note that the insulator 602 may have a laminated structure of two or more layers, similar to the insulator 520 shown in Figs. 18B and 18C.

[0417] Also, the configurations of the transistor and the ferroelectric capacitor shown in Fig. 20A can be applied, for example, to the transistor M1 and the capacitor FEC1 shown in Figs. 1A and 1B, etc., described in Embodiment 1.

[0418] Fig. 20B shows an example of the configuration of a transistor in which a dielectric having ferroelectricity is provided in the configuration of the transistor 500 in Figs. 13, 14A, etc., which is different from each of the transistors in Figs. 18A to 18C, 19, and 20A.

[0419] The transistor shown in FIG. 20B has a configuration in which insulators 552, 550, and 554 that function as a first gate insulator are replaced with insulator 553. As an example, insulator 553 can be a dielectric that can have ferroelectricity and can be applied to insulator 520 in FIG. 18A.

[0420] Therefore, a ferroelectric capacitor can be provided between conductor 560 that functions as a first gate electrode and oxide 530 in the transistor of FIG. 20B. In other words, the transistor of FIG. 20B can be an FeFET in which a dielectric that can have ferroelectricity is provided in a part of the first gate insulator.

[0421] Note that insulator 553 may have a stacked structure of two or more layers, similar to insulator 520 shown in FIGS. 18B and 18C.

[0422] In addition, in FIG. 20B, insulators 552, 550, and 554 are replaced with insulator 553. As another configuration example, at least one of insulators 552, 550, and 554 can be replaced with insulator 553, and the remaining insulators and insulator 553 can have a stacked structure.

[0423] In addition, the configurations of the transistor and the ferroelectric capacitor shown in FIG. 20B can be applied to, for example, transistor M1 and capacitor FEC1 shown in FIGS. 1A and 1B described in Embodiment 1. Also, the transistor of FIG. 20B can be used as an FeFET and applied to transistor FEM in FIG. 8B.

[0424] FIG. 21A shows an example of the configuration of transistor 500 and a capacitor provided around transistor 500 and including a dielectric that can have ferroelectricity.

[0425] The transistor shown in FIG. 21A, as an example, has a plurality of openings formed in the regions overlapping with the conductor 542b in the insulators 544, 571b, 580, 574, 576, and 581. Further, inside one opening, a conductor 540c functioning as a plug is provided, and an insulator 541c is provided between the side surface of the opening and the conductor 540c as an insulator having a barrier property against impurities. Further, inside another opening, a conductor 540d functioning as a plug is provided, and an insulator 541d is provided between the side surface of the opening and the conductor 540d as an insulator having a barrier property against impurities. Note that, as the conductor 540c and the conductor 540d, for example, materials applicable to the conductor 540a and the conductor 540b can be used, and as the insulator 541c and the insulator 541d, for example, materials applicable to the insulator 541a and the insulator 541b can be used.

[0426] An insulator 601 is provided so as to contact the upper portions of the conductor 540c and the conductor 540d. As the insulator 601, for example, a dielectric having ferroelectricity applicable to the insulator 520 in FIG. 18A can be used.

[0427] Further, a conductor 611 is provided so as to contact the upper portion of the insulator 601. As the conductor 611, for example, it can be provided using the same materials as the conductor 328 and the conductor 330.

[0428] Therefore, with the configuration shown in FIG. 21A, a ferroelectric capacitor can be provided between the conductor 540c and the conductor 540d functioning as plugs and the conductor 611.

[0429] Note that the insulator 601 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0430] In addition, in FIG. 21A, the number of plugs in contact with the insulator 601 is two (the conductor 540c and the conductor 540d), but the number of the plugs may be one or three or more. In other words, in FIG. 21A, an example in which two openings each having a conductor as a plug are provided in the region overlapping the insulator 601 is illustrated, but the number of openings provided in the region overlapping the insulator 601 may be one or three or more.

[0431] In addition, the configurations of the transistor and the ferroelectric capacitor shown in FIG. 21A can be applied to the transistor M2 and the capacitor FEC1 shown in FIGS. 1A and 1B, for example, described in Embodiment 1.

[0432] FIG. 21B shows an example of the configuration of the transistor 500 and the capacitor in which a capacitor including a dielectric that may have ferroelectricity is provided around the transistor 500, which is different from FIG. 21A.

[0433] In the transistor shown in FIG. 21B, an insulator 631 is provided on the conductor 610 located on the conductor 540b that functions as a plug and on the upper surface of a partial region of the insulator 581. As an example, the insulator 631 can use a dielectric that may have ferroelectricity and can be applied to the insulator 520 in FIG. 18A.

[0434] In addition, a conductor 620 is provided on the upper surface of the insulator 631, and an insulator 640 and an insulator 650 are sequentially provided on the upper surfaces of the insulator 581, the conductor 612, the conductor 620, and a partial region of the insulator 631.

[0435] Therefore, a ferroelectric capacitor can be provided between the conductor 610 and the conductor 620 according to the configuration shown in FIG. 21B.

[0436] Note that the insulator 631 may have a stacked structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0437] The configurations of the transistor and the ferroelectric capacitor shown in FIG. 21B can be applied to, for example, the transistor M2 and the capacitor FEC1 shown in FIGS. 1A and 1B described in Embodiment 1.

[0438] FIG. 22 shows an example of the configuration of the transistor 500 and the capacitor provided with a dielectric that may have ferroelectricity around the transistor 500, which is different from FIGS. 21A and 25B.

[0439] In FIG. 22, a plurality of openings are formed in the insulator 516, a conductor 503 is embedded in one opening, and a conductor 503A is embedded in another opening.

[0440] As the conductor 503A, for example, a material applicable to the conductor 503 can be used.

[0441] Also, an insulator 517 and a conductor 519 are provided in this order on the upper part of the conductor 503A. Further, the insulator 522 described in the transistor 500 of FIG. 14A covers the insulator 517 and the conductor 519. Further, the insulator 544 described in the transistor 500 of FIG. 14A covers the insulator 522.

[0442] As the insulator 517, as an example, a dielectric that may have ferroelectricity and is applicable to the insulator 520 of FIG. 18A can be used.

[0443] As the conductor 519, for example, it can be provided using the same materials as the conductor 328 and the conductor 330.

[0444] Therefore, with the configuration shown in FIG. 22, a ferroelectric capacitor can be provided between the conductor 503A and the conductor 519.

[0445] Note that the insulator 517 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0446] After providing up to the insulator 581, openings are formed in the insulator 522, insulator 544, insulator 580, insulator 574, insulator 576, and insulator 581 in the region overlapping the conductor 503. Also, inside the openings, a conductor 540e that functions as a plug is provided, and an insulator 541e is provided between the side surface of the opening and the conductor 540e as an insulator having a barrier property against impurities. Note that, as the conductor 540e, for example, materials applicable to the conductor 540a and the conductor 540b can be used, and as the insulator 541e, for example, materials applicable to the insulator 541a and the insulator 541b can be used.

[0447] Also, on the upper surface of a part of the region of the insulator 581 and the conductors 540a and 540e that function as plugs, a conductor 611 is provided. As the conductor 611, for example, materials similar to those of the conductor 328 and the conductor 330 can be used for the provision.

[0448] Also, on the upper surface of the conductor 611 and a part of the region of the insulator 581, an insulator 640 and an insulator 650 are provided in this order.

[0449] The configurations of the transistor and the ferroelectric capacitor shown in FIG. 22 can be applied to, for example, the transistor M2 and the capacitor FEC1 shown in FIGS. 1A and 1B described in Embodiment 1.

[0450] <Configuration Example 2 of Semiconductor Device> Next, a configuration example when the above-described semiconductor device is provided with a ferroelectric capacitor will be described.

[0451] FIG. 23 shows an example in which the configuration of the capacitor element 600 located on the upper surfaces of the insulator 582 and the conductor 546 in the semiconductor device shown in FIG. 13 is changed.

[0452] Specifically, as an example, the capacitive element 600 includes a conductor 610, a conductor 620, an insulator 630, and an insulator 631. In particular, as the insulator 631, a dielectric that can have ferroelectricity can be used as described with reference to FIG. 21B.

[0453] In FIG. 23, the conductor 610 and the conductor 612 can be made of the same materials as the conductor 610 and the conductor 612 in FIG. 13. Also, in FIG. 23, the conductor 610 and the conductor 612 can be formed in the same manner as the conductor 610 and the conductor 612 in FIG. 13.

[0454] Also, in FIG. 23, the insulator 630 is provided on the upper surfaces of the conductor 610 and a partial region of the insulator 586. Further, the insulator 631 is provided on the upper surface of the insulator 630, and the conductor 620 is provided on the upper surface of the insulator 631.

[0455] As the insulator 630, for example, a material applicable to the insulator 630 in FIG. 13 can be used.

[0456] Also, in FIG. 23, the insulator 640 is provided on the upper surfaces of a region including the end portion of the insulator 630, a region including the end portion of the insulator 631, the conductor 620, and a partial region of the insulator 586.

[0457] As the insulator 640, for example, a material applicable to the insulator 640 in FIG. 13 can be used.

[0458] As shown in FIG. 23, by applying the configuration of the capacitive element 600, a ferroelectric capacitor can be provided in the semiconductor device shown in FIG. 13.

[0459] Next, a configuration example of a semiconductor device including a ferroelectric capacitor, which is different from FIG. 23, will be described.

[0460] The semiconductor device shown in FIG. 24 is a modified example of the semiconductor device in FIG. 23, and has a structure in which the transistor 500 and the capacitor element 600 are surrounded by the insulators 514, 544, 574, 576, 581, 641, 642, etc.

[0461] Also, in each of the semiconductor devices of FIGS. 13 and 23, after the insulator 574 is sequentially provided from the substrate 310, an opening reaching the insulator 514 is provided. However, in the semiconductor device of FIG. 24, after the insulator 640 is sequentially provided from the substrate 310, an opening reaching the insulator 514 is provided.

[0462] Also, in the semiconductor device of FIG. 24, the insulator 641, the insulator 642, and the insulator 650 are sequentially provided on the upper surfaces of the bottom of the opening and the insulator 640.

[0463] As the insulators 641 and 642, for example, it is preferable that they function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from above the transistor 500 and the capacitor element 600 to the transistor 500 and the capacitor element 600.

[0464] As a method for forming the insulator 641, for example, a sputtering method can be used. For example, silicon nitride formed by a sputtering method can be used as the insulator 641. Since the sputtering method does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration of the insulator 641 can be reduced. In this way, since the hydrogen concentration of the insulator 641 in contact with the conductor 610, the conductor 612, and the insulator 586 is reduced, the diffusion of hydrogen from the insulator 641 to the conductor 610, the conductor 612, and the insulator 586 can be suppressed.

[0465] As the insulator 642, for example, it is preferable to form a film using the ALD method, particularly the PEALD method. For example, silicon nitride formed by the PEALD method can be used as the insulator 642. Thereby, since the insulator 642 can be formed with good coverage, even if pinholes or steps are formed in the insulator 641 due to the unevenness of the base, by covering them with the insulator 642, it is possible to reduce the diffusion of hydrogen to the conductor 610, the conductor 612, and the insulator 586.

[0466] By applying the configuration shown in FIG. 24, it is possible to prevent impurities such as water and hydrogen from diffusing to the transistor 500 and the capacitor element 600 side through the insulator 512, the insulator 514, the insulator 641, the insulator 642, etc. Also, oxygen contained in the insulator 580, etc., can be prevented from diffusing to the outside through the insulator 574, the insulator 641, the insulator 642, etc.

[0467] As a semiconductor device using a transistor having an oxide semiconductor, by applying the present structure described in this embodiment, fluctuations in the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0468] Also, in a semiconductor device using a transistor having an oxide semiconductor, by aiming for a stacked structure, miniaturization, high integration, etc., the area of the circuit constituting the semiconductor device can be reduced. In particular, as a capacitor element included in the semiconductor device, by using a ferroelectric capacitor, the value of the capacitance of the capacitor element can be increased, so that miniaturization of the capacitor element can be achieved. For this reason, the area of the circuit including the capacitor element can be reduced. Also, as described in this embodiment, by stacking the transistor and the capacitor element, the increase in the circuit area of the semiconductor device can be suppressed while increasing the circuit scale.

[0469] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0470] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0471] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0472] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 25A. FIG. 25A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0473] As shown in FIG. 25A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Also, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0474] Note that the structure within the thick frame shown in Fig. 25A is in an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0475] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, Fig. 25B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" (the horizontal axis is 2θ [deg.], and the vertical axis represents the intensity (Intensity) in arbitrary units (a.u.)). Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 25B may be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 25B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 25B is 500 nm.

[0476] As shown in Fig. 25B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in Fig. 25B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity is detected.

[0477] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 25C. FIG. 25C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 25C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0478] As shown in FIG. 25C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0479] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 25A. For example, the oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single-crystalline oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0480] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0481] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. The strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor with c-axis orientation and no obvious orientation in the a-b plane direction.

[0482] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0483] Also, in In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. The In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0484] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0485] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0486] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be lattice arrangements such as pentagons and heptagons. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0487] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carriers being trapped. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0488] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities and the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities, defects (such as oxygen deficiencies), etc. Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0489] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano-crystals. Also, nc-OS does not show regularity in the crystal orientation between different nano-crystals. Therefore, no orientation is seen in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, in out-of-plane XRD measurement using θ / 2θ scan, no peak indicating crystallinity is detected. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nano-crystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nano-crystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0490] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0491] [<Constitution of Oxide Semiconductor>] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0492] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. Hereinafter, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0493] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0494] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is greater than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is greater than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0495] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0496] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0497] For example, in the CAC-OS of the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0498] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0499] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0500] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0501] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0502] It is preferable to use an oxide semiconductor with a low carrier concentration in a transistor. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor with a low carrier concentration may sometimes be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0503] In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because the density of defect levels is low.

[0504] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0505] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0506] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0507] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0508] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less.

[0509] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5 × 10 19 atoms / cm 3 preferably less than 5 × 10 18 atoms / cm 3 more preferably 1 × 10 18 atoms / cm 3 or less, even more preferably 5 × 10 17 atoms / cm 3 or less.

[0510] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 less than.

[0511] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0512] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0513] (Embodiment 5) This embodiment shows an example of a semiconductor wafer on which a memory device or the like described in the above embodiment is formed, and an example of an electronic component in which the memory device is incorporated.

[0514] <Semiconductor Wafer> First, an example of a semiconductor wafer on which a memory device or the like is formed will be described with reference to FIG. 26A.

[0515] The semiconductor wafer 4800 shown in FIG. 26A has a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portions 4802 is a spacing 4803, which is a dicing area.

[0516] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the opposite side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warping of the wafer 4801 and the like can be reduced, and miniaturization as a component can be achieved.

[0517] As the next process, a dicing process is performed. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by the dashed line. Note that the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular in order to facilitate the dicing process.

[0518] By performing the dicing process, a chip 4800a as shown in FIG. 26B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately the same length as the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0519] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 26A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0520] <Electronic Component> FIG. 26C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 26C has a chip 4800a within a mold 4711. Note that the chip 4800a shown in FIG. 26C shows a configuration in which a circuit portion 4802 is laminated. That is, as the circuit portion 4802, the storage device described in the above embodiment can be applied. FIG. 26C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 outside the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0521] FIG. 26D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0522] The electronic component 4730 has a semiconductor device 4710. As the semiconductor device 4710, for example, a memory device, a high bandwidth memory (HBM), etc. described in the above embodiment can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device can be used.

[0523] As the package substrate 4732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used. As the interposer 4731, a silicon interposer, a resin interposer, etc. can be used.

[0524] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0525] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult for a resin interposer.

[0526] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. Therefore, for the interposer on which HBM is implemented, formation of fine and high-density wirings is required. Thus, it is preferable to use a silicon interposer for the interposer on which HBM is implemented.

[0527] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Further, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional implementation) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0528] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0529] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 26D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix form at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix form at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0530] The electronic component 4730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0531] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0532] (Embodiment 6) In this embodiment, a CPU equipped with the storage device of the above embodiment will be described.

[0533] FIG. 27 is a block diagram showing a configuration example of a CPU that partially uses the storage device described in the above embodiment.

[0534] The CPU shown in FIG. 27 has, on the substrate 1190, an ALU 1191 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), an erasable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 27 is only an example showing a simplified configuration, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in FIG. 27 may be regarded as one core, and a configuration including a plurality of such cores operating in parallel, that is, a configuration such as a GPU, may be used. Also, the number of bits that the CPU can handle with its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0535] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0536] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. during the execution of the CPU program, based on their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from or writes to the register 1196 according to the state of the CPU.

[0537] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0538] In the CPU shown in FIG. 27, a memory cell is provided in the register 1196. The register 1196 may have, for example, a storage device shown in the previous embodiment.

[0539] In the CPU shown in FIG. 27, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cell included in the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When holding data in the capacitive element is selected, data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

[0540] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0541] (Embodiment 7) In this embodiment, an example of an electronic device having the storage device described in the above embodiment will be described. FIGS. 28A to 28J and FIGS. 29A to 29E illustrate how an electronic component 4700 having the storage device is included in each electronic device.

[0542] [Mobile phone] The information terminal 5500 shown in FIG. 28A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0543] By applying the storage device described in the above embodiment, the information terminal 5500 can hold temporary files (for example, caches when using a web browser, etc.) generated during the execution of an application.

[0544] [Wearable Terminal] Also, FIG. 28B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 has a housing 5901, a display unit 5902, operation buttons 5903, a faucet 5904, a band 5905, etc.

[0545] Similar to the above-described information terminal 5500, the wearable terminal can hold temporary files generated during the execution of an application by applying the storage device described in the above embodiment.

[0546] [Information Terminal] Also, FIG. 28C shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0547] Similar to the above-described information terminal 5500, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the storage device described in the above embodiment.

[0548] In the above description, smartphones, wearable terminals, and desktop information terminals are illustrated in FIGS. 28A to 28C respectively as examples of electronic devices. However, information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0549] [Electrical Appliance] In addition, FIG. 28D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0550] By applying the storage device described in the above embodiment to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 can be used, for example, as an IoT (Internet of Things). By using the IoT, the electric refrigerator-freezer 5800 can transmit and receive information such as the food stored in the electric refrigerator-freezer 5800 and the expiration date of the food to and from information terminals as described above through the Internet or the like. Also, when transmitting the information, the electric refrigerator-freezer 5800 can hold the information as a temporary file in the storage device.

[0551] In this example, an electric refrigerator-freezer is described as an electrical appliance. Other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual equipment, and the like.

[0552] [Game Machine] In addition, FIG. 28E shows a portable game machine 5200 as an example of a game machine. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0553] Furthermore, FIG. 28F shows an example of a stationary game machine 7500. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 28F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like. Further, the controller 7522 is not limited to the shape shown in FIG. 28F, and the shape of the controller 7522 may be variously changed according to the genre of the game. For example, in a shooting game such as a first-person shooter (FPS), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to be operated by a gesture and / or voice of a game player, instead of using a controller, and instead including a camera, a depth sensor, a microphone, and the like.

[0554] In addition, the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.

[0555] By applying the storage device described in the above embodiment to the portable game machine 5200 and the stationary game machine 7500, a portable game machine 5200 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0556] Furthermore, by applying the storage device described in the above embodiment to the portable game machine 5200 and the stationary game machine 7500, it is possible to hold temporary files and the like necessary for operations occurring during the execution of the game.

[0557] In FIGS. 28E and 28F, a portable game machine and a stationary game machine are illustrated as examples of a game machine, but the electronic device according to one aspect of the present invention is not limited thereto. Examples of the electronic device according to one aspect of the present invention include, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), a pitching machine for batting practice installed in a sports facility, and the like.

[0558] [Mobile body] The storage device described in the above embodiment can be applied to an automobile which is a mobile body and the periphery of the driver's seat of the automobile.

[0559] An automobile 5700 which is an example of a mobile body is illustrated in FIG. 28G.

[0560] Around the driver's seat of the automobile 5700, there is provided an instrument panel which provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. Further, a display device for indicating those information may be provided around the driver's seat.

[0561] In particular, the display device can project an image from an imaging device (not shown) provided in the automobile 5700, thereby compensating for a field of view blocked by a pillar or the like, a blind spot of the driver's seat, and the like, and enhancing safety.

[0562] Since the storage device described in the above embodiment can temporarily hold information, for example, the storage device can be used for holding necessary temporary information in a system for performing an automatic driving system, a road guidance, a danger prediction, etc. of the automobile 5700. Further, the display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold an image of a driving recorder provided in the automobile 5700.

[0563] In the above description, an automobile has been described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and the like.

[0564] [Camera] The storage device described in the above embodiment can be applied to a camera.

[0565] FIG. 28H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0566] By applying the storage device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0567] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0568] FIG. 28I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0569] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the storage device described above, the video camera 6300 can hold temporary files generated during encoding.

[0570] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0571] FIG. 28(J) is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0572] The ICD body 5400 is implanted into the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0573] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia, ventricular fibrillation, etc.), treatment by electric shock is performed.

[0574] In order to appropriately perform pacing and electric shock, the ICD main body 5400 needs to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate acquired by the sensor, etc., the number of times and time of treatment by pacing, etc. in the electronic component 4700.

[0575] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, by having a plurality of batteries in the ICD main body 5400, the safety can be increased. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0576] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured such that physiological signals such as pulse, respiratory rate, heart rate, body temperature, etc. can be confirmed by an external monitoring device.

[0577] [Expansion device for PC] The storage device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0578] FIG. 29A shows an expansion device 6100, which is an example of the expansion device and can be carried around and has a chip capable of storing information and is externally attached to a PC. The expansion device 6100 can store information by the chip by connecting to the PC, for example, via a USB (Universal Serial Bus). Note that FIG. 29A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0579] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving the storage device and the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0580] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0581] FIG. 29B is a schematic diagram of the appearance of an SD card, and FIG. 29C is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a write circuit, a loader, a read circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0582] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0583] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0584] FIG. 29D is a schematic diagram of the appearance of the SSD, and FIG. 29E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a storage device and a circuit for driving the storage device. For example, electronic components 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic components 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. Note that the circuit configurations of each of the electronic components 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a memory that functions as a work memory may also be provided in the controller chip 5156.

[0585] By applying the semiconductor device or the storage device described in Embodiment 1 or Embodiment 2 to the storage device included in the above-described electronic device, a new electronic device can be provided.

[0586] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

Description of Reference Numerals

[0587] HC: Circuit, HC1: Circuit, HC2: Circuit, CP: Circuit, NGE: Negative Voltage Generation Circuit, MCA: Memory Cell Array, MC: Memory Cell, M1: Transistor, M2: Transistor, M2B: Transistor, M3: Transistor, ME: Transistor, FEM: Transistor, C1: Capacitor, C1B: Capacitor, C2: Capacitor, CA: Capacitor, CB: Capacitor, FEC1: Capacitor, FEC1B: Capacitor, FEC2: Capacitor, VIL: Wiring, VCL: Wiring, VCL1: Wiring, VCL2: Wiring, VCLB: Wiring, VGL: Wiring, VGL1: Wiring, VGL2: Wiring, VGLB: Wiring, VBL: Wiring, BGL: Wiring, BL: Wiring, WL: Wiring, WWL: Wiring, RWL: Wiring, WBL: Wiring, RBL: Wiring, SL: Wiring, CL: Wiring, N1: Node, N1B: Node, N2: Node, N2B: Node, NBG: Node, SCL1: Scribe Line, SCL2: Scribe Line, 200: Semiconductor Device, 251: Wiring, 252: Wiring, 261: Control Logic Circuit, 262: Row Driving Circuit, 263: Column Driving Circuit, 264: Output Circuit, 271: Row Decoder, 272: Word Line Driver Circuit, 280: Peripheral Circuit, 281: Column Decoder, 282: Precharge Circuit, 283: Amplification Circuit, 284: Circuit, 300: Transistor, 310: Substrate, 310A: Substrate, 312: Element Isolation Layer, 313: Semiconductor Region, 314a: Low Resistance Region, 314b: Low Resistance Region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 411: Insulator, 412: Insulator, 413: Insulator, 414: Insulator, 416: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 503A: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 519: Conductor, 520: Insulator, 520a: Insulator, 520b: Insulator, 520c: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530ba: Region, 530bb: Region, 530bc: Region, 540a: Conductor, 540b: Conductor, 540c: Conductor, 540d: Conductor,540e: Conductor, 541a: Insulator, 541b: Insulator, 541c: Insulator, 541d: Insulator, 541e: Insulator, 542a: Conductor, 542b: Conductor, 543a: Oxide, 543b: Oxide, 544: Insulator, 546: Conductor, 550: Insulator, 550a: Insulator, 550b: Insulator, 552: Insulator, 553: Insulator, 554: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 561: Insulator, 562: Conductor, 571a: Insulator, 571b: Insulator, 574: Insulator, 576: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitor element, 601: Insulator, 602: Insulator, 610: Conductor, 611: Conductor, 612: Conductor, 613: Conductor, 620: Conductor, 630: Insulator, 631: Insulator, 640: Insulator, 641: Insulator, 642: Insulator, 650: Insulator, 660: Conductor, 1189: ROM Interface, 1190: Substrate, 1191: ALU, 1192: ALU Controller, 1193: Instruction Decoder, 1194: Interrupt Controller, 1195: Timing Controller, 1196: Register, 1197: Register Controller, 1198: Bus Interface, 4700: Electronic Component, 4702: Printed Circuit Board, 4704: Mounting Substrate, 4710: Semiconductor Device, 4714: Wire, 4730: Electronic Component, 4731: Interposer, 4732: Package Substrate, 4733: Electrode, 4735: Semiconductor Device, 4800: Semiconductor Wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit Section, 4803: Spacing, 4803a: Spacing, 5110: SD Card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller Chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory Chip, 5156: Controller Chip, 5200: Portable Game Machine, 5201: Housing, 5202: Display Unit, 5203: Button, 5300: Desktop Information Terminal, 5301: Main Body, 5302: Display, 5303: Keyboard, 5400: ICD Main Body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian Vein, 5406: Superior Vena Cava, 5500: Information Terminal, 5510: Housing5511: Display unit, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Cabinet, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Cabinet, 5902: Display unit, 5903: Operation button, 5904: Faucet, 5905: Band, 6100: Expansion device, 6101: Cabinet, 6102: Cap, 6103: USB connector, 6104: Substrate, 6106: Controller chip, 6240: Digital camera, 6241: Cabinet, 6242: Display unit, 6243: Operation button, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First cabinet, 6302: Second cabinet, 6303: Display unit, 6304: Operation key, 6305: Lens, 6306: Connection part, 7500: Console game machine, 7520: Main body, 7522: Controller

Claims

1. A semiconductor device having a first transistor, a second transistor, a ferroelectric capacitor, and a first capacitor, wherein a first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor, a second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. Semiconductor device.

2. The semiconductor device according to claim 1, wherein the ferroelectric capacitor has a dielectric, and the dielectric has an oxide containing one or both of hafnium and zirconium. Semiconductor device.

3. A semiconductor device having a first transistor, a second transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor, wherein a first gate of the first transistor is electrically connected to a first terminal of the first ferroelectric capacitor, a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor, and a second terminal of the second transistor is electrically connected to a second terminal of the first ferroelectric capacitor and a first terminal of the second ferroelectric capacitor. Semiconductor device.

4. The semiconductor device according to claim 3, wherein each of the first ferroelectric capacitor and the second ferroelectric capacitor has a dielectric, and the dielectric has an oxide containing one or both of hafnium and zirconium. Semiconductor device.

5. The semiconductor device according to any one of claims 1 to 4, having a second capacitor, wherein a first terminal of the second capacitor is electrically connected to a first terminal of the first transistor and a first terminal of the second transistor, and a second terminal of the second capacitor is electrically connected to a first gate of the first transistor. Semiconductor device.

6. The semiconductor device according to any one of claims 1 to 5, wherein a second gate of the second transistor is electrically connected to a first gate of the second transistor. Semiconductor device.

7. The semiconductor device according to any one of claims 1 to 6, having a memory cell including a third transistor, wherein one of a first gate and a second gate of the third transistor is electrically connected to a first terminal of the first transistor. Semiconductor device.

8. An electronic device having any one of the semiconductor devices according to claims 1 to 7 and a housing. Electronic device.

Images