Semiconductor device

Abstract

To provide a semiconductor device with a new configuration.SOLUTION: A semiconductor device has: a silicon substrate having a first circuit; a first element layer having a second circuit; and a second element layer having a third circuit. The first circuit has a first transistor. The second circuit has a second transistor. The third circuit has a memory cell. The memory cell has a third transistor and a capacitor. The first element layer and the second element layer constitute a laminated block so provided as to be laminated in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate. A plurality of laminated blocks are so provided as to be laminated in the direction perpendicular to or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of laminated blocks has a first wire provided in the direction perpendicular to or substantially perpendicular to the surface of the silicon substrate and is electrically connected via the aforementioned wire.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc., are semiconductor devices themselves and may have a semiconductor device.

Background Art

[0003] Metal oxides have attracted attention as semiconductors applicable to transistors. Indium-gallium-zinc oxide, called "IGZO", "Igzo", etc., is a typical multi-component metal oxide. In research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystals nor amorphous, have been found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has been reported to have an extremely small off-current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process of OS transistors can be incorporated into the CMOS process with conventional Si transistors, and OS transistors can be stacked on Si transistors. For example, Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having OS transistors are stacked on a substrate provided with Si transistors.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device or the like having a novel configuration as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration capable of reducing manufacturing costs in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration capable of miniaturizing the device in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration with small fluctuations in the electrical characteristics of transistors and excellent reliability in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems.

[0009] The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all the exemplified problems. Also, problems other than those listed will naturally become apparent from the description of this specification, and such problems can also be the problems of one aspect of the present invention.

Means for Solving the Problems

[0010] One aspect of the present invention has a silicon substrate having a first circuit, a first element layer having a second circuit, and a second element layer having a third circuit. The first circuit has a first transistor, the second circuit has a second transistor, the third circuit has a memory cell, and the memory cell has a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block provided by being stacked in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate. A plurality of stacked blocks are provided by being stacked in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate, and each of the plurality of stacked blocks has a first wiring provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected by the first wiring. It is a semiconductor device.

[0011] In one aspect of the present invention, it is preferable that the semiconductor device has a function of outputting a signal for driving the memory cell and data to be written to the memory cell to the first wiring, and a function of amplifying data read from the memory cell to the first wiring.

[0012] In one aspect of the present invention, it is preferable that the semiconductor device has a function of amplifying the potential of the second wiring electrically connected to the memory cell and transmitting it to the first wiring, and a function of transmitting the potential of the first wiring to the second wiring.

[0013] In one aspect of the present invention, the second transistor and the third transistor each have a semiconductor layer having a metal oxide in a channel formation region. It is a semiconductor device.

[0014] In one aspect of the present invention, it is preferable that the semiconductor device in which the metal oxide contains In, Ga, and Zn.

[0015] In one aspect of the present invention, it is preferable that the layer having the capacitor is provided above the layer having the third transistor. It is a semiconductor device.

[0016] In one aspect of the present invention, a semiconductor device in which a layer having a capacitor is provided in a stacked manner is preferable.

[0017] Other aspects of the present invention are described and illustrated in the embodiments described below and in the drawings.

Advantages of the Invention

[0018] One aspect of the present invention can provide a semiconductor device or the like having a novel configuration. Or one aspect of the present invention can provide a semiconductor device or the like having a novel configuration that can reduce manufacturing costs in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like having a novel configuration that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like having a novel configuration that can miniaturize the device in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like having a novel configuration in which variations in the electrical characteristics of transistors are small and reliability is excellent in a semiconductor device that functions as a memory device using an extremely small off-current.

[0019] The description of multiple advantages does not prevent the existence of other advantages. Also, one aspect of the present invention does not necessarily have all of the advantages exemplified. Also, regarding one aspect of the present invention, other problems, advantages, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

DETAILED DESCRIPTION OF THE INVENTION

[0021] Embodiments of the present invention will be described below. However, one embodiment of the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0022] In this specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or the claims. Also, for example, the component referred to as "first" in one of the embodiments of this specification and the like may be omitted in other embodiments or the claims.

[0023] In the drawings, the same reference numerals may be given to the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously, and repeated explanations may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0025] Also, when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, an identification symbol such as "_1", "_2", "[n]", "[m,n]" may be appended to the reference numeral for description. For example, the second wiring GL is described as wiring GL[2].

[0026] (Embodiment 1) A configuration example of a semiconductor device, which is one aspect of the present invention, will be described with reference to FIGS. 1 to 11.

[0027] A semiconductor device is a device that utilizes semiconductor characteristics and includes a circuit containing semiconductor elements (such as transistors, diodes, photodiodes, etc.) and a device having the same circuit. The semiconductor device described in this embodiment can function as a memory device that utilizes transistors with an extremely small off-current.

[0028] FIG. 1 is a diagram showing a block diagram of the semiconductor device described in this embodiment. The semiconductor device 10 shown in FIG. 1 has a peripheral circuit 20 provided on a silicon substrate and stacked blocks 30_1 to 30_N (N is a natural number) in which a plurality of memory cells constituting a memory cell array are provided. The stacked blocks 30_1 to 30_N may sometimes be collectively referred to as the stacked block 30. Alternatively, the configuration applicable to the stacked blocks 30_1 to 30_N may sometimes be described as the stacked block 30.

[0029] Although the peripheral circuit 20 is described as being provided on a silicon substrate, this embodiment is not limited thereto. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystalline silicon substrate. Not limited to silicon, materials having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. may be used for the substrate.

[0030] The peripheral circuit 20 includes a circuit for outputting signals for driving memory cells, such as a row driver and a column driver. The row driver and the column driver may sometimes simply be referred to as a driving circuit or a driver.

[0031] It is preferable that the row driver and the column driver drive the memory cells at high speed. Therefore, it is preferable that the row driver and the column driver have transistors that operate at high speed. The transistors included in the row driver and the column driver are preferably transistors (Si transistors) having a channel formation region made of silicon and excellent in field-effect mobility.

[0032] A row driver is a circuit having a function of outputting a signal for driving a memory cell to a word line. The word line has a function of transmitting a word signal to the memory cell. The row driver may be referred to as a word line side driving circuit. Note that the row driver includes a decoder circuit for selecting a word line corresponding to a specified address, a buffer circuit, and the like. A column driver is a circuit having a function of outputting a signal for driving a memory cell to a bit line, a function of outputting data to be written to the memory cell, and a function of amplifying data read from the memory cell to the bit line. The bit line BL has a function of transmitting data to the memory cell. The column driver may be referred to as a bit line side driving circuit. Note that the column driver includes a sense amplifier, a precharge circuit, a decoder circuit for selecting a bit line corresponding to a specified address, and the like.

[0033] The data signal applied to the bit line corresponds to the signal written to the memory cell or the signal read from the memory cell. The data signal is described as a binary signal having a high-level or low-level potential corresponding to data 1 or data 0. Note that the data signal may be a multi-value of three or more values. The high-level potential is VDD, the low-level potential is VSS, or the ground potential (GND). As the signal applied to the bit line BL, in addition to the data signal, there is a precharge potential for reading data and the like. The precharge potential can be set to VDD / 2.

[0034] The stacked blocks 30_1 to 30_N each have an element layer 40 and an element layer 50.

[0035] The element layer 50 has a plurality of memory cells having transistors and capacitors.

[0036] The memory cells included in the element layer 50 can be called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) that uses a transistor having an oxide semiconductor in the channel formation region (hereinafter referred to as an OS transistor) as memory. Since it can be composed of one transistor and one capacitor, high density of the memory can be achieved. Also, by using the OS transistor, the data retention period can be extended.

[0037] In the configuration of one aspect of the present invention, by adopting a configuration using a memory cell having an OS transistor, by taking advantage of the fact that the leakage current (hereinafter referred to as the off-current) flowing between the source and the drain during the off state is extremely low, a charge corresponding to a desired voltage can be held in a capacitor located on the other side of the source or the drain. That is, in the memory cell, the data once written can be held for a long time. Therefore, the frequency of data refresh can be reduced and low power consumption can be achieved.

[0038] In addition, in a memory cell using an OS transistor, since data can be rewritten and read by charging or discharging a charge, it is substantially possible to perform the data writing and reading operations without limitation. A memory cell using an OS transistor does not involve a structural change at the atomic level like a magnetic memory or a resistive change memory, etc., and thus has excellent rewrite resistance. Also, a memory cell using an OS transistor does not show instability due to an increase in electron trapping centers even in repeated rewrite operations like a flash memory.

[0039] Also, a memory cell using an OS transistor can be freely arranged on a silicon substrate having a transistor having silicon in the channel formation region (hereinafter referred to as an Si transistor), or on an element layer having an OS transistor, etc., and thus integration can be easily performed. Also, since the OS transistor can be manufactured using the same manufacturing equipment as the Si transistor, it can be manufactured at low cost.

[0040] In addition, an OS transistor can be a four-terminal semiconductor device by including a back gate electrode in addition to the gate electrode, source electrode, and drain electrode. Depending on the voltage applied to the gate electrode or the back gate electrode, it can be configured with an electric circuit network in which the input and output of the signal flowing between the source and the drain can be independently controlled. Therefore, circuit design can be performed with the same concept as that of an LSI. In addition, the OS transistor has better electrical characteristics than Si transistors in a high-temperature environment. Specifically, since the ratio of the on-current to the off-current is large even at high temperatures such as 125°C or higher and 150°C or lower, a good switching operation can be performed. Also, the OS transistor operates well within the range of -40°C or higher and 190°C or lower. In other words, the OS transistor has very good heat resistance. This is also good heat resistance compared to the heat resistance of phase change memory (PCM: Phase Change Memory) (-40°C or higher and 150°C or lower), resistance change memory (ReRAM: Resistance Random Access Memory) (-40°C or higher and 125°C or lower), magnetoresistive random access memory (MRAM: Magnetoresistive Random Access Memory) (-40°C or higher and 105°C or lower), etc.

[0041] The element layer 40 has a circuit having functions of amplifying the potential of the bit line connected to the memory cell and transmitting it to the bit line connected to the peripheral circuit 20, and transmitting the potential of the peripheral circuit 20 to the bit line connected to the memory cell. The bit line connected to the peripheral circuit 20 is illustrated as the wiring GBL. Also, the bit line connected to the element layer 50 having the memory cell is illustrated as the wiring LBL. The wiring GBL may be called a global bit line. The wiring LBL may be called a local bit line. The wiring LBL and the wiring GBL have the function of a bit line for writing or reading data of the memory cell. In the drawing, the wiring LBL and the wiring GBL may be illustrated with thick lines, dotted thick lines, etc. to enhance visibility.

[0042] The schematic diagram shown in Fig. 1 defines the z-axis direction for explaining the arrangement of each component. For ease of understanding, in the specification, the z-axis direction may sometimes be referred to as the direction perpendicular to the surface of the silicon substrate 11.

[0043] As shown in Fig. 1, the stacked block 30, or the element layers 40 and 50 constituting the stacked block 30, are stacked and provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate 11. Note that "substantially perpendicular" means a state where the angle is 85 degrees or more and 95 degrees or less. Also, the wiring LBL and the wiring GBL provided in the stacked block 30 are provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate 11. With this configuration, the number of memory cells arranged per unit area can be increased, so the memory density can be enhanced.

[0044] Fig. 2 is a circuit diagram of the stacked block 30_1 showing a configuration example of the circuit included in the element layer 40 and a configuration example of the memory cell included in the element layer 50. The memory cell 51_1 includes a transistor 52 and a capacitor 53.

[0045] One of the source or drain of the transistor 52 is connected to the wiring LBL. The gate of the transistor 52 is connected to the wiring (also referred to as the word line WL) that supplies the word signal. The transistor 52 is connected to the capacitor 53.

[0046] The transistor 52 is preferably an OS transistor. As described above, the OS transistor has an extremely low off-current. Therefore, the charge corresponding to the data written in the memory cell 51_1 can be held in the capacitor 53 for a long time. That is, in the memory cells 51_1 to 51_N, the data once written can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device according to one aspect of the present invention can be decreased.

[0047] In addition, since the memory cells 51_1 to 51_N using OS transistors can be freely arranged on a silicon substrate and an element layer having OS transistors, etc., integration can be easily performed. Therefore, the number of memory cells arranged per unit area can be increased, and the memory density can be increased.

[0048] The transistor 52 preferably has a back gate electrode. By controlling the potential applied to the back gate electrode, the threshold voltage of the transistor 52 can be controlled. Thereby, for example, the on-current of the transistor 52 can be increased and the off-current can be decreased.

[0049] The element layer 40 shown in FIG. 2 has transistors 41 to 44. The transistors 41 to 44 can each be composed of an OS transistor, and are illustrated as n-channel type transistors.

[0050] The transistor 41 is a transistor for controlling the wiring GBL to a potential corresponding to the potential of the wiring LBL during the period of reading data from the memory cell 51_1. The transistor 42 is a transistor that functions as a switch in which a selection signal MUX is input to the gate, and the on or off between the source and the drain is controlled according to the selection signal MUX. The transistor 43 is a transistor that functions as a switch in which a write control signal WE is input to the gate, and the on or off between the source and the drain is controlled according to the write control signal WE. The transistor 44 is a transistor that functions as a switch in which a read control signal RE is input to the gate, and the on or off between the source and the drain is controlled according to the read control signal RE. Note that the source side of the transistor 44 is supplied with a ground potential GND which is a fixed potential.

[0051] Note that although the element layer 50 illustrated in FIG. 2 is illustrated as a single layer, a configuration in which a plurality of element layers 50 are stacked may be employed. This configuration is illustrated in FIG. 3.

[0052] FIG. 3 is a circuit diagram of a stacked block 30_1 showing a configuration example of memory cells included in a plurality of element layers 50, namely element layers 50_1 to 50_p (p is a natural number of 2 or more). The element layers 50_1 to 50_p have memory cells 51_1 to 51_p (also referred to as memory cells 51) connected to local bit lines LBL extending in the z-axis direction. With such a configuration, a plurality of memory cells can be arranged per unit area, so that the memory density can be increased.

[0053] In FIG. 3, as an example of the element layer 50, a configuration in which a plurality of element layers 50_1 to 50_p are stacked in the z-axis direction and memory cells are connected by local bit lines LBL provided in the z-axis direction is shown, but another configuration may be used. Another configuration example will be described with reference to FIGS. 4A, 4B, 5, and 6.

[0054] In FIG. 4A, as an example, a configuration in which transistors 41 to 44 included in the element layer 40 and four element layers 50_1 to 50_4 are provided in the z-axis direction is illustrated. Each of the element layers 50_1 to 50_4 has a memory cell 51. Each memory cell 51 is connected to the gate of the transistor 41 via a local bit line LBL provided in the z-axis direction. The number of transistors included in the element layer 40 is four, namely transistors 41 to 44. When memory cells are stacked and provided with four layers of element layers as in FIG. 4A, four memory cells can be provided in each layer of the element layer 40. A configuration can be adopted in which 16 memory cells are connected to the gate of the transistor 41 via local bit lines LBL.

[0055] The configuration of FIG. 4A can be represented as a schematic diagram shown in FIG. 4B. FIG. 4B shows the memory cells 51 included in the element layers 50_1 to 50_4, the local bit lines LBL, and the transistor 41 included in the element layer 40.

[0056] In the configurations of FIGS. 4A and 4B, although memory cells can be arranged at high density, the transistors included in the element layer 40 also need to be arranged at high density. When adopting a process with a large number of steps, such as a process of forming a gate electrode self-alignedly, for miniaturizing the structure of the transistors included in the memory cell 51, since the transistors included in the element layer 40 also need to adopt a process with a large number of steps for miniaturization, there is a risk of increasing the manufacturing cost.

[0057] Therefore, it is preferable that the transistors included in the element layer 40 have a transistor shape different from that of the memory cells, that is, a transistor shape capable of reducing the number of steps instead of a transistor shape with a large number of steps for miniaturization. That is, the transistors included in the element layer 40 are not a transistor shape that prioritizes miniaturization, but a transistor shape that reduces the manufacturing cost. For example, by making the channel length and channel width of the transistor, that is, the size of the transistor, larger than that of the transistors included in the memory cell 51, an increase in the manufacturing cost can be suppressed.

[0058] In order to make the transistor size of the element layer 40 larger than that of the transistors included in the memory cell 51 in FIGS. 4A and 4B, it is important to increase the area occupied by the element layer 40. A configuration capable of increasing the area occupied by the element layer 40 will be described with reference to FIGS. 5 and 6.

[0059] FIG. 5 is a schematic diagram similar to FIG. 4B and shows a configuration example capable of increasing the area occupied by the element layer 40. In the schematic diagram shown in FIG. 5, a configuration in which a wiring layer 54 and an element layer 50 are provided on the element layer 40 is illustrated. The wiring layer 54 has wirings 54_1 and 54_2 connected to the memory cell 51 included in the element layer 50. The wiring 54_1 is connected to the gate of the transistor 41_1 included in the element layer 40_1 that constitutes the element layer 40. The wiring 54_2 is connected to the gate of the transistor 41_2 included in the element layer 40_2 that constitutes the element layer 40.

[0060] As shown in FIG. 5, by having the wiring layer 54 between the element layer 40 and the element layer 50, the areas occupied by the element layers 40_1 and 40_2 can be increased with respect to the area occupied by the memory cells 51 provided in the x direction and the y direction. Therefore, the transistors included in the element layer 40 can have a transistor shape that reduces manufacturing cost instead of a transistor shape that prioritizes miniaturization, and thus an increase in manufacturing cost can be suppressed.

[0061] FIG. 6 is a diagram obtained by visualizing the schematic diagram shown in FIG. 5 based on the layout diagram of the memory cells. In FIG. 6, the region surrounded by the thick line corresponds to one memory cell 51. The memory cell 51 includes a transistor 52 provided to overlap the word line WL and a capacitor 53 connected to the transistor 52. In the diagram shown in FIG. 6, similar to FIG. 5, a configuration in which the wiring layer 54 and the element layer 50 are provided on the element layer 40 is illustrated. The wirings 54_1 and 54_2 are connected to the memory cells provided in the y direction through the openings 57_1 and 57_2. The wirings 54_1 and 54_2 are connected to the element layers 40_1 and 40_2 provided in the y direction through the openings 58_1 and 58_2.

[0062] As shown in FIG. 6, by having the wiring layer 54 between the element layer 40 and the element layer 50, the areas occupied by the element layers 40_1 and 40_2 can be increased with respect to the area occupied by the memory cells 51 provided in the x direction and the y direction. Therefore, the transistors included in the element layer 40 can have a transistor shape that reduces manufacturing cost instead of a transistor shape that prioritizes miniaturization, and thus an increase in manufacturing cost can be suppressed.

[0063] Note that although the element layer 50_1 shown in FIG. 2 is illustrated with the transistors and the capacitors being in the same layer, they may be provided in different layers. This configuration is illustrated in FIG. 7B.

[0064] FIG. 7A is a circuit diagram of a stacked block 30_1 showing a configuration example of a memory cell 51_1 having an element layer 50_A as the element layer 50 in which the transistor 52 is provided, and an element layer 50_B as the element layer 50 in which the capacitor 53 is provided. The element layer 50_A has the transistor 52, and the element layer 50_B has the capacitor 53. With this configuration, the manufacturing process can be reduced as compared with the configuration in which transistors are stacked.

[0065] Note that although the element layer 50_1 illustrated in FIG. 2 is illustrated as having a plurality of capacitors provided in the same layer, it may be configured to be provided in different layers. This configuration is illustrated in FIG. 7B.

[0066] FIG. 7B is a circuit diagram of a stacked block 30_1 showing a configuration example of memory cells 51_A and 51_B having an element layer 50_A as the element layer 50 in which the transistor 52 is provided, an element layer 50_B as the element layer 50 in which the capacitor 53_A is provided, and an element layer 50_C as the element layer 50 in which the capacitor 53_B is provided. The memory cell 51_A has a transistor 52_A provided in the element layer 50_A and a capacitor 53_A provided in the element layer 50_B. The memory cell 51_B has a transistor 52_B provided in the element layer 50_A and a capacitor 53_B provided in the element layer 50_C. With this configuration, the manufacturing process can be reduced as compared with the configuration in which transistors are stacked.

[0067] Next, an example of an integrated circuit (referred to as an IC chip) that functions as having the semiconductor device 10 is shown. The semiconductor device 10 can be made into one IC chip by mounting a plurality of dies on a package substrate. FIGS. 8, 9A, and 9B show an example of the configuration.

[0068] The schematic cross-sectional view of the IC chip 100 shown in FIG. 8 has a stacked block in which a silicon substrate 11, and element layers 40 and 50_1 to 50_3 are stacked on a package substrate 101. The package substrate 101 is provided with solder balls 102 for connecting the IC chip 100 to a printed circuit board or the like. The element layers 40 and 50_1 to 50_3 can be stacked by repeating the configuration for creating an OS transistor. Also, each circuit such as the peripheral circuit provided on the silicon substrate and the memory cells included in the element layers 40 and 50_1 to 50_3 can be electrically connected via through electrodes 103 provided penetrating each layer. As the through electrodes 103, TSV (Through Silicon Via) can be used.

[0069] As another example, the schematic cross-sectional view of the IC chip 100A shown in FIG. 9A has a stacked block in which a silicon substrate 11, and element layers 40 and 50_1 to 50_3 are stacked on a package substrate 101. Each circuit such as the peripheral circuit provided on the silicon substrate and the memory cells included in the element layers 40 and 50_1 to 50_3 are bonded using a silicon substrate 105. Also, each layer can be electrically connected via through electrodes 103 provided penetrating each layer and metal bumps 104 provided between the layers.

[0070] As another example, the schematic cross-sectional view of the IC chip 100B shown in FIG. 9B has a stacked block in which a silicon substrate 11, and element layers 40 and 50_1 to 50_3 are stacked on a package substrate 101. Each circuit such as the peripheral circuit provided on the silicon substrate and the memory cells included in the element layers 40 and 50_1 to 50_3 are bonded using a silicon substrate 105. Also, each layer can be electrically connected via through electrodes 103 provided penetrating each layer and metal bumps 104 provided between the layers.

[0071] FIG. 10 is a circuit diagram for explaining a circuit configuration example of the memory cell 51 included in the element layer 50 and a specific circuit configuration example of the peripheral circuit 22 connected to the memory cell, which were described with reference to FIG. 3.

[0072] FIG. 10 shows element layers 50_1 to 50_p. In FIG. 10, memory cell 51_p is shown as a memory cell of the element layer 50_p connected to wiring LBL_A. Memory cell 51_p includes a transistor 52 whose gate is connected to word line WL_A and a capacitor 53. Also in FIG. 10, memory cell 51_c is shown as a memory cell of the element layer 50_p connected to wiring LBL_B. Memory cell 51_c includes a transistor 52B whose gate is connected to word line WL_B and a capacitor 53B.

[0073] FIG. 10 shows an element layer 40 having transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, 44_b. Wirings LBL_A and LBL_B are connected to the gates of transistors 41_a and 41_b.

[0074] Also, transistors 42_a, 42_b, 43_a, 43_b included in the element layer 40 are connected to wirings GBL_A and GBL_B as shown in FIG. 10. Wirings GBL_A and GBL_B are connected to transistors included in the peripheral circuit 22. Further, control signals WE, RE, MUX are applied to the gates of transistors 42_a, 42_b, 43_a, 43_b, 44_a, 44_b included in the element layer 40 as shown in FIG. 10.

[0075] Figure 10 also shows, as circuits included in the peripheral circuit 22, a precharge circuit 22_A, a precharge circuit 22_B, a sense amplifier 22_C, a switch circuit 22_D, a switch circuit 22_E, and a write / read circuit 29 on the silicon substrate side. The transistors constituting the precharge circuit 22_A, the precharge circuit 22_B, and the sense amplifier 22_C are composed of Si transistors. The switches 23_A to 23_D constituting the switch circuit 22_D and the switch circuit 22_E can also be composed of Si transistors. One of the source or drain of the transistors 42_a, 42_b, 43_a, 43_b is connected to the transistors constituting the precharge circuit 22_A, the precharge circuit 22_B, the sense amplifier 22_C, and the switch circuit 22_D.

[0076] The precharge circuit 22_A is composed of n-channel transistors 24_1 to 24_3. The precharge circuit 22_A is a circuit for precharging the wirings LBL_A and LBL_B to an intermediate potential VPC corresponding to the potential VDD / 2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL1.

[0077] The precharge circuit 22_B is composed of n-channel transistors 24_4 to 24_6. The precharge circuit 22_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to the potential VDD / 2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL2.

[0078] Sense amplifier 22_C is composed of p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to wiring VHH or wiring VLL. Wiring VHH or wiring VLL is wiring that has the function of supplying VDD or VSS. Transistors 25_1 to 25_4 are transistors that form an inverter loop. By selecting memory cells 31_N_A and 31_N_B with word lines WL_A and WL_B at a high level, the potentials of pre-charged wirings LBL_A and LBL_B change, and according to this change, the potentials of wirings GBL_A and GBL_B are set to the high power supply potential VDD or the low power supply potential VSS. The potentials of wirings GBL_A and GBL_B can be output externally via switch circuits 22_D and 22_E and via write / read circuit 29. Wirings LBL_A and LBL_B, and wirings GBL_A and GBL_B correspond to a bit line pair. Write / read circuit 25 controls the writing of data signals according to signal EN_data.

[0079] Switch circuit 22_D is a circuit for controlling the conduction state between sense amplifier 22_C and wirings GBL_A and GBL_B. Switch circuit 22_D is switched on or off under the control of switching signal CSEL1. When switches 23_A and 23_B are n-channel transistors, switching signal CSEL1 is on when at a high level and off when at a low level. Switch circuit 22_E is a circuit for controlling the conduction state between write / read circuit 29 and the bit line pair connected to sense amplifier 22_C. Switch circuit 22_D is switched on or off under the control of switching signal CSEL1. Switches 23_C and 23_D may be the same as switches 23_A and 23_B.

[0080] Also, FIG. 11 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. 10. In the timing chart shown in FIG. 11, period T11 corresponds to the period for explaining the write operation, period T12 corresponds to the precharge operation of wiring LBL, period T13 corresponds to the precharge operation of wiring GBL, period T14 corresponds to the charge sharing operation, period T15 corresponds to the read standby operation, and period T16 corresponds to the read operation.

[0081] In period T11, the word line connected to the gate of the transistor included in the memory cell to which the data signal is to be written is set to a high level. At this time, the control signal WE and the signal EN_data are set to a high level, and the data signal is written into the memory cell via the wiring GBL and the bit line BL.

[0082] In period T12, in order to precharge the wiring LBL, with the control signal WE set to a high level, the precharge line PCL1 is set to a high level. The bit line BL is precharged to the precharge potential. In period T12, it is preferable that both the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 22_C are set to VDD / 2 to suppress the power consumption due to the through current.

[0083] In period T13, in order to precharge the wiring GBL, the precharge line PCL2 is set to a high level. The wiring GBL is precharged to the precharge potential. In period T13, by setting both the wiring VHH and the wiring VLL to VDD, the wiring GBL with a large load can be precharged in a short time.

[0084] In period T14, for charge sharing to balance the charges precharged on the bit line BL and the wiring GBL, the control signal WL and the control signal MUX are set to a high level. The bit line BL and the wiring GBL become equipotential. In period T14, it is preferable that both the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 22_C are set to VDD / 2 to suppress the power consumption due to the through current.

[0085] In period T15, the control signal RE is set to the high level. This is a period during which, according to the potential of the bit line BL, current flows through the transistor 41, and the potential of the wiring GBL fluctuates according to the amount of this current. The switching signal CSEL1 is set to the low level so that the fluctuation of the potential of the wiring GBL is not affected by the sense amplifier 22_C. The wiring VHH or the wiring VLL is the same as in period T14.

[0086] In period T16, the switching signal CSEL1 is set to the high level, and the data signal written in the memory cell is read out by amplifying the fluctuation of the potential of the wiring GBL with the bit line pair connected to the sense amplifier 22_C.

[0087] In one embodiment of the semiconductor device of the present invention, as the transistor provided in each element layer, an OS transistor with an extremely low off-current is used. The OS transistor can be provided laminated on a silicon substrate on which an Si transistor is provided. Therefore, it can be manufactured by repeatedly using the same manufacturing process in the vertical direction, and the manufacturing cost can be reduced. Also, in one embodiment of the present invention, the transistors constituting the memory cell are arranged not in the planar direction but in the vertical direction, so that the memory density can be improved and the device can be miniaturized.

[0088] In addition, in one embodiment of the present invention, since the wiring LBL is connected to the gate of the transistor 41, data can be read using a slight potential difference of the wiring LBL. Since circuits such as a sense amplifier using an Si transistor can be miniaturized, the semiconductor device can be miniaturized. Also, it becomes possible to operate even if the capacitance of the capacitor included in the memory cell is reduced.

[0089] In one aspect of the present invention, an OS transistor with an extremely low off-current is used as the transistor provided in each element layer. Therefore, the refresh frequency of the data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be achieved. The OS transistors can be stacked and manufactured by repeatedly using the same manufacturing process in the vertical direction, thereby reducing the manufacturing cost. Also, in one aspect of the present invention, the transistors constituting the memory cell are arranged not in the planar direction but in the vertical direction, thereby improving the memory density and miniaturizing the device. Further, since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high-temperature environment, it can be a semiconductor device that functions as a storage device with less variation in the electrical characteristics of the transistors when stacked and integrated and excellent reliability.

[0090] (Embodiment 2) In this embodiment, a modified example of a circuit applicable to the semiconductor device described in the above Embodiment 1 will be described with reference to FIG. 12.

[0091] In the memory cell included in the element layer 50 described above, the transistor is illustrated as a top-gate structure or a bottom-gate structure transistor without a back-gate electrode, but the structure of the transistor 52 is not limited thereto. For example, as illustrated in FIG. 12, the transistor included in the memory cell 51 may be a transistor 52 having a back-gate electrode connected to the back-gate electrode line BGL. By adopting the configuration of FIG. 12, it is possible to easily control electrical characteristics such as the threshold voltage of the transistor 52 from the outside.

[0092] (Embodiment 3) Hereinafter, an example of a semiconductor device that functions as a storage device according to one aspect of the present invention will be described.

[0093] FIG. 13 is a diagram showing an example of a semiconductor device in which memory units 470 (memory units 470_1 to 470_m: m is a natural number of 2 or more. FIG. 13 shows the case where m = 2.) are stacked on an element layer 411 having a circuit provided on a semiconductor substrate 311. In FIG. 13, a plurality of memory units 470 are stacked on the element layer 411. In the plurality of memory units 470, a transistor layer 413 (transistor layers 413_1 to 413_m) corresponding to each memory unit 470 and a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is a natural number of 2 or more) on each transistor layer 413 are provided as an example. Note that, in each memory unit 470, an example is shown in which the transistor layer 413 is provided on the substrate 450 and the memory device layer 415 is provided on the transistor layer 413, but the present embodiment is not limited to this. A plurality of memory device layers 415 may be provided on the substrate 450, and the transistor layer 413 may be provided on the plurality of memory device layers 415. Alternatively, on the substrate 450, the memory device layers 415 may be provided above and below the transistor layer 413.

[0094] As materials included in the semiconductor substrate 311 and the substrate 450, materials selected from Si, Ge, SiGe, GaAs, GaAlAs, GaN, and InP can be used respectively.

[0095] The element layer 411 has transistors 300 provided on the semiconductor substrate 311 and can function as a circuit (sometimes referred to as a peripheral circuit) of the semiconductor device. Examples of the circuit include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, a control logic circuit, and the like.

[0096] The transistor layer 413 has transistors 200T and can function as a circuit for controlling each memory unit 470. The memory device layer 415 has memory devices 420. The memory device 420 shown in this embodiment has a transistor and a capacitor.

[0097] Note that the value of m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. Also, the value of n is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. Further, the product of m and n is 4 or more and 256 or less, preferably 4 or more and 128 or less, and more preferably 4 or more and 64 or less.

[0098] Also, FIG. 13 shows a cross-sectional view in the channel length direction of the transistor 200T included in the memory unit and the transistor of the memory device 420.

[0099] As shown in FIG. 13, a transistor 300 is provided on a semiconductor substrate 311. On the transistor 300, a transistor layer 413 and a memory device layer 415 of the memory unit 470 are provided. In one memory unit 470, the transistor 200T of the transistor layer 413 and the memory device 420 of the memory device layer 415 are electrically connected by a plurality of conductors 424. The transistor 300 and the transistor 200T of the transistor layer 413 in each memory unit 470 are electrically connected by a conductor 426, a conductor 427, and a conductor 430. Also, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 that is electrically connected to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. The conductor 427 is provided on the uppermost layer of each memory unit 470 and is electrically connected to the conductor 426 and the conductor 430.

[0100] As materials included in the conductor 426, the conductor 427, and the conductor 430, materials respectively selected from Cu, W, Ti, Ta, and Al can be used.

[0101] In addition, in FIG. 13, an example in which the substrate 450 of the memory unit 470 is provided on the transistor 300 side is shown, but the present embodiment is not limited to this. As shown in FIG. 14, the memory unit 470 may be provided such that the memory device layer 415 is provided on the transistor 300 side.

[0102] In FIG. 13, the conductor 426 is provided so as to penetrate the memory device layer 415, and the conductor 430 is provided so as to penetrate the memory device layer 415, the transistor layer 413, and the substrate 450.

[0103] On the other hand, in FIG. 14, the conductor 426 is provided so as to penetrate the substrate 450 and the transistor layer 413, and the conductor 430 is provided so as to penetrate the substrate 450, the transistor layer 413, and the memory device layer 415.

[0104] In order to suppress leakage between the conductor 426 and the conductor 430, it is preferable that insulators are provided on their respective side surfaces.

[0105] Also, although details will be described later, it is preferable to provide insulators that suppress the permeation of impurities such as water or hydrogen and oxygen on the side surfaces of the conductor 424 and the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon oxynitride may be used.

[0106] The memory device 420 can have the same structure as the transistor 200T included in the transistor layer 413, with a capacitor on its side surface.

[0107] Here, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region) in the transistor 200T.

[0108] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Further, as the oxide semiconductor, indium oxide, In-Ga oxide, or In-Zn oxide may be used. Note that by using an oxide semiconductor having a high indium ratio, the on-current or field-effect mobility of the transistor can be increased.

[0109] Since the transistor 200T using an oxide semiconductor in the channel formation region has an extremely small leakage current in the non-conducting state, a semiconductor device with low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for the transistor 200T that constitutes a highly integrated semiconductor device.

[0110] On the other hand, in a transistor using an oxide semiconductor, its electrical characteristics fluctuate due to impurities and oxygen vacancies (also referred to as V O :oxygen vacancy) in the oxide semiconductor, and it is likely to have a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to the gate electrode and a current flows through the transistor).

[0111] Therefore, it is preferable to use an oxide semiconductor with a reduced impurity concentration and defect level density. Note that in this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0112] Therefore, it is preferable that the impurity concentration in the oxide semiconductor is reduced as much as possible. Examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0113] In particular, hydrogen as an impurity contained in the oxide semiconductor may form oxygen vacancies in the oxide semiconductor. Further, a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as VH) may generate electrons serving as carriers. Furthermore, a part of hydrogen may react with oxygen bonded to a metal atom to generate electrons serving as carriers. O (Sometimes referred to as H.) may generate electrons serving as carriers. Furthermore, a part of hydrogen may react with oxygen bonded to a metal atom to generate electrons serving as carriers.

[0114] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.

[0115] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced for the oxide semiconductor used in the transistor 200T.

[0116] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0117] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0118] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that it contains one or more selected from aluminum, gallium, yttrium, and tin. Further, it may contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. For example, a metal oxide having indium, zinc, and gallium (In-Ga-Zn-based oxide), a metal oxide having indium, zinc, and tin (In-Sn-Zn-based oxide), or a metal oxide having indium, zinc, gallium, and tin (In-Ga-Zn-Sn-based oxide) can be preferably used.

[0119] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 15A. FIG. 15A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0120] As shown in FIG. 15A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, "Crystal" includes single crystal and poly crystal.

[0121] Note that the structure within the thick frame shown in Fig. 15A is in an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, this structure can be described as a structure that is energetically unstable "Amorphous" and is completely different from "Crystal".

[0122] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 15B (the vertical axis represents the intensity in arbitrary units (a.u.)). Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 15B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 15B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 15B is 500 nm.

[0123] As shown in Fig. 15B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. Note that, as shown in Fig. 15B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0124] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 15C. Fig. 15C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in Fig. 15C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0125] As shown in Fig. 15C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0126] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from Fig. 15A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0127] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0128] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are such that the c-axis is oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0129] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0130] Also, in an In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and the element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0131] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0132] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0133] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0134] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0135] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0136] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0137] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared with the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared with the nc-OS and the CAAC-OS.

[0138] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0139] [CAC-OS] The CAC-OS is, for example, a constitution of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in a metal oxide, a state in which one or a plurality of metal elements are unevenly distributed and regions having the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0140] Furthermore, the CAC-OS is a constitution in which materials are separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a constitution in which the first region and the second region are mixed.

[0141] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0142] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0143] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0144] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0145] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0146] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0147] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0148] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0149] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0150] In addition, since the oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0151] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap levels may have unstable electrical characteristics.

[0152] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0153] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0154] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0155] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0156] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0157] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, carriers, i.e., electrons, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate carriers, i.e., electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , even more preferably less than 1×10 18 atoms / cm 3 .

[0158] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0159] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0160] (Embodiment 5) In this embodiment, details of a memory cell array including the memory cell 51 in the semiconductor device 10 described in Embodiment 1 and a peripheral circuit 20 having a circuit for driving the memory cell array will be described.

[0161] FIG. 16 is a block diagram showing a configuration example of a semiconductor device functioning as a memory device. The semiconductor device 10s includes a peripheral circuit 20 and a memory cell array 90. The peripheral circuit 20 includes a row decoder 71, a word line driver circuit 72, a column driver 75, an output circuit 73, and a control logic circuit 74.

[0162] Column driver 75 includes a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 has a function of precharging wirings such as wiring LBL and wiring GBL. The amplifier circuit 83 has a function of amplifying a data signal read from wiring GBL. The amplified data signal is output to the outside of the semiconductor device 10s as a digital data signal RDATA via the output circuit 73.

[0163] A low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 20, and a high power supply voltage (VIL) for the memory cell array 90 are supplied to the semiconductor device 10s.

[0164] Also, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the semiconductor device 10s from the outside. The address signal ADDR is input to the row decoder 71 and the column decoder 81, and WDATA is input to the write circuit 84.

[0165] The control logic circuit 74 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder 71 and the column decoder 81. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 74 are not limited to these, and other control signals may be input as necessary. For example, a control signal for determining defective bits may be input, and a data signal read from the address of a specific memory cell may be specified as a defective bit.

[0166] Note that each of the above circuits or signals can be appropriately selected or discarded as necessary.

[0167] Generally, in semiconductor devices such as computers, various storage devices (memories) are used according to the application. Fig. 17 shows various storage devices by layer. The storage device located in the upper layer is required to have a faster access speed, and the storage device located in the lower layer is required to have a larger storage capacity and a higher recording density. In Fig. 17, from the top layer in order, it shows the memory that is mounted as a register in an arithmetic processing device such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0168] The memory that is mounted as a register in an arithmetic processing device such as a CPU is used for temporarily storing calculation results and the like, so the access frequency from the arithmetic processing device is high. Therefore, a faster operating speed is required rather than a storage capacity. Also, the register has a function of holding the setting information of the arithmetic processing device and the like.

[0169] SRAM is used, for example, for caches. A cache has a function of replicating and holding a part of the information held in the main memory. By replicating frequently used data in the cache, the access speed to the data can be increased.

[0170] DRAM is used, for example, for the main memory. The main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0171] 3D NAND memory is used, for example, for storage. Storage has a function of holding data that needs to be stored long-term and various programs used in the arithmetic processing device. Therefore, storage is required to have a larger storage capacity and a higher recording density than the operating speed. The recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0172] A semiconductor device functioning as a memory device according to an aspect of the present invention has a high operating speed and can hold data for a long period of time. The semiconductor device according to an aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 901 including both a layer where a cache is located and a layer where a main memory is located. Further, the semiconductor device according to an aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 902 including both a layer where a main memory is located and a layer where a storage is located.

[0173] (Embodiment 6) This embodiment shows an example of an electronic component and an electronic device in which the semiconductor device and the like shown in the above embodiment are incorporated.

[0174] <Electronic component> First, an example of an electronic component in which the semiconductor device 10 and the like are incorporated will be described with reference to FIGS. 18A and 18B.

[0175] FIG. 18A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 18A has a semiconductor device 10 in which a stacked block 30 is stacked on a silicon substrate 11 within a mold 711. FIG. 18A does not show a part of the electronic component 700 in order to show the inside thereof. The electronic component 700 has lands 712 outside the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 10 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0176] Fig. 18B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 are provided on the interposer 731.

[0177] In the electronic component 730, an example is shown in which the semiconductor device 10 is used as a high bandwidth memory (HBM). Also, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0178] As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

[0179] The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Also, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Also, a through electrode may be provided on the interposer 731 and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0180] It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult in a resin interposer.

[0181] In HBM, it is necessary to connect a large number of wirings to realize a wide memory bandwidth. Therefore, the interposer for mounting HBM is required to form fine and high-density wirings. Thus, it is preferable to use a silicon interposer as the interposer for mounting HBM.

[0182] In addition, in a SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Further, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0183] Also, a heat sink (heat radiation plate) may be provided so as to overlap with the electronic component 730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 10 and the semiconductor device 735 uniform.

[0184] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. In FIG. 18B, an example of forming the electrodes 733 with solder balls is shown. By providing the solder balls in a matrix pattern at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 733 may be formed with conductive pins. By providing the conductive pins in a matrix pattern at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0185] The electronic component 730 can be mounted on another substrate using various mounting methods not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J - leaded package), or QFN (Quad Flat Non - leaded package) can be used.

[0186] <Electronic device> Next, an example of an electronic device including the above - mentioned electronic component will be described with reference to FIG. 19.

[0187] The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, a gyro sensor, etc.), and a moving mechanism. The electronic component 730 has a processor or the like and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by the sensors.

[0188] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. Also, the speaker has a function of emitting audio signals such as voice and warning sounds. The robot 7100 can analyze the audio signals input via the microphone and emit the necessary audio signals from the speaker. In the robot 7100, it is possible to communicate with the user using the microphone and the speaker.

[0189] The camera has a function of imaging the surroundings of the robot 7100. Also, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can use the camera to image the surrounding images and analyze the images to detect the presence or absence of obstacles when moving.

[0190] The flying object 7120 has a propeller, a camera, a battery, etc., and has a function of flying autonomously. The electronic component 730 has a function of controlling these peripheral devices.

[0191] For example, the image data captured by the camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. Also, the remaining battery level can be estimated from the change in the battery's charge capacity by the electronic component 730.

[0192] The cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras arranged on the side surface, a brush, operation buttons, various sensors, etc. Although not shown, the cleaning robot 7140 is equipped with tires, a suction port, etc. The cleaning robot 7140 can move automatically, detect dust, and suck dust from the suction port provided on the lower surface.

[0193] For example, the electronic component 730 can analyze the image captured by the camera and determine the presence or absence of obstacles such as walls, furniture, or steps. Also, when an object that is likely to get caught in the brush, such as wiring, is detected by image analysis, the rotation of the brush can be stopped.

[0194] Automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency, electronic component 730 performs control to optimize the driving state of automobile 7160. For example, the image data captured by the camera is stored in electronic component 700.

[0195] Electronic component 700 and / or electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, PCs (personal computers) 7220, 7230, a game console 7240, a game console 7260, etc.

[0196] For example, electronic component 730 incorporated in TV device 7200 can function as an image engine. For example, electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0197] Smartphone 7210 is an example of a mobile information terminal. Smartphone 7210 has a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by electronic component 730.

[0198] PCs 7220, 7230 are examples of a notebook PC and a desktop PC respectively. A keyboard 7232 and a monitor device 7233 can be connected to PC 7230 wirelessly or by wire. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a desktop game console. A controller 7262 is connected to game console 7260 wirelessly or by wire. Electronic component 700 and / or electronic component 730 can also be incorporated into controller 7262.

[0199] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0200] (Supplementary Note Regarding the Descriptions in this Specification, etc.) Regarding the above embodiments and the description of each configuration in the embodiments, the following supplementary notes are provided.

[0201] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form an aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples.

[0202] Note that the content described in one embodiment (even part of the content) can be applied, combined, or replaced with respect to other content (even part of the content) described in that embodiment, and / or content (even part of the content) described in one or more other embodiments.

[0203] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0204] Note that the figure (even part of it) described in one embodiment can be combined with another part of that figure, another figure (even part of it) described in that embodiment, and / or figures (even part of them) described in one or more other embodiments to form even more figures.

[0205] Also, in this specification, etc., in the block diagram, the components are classified by function and shown as independent blocks. However, in an actual circuit, etc., it is difficult to separate the components by function, and there may be cases where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0206] In the drawings, the size, layer thickness, or area is shown in an arbitrary size for the convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are schematically shown for clarity and are not limited to the shapes or values shown in the drawings. For example, it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0207] Also, in the drawings and the like, the positional relationship of the components shown is relative. Therefore, when explaining the components with reference to the drawings, terms such as "above" and "below" indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description in this specification and can be appropriately rephrased according to the situation.

[0208] In this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or drain" (or the first electrode, or the first terminal), "the other of the source or drain" (or the second electrode, or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of the transistor can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode.

[0209] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0210] Also, in this specification and the like, voltage and potential can be appropriately rephrased. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground voltage (earthing voltage), the voltage can be rephrased as potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to wiring or the like may be changed.

[0211] Also, in this specification and the like, a node can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., according to the circuit configuration, device structure, etc. Also, it is possible to rephrase a terminal, wiring, etc. as a node.

[0212] In this specification and the like, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection where, when there is an object (such as an element like a switch, transistor element, or diode, or a circuit including the element and wiring) between A and B, the electrical signal can be transmitted between A and B. Note that when A and B are electrically connected, it includes the case where A and B are directly connected. Here, "A and B are directly connected" means a connection where the electrical signal can be transmitted between A and B through the wiring (or electrode) etc. between A and B without passing through the above object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0213] In this specification and the like, a switch is something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch is something that has a function of selecting and switching the path through which current flows.

[0214] In this specification and the like, the channel length refers to, for example, in the top view of a transistor, the distance between the source and the drain in the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate overlap, or in the region where the channel is formed.

[0215] In this specification and the like, the channel width refers to, for example, the length of the portion where the source and the drain face each other in the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed.

[0216] Note that in this specification and the like, terms such as "film" and "layer" can be interchanged with each other in some cases or according to the situation. For example, the term "conductive layer" may be changed to the term "conductive film" in some cases. Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases.

Description of Reference Numerals

[0217] PCL1: Precharge line, PCL2: Precharge line, T11: Period, T12: Period, T13: Period, T14: Period, T15: Period, T16: Period, 10: Semiconductor device, 10A: Semiconductor device, 10s: Semiconductor device, 11: Silicon substrate, 20: Peripheral circuit, 21: Loud driver, 22: Peripheral circuit, 22_A: Precharge circuit, 22_B: Precharge circuit, 22_C: Sense amplifier, 22_D: Switch circuit, 22_E: Switch circuit, 23_A: Switch, 23_C: Switch, 23_D: Switch, 24_1: Transistor, 24_3: Transistor, 24_4: Transistor, 24_6: Transistor, 25: Circuit, 25_1: Transistor, 25_2: Transistor, 25_3: Transistor, 25_4: Transistor, 29: Circuit, 30: Stacked block, 30_N: Stacked block, 30_1: Stacked block, 31_N_A: Memory cell, 31_N_B: Memory cell, 40: Element layer, 40_1: Element layer, 40_2: Element layer, 41: Transistor, 41_a: Transistor, 41_b: Transistor, 41_1: Transistor, 41_2: Transistor, 42: Transistor, 42_a: Transistor, 42_b: Transistor, 43: Transistor, 43_a: Transistor, 43_b: Transistor, 44: Transistor, 44_a: Transistor, 44_b: Transistor, 50: Element layer, 50_A: Element layer, 50_B: Element layer, 50_C: Element layer, 50_p: Element layer, 50_1: Element layer, 50_3: Element layer, 50_4: Element layer, 51: Memory cell, 51_A: Memory cell, 51_B: Memory cell, 51_c: Memory cell, 51_p: Memory cell, 51_1: Memory cell, 52: Transistor, 52_A: Transistor, 52_B: Transistor, 52B: Transistor, 53: Capacitor, 53_A: Capacitor, 53_B: Capacitor, 53A: Capacitor, 53B: Capacitor, 54: Wiring layer, 54_1: Wiring, 54_2: Wiring, 56: Transistor, 57_1: Opening, 58_1: Opening, 71: Row decoder, 72: Word line driver circuit, 73: Output circuit, 74: Control logic circuit, 75: Column driver, 81: Column decoder, 82: Precharge circuit, 83: Amplification circuit, 84: Circuit, 90: Memory cell array, 100: IC chip, 100A: IC chip, 100B: IC chip,101: Package substrate, 102: Solder ball, 103: Through electrode, 104: Metal bump, 105: Silicon substrate, 200T: Transistor, 300: Transistor, 311: Semiconductor substrate, 411: Element layer, 413: Transistor layer, 413_m: Transistor layer, 413_1: Transistor layer, 415: Memory device layer, 415_n: Memory device layer, 415_1: Memory device layer, 420: Memory device, 424: Conductor, 426: Conductor, 427: Conductor, 428: Conductor, 430: Conductor, 450: Substrate, 470: Memory unit, 470_m: Memory unit, 470_1: Memory unit, 700: Electronic component, 702: Printed circuit board, 704: Mounting substrate, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 901: Boundary region, 902: Boundary region, 7100: Robot, 7120: Aircraft, 7140: Cleaning robot, 7160: Automobile, 7200: TV device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard, 7233: Monitor device, 7240: Game console, 7260: Game console, 7262: Controller, 7300: Cleaning robot,

Claims

1. A silicon substrate having a first circuit, and a plurality of stacked blocks disposed above the silicon substrate and arranged to be stacked in order, wherein each of the stacked blocks has a first element layer having a second circuit, a second element layer having a third circuit, and a first bit line, the first circuit has a first transistor including silicon in a channel formation region, the second circuit has a second transistor including a metal oxide in a channel formation region, the third circuit has a memory cell, the memory cell has a third transistor including a metal oxide in a channel formation region and a capacitor, the first circuit has a function of controlling a signal for driving the memory cell, a function of outputting data to be written to the memory cell, and a function of amplifying data read from the memory cell to the first bit line, the second circuit has a function of amplifying a potential output from the memory cell and transmitting it to the first bit line, and a function of supplying the potential of the first bit line to the memory cell, in each of the plurality of stacked blocks, the second element layer is disposed above the first element layer, the first bit line is disposed to penetrate the first element layer and the second element layer, the first bit lines of each of the plurality of stacked blocks are electrically connected to each other, a semiconductor device.

2. A silicon substrate having a first circuit, and a plurality of stacked blocks disposed above the silicon substrate and arranged to be stacked in order, wherein each of the stacked blocks has a first element layer having a second circuit, a second element layer having a third circuit, and a first bit line, the first circuit has a first transistor including silicon in a channel formation region, the second circuit has a second transistor including a metal oxide in a channel formation region, the third circuit has a memory cell, the memory cell has a third transistor including a metal oxide in a channel formation region and a capacitor, the first circuit has a function of controlling a signal for driving the memory cell, a function of outputting data to be written to the memory cell, and a function of amplifying data read from the memory cell to the first bit line, The second circuit has a function of amplifying the potential output from the memory cell and transmitting it to the first bit line, and a function of supplying the potential of the first bit line to the memory cell. In each of the plurality of stacked blocks, the second element layer is disposed above the first element layer. The first bit line is disposed so as to penetrate the first element layer and the second element layer. The first bit lines included in each of the plurality of stacked blocks are electrically connected to each other. The metal oxide is indium oxide. Semiconductor device.

Images