Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Abstract

To provide a method of manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device, capable of reducing the VF of a built-in diode by introducing a Ni / Al / Ni structure on a p+-type contact region.SOLUTION: On a silicon carbide semiconductor substrate of a first conductivity type, there are formed a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, an interlayer insulating film, first electrodes, and a second electrode. Each of the first electrodes is formed by: depositing a lower Ni film, an Al film, and an upper Ni film and etching the films not to be in contact with the interlayer insulating film; sintering the lower Ni film by a heat treatment and thereby forming a Ni silicide film; depositing a Ti film, a TiN film, and an AlSi film; and etching the AlSi film.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). Compared to conventional semiconductor elements that use silicon carbide as a semiconductor material, semiconductor elements that use silicon carbide as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements that use silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] Silicon carbide semiconductor devices that have been commercially available to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) having a planar gate structure or a trench gate structure.

[0004] The planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of a semiconductor substrate, the unit cell (element constituent unit) density per unit area can be increased, and the current density per unit area can be increased, which is advantageous in terms of cost.

[0005] FIG. 10 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The structure of the conventional silicon carbide semiconductor device will be described by taking the trench-type MOSFET 170 as an example. In the trench-type MOSFET 170, n + -type silicon carbide substrate 101, an n - -type silicon carbide epitaxial layer 102 is deposited on the front surface. On the surface side opposite to the n - -type silicon carbide epitaxial layer 102 with respect to the n + -type silicon carbide substrate 101 side, an n-type high-concentration region 105 is provided. On the surface layer of the n-type high-concentration region 105, a first p + -type base region 103 is selectively provided between the trenches 116. Also, in the n-type high-concentration region 105, a second p + -type base region 104 is selectively provided so as to cover the entire bottom surface of the trench 116.

[0006] The MOS gate of the trench gate structure is composed of a p-type base layer 106, an n + -type source region 107, a p + -type contact region 108, a trench 116, a gate insulating film 109, and a gate electrode 110. Hereinafter, the n + -type silicon carbide substrate 101, the n - -type silicon carbide epitaxial layer 102, the n-type high-concentration region 105, and the p-type base layer 106 are combined into a silicon carbide semiconductor substrate 118.

[0007] Also, an interlayer insulating film 111 is provided on the gate electrode 110, and in the opening of the interlayer insulating film 111, a Ni silicide film 115 serving as a source electrode 112 in contact with the n + -type source region 107 and the p + -type contact region 108 is provided. On the Ni silicide film 115 and the interlayer insulating film 111, a Ti / TiN film 114 serving as a barrier metal for preventing the diffusion of metal atoms toward the gate electrode 110 is provided. On the Ti / TiN film 114, an AlSi film 119 serving as a source electrode pad is provided. An electrode 113 is provided on the back surface of the n + -type silicon carbide substrate 101 to serve as a drain electrode.

[0008] In a conventional silicon carbide semiconductor device, the Ni silicide film 115, the Ti / TiN film 114, and the AlSi film 119 are formed as follows. FIGS. 11 to 13 are cross-sectional views showing the state during the manufacture of a conventional silicon carbide semiconductor device. FIG. 11 shows the state during the manufacture of the semiconductor device after the formation of the interlayer insulating film 111.

[0009] After the formation of the interlayer insulating film 111, a Ni (nickel) film 121 is formed by sputtering on the entire front surface of the silicon carbide semiconductor substrate 118. Next, the first sintering is performed. Here, pseudo-sintering is performed at a relatively low temperature of about 600° C. so that the interlayer insulating film 111 does not react with Ni. Next, the Ni film 121 after the first sintering is patterned by photolithography and removed from above the interlayer insulating film 111. The state up to this point is described in FIG. 12.

[0010] Next, the second sintering is performed. The second sintering is performed at a higher temperature than the first sintering, about 975° C., and by reacting Ni and SiC, the Ni silicide film 115 is formed. Next, a Ti (titanium) / TiN (titanium nitride) film 114 is formed by depositing Ti and TiN by sputtering, and then an AlSi film 119 is formed by depositing AlSi by sputtering. After that, the AlSi film 119 is patterned by photolithography. The state up to this point is described in FIG. 13. In this way, the Ni silicide film 115, the Ti / TiN film 114, and the AlSi film 119 are formed.

[0011] Also, by forming a pn junction between the first and second p-type base regions and the n-type drift layer, it is possible to prevent a high electric field from being applied to the gate insulating film at the bottom of the trench, and a semiconductor device capable of achieving high breakdown voltage even when a wide bandgap semiconductor is used as a semiconductor material is known (for example, see Patent Document 1 below).

Prior Art Documents

Patent Documents

[0012] Patent Document 1 International Publication No. 2017 / 064949 Summary of the Invention Problems to be Solved by the Invention

[0013] As described above, conventionally, a Ni film 121 is formed on the p + -type contact region 108 and above the n + -type source region 107, and a Ni silicide film 115 is formed by heat treatment, and then excess Ni is removed. In this way, a Ni silicide film 115 that can reduce the contact resistance is formed in both the n + -type source region 107 (source region) and the p + -type contact region 108 (contact region).

[0014] Here, the silicon carbide semiconductor device performs post-manufacturing screening and ships only products having specified electrical characteristics. As post-manufacturing screening, in a silicon carbide MOSFET, screening is performed by passing a current through a built-in diode. At this time, it is preferable to perform screening by passing a large current through the p + -type contact region 108 for a short time. When the forward voltage (VF) is high, heat is generated and a large current cannot flow, so it is preferable to lower the VF of the built-in diode.

[0015] However, in the conventional silicon carbide semiconductor device, since a common Ni silicide film 115 is in contact with the upper parts of the p + -type contact region 108 and the n + -type source region 107, there is a problem that the VF of the built-in diode cannot be lowered.

[0016] In order to solve the problems caused by the above-described conventional technology, an object of this invention is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device capable of lowering the VF of a built-in diode by providing a Ni / Al / Ni structure on the p + -type contact region.

Means for Solving the Problems

[0017] In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, a second step of forming a second semiconductor layer of a second conductivity type is performed on the surface of the first semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. Next, a third step of selectively forming a first semiconductor region of a first conductivity type in the surface layer of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate is performed. Next, a fourth step of selectively forming a second semiconductor region of the second conductivity type in contact with the first semiconductor region in the surface layer of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate is performed. Next, a fifth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the second semiconductor layer located between the first semiconductor region and the first semiconductor layer is performed. Next, a sixth step of forming an interlayer insulating film so as to cover the gate electrode is performed. Next, a seventh step of forming a first electrode on the surfaces of the first semiconductor region and the second semiconductor region is performed. Next, an eighth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed. The seventh step includes a ninth step of forming a lower Ni film, an Al film, and an upper Ni film on the surface side of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate and etching them so as not to contact the interlayer insulating film, a tenth step of sintering the lower Ni film by heat treatment to form a Ni silicide film, an eleventh step of forming a Ti film, a TiN film, and an AlSi film on the surface side of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate, and a twelfth step of etching the AlSi film.

[0018] Further, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, the ninth step includes a step of forming the lower Ni film and the Al film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a step of leaving only the lower Ni film and the Al film on the surface of the second semiconductor region by etching, a step of forming the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, and a step of leaving only the upper Ni film on the surfaces of the first semiconductor region and the Al film by etching.

[0019] Further, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, the ninth step includes a step of forming the lower Ni film, the Al film, and the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, and a step of leaving only the lower Ni film, the Al film, and the upper Ni film on the surfaces of the first semiconductor region and the second semiconductor region by etching.

[0020] Further, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, the ninth step includes a step of forming the lower Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a step of leaving only the lower Ni film on the surfaces of the first semiconductor region and the second semiconductor region by etching, a step of forming the Al film and the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, and a step of leaving only the Al film and the upper Ni film on the surface of the second semiconductor region by etching.

[0021] Further, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the tenth step, the heat treatment is performed at 800°C or higher and 1000°C or lower.

[0022] In addition, the silicon carbide semiconductor device according to the present invention includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate provided on the front surface of the silicon carbide semiconductor substrate, a second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, a first semiconductor region of the first conductivity type selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a second semiconductor region of the second conductivity type in contact with the first semiconductor region selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a gate electrode provided via a gate insulating film on at least a part of the surface of the second semiconductor layer located between the first semiconductor region and the first semiconductor layer, an interlayer insulating film provided to cover the gate electrode, a first electrode provided on the surfaces of the first semiconductor region and the second semiconductor region, and a second electrode provided on the back surface of the silicon carbide semiconductor substrate. The first electrode contains NiAl silicide Film and Ni silicide film and is The NiAl silicide film is in contact with the second semiconductor region, the Ni silicide film is in contact with the first semiconductor region, and the first electrode is spaced apart from the interlayer insulating film. Further, a barrier metal is provided between the first electrode and the interlayer insulating film. Also, the NiAl silicide film is thicker than the Ni silicide film.

[0023] According to the above-described invention, the metal in contact with the p + -type contact region (second semiconductor region of the second conductivity type) has a three-layer structure of a Ni silicide film, an Al film, and a Ni film. Thereby, the contact resistance of the p + -type contact region can be reduced, and the VF of the body diode can be reduced. For this reason, the heat generation during BD screening is reduced, a large current can be passed during BD screening, and the screening time can be shortened.

[0024] In addition, the formation of the Ni silicide film is performed by one-time high-temperature sintering. For this reason, Al in the Al film easily thermally diffuses into the lower Ni film, and the contact resistance can be reduced.

Effects of the Invention

[0025] According to the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present invention, by forming a Ni / Al / Ni structure on the p + type contact region, the effect of reducing the VF of the built-in diode can be achieved.

Brief Description of the Drawings

[0026]

Figure 1

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Figure 13

Embodiments for Carrying Out the Invention

[0027] Hereinafter, with reference to the accompanying drawings, a method for manufacturing a silicon carbide semiconductor device and a preferred embodiment of the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the case of a layer or region with n or p prefixed, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and duplicate explanations are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index. And the description of the same or equivalent shall preferably include within 5% in consideration of variations in manufacturing.

[0028] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In an embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described by taking a trench type MOSFET 70 as an example. FIGS. 1 to 3 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the embodiment. In FIGS. 1 to 3, only the active region through which the main current of the trench type MOSFET 70 flows is shown.

[0029] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment is an n + -type silicon carbide substrate (silicon carbide semiconductor substrate of the first conductivity type) 1 on the first main surface (front surface), for example, the (0001) surface (Si surface), an n - -type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 is deposited.

[0030] n +The silicon carbide substrate 1 is a single-crystal silicon carbide substrate. n - The n-type silicon carbide epitaxial layer 2 has an impurity concentration lower than that of the n + type silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. n - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n + type silicon carbide substrate 1, an n-type high-concentration region 5 may be provided. The n-type high-concentration region 5 has an n + impurity concentration lower than that of the n - type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2, and is a high-concentration n-type drift layer.

[0031] n - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n + type silicon carbide substrate 1, a p-type base layer (a second semiconductor layer of the second conductivity type) 6 is provided. Hereinafter, n + the n-type silicon carbide substrate 1 and n - the n-type silicon carbide epitaxial layer 2, the n-type high-concentration region 5, and the p-type base layer 6 are combined to form a silicon carbide semiconductor substrate (a semiconductor substrate made of silicon carbide) 18.

[0032] n + On the second main surface (the back surface, that is, the back surface of the silicon carbide semiconductor substrate 18) of the n-type silicon carbide substrate 1, a drain electrode serving as a back surface electrode 13 is provided. On the surface of the back surface electrode 13, a drain electrode pad (not shown) is provided.

[0033] On the first main surface side (the p-type base layer 6 side) of the silicon carbide semiconductor substrate 18, a trench structure is formed. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface on the side opposite to the side of the n + type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate 18) and reaches the n-type high-concentration region 5 (when the n-type high-concentration region 5 is not provided, n -The type silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) is reached. Along the inner wall of the trench 16, a gate insulating film 9 is formed on the bottom and side walls of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate electrode 10 is insulated from the n-type high-concentration region 5(2) and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12 described later is provided) toward the source electrode 12 side.

[0034] n of the n-type high-concentration region 5(2) + On the surface layer on the side opposite to the type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate 18), a first p is provided between the trenches 16. + type base region 3 is provided. Also, in the n-type high-concentration region 5(2), a second p in contact with the bottom of the trench 16. + type base region 4 is provided. The second p + type base region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the back electrode 13). The second p + type base region 4 has a width equal to or wider than the width of the trench 16. The bottom of the trench 16 may reach the second p + type base region 4, or may be located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p + type base region 4.

[0035] Inside the p-type base layer 6, an n is provided on the first main surface side of the silicon carbide semiconductor substrate 18. + type source region (the first semiconductor region of the first conductivity type) 7 and a p + type contact region (the second semiconductor region of the second conductivity type) 8 are selectively provided. Also, an n + type source region 7 and a p + type contact region 8 are in contact with each other.

[0036] Here, in order to adjust the threshold voltage (Vth), ion implantation is performed on a portion of the p-type base layer 6 where a channel is to be formed. As a result, a channel implantation portion 22 having a higher impurity concentration than the p-type base layer 6 is formed.

[0037] In addition, to increase the breakdown voltage, - In the silicon carbide epitaxial layer 2, a first p + A region deeper than the n-type base region 3 has a peak impurity concentration higher than that of the n-type high concentration region 5(2). + The mold region 17 is provided. + This refers to a position closer to the back surface electrode 13 than the mold base region 3 .

[0038] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate 18 so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type + Type source region 7 and p + The source electrode 12 is in contact with the type contact region 8. In this embodiment, the source electrode 12 is made of a Ni silicide film 15 and a NiAl silicide film 20.

[0039] For example, as shown in FIG. 1, when the NiAl silicide film 20 is p + The Ni silicide film 15 is in contact with the n-type contact region 8. + The Ni silicide film 15 is provided so as to contact the n-type source region 7. At this time, the Ni silicide film 15 does not contact the interlayer insulating film 11. The boundary between the Ni silicide film 15 and the NiAl silicide film 20 is + Even if it is on the upper surface side of the p type source region 7, + It may be on the upper surface side of the mold contact region 8 .

[0040] Also, as shown in Figure 2, p + Type contact region 8 and n +The NiAl silicide film 20 may be formed on both upper surfaces of the source region 7. In this case, the NiAl silicide film 20 is separated from the interlayer insulating film 11. As shown in FIG. 3, the NiAl silicide film 20 may be provided thicker than the Ni silicide film 15. In this case, the NiAl silicide film 20 has a p + The Ni silicide film 15 is in contact with the n-type contact region 8. + The Ni silicide film 15 is in contact with the source region 7. A barrier metal 14 is provided between the Ni silicide film 15 and the interlayer insulating film 11.

[0041] Thus, in the embodiment, p + The metal with which the contact region 8 comes into contact is the NiAl silicide film 20. + The contact resistance of the contact region 8 can be reduced, and the VF of the body diode can be reduced. This reduces heat generation during BD (Body Diode) screening, making it possible to pass a large current during BD screening, and shortening the screening time.

[0042] Furthermore, p + By lowering the contact resistance of the contact region 8, the loss during switching can be reduced. + Since the contact resistance of the mold contact region 8 can be reduced, a predetermined design value of the surge current withstand capability (IFSM) can be obtained.

[0043] The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. An AlSi film 19 serving as a source electrode pad is provided on the source electrode 12. A Ti / TiN film 14 serving as a barrier metal for preventing, for example, diffusion of metal atoms from the source electrode 12 toward the gate electrode 10 is provided between the source electrode 12 and the interlayer insulating film 11. The barrier metal 14 covers the entire sidewall of the interlayer insulating film 11, so that the interlayer insulating film 11 is not in direct contact with the Ni silicide film 15 or the NiAl silicide film 20.

[0044] (Manufacturing Method of Silicon Carbide Semiconductor Device According to Embodiment) Next, a manufacturing method of a silicon carbide semiconductor device according to an embodiment will be described. FIG. 4 is a flowchart showing an outline of the manufacturing method of the silicon carbide semiconductor device according to the embodiment. FIGS. 5, 7, and 9 are cross-sectional views showing states during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIGS. 6 and 8 are top views showing states during the manufacture of the silicon carbide semiconductor device according to the embodiment.

[0045] First, an n + type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Next, a semiconductor element is formed on the front surface (first main surface) of the n + type silicon carbide substrate 1 (steps S1, first to fifth steps). Details of the steps for forming the semiconductor element will be described below. On the first main surface of this n + type silicon carbide substrate 1, a lower n - type silicon carbide epitaxial layer (not shown) made of silicon carbide while doping with an n-type impurity, for example, nitrogen atoms (N), is epitaxially grown to a thickness of about 30 μm, for example.

[0046] Next, a mask (not shown) having a desired opening is formed on the surface of the lower n - type silicon carbide epitaxial layer by photolithography technology, for example, an oxide film. Then, an n-type impurity, for example, nitrogen atoms, may be ion-implanted using this oxide film as a mask by the ion implantation method. As a result, an n - type region 17 is formed inside the lower n + type silicon carbide epitaxial layer.

[0047] Next, the mask used during the ion implantation for forming the n + type region 17 is removed. Next, an ion implantation mask having a predetermined opening is formed by photolithography technology, for example, an oxide film. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p + type base region (not shown) and a second p + type base region 4 having a depth of about 0.5 μm. n+ When forming the n-type region 17, the n of the n-type region 17 + of the n-type region 17 + On the surface opposite to the silicon carbide substrate 1 of the n-type, a lower first p-type base region is formed so as to overlap the n-type region 17 + type base region to be n + type region 17 is formed so as to overlap it.

[0048] Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening, and a lower n-type high-concentration region with a depth of about 0.5 μm may be formed in a part of the surface region of the lower n-type silicon carbide epitaxial layer. The impurity concentration of the lower n-type high-concentration region is set to, for example, 1×10 - / cm 17 / cm 3 or so.

[0049] Next, on the surface of the lower n-type silicon carbide epitaxial layer, an upper n-type silicon carbide epitaxial layer doped with an n-type impurity such as nitrogen is formed with a thickness of about 0.5 μm. The impurity concentration of the upper n-type silicon carbide epitaxial layer is set to be about 8×10 - type silicon carbide epitaxial layer doped with an n-type impurity such as nitrogen is formed with a thickness of about 0.5 μm. The upper n - type silicon carbide epitaxial layer is formed with a thickness of about 0.5 μm. The upper n - type silicon carbide epitaxial layer has an impurity concentration of 8×10 15 / cm 3 or so. Thereafter, the lower n - type silicon carbide epitaxial layer and the upper n - type silicon carbide epitaxial layer together form an n - type silicon carbide epitaxial layer 2.

[0050] Next, on the surface of the upper n-type silicon carbide epitaxial layer, an ion implantation mask having a predetermined opening is formed by photolithography, for example, with an oxide film. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film, and an upper first p-type base region (not shown) with a depth of about 0.5 μm is formed so as to overlap the lower first p-type base region. The upper first p - type silicon carbide epitaxial layer doped with an n-type impurity such as nitrogen is formed with a thickness of about 0.5 μm. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film, and an upper first p + type base region (not shown) with a depth of about 0.5 μm is formed so as to overlap the lower first p + type base region. The upper first p + type base region and the lower first p + type base region form a continuous region, and the first p + type base region 3 is formed. The upper first p+ The impurity concentration of the base region is, for example, 5×10 18 / cm 3 Set it so that it is about the same.

[0051] Next, a part of the ion implantation mask may be removed, and an n-type impurity such as nitrogen may be ion-implanted into the opening to form an upper n-type high concentration region having a depth of, for example, about 0.5 μm in a part of the surface region of the second silicon carbide epitaxial layer 2. The impurity concentration of the upper n-type high concentration region may be set to, for example, 1×10 17 / cm 3 The upper n-type heavily doped region and the lower n-type heavily doped region are formed so that at least a portion of them are in contact with each other to form the n-type heavily doped region 5. However, there are cases where the n-type heavily doped region 5 is formed over the entire surface of the substrate, and cases where it is not formed.

[0052] Next, n - On the surface of the silicon carbide epitaxial layer 2, a p-type base layer 6 is formed by epitaxial growth to a thickness of about 1.1 μm. The impurity concentration of the p-type base layer 6 is 5×10 15 / cm 3 ~5×10 16 / cm 3 Set it to a certain extent.

[0053] Next, p-type impurities such as aluminum are implanted from the surface of the p-type base layer 6 to form a channel implantation portion 22 inside the p-type base layer 6. The impurity concentration of the channel implantation portion 22 is 1×10 17 / cm 3 Set it to a certain extent.

[0054] Next, a predetermined region constituting a MOS gate is formed on the first main surface layer (surface layer of the p-type base layer 6) of the silicon carbide semiconductor substrate 18. Specifically, an ion implantation mask having a predetermined opening is formed on the surface of the p-type base layer 6 by photolithography, for example, from an oxide film. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening, and n-type impurities are implanted into a portion of the surface of the p-type base layer 6. + Next, the n-type source region 7 is formed. +Remove the ion implantation mask used to form the p-type source region 7, and in the same manner, form an ion implantation mask having a predetermined opening, and implant p-type impurities such as boron into a part of the surface of the p-type base layer 6 to form a p + type contact region 8. p + The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6.

[0055] Next, perform a heat treatment (activation annealing) for activating all the regions formed by ion implantation. For example, perform heat treatment (annealing) in an inert gas atmosphere at about 1700 °C to activate the first p + type base region 3, the second p + type base region 4, the n + type source region 7, and the p + type contact region 8. Note that, as described above, each ion implantation region may be activated collectively by one heat treatment, or may be activated by performing heat treatment each time ion implantation is performed.

[0056] Next, on the surface of the p-type base layer 6, form a trench formation mask having a predetermined opening by photolithography, for example, with an oxide film. Next, form a trench 16 that penetrates the p-type base layer 6 and reaches the n-type high-concentration region 5(2) by dry etching. The bottom of the trench 16 may reach the second p + type base region 4 formed in the n-type high-concentration region 5(2). Next, remove the trench formation mask. Next, perform, for example, RCA cleaning (wet cleaning using a strong acid and a high-base solution) on the front surface of the silicon carbide semiconductor substrate 18.

[0057] Next, form a gate insulating film 9 along the surface of the n + type source region 7, the bottom, and the side walls of the trench 16. First, an oxide film is deposited in the trench by a chemical reaction (chemical vapor deposition method) such as thermal oxidation or high-temperature oxidation (High Temperature Oxide: HTO) at a temperature of about 1000 °C in an oxygen atmosphere.

[0058] Next, sacrificial oxidation may be performed to round the bottom of the trench and the corners of the trench opening. Next, an annealing process is performed on the oxide film. When formed by thermal oxidation, the interface trap density at the interface between the oxide film and the semiconductor portion may be reduced by a heat treatment (POA (Post Oxidation Anneal) treatment). When the oxide film is formed by a deposition method such as HTO, post-annealing is generally performed with a gas containing nitrogen (N2) or the like after HTO film formation in order to improve electrical characteristics (such as mobility). For example, NO annealing is performed at a temperature of 1300°C with a NO 10% / N2 gas for about 30 minutes. Thereby, the gate insulating film 9 is formed.

[0059] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. The polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0060] Next, for example, phosphosilicate glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, and the interlayer insulating film 11 is formed. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form contact holes exposing the n + -type source region 7 and the p + -type contact region 8. Thereafter, a heat treatment (reflow) is performed to planarize the interlayer insulating film 11. The state up to this point is described in FIGS. 5 and 6.

[0061] Next, a lower Ni film 23, an Al film 24, and an upper Ni film 25 are formed and etched in this order on the surface of the silicon carbide semiconductor substrate 18 from which the interlayer insulating film 11 has been selectively removed (step S2, sixth step). The lower Ni film 23 is formed by sputtering, for example, to have a thickness of 50 nm or more and 120 nm or less. The Al film 24 is formed by sputtering, for example, to have a thickness of 50 nm or more and 120 nm or less. The upper Ni film 25 is formed by sputtering, for example, to have a thickness of 50 nm or more and 100 nm or less. In the cases of FIGS. 2 and 3, the upper Ni film 25 may be a high melting point metal of 1400° C. or higher other than Ni, for example, titanium (Ti) or molybdenum (Mo).

[0062] In the case of the structure of FIG. 1, the lower Ni film 23 and the Al film 24 are formed over the entire surface and etched by photolithography to leave only the upper surface side of the p + type contact region 8. Next, the upper Ni film 25 is formed over the entire surface and etched by photolithography to leave only the upper surface side of the p + type contact region 8 and the n + type source region 7 (eighth step). At this time, the upper Ni film 25 is etched so as not to contact the interlayer insulating film 11. The state up to this point is described in FIGS. 7 and 8.

[0063] In the case of the structure of FIG. 2, the lower Ni film 23, the Al film 24, and the upper Ni film 25 are formed over the entire surface and etched by photolithography to leave only the upper surface side of the p + type contact region 8 and the n + type source region 7 (eighth step). At this time, the lower Ni film 23, the Al film 24, and the upper Ni film 25 are all etched so as not to contact the interlayer insulating film 11. In the case of the structure of FIG. 2, the description of the state up to this point is omitted.

[0064] In the case of the structure of FIG. 3, the lower Ni film 23 is formed over the entire surface and etched by photolithography to leave only the upper surface side of the p + type contact region 8 and the n +Leave only on the upper surface side of the p-type source region 7. Next, deposit the Al film 24 and the upper Ni film 25 over the entire surface, and etch them by photolithography to leave only on the upper surface side of the p + -type contact region 8 (8th step). At this time, etch the lower Ni film 23 so as not to contact the interlayer insulating film 11. In the case of the structure of FIG. 3, the description of the state so far is omitted.

[0065] Next, perform sintering by heat treatment (step S3, 9th step). As a result, in a part where there are three layers of the lower Ni film 23, the Al film 24, and the upper Ni film 25, the three layers react with the SiC on the surface of the p + -type contact region 8 or the n + -type source region 7 to be silicided, and the NiAl silicide film 20 is formed. In a part where there is a single layer of the lower Ni film 23 or the upper Ni film 25, the single layer reacts with the SiC on the surface of the n + -type source region 7 to be silicided, and the Ni silicide film 15 is formed. The heat treatment temperature is preferably, for example, 800°C or higher and 1000°C or lower. If it is less than 800°C, sintering is not sufficiently performed, and the Ni silicide film 15 may peel off. If it is 1000°C or higher, the upper Ni film 21 reacts and is silicided, the composition of the upper Ni film 21 changes, the density decreases, and the coverage deteriorates.

[0066] As described above, in the embodiment, high-temperature sintering is performed only once. Therefore, Al in the Al film 24 easily diffuses thermally into the lower Ni film 23, and the contact resistance can be reduced.

[0067] Next, remove unreacted excess Ni and excess Al in the sintering step of step S3 (step S4). Next, deposit Ti, TiN, and AlSi over the entire surface (step S5, 10th step). As a result, the Ti / TiN film 14 serving as a barrier metal and the AlSi film 19 are formed. At this stage, the space between the Ni silicide film 15 and the interlayer insulating film 11 is filled with the Ti / TiN film 14. The state so far is described in FIG. 9.

[0068] Next, the Ti / TiN film 14 and the AlSi film 19 are etched (step S6, the 11th step). By selectively removing the Ti / TiN film 14 and the AlSi film 19 and leaving them so as to cover the active part of the entire element, a source electrode pad and a gate electrode pad are formed.

[0069] Next, an + A back surface electrode 13 made of, for example, a nickel (Ni) film is formed on the second main surface of the n-type silicon carbide substrate 1. Thereafter, for example, laser annealing is performed to + perform an ohmic junction between the n-type silicon carbide substrate 1 and the back surface electrode 13.

[0070] Next, for example, titanium (Ti), nickel (Ni), and gold (Au) are sequentially formed as a drain electrode pad (not shown) on the surface of the back surface electrode 13. In this way, the semiconductor device shown in FIGS. 1 to 3 is completed.

[0071] As described above, according to the embodiment, the metal in contact with the p + type contact region is a NiAl silicide film. Thereby, the contact resistance of the p + type contact region can be reduced, and the VF of the body diode can be reduced. For this reason, the heat generation during BD screening is reduced, a large current can flow during BD screening, and the screening time can be shortened.

[0072] Also, the formation of the Ni silicide film is performed by one-time high-temperature sintering. For this reason, Al of the Al film easily diffuses into the lower Ni film, and the contact resistance can be reduced.

[0073] In the above, the present invention can be variously modified without departing from the gist of the present invention. In each of the above-described embodiments, for example, the dimensions, impurity concentrations, etc. of each part are variously set according to required specifications and the like. Also, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention also holds similarly when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0074] As described above, the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters for automobiles.

Explanation of Signs

[0075] 1, 101 n + -type silicon carbide substrate 2, 102 n - -type silicon carbide epitaxial layer 3, 103 First p + -type base region 4, 104 Second p + -type base region 5, 105 n-type high concentration region 6, 106 p-type base layer 7, 107 n + -type source region 8, 108 p + -type contact region 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back surface electrode 14, 114 Ti / TiN film 15, 115 Ni silicide film 16, 116 Trench 17, 117 n + -type region 18, 118 Silicon carbide semiconductor substrate 19, 119 AlSi film 20 NiAl silicide film 22, 122 Channel implant part 23 Lower Ni film 24 Al film 25 Upper Ni film 70, 170 Trench type MOSFET 121 Ni film

Claims

1. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate on the front surface of the silicon carbide semiconductor substrate of the first conductivity type; A second step of forming a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side; A third step of selectively forming a first semiconductor region of a first conductivity type in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A fourth step of selectively forming a second semiconductor region of a second conductivity type in contact with the first semiconductor region in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A fifth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the second semiconductor layer located between the first semiconductor region and the first semiconductor layer; A sixth step of forming an interlayer insulating film so as to cover the gate electrode; A seventh step of forming a first electrode on the surfaces of the first semiconductor region and the second semiconductor region; An eighth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate; comprising, The seventh step is A ninth step of forming a lower Ni film, an Al film, and an upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, and etching so as not to contact the interlayer insulating film; A tenth step of sintering the lower Ni film by heat treatment to form a Ni silicide film; An eleventh step of forming a Ti film, a TiN film, and an AlSi film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A twelfth step of etching the AlSi film; A method for manufacturing a silicon carbide semiconductor device, characterized by including the above.

2. The ninth step is A step of forming the lower Ni film and the Al film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A step of leaving the lower Ni film and the Al film only on the surface of the second semiconductor region by etching; A step of forming the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A step of leaving the upper Ni film only on the surfaces of the first semiconductor region and the Al film by etching; The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized by including the above.

3. The ninth step is A step of forming the lower Ni film, the Al film, and the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A step of leaving only the lower Ni film, the Al film, and the upper Ni film on the surfaces of the first semiconductor region and the second semiconductor region by etching; The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized by including the above.

4. The ninth step is: A step of forming the lower Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A step of leaving only the lower Ni film on the surfaces of the first semiconductor region and the second semiconductor region by etching; A step of forming the Al film and the upper Ni film on the surface side of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A step of leaving only the Al film and the upper Ni film on the surface of the second semiconductor region by etching; The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized by including the above.

5. In the tenth step, the heat treatment is performed at 800°C or higher and 1000°C or lower. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4.

6. A silicon carbide semiconductor substrate of a first conductivity type; A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, provided on the front surface of the silicon carbide semiconductor substrate; A second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side; A first semiconductor region of a first conductivity type selectively provided in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A second semiconductor region of a second conductivity type in contact with the first semiconductor region selectively provided in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A gate electrode provided via a gate insulating film on at least a part of the surface of the second semiconductor layer located between the first semiconductor region and the first semiconductor layer; An interlayer insulating film provided so as to cover the gate electrode; A first electrode provided on the surfaces of the first semiconductor region and the second semiconductor region; A second electrode provided on the back surface of the silicon carbide semiconductor substrate; Including The first electrode includes a NiAl silicide film and a Ni silicide film. The NiAl silicide film is in contact with the second semiconductor region, and the Ni silicide film is in contact with the first semiconductor region. The first electrode is spaced apart from the interlayer insulating film. A silicon carbide semiconductor device characterized by this.

7. The silicon carbide semiconductor device according to claim 6, characterized in that a barrier metal is provided between the first electrode and the interlayer insulating film.

8. The silicon carbide semiconductor device according to claim 6 or 7, characterized in that the NiAl silicide film is thicker than the Ni silicide film.

Images