A / D Converter

Abstract

To provide an A / D converter capable of converting an analog signal into a digital value with high precision.SOLUTION: Each delay unit 13 of an A / D converter 1 is configured such that the time difference between a first required time and a second required time becomes small, and a first transit time and a second transit time are different as compared with a case in which the first transit time is equal to the second transit time. A time until a pulse signal goes through the plurality of delay units 13 of a first digitizing portion 10 is the first required time, and a time until the pulse signal goes through the plurality of delay units 13 of a second digitizing portion 20 is the second required time. An average time required for the pulse signal to pass through one of the plurality of delay units 13 of the first digitizing portion 10 is the first transit time. An average time required for the pulse signal to pass through one of the delay units 13 of the second digitizing section 20 is a second transit time.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to an A / D converter configured to output a digital value corresponding to the potential of an analog signal.

Background Art

[0002] For example, Patent Document 1 below discloses an A / D converter including a pair of ring-shaped pulse delay circuits (hereinafter also referred to as ring delay lines: RDLs) composed of serially connected delay units. The delay units are composed of various gate circuits and inverter circuits. Note that an A / D converter is an abbreviation for an analog / digital converter.

[0003] In this A / D converter, while a pulse signal is circulated through a pulse delay circuit, an analog signal is input to the power supply line of the pulse delay circuit. Then, the number of delay units through which the pulse signal passes within a predetermined sampling time changes according to the potential of the analog signal. By counting this number, the analog signal is converted into a digital value.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, as a result of the inventors' detailed examination, it has been found that the above A / D converter has a problem that the error becomes large depending on the situation. Specifically, in the above A / D converter, the number of delay units provided in a pair of RDLs is set to be different. And when an overflow occurs in each RDL, that is, a phenomenon where a pulse returns from the last delay unit to the first delay unit, code dropout occurs. However, in the above A / D converter, the code dropout is complemented by a pair of RDLs, and it is configured such that the error due to the code dropout is reduced.

[0006] However, in the above A / D converter, since the number of delay units provided in a pair of RDLs is different, the frequency of overflow in each RDL tends to be different. In this case, the effect of complementing the code dropout is difficult to be exerted. As a result, the error becomes large.

[0007] One aspect of the present disclosure is to provide an A / D converter capable of converting an analog signal into a digital value with high precision.

Means for Solving the Problems

[0008] One aspect of the present disclosure is an A / D converter (1) configured to output a digital value corresponding to the potential of an analog signal. The A / D converter includes a first digitizing unit (10), a second digitizing unit (20), and an addition output unit (40).

[0009] The first digitizing unit includes a plurality of first delay units (11:12, 13) connected in series, and a first output unit (15) configured to output data corresponding to the number of times the pulse signal has passed through the plurality of first delay units. The second digitizing unit includes a plurality of second delay units (21:12, 13) connected in series by a number greater than the plurality of first delay units, and a second output unit (25) configured to output data corresponding to the number of times the pulse signal has passed through the plurality of second delay units.

[0010] The addition output unit is configured to output, as a digital value, an addition value obtained by adding a numerical value based on the output of the first digitization unit and a numerical value based on the output of the second digitization unit. Each delay unit representing each of the plurality of first delay units and the plurality of second delay units is configured such that the delay time of a pulse signal passing through each delay unit is changed according to the potential of an analog signal.

[0011] Here, let the time until the pulse signal makes one round through the plurality of first delay units be the first required time, and the time until the pulse signal makes one round through the plurality of second delay units be the second required time. Also, let the average time required for the pulse signal to pass through one of the plurality of first delay units be the first passing time, and the average time required for the pulse signal to pass through one of the plurality of second delay units be the second passing time.

[0012] Each delay unit is configured such that the first passing time and the second passing time are different so that the time difference between the first required time and the second required time becomes smaller compared to the case where the first passing time and the second passing time are equal.

[0013] According to such a configuration, the time difference until the pulse signal makes one round in each delay unit can be reduced, so the frequencies of overflow occurring in each delay unit can be made as uniform as possible. Therefore, it is possible to provide an A / D converter that can convert an analog signal into a digital value with high precision.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 8C

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1-1. Configuration] The A / D converter 1 of the present embodiment shown in FIG. 1 functions as an A / D (that is, analog / digital) converter that outputs a digital value corresponding to the potential of an analog input signal.

[0016] The A / D converter 1 shown in FIG. 1 includes a first digitization unit 10, a second digitization unit 20, and an addition output unit 40. The first digitization unit 10 and the second digitization unit 20 may be input with VBB which is a power supply voltage, GND which is a ground voltage, CKs which is a clock, and VIN which is an analog signal. The first digitization unit 10 and the second digitization unit 20 have functions as well-known A / D converters that output A / D conversion values.

[0017] The A / D conversion value here represents the digital value corresponding to the voltage of the input analog signal. For example, the numerical data DTc1 and DTc2 are A / D conversion values. Each of these numerical data DTc1 and DTc2 is input to the addition output unit 40.

[0018] The addition output unit 40 calculates the sum of the numerical data DTc1 and the numerical data DTc2, that is, (DTc1 + DTc2), and outputs it as the A / D conversion data DT of the analog input signal VIN. Here, the first digitization unit 10 includes a ring-shaped pulse delay circuit 11 and a first output unit 15. The second digitization unit 20 includes a ring-shaped pulse delay circuit 21 and a second output unit 25. The first output unit 15 and the second output unit 25 are hereinafter also referred to as each output unit 15, 25.

[0019] As shown in FIGS. 1 and 2, the ring-shaped pulse delay circuits 11 and 21 include a plurality of delay units 13. By configuring the plurality of delay units 13 to form a pulse delay circuit, it functions as a time A / D conversion circuit, that is, TAD. Note that TAD is an abbreviation for Time A / D converter.

[0020] The ring-shaped pulse delay circuits 11 and 21 include a large number (for example, an odd number) of inverters INV13 as the plurality of delay units 13. By connecting these delay units 13 in a ring shape, a ring delay line is formed.

[0021] In particular, in the present embodiment, the ring-shaped pulse delay circuit 11 of the first digitization unit 10 is configured to include a plurality of delay units 13 connected in series, with 127 (that is, 2 to the 7th power - 1) units.

[0022] The ring-shaped pulse delay circuit 21 of the second digitization unit 20 includes a plurality of delay units 13 connected in series, with 129 (that is, 2 to the 7th power + 1) units. INV13 is a CMOS inverter and a switching element.

[0023] And positive and negative power lines are connected to each of these delay units 13. Each delay unit 13 delays and transmits a pulse signal with a delay time corresponding to the voltage between these terminals when a positive power supply voltage is applied to the power supply terminal VIN and the ground terminal GND is set to a lower potential than the power supply terminal VIN. In the case of this embodiment, the first digitizing unit 10 and the second digitizing unit 20 input an analog signal as VIN to the pulse delay circuit, and the speed at which the pulse signal circulates while passing through the delay unit 13 is changed according to the potential of VIN.

[0024] Note that in this embodiment, a pulse signal is not input from the outside. The pulse signal is naturally generated by noise such as thermal noise immediately after the activation of the A / D converter 1, and the pulse signal becomes stable and circulates by the time the data from the A / D converter 1 is required. In particular, for example, in the ring-shaped pulse delay circuits 11 and 21, even if a plurality of pulse signals are generated, it has been experimentally clarified that the pulse signals other than the strongest pulse signal are absorbed by the strongest pulse signal or disappear. For this reason, the ring-shaped pulse delay circuits 11 and 21 can operate stably without problem even if a pulse signal is not intentionally input.

[0025] Here, "passing" means that the pulse signal reaches the gate of the delay unit 13, that is, the potential level of the gate changes from low to high or from high to low, and the output of this delay unit 13 is inverted. When the pulse signal passes through this delay unit 13, the pulse signal is input to the gate of the next delay unit 13, and this operation occurs in a chained and continuous manner for a plurality of delay units 13.

[0026] Also, "speed" represents the number of delay units 13 that a pulse signal can pass through per unit time. When the speed increases, the number of delay units 13 that a pulse signal can pass through per unit time increases.

[0027] For example, as shown in FIG. 5, when the potential of the analog input signal input as VIN is high, the time until the ring-shaped pulse delay circuits 11 and 21 overflow (for example, Trdl which is one cycle of the pulse signal P1 in FIG. 5) becomes short, and overflows frequently occur. Note that overflow means that a phenomenon occurs in which the pulse signal returns from the last delay unit 13 to the first delay unit 13.

[0028] In other words, it is a phenomenon in which the output DTp from the count units 16 and 26 returns to 0 after reaching the maximum value. In this configuration, as the potential of the analog input signal VIN decreases, the time until the ring-shaped pulse delay circuits 11 and 21 overflow becomes longer. Note that the passage of the pulse signal through all the delay units 13 is also expressed as the pulse signal making one round.

[0029] Also, as shown in FIG. 2, the back gate bias of the P-channel transistor constituting the delay unit 13 has the power supply VBB applied thereto. The speed at which the pulse signal PA passes through the delay unit 13 can also be changed by the potential of VBB.

[0030] Each output unit 15 and 25 includes a count unit 16 and 26, latches 17 and 27, and adders 18 and 28. The count units 16 and 26 are configured as, for example, latches and encoders.

[0031] The count units 16 and 26 repeatedly capture the outputs P1 to P127 or P1 to P129 of the delay units 13 constituting the ring-shaped pulse delay circuits 11 and 21 at a predetermined timing according to the clock CKs. Then, an output DTp corresponding to the position of the pulse signal passing through the delay unit 13, that is, the output, is generated.

[0032] The output DTp from the count unit 16 in the first digitization unit 10 is output in 7 bits, and the output DTp from the count unit 26 in the second digitization unit 20 is output in 8 bits, which is 1 bit more than the output DTp from the count unit 16. This is configured in this way because the number of delay units 13 in the second digitization unit 20 is more than 2 to the power of 7, and 8 bits are required to represent the output P129.

[0033] These outputs DTp are input to the latches 17, 27 and the adders 18 respectively. The latches 17, 27 hold the latest output DTp received from the count unit 26, and send the output DTp held immediately before the latest output DTp as a comparison value to the adders 18, 28.

[0034] In the adders 18, 28, the comparison value is subtracted from the latest output DTp. That is, the difference in the positions of the pulse signals before and after the elapse of the time corresponding to the preset number of clock CKs is calculated. Here, in order to enable subtraction in the adders 18, 28, subtraction using the two's complement in binary numbers is performed. The adders 18, 28 output the calculation results as numerical data DTc1, DTc2 to the addition output unit 40.

[0035] In the following of FIG. 3, for the sake of simplicity of explanation, the ring-shaped pulse delay circuits 11, 21 are described as having a configuration including 2 to the power of 4 (i.e., 16) ± 1 delay units 13. Also, the time until the pulse signal makes one round through the plurality of delay units 13 in the first digitization unit 10 is defined as the first required time, and the time until the pulse signal makes one round through the plurality of delay units 13 in the second digitization unit 20 is defined as the second required time. Also, the average time required for the pulse signal to pass through one of the plurality of delay units 13 in the first digitization unit 10, that is, the value obtained by dividing the first required time by the number of the plurality of delay units 13 in the first digitization unit 10 is defined as the first passing time. Also, the average time required for the pulse signal to pass through one of the delay units 13 in the second digitization unit 20, that is, the value obtained by dividing the second required time by the number of the plurality of delay units 13 is defined as the second passing time.

[0036] Each delay unit 13 is configured such that the first transit time and the second transit time are different from each other, so that the time difference between the first required time and the second required time is smaller than the case where the first transit time and the second transit time are equal. In the present embodiment, in the first digitizing unit 10 with a small number of delay units 13, the speed of the pulse signal is slower than that of the second digitizing unit 20. In other words, the first transit time is set to be larger than the second transit time.

[0037] As a configuration for making the first transit time larger than the second transit time, the A / D converter 1 includes adjustment units C1 to C15 as shown in FIG. 3. The adjustment units C1 to C15 are evenly provided for all of the plurality of delay units 13 of the first digitizing unit 10. That is, the adjustment units C1 to C15 are configured in the same manner so that the time required for the pulse signal to pass through all of the plurality of delay units 13 is equal.

[0038] More specifically, the adjustment units C1 to C15 are configured as wiring capacitances as shown in FIG. 4. Note that in FIG. 4, only C1 and C2 of the adjustment units C1 to C15 are illustrated. The others of the adjustment units C1 to C15 are configured in the same manner as the adjustment units C1 and C2.

[0039] Note that the adjustment units C1 to C15 may be provided for at least a part of the plurality of delay units 13 of the first digitizing unit 10. In FIG. 4, the adjustment units C1 to C15 are the hatched portions. The adjustment units C1 to C15 function as wiring capacitances by generating a capacitance component Cp, for example, by expanding a part of aluminum wiring.

[0040] The adjustment units C1 to C15 act to increase the time constant t in each delay unit 13, thereby slowing down the switching of the CMOS transistors in the delay unit 13 and reducing the speed of the pulse signal. Note that the time constant t is obtained by the product of the capacitance component Cp and the resistance component R of the wiring and the transistors.

[0041] The adjustment units C1 to C15 are provided in the plurality of delay units 13 of the first digitization unit 10, but not in the plurality of delay units 13 of the second digitization unit 20. That is, the portion indicated by the hatching in FIG. 4 is not provided in the plurality of delay units 13 of the second digitization unit 20, and in the second digitization unit 20, the wiring becomes thinner by the amount that the adjustment units C1 to C15 are not provided.

[0042] Here, FIG. 5 exemplifies the numerical values handled by the first digitization unit 10 and the second digitization unit 20. In FIG. 5, the output values from the count units 16, 26 are represented as ED1, ED2 respectively, and the final outputs from the first digitization unit 10 and the second digitization unit 20 are represented as DTc1, DTc2 respectively.

[0043] When the output value ED from the count units 16, 26 passes through 5 DUs, that is, 5 delay units 13 during one cycle of the clock CKs, the output value ED1 increases by 5 in the order of, for example, 1, 6, 11. After 11, it does not become 16 but becomes 17. This is because a code missing where it increases by 1 bit occurs. On the other hand, the output value ED2 increases by 5 in the order of, for example, 3, 8, 13. After 13, it does not become 18 but becomes 17. This is because a code missing where it decreases by 1 bit occurs.

[0044] That is, as shown in the upper diagram of FIG. 6, the output DTc1 from the first digitization unit 10 may be 1 larger than the correct value C because the number of delay units 13 is 1 less than a power of 2. On the other hand, as shown in the lower diagram of FIG. 6, the output DTc2 from the second digitization unit 20 may be 1 smaller than the correct value C because the number of delay units 13 is 1 more than a power of 2.

[0045] However, since the addition output unit 40 adds and outputs the outputs DTc1, DTc2 from the respective digitization units 10, 20, as shown in FIG. 7, when a 1-bit increase and a 1-bit decrease occur simultaneously, these can be offset. That is, the value increased by 1 bit can be complemented with the 1-bit decreased value, and the correct value 2C can be output.

[0046] However, in reality, when only one set of digitization units 10 and 20 is used, it is not possible to expect that an increase of 1 bit and a decrease of 1 bit occur simultaneously, that is, the overflow timings in the ring-shaped pulse delay circuits 11 and 21 coincide. Therefore, the A / D converter 1 of this embodiment makes the following improvements.

[0047] Here, as shown in FIG. 8A, a configuration including one each of a first digitization unit 10, a second digitization unit 20, and an addition output unit 40 is defined as one basic unit 5. As shown in FIG. 8B, the basic unit 5 is expressed as "TU".

[0048] As shown in FIG. 8C, the A / D converter 1 is configured to include a plurality of basic units 5. FIG. 8C illustrates a configuration in which the A / D converter 1 includes four basic units 5. The A / D converter 1 includes addition units 40A, 40B, and 40C that sequentially add the outputs from the four basic units 5. The output DT3 obtained by adding all the outputs of the four basic units 5 is the output from the A / D converter 1. Note that the output from the A / D converter 1 may be a value obtained by dividing the output DT3 by the number of basic units 5 (for example, 4 in the case of FIG. 8C).

[0049] With such a configuration, as the number of basic units 5 increases, the probability that an overflow occurs simultaneously in any of the digitization units 10 and 20 increases. Therefore, the probability that the A / D converter 1 can complement code missing increases, and the accuracy of the A / D converter 1 can be improved. If the number of basic units 5 is N, it is considered that the accuracy can be improved by √N times.

[0050] [1-2. Effect] According to the embodiment described in detail above, the following effects can be obtained. (1a) One aspect of the present disclosure is an A / D converter 1 configured to output a digital value corresponding to the potential of an analog signal. The A / D converter 1 includes a first digitization unit 10, a second digitization unit 20, and an addition output unit 40.

[0051] The first digitization unit 10 includes a plurality of delay units 13 connected in series, and a first output unit 15 configured to output data corresponding to the number of times the pulse signal has passed through the plurality of delay units 13. The second digitization unit 20 includes a plurality of delay units 13 connected in series by a number greater than the plurality of delay units 13 of the first digitization unit 10, and a second output unit 25 configured to output data corresponding to the number of times the pulse signal has passed through the plurality of delay units 13.

[0052] The addition output unit 40 is configured to output, as a digital value, an addition value obtained by adding a numerical value based on the output by the first digitization unit 10 and a numerical value based on the output by the second digitization unit 20. Each delay unit 13 representing each of the delay units 13 of the first digitization unit 10 and the second digitization unit 20 is configured such that the delay time of the pulse signal passing through each delay unit 13 is changed according to the potential of the analog signal.

[0053] Each delay unit 13 is configured such that the first passing time and the second passing time are different from each other so that the time difference between the first required time and the second required time is smaller than the case where the first passing time and the second passing time are equal.

[0054] According to such a configuration, the time difference until the pulse signal makes one round in each ring-shaped pulse delay circuit 11, 21 can be reduced, so that the frequencies at which overflows occur in each ring-shaped pulse delay circuit 11, 21 can be made as uniform as possible. Therefore, it is possible to provide the A / D converter 1 capable of converting an analog signal into a digital value with high accuracy.

[0055] (1b) In one aspect of the present disclosure, at least a part of the plurality of delay units 13 of the first digitization unit 10 further includes adjustment units C1 to C15 for increasing the first passing time. According to such a configuration, by adding the adjustment units C1 to C15, it is possible to adjust so that the first passing time becomes longer.

[0056] (1c) In one aspect of the present disclosure, the adjustment units C1 to C15 are provided in all of the plurality of delay units 13 of the first digitization unit 10. According to such a configuration, the first passing time can be largely adjusted by adjusting the passing time of the pulse signal in each delay unit 13 of the first digitization unit 10 little by little. Therefore, it is possible to suppress the occurrence of variations in the output from the ring-shaped pulse delay circuit 11 including the delay units 13.

[0057] (1d) In one aspect of the present disclosure, the adjustment units C1 to C15 are configured as wiring capacitances. According to such a configuration, a configuration as the adjustment units C1 to C15 can be realized with a simple configuration.

[0058] Note that the adjustment units C1 to C15 can be configured such that the switching becomes slower as the time constant t in each delay unit 13 increases. Note that the time constant t is obtained by the product of the capacitance component C and the resistance component R.

[0059] (1e) In one aspect of the present disclosure, each delay unit 13 includes only a plurality of inverter circuits (that is, a plurality of INV13) as switching elements. According to such a configuration, since it includes only inverter circuits that occupy a smaller area or volume than gate circuits, the A / D converter 1 can be made more miniaturized.

[0060] (1f) One aspect of the present disclosure is an A / D converter 1, and a configuration including one each of a first digitization unit 10, a second digitization unit 20, and an addition output unit 40 is used as one basic unit 5, and the A / D converter 1 is configured to include a plurality of basic units 5.

[0061] According to such a configuration, it is possible to disperse the timing at which an overflow occurs in each basic unit 5. Therefore, the probability of being able to complement code missing due to an overflow increases, and thus it can be configured as a more accurate A / D converter 1.

[0062] (1g) In one aspect of the present disclosure, each delay unit 13 is configured such that an analog signal is input to the power supply line of each delay unit 13. The first output unit 15 and the second output unit 25 are configured to output the numerical data DTc1 and DTc2 indicating the number of delay units 13 through which the pulse signal has passed within a preset time.

[0063] According to such a configuration, digital values corresponding to the potential of the analog signal can be output as the numerical data DTc1 and DTc2. [2. Other Embodiments] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modifications.

[0064] (2a) In the above embodiment, each delay unit 13 includes only a plurality of inverter circuits as switching elements, but the configuration is not limited thereto. Each digitization unit 10, 20 may include delay units 12, 13 including a gate circuit such as a NAND 12 as shown in the first modification example of FIG. 9, for example. That is, each delay unit 12, 13 may be configured to include at least one of a gate circuit and an inverter circuit. In this case, the pulse signal PA can be input to the gate circuit.

[0065] Note that in circuits used in communication system devices and the like that require high speed, miniaturization has advanced significantly. When there is a requirement for miniaturization, a configuration including only an inverter circuit as a switching element is preferable as in the above embodiment. This is because the gate circuit has a slower operating speed and requires more space for layout compared to the inverter circuit. On the other hand, in devices that handle low frequencies such as biosensors (for example, physical quantity sensors), high speed is not easily required. In such a case, there is no problem in adopting the delay units 12, 13 including a gate circuit.

[0066] (2b) In the above embodiment, the adjustment units C1 to C15 are configured as wiring capacitances, but the configuration is not limited to this. The adjustment unit may be configured as adjustment units R1 to R15 as wiring resistances, for example, as in the second modification example shown in FIG. 10. Even with such a configuration, the time constant t in each of the delay units 12 and 13 can be made satisfactorily large.

[0067] (2c) Alternatively, the adjustment unit may be configured as adjustment units L1 to L15 as wiring inductances, for example, as in the third modification example shown in FIG. 11. Even with such a configuration, since an action of suppressing potential fluctuations occurs at the connection portion of the delay units 12 and 13, it is possible to adjust so that the first passage time becomes large.

[0068] (2d) In the above embodiment, in the ring-shaped pulse delay circuits 11 and 21, the plurality of delay units 13 are configured to be provided only in a number of 2 to the power of n ± 1, but the present invention is not limited to this. For example, in the ring-shaped pulse delay circuits 11 and 21, if the number of delay units 13 in the second digitization unit 20 is larger than the number of delay units 13 in the first digitization unit 10 among the plurality of delay units 13, any number can be adopted.

[0069] (2e) In the ring-shaped pulse delay circuits 11 and 21, the plurality of delay units 13 may be provided only in a number of 2 to the power of n ± (2m - 1). However, n and m are natural numbers, and it is preferable that n ≥ m.

[0070] According to such a configuration, the number of the plurality of delay units 13 provided in the ring-shaped pulse delay circuits 11 and 21 can be made an odd number, and the output can be inverted every time the pulse signal makes one round. Therefore, a configuration for re-inputting the pulse signal is unnecessary. Thus, the A / D converter 1 can be miniaturized.

[0071] (2f) In the above embodiment, a plurality of delay units 13 are connected in series in a ring shape, but the present invention is not limited to this. For example, a plurality of delay units 13 may be arranged linearly, and when a pulse passes through the last delay unit 13, another pulse may be input to the first delay unit 13.

[0072] (2g) In the above embodiment, an example in which the ring-shaped pulse delay circuits 11 and 21 are used for the A / D converter 1 is disclosed, but the present invention is not limited to this. For example, it may be configured as a digitizing device that outputs preset analog information such as time, temperature, and stress as digital values.

[0073] Regarding time, if VIN, VBB, and GND are kept constant and CKs are input at the measurement start time and the measurement end time, a value representing the difference between these times can be obtained as a digital value. Regarding temperature and stress, it is advisable to record in advance the digital values obtained when VIN, VBB, and GND are kept constant and the interval at which CKs are input is kept constant for each temperature and stress. Then, when actually measuring temperature and stress, it is only necessary to check which temperature or stress the obtained digital value corresponds to.

[0074] (2h) A plurality of functions of one component in the above embodiment may be realized by a plurality of components, or one function of one component may be realized by a plurality of components. Also, a plurality of functions of a plurality of components may be realized by one component, or one function realized by a plurality of components may be realized by one component. Also, a part of the configuration of the above embodiment may be omitted. Also, at least a part of the configuration of the above embodiment may be added to or replaced with the configuration of another above embodiment.

[0075] (2i) In addition to the A / D converter 1 described above, the present disclosure can also be realized in various forms such as a system including the A / D converter 1 as a component and an A / D conversion method.

Explanation of Reference Numerals

[0076] 1…A / D converter, 5…basic unit, 10…first digitization unit, 11, 21…ring-shaped pulse delay circuits, 12, 13…delay units, 15…first output unit, 16, 26…counting units, 17, 27…latches, 18, 28…adders, 20…second digitization unit, 25…second output unit, 40…addition output unit, 40A to 40C…addition units, C1 to C15, R1 to R15, L1 to 15…adjustment units.

Claims

1. An A / D converter (1) configured to output a digital value corresponding to the potential of an analog signal, comprising: a plurality of first delay units (11:12, 13) connected in series, and a first output unit (15) configured to output data corresponding to the number of times the pulse signal has passed through the plurality of first delay units, a first digitizing unit (10) including the above; a plurality of second delay units (21:12, 13) connected in series by a number greater than the plurality of first delay units, and a second output unit (25) configured to output data corresponding to the number of times the pulse signal has passed through the plurality of second delay units, a second digitizing unit (20) including the above; an addition output unit (40) configured to output, as the digital value, an addition value obtained by adding a numerical value based on the output by the first digitizing unit and a numerical value based on the output by the second digitizing unit; and comprising each of the delay units representing each of the plurality of first delay units and the plurality of second delay units is configured such that the delay time of the pulse signal passing through each delay unit is changed according to the potential of the analog signal, defining the time for the pulse signal to make one round through the plurality of first delay units as the first required time, the time for the pulse signal to make one round through the plurality of second delay units as the second required time, the average time required for the pulse signal to pass through one of the plurality of first delay units as the first passing time, and the average time required for the pulse signal to pass through one of the plurality of second delay units as the second passing time, each of the delay units is configured such that the first passing time and the second passing time are different so that the time difference between the first required time and the second required time is smaller compared to the case where the first passing time and the second passing time are equal. An A / D converter configured as above.

2. The A / D converter according to claim 1, further comprising: at least a part of the plurality of first delay units includes an adjustment unit (C1 to C15, R1 to R15, L1 to L15) for increasing the first passing time. An A / D converter further including the above.

3. The A / D converter according to claim 2, wherein the adjustment unit is provided in all of the plurality of first delay units. An A / D converter.

4. The A / D converter according to claim 2 or claim 3, wherein the adjustment unit is configured as wiring capacitance. An A / D converter.

5. An A / D converter according to any one of claims 2 to 4, wherein the adjustment unit is configured as a wiring resistance or a wiring inductance A / D converter.

6. An A / D converter according to any one of claims 1 to 5, wherein each of the delay units is constituted by at least one of a gate circuit and an inverter circuit A / D converter.

7. An A / D converter according to claim 6, wherein each of the delay units includes only a plurality of inverter circuits as switching elements A / D converter.

8. An A / D converter according to any one of claims 1 to 7, wherein one set of the first digitizing unit, the second digitizing unit, and the addition output unit is used as one basic unit, and the A / D converter includes a plurality of the basic units A / D converter configured as such.

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