Ceramic electronic components and circuit boards

Abstract

To provide a ceramic electronic component that is less likely to cause mounting failures.SOLUTION: A ceramic electronic component comprises: a ceramic element body that has first and second principal surfaces perpendicular to a first axis and first and second end surfaces perpendicular to a second axis orthogonal to the first axis; and first and second external electrodes that cover the first and second end surfaces, extending on the principal surfaces from the first and second end surfaces, respectively. Each of the first and second external electrodes is configured by: a first or second surface layer part consisting of a Sn plated layer; and a first or second inner layer part including a Ni plated layer adjacent to the Sn plated layer, having a first or second rounded inner end part on the principal surfaces. In a cross section perpendicular to a third axis at the center in a third axial direction orthogonal to the first and second axes, a ratio t2 / t1 of a thickness t2 in the first axial direction of a portion where inclinations of tangent lines of outer surfaces at the first and second inner end parts to the principal surfaces are 45°, to the maximum thickness t1 in the first axial direction of the first and second inner layer parts on the principal surfaces, is 0.4 or more.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a ceramic electronic component and a circuit board having a pair of external electrodes.

Background Art

[0002] A multilayer ceramic capacitor includes a ceramic body including a plurality of stacked internal electrodes, and a pair of external electrodes covering ends of the ceramic body. The multilayer ceramic capacitor is mounted by soldering the pair of external electrodes to a pair of terminals of a mounting substrate, respectively. For example, a reflow method is used for mounting the multilayer ceramic capacitor.

[0003] When mounting a multilayer ceramic capacitor, the solder may spread first on one of the pair of external electrodes, and the multilayer ceramic capacitor may stand up due to the surface tension of the solder acting on the one external electrode (see, for example, paragraph 0008 and FIG. 3 of Patent Document 1). This phenomenon is called the two-tone phenomenon.

[0004] On the other hand, in the multilayer ceramic capacitor described in Patent Document 1, the occurrence of the two-tone phenomenon during mounting is suppressed by making the end face of the external electrode less likely to bulge outward. Specifically, in this multilayer ceramic capacitor, by making the end face of the ceramic body a concave surface, the end face of the external electrode is likely to become flat.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In recent years, due to the shortage of mounting space associated with the high density and high integration of electronic circuits, there has been an increasing demand for passive components to be miniaturized and made thinner. In multilayer ceramic capacitors, the progress of weight reduction accompanying miniaturization and thinning makes it easier for the tombstone phenomenon to occur during mounting, so there is a need for a technology that can further suppress the occurrence of mounting defects.

[0007] In view of the above circumstances, an object of the present invention is to provide a ceramic electronic component and a circuit board in which mounting defects are less likely to occur.

Means for Solving the Problems

[0008] To achieve the above object, a ceramic electronic component according to one embodiment of the present invention includes a ceramic element body having first and second main surfaces perpendicular to a first axis, and first and second end surfaces perpendicular to a second axis orthogonal to the first axis, a first external electrode covering the first end surface and extending from the first end surface onto the main surface, and a second external electrode covering the second end surface and extending from the second end surface onto the main surface. The first and second external electrodes each include first and second surface layer portions made of an Sn plating layer and a Ni plating layer adjacent to the Sn plating layer, and first and second inner layer portions having first and second inner end portions rounded on the main surface. In a cross-section perpendicular to the third axis at the center in the third axis direction orthogonal to the first and second axes, the ratio t2 / t1 of the thickness t2 in the first axis direction of the portion where the inclination of the tangent line of the outer surface at the first and second inner end portions with respect to the main surface is 45° to the maximum thickness t1 in the first axis direction of the first and second inner layer portions on the main surface is 0.4 or more.

[0009] The present invention is based on the new finding that in a ceramic electronic component in which the inclination of the outer surface of the Ni plating layer is steep at the inner end portion of the inner layer portion of the external electrode, the tombstone phenomenon is less likely to occur during mounting. In the above configuration, by setting the ratio t2 / t1 of the thicknesses t1 and t2 to 0.4 or more, a configuration capable of sufficiently suppressing the occurrence of the tombstone phenomenon during mounting in the ceramic electronic component can be obtained.

[0010] The above ceramic electronic component may have a size of 0.4 ± 0.05 mm × 0.2 ± 0.05 mm × 0.2 ± 0.05 mm or less. The ratio t2 / W of the above thickness t2 (μm) to the weight W (mg) of the above ceramic electronic component may be 35 or more. The above first and second inner layer portions may further include a Cu base layer adjacent to the inside of the above Ni plating layer. The above first and second inner layer portions may further include a Cu plating layer adjacent to the inside of the above Ni plating layer and a Ni base layer adjacent to the inside of the above Cu plating layer. The ratio t2 / t1 may be 0.57 or less.

[0011] A circuit board according to one embodiment of the present invention includes a ceramic electronic component and a mounting board. The above ceramic electronic component includes a ceramic body having first and second main surfaces perpendicular to a first axis and first and second end surfaces perpendicular to a second axis orthogonal to the first axis, a first external electrode covering the first end surface and extending from the first end surface onto the main surface, and a second external electrode covering the second end surface and extending from the second end surface onto the main surface. The above mounting board has a board body, a first terminal provided on the board body and soldered with the first external electrode, and a second terminal provided on the board body and soldered with the second external electrode. The above first and second external electrodes each include a Ni plating layer in contact with solder on the first terminal and the second terminal, and have first and second inner layer portions having first and second inner end portions rounded on the main surface. In a cross-section perpendicular to the third axis at the center in the third axis direction orthogonal to the above first and second axes, the ratio t2 / t1 of the thickness t2 in the first axis direction of a portion where the inclination of the tangent line of the outer surface at the above first and second inner end portions with respect to the main surface is 45° to the maximum thickness t1 in the first axis direction of the above first and second inner layer portions on the main surface is 0.4 or more.

Advantages of the Invention

[0012] According to the present invention, it is possible to provide a ceramic electronic component and a circuit board in which mounting defects are less likely to occur.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings show an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other. The X-axis, Y-axis, and Z-axis are common throughout the figures.

[0015] [Overall Configuration of Multilayer Ceramic Capacitor 10] FIGS. 1 to 3 are diagrams showing a multilayer ceramic capacitor 10 according to an embodiment of the present invention. FIG. 1 is a perspective view of the multilayer ceramic capacitor 10. FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 and passing through the center in the Y-axis direction of the multilayer ceramic capacitor 10. FIG. 3 is a cross-sectional view taken along line B-B' of FIG. 1 and passing through the center in the X-axis direction of the multilayer ceramic capacitor 10.

[0016] The multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The ceramic body 11 is configured as the main body of the multilayer ceramic capacitor 10. The external electrodes 14 and 15 constitute a pair of terminals for receiving electrical connection in the multilayer ceramic capacitor 10.

[0017] The ceramic body 11 is configured as a hexahedron having an outer surface including first and second end faces E1 and E2 perpendicular to the X axis, first and second side faces S1 and S2 perpendicular to the Y axis, and first and second main faces M1 and M2 perpendicular to the Z axis. The end faces E1 and E2, the side faces S1 and S2, and the main faces M1 and M2 of the ceramic body 11 are all configured as flat surfaces.

[0018] The flat surface according to this embodiment does not have to be a strictly flat surface as long as it is recognized as flat when viewed as a whole. For example, it also includes a surface having minute uneven shapes on the surface or a gentle curved shape existing in a predetermined range. The end faces E1 and E2, the side faces S1 and S2, and the main faces M1 and M2 only have to be perpendicular to the X axis, the Y axis, and the Z axis in a part thereof, respectively.

[0019] The first and second external electrodes 14 and 15 cover the first and second end faces E1 and E2 of the ceramic body 11 and face each other in the X-axis direction with the ceramic body 11 interposed therebetween. The external electrodes 14 and 15 extend from the respective end faces E1 and E2 of the ceramic body 11 to the main faces M1 and M2 and the side faces S1 and S2 and are spaced apart in the X-axis direction on the main faces M1 and M2 and the side faces S1 and S2.

[0020] The ceramic body 11 is formed of a dielectric ceramic. The ceramic body 11 has a plurality of first internal electrodes 12 and second internal electrodes 13 covered with the dielectric ceramic. The plurality of internal electrodes 12 and 13 are both in the form of sheets extending along the X-Y plane and are alternately arranged along the Z-axis direction.

[0021] That is, in the ceramic body 11, an opposing region is formed in which the internal electrodes 12 and 13 oppose each other in the Z-axis direction with a ceramic layer interposed therebetween. The first internal electrode 12 is drawn out from the opposing region to the first end face E1 and connected to the first external electrode 14. The second internal electrode 13 is drawn out from the opposing region to the second end face E2 and connected to the second external electrode 15.

[0022] With such a configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a voltage is applied to a plurality of ceramic layers in the opposing region of the internal electrodes 12 and 13. As a result, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored.

[0023] In the ceramic body 11, a dielectric ceramic with a high dielectric constant is used in order to increase the capacitance of each ceramic layer between the internal electrodes 12 and 13. Examples of the dielectric ceramic with a high dielectric constant include materials having a perovskite structure containing barium (Ba) and titanium (Ti), typified by barium titanate (BaTiO3).

[0024] Note that the dielectric ceramic may be a composition system such as strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and barium calcium zirconate titanate (Ba 1-x-y Ca x Ti 1-z Zr z O3).

[0025] The first external electrode 14 is composed of a first inner layer portion 14a and a first surface layer portion 14b. The first inner layer portion 14a is provided adjacent to the ceramic element body 11 and constitutes the inner portion of the first external electrode 14 covered by the first surface layer portion 14b. The first surface layer portion 14b is provided outside the first inner layer portion 14a and constitutes the outermost layer of the first external electrode 14.

[0026] The second external electrode 15 is composed of a second inner layer portion 15a and a second surface layer portion 15b. The second inner layer portion 15a is provided adjacent to the ceramic element body 11 and constitutes the inner portion of the second external electrode 15 covered by the second surface layer portion 15b. The second surface layer portion 15b is provided outside the second inner layer portion 15a and constitutes the outermost layer of the second external electrode 15.

[0027] The first inner layer portion 14a is composed of a first base layer 14a1 and a first intermediate layer 14a2. The second inner layer portion 15a is composed of a second base layer 15a1 and a second intermediate layer 15a2. The base layers 14a1, 15a1 are configured as sintered films of conductors, and the intermediate layers 14a2, 15a2 are configured as plated films of conductors.

[0028] More specifically, the base layers 14a1, 15a1 are configured as Cu base layers which are sintered films mainly composed of copper (Cu) or a Cu alloy. The intermediate layers 14a2, 15a2 are configured as Ni plating layers mainly composed of nickel (Ni) or a Ni alloy. In this embodiment, the main component refers to the component with the highest content ratio.

[0029] The surface layer portions 14b, 15b are configured as Sn plating layers mainly composed of tin (Sn) or an Sn alloy. The Sn plating layers constituting the surface layer portions 14b, 15b melt together with solder during mounting, thereby enhancing the wettability of the solder to the external electrodes 14, 15. Therefore, in the external electrodes 14, 15 after mounting, the intermediate layers 14a2, 15a2 are in a state of directly contacting the solder.

[0030] The underlying layers 14a1 and 15a1 can be formed by baking a conductive paste applied at positions corresponding to the external electrodes 14 and 15 on the outer surface of the ceramic body 11. Further, the intermediate layers 14a2 and 15a2 and the surface layer portions 14b and 15b can each be formed by a wet plating method.

[0031] Note that the configuration of the external electrodes 14 and 15 is not limited to the above, and can be variously changed within the range in which the effects of the present invention can be obtained. For example, the underlying layers 14a1 and 15a1 are not limited to Cu underlying layers, and may be, for example, Ni underlying layers mainly composed of nickel (Ni) or Ni alloys, Ag underlying layers mainly composed of silver (Ag) or Ag alloys, and the like.

[0032] Further, the intermediate layers 14a2 and 15a2 may have a multilayer structure with a Ni plating layer as the outermost layer, and may include, for example, a Cu plating layer mainly composed of copper (Cu) or a Cu alloy adjacent to the inside of the Ni plating layer. When the Cu plating layer is provided in the intermediate layers 14a2 and 15a2 in this way, it is preferable that the underlying layers 14a1 and 15a1 be Ni underlying layers.

[0033] The multilayer ceramic capacitor 10 can effectively suppress the occurrence of mounting defects due to the tombstones phenomenon by the action of the shape of the inner layer portions 14a and 15a. In particular, in the multilayer ceramic capacitor 10, even in a small and lightweight configuration in which the tombstones phenomenon is more likely to occur during mounting, the occurrence of mounting defects can be more effectively prevented.

[0034] Specifically, in the multilayer ceramic capacitor 10, the effect of suppressing the occurrence of mounting defects is more effectively obtained at a size of 0.4 ± 0.05 mm × 0.2 ± 0.05 mm × 0.2 ± 0.05 mm or less. That is, in the multilayer ceramic capacitor 10, it is preferable that the dimension in the X-axis direction is 0.4 mm or less, and the dimensions in the Y-axis and Z-axis directions are 0.2 mm or less.

[0035] The size of the multilayer ceramic capacitor 10 can be, for example, 0.4 ± 0.05 mm × 0.2 ± 0.05 mm × 0.2 ± 0.05 mm, 0.2 ± 0.015 mm × 0.1 ± 0.015 mm × 0.1 ± 0.015 mm, etc. Note that the multilayer ceramic capacitor 10 is not limited to these sizes and can have various sizes according to the application, etc.

[0036] [Inner layer portions 14a, 15a] As shown in FIG. 2, the inner layer portions 14a, 15a of the external electrodes 14, 15 have first and second inner end portions P1, P2 which are end portions facing the inside in the X-axis direction located on the main surfaces M1, M2, respectively. The inner end portions P1, P2 of the inner layer portions 14a, 15a extend along the Y-axis direction on the main surfaces M1, M2 and are covered by the surface layer portions 14b, 15b.

[0037] The inner end portions P1, P2 of the inner layer portions 14a, 15a have a rounded shape and the thickness becomes smaller toward the inside in the X-axis direction. That is, at the inner end portions P1, P2, the outer surfaces of the inner layer portions 14a, 15a which are the surfaces adjacent to the surface layer portions 14b, 15b in the intermediate layers 14a2, 15a2 are inclined so as to approach the main surfaces M1, M2 toward the inside in the X-axis direction.

[0038] FIG. 4 is a partial cross-sectional view showing an enlarged view of the vicinity of the inner end portions P1, P2 in FIG. 2. FIG. 4 shows the first inner end portion P1 on the second main surface M2 of the first inner layer portion 14a, but both the first inner end portion P1 on the first main surface M1 of the first inner layer portion 14a and the second inner end portion P2 on the main surfaces M1, M2 of the second inner layer portion 15a are configured in the same manner as the first inner end portion P1 shown in FIG. 4.

[0039] In FIG. 4, the thickness t1 of the first inner layer portion 14a is shown. The thickness t1 indicates the maximum thickness in the Z-axis direction of the inner layer portions 14a, 15a in the cross-sections shown in FIGS. 2 and 4 on the main surfaces M1, M2. That is, the thickness t1 corresponds to the maximum value of the distance in the Z-axis direction from the main surfaces M1, M2 of the outer surfaces of the inner layer portions 14a, 15a in the cross-sections shown in FIGS. 2 and 4.

[0040] In addition, Fig. 4 shows the thickness t2 of the first inner layer portion 14a. The thickness t2 indicates the Z-axis direction thickness of the portions where the inclination of the tangent line L of the outer surface with respect to the main surfaces M1 and M2 of the inner layer portions 14a and 15a in the cross section shown in Figs. 2 and 4 is 45°, in other words, the portions where the inclination of the normal vector N in the Z-axis direction outward on the outer surface is 45°.

[0041] At the inner ends P1 and P2 of the inner layer portions 14a and 15a, the ratio t2 / t1 of the thickness t2 to the thickness t1 is set to 0.4 or more so that the portions where the inclination of the tangent line L of the outer surface with respect to the main surfaces M1 and M2 is 45° are located on the outer side in the Z-axis direction. Thereby, on the outer surface of the inner ends P1 and P2 of the inner layer portions 14a and 15a, the inclination with respect to the main surfaces M1 and M2 becomes steep.

[0042] That is, by setting the ratio t2 / t1 of the thicknesses t1 and t2 to 0.4 or more, the outer surfaces of the inner ends P1 and P2 of the inner layer portions 14a and 15a rise greatly outward in the Z-axis direction from the connection portions with the main surfaces M1 and M2 toward the outer side in the X-axis direction, and the inner ends P1 and P2 of the inner layer portions 14a and 15a have a shape that protrudes greatly obliquely inward in the X-axis direction toward the outer side in the Z-axis direction.

[0043] The shapes of the inner ends P1 and P2 of the inner layer portions 14a and 15a can be controlled by conditions of the wet plating for forming the intermediate layer portions 14a2 and 15a2, the viscosity of the conductive paste when forming the base layer portions 14a1 and 15a1, and the like. Specifically, in the intermediate layer portions 14a2 and 15a2, by increasing the current density during wet plating, a shape in which the inner ends P1 and P2 protrude greatly is likely to be obtained.

[0044] Fig. 5 is a side view of a circuit board 100 on which the multilayer ceramic capacitor 10 is mounted. The circuit board 100 includes a mounting board 20 having a board body 21, a first terminal 22, and a second terminal 23. The terminals 22 and 23 constitute a pair of terminals of the mounting board 20 and are provided on the mounting surface facing upward in the Z-axis direction on the board body 21.

[0045] In the circuit board 100, the external electrodes 14 and 15 of the multilayer ceramic capacitor 10 are soldered to the terminals 22 and 23 of the mounting board 20, respectively. As a result, in the circuit board 100, the multilayer ceramic capacitor 10 is electrically connected to the mounting board 20 and physically fixed thereto.

[0046] For mounting the multilayer ceramic capacitor 10 on the mounting board 20, a general reflow method can be used. In the reflow method, the solder H is melted and then solidified in the process of passing through a reflow furnace with the external electrodes 14 and 15 of the multilayer ceramic capacitor 10 placed on the terminals 22 and 23 of the mounting board 20 where the solder H is disposed.

[0047] In the multilayer ceramic capacitor 10, in the above process, the Sn plating layers constituting the surface layer portions 14b and 15b are melted together with the solder H. Therefore, in the circuit board 100, the surface layer portions 14b and 15b are removed from the portions of the external electrodes 14 and 15 that come into contact with the solder H, and the outer surfaces of the inner layer portions 14a and 15a are in direct contact with the solder H.

[0048] In the multilayer ceramic capacitor 10, by forming the outer surfaces of the inner end portions P1 and P2 of the inner layer portions 14a and 15a into a shape that protrudes greatly, it is possible to suppress the occurrence of the tombstone phenomenon that rises at one of the terminals 22 and 23 due to the action of the surface tension of the molten solder H. Hereinafter, this effect will be described in detail.

[0049] FIG. 6 is a side view showing the process of mounting the multilayer ceramic capacitor 10' according to the comparative example of the present embodiment. The multilayer ceramic capacitor 10' according to the comparative example is different from the present embodiment in that the ratio t2 / t1 of the thicknesses t1 and t2 is less than 0.4, and the first and second external electrodes 14' and 15' having a gentle inclination at the inner end portions are provided.

[0050] In the multilayer ceramic capacitor 10' shown in FIG. 6, a tombstone phenomenon that rises on the second terminal 23 of the mounting substrate 20 occurs. This tombstone phenomenon is caused by the generation of a moment in the direction indicated by the arrow in FIG. 6 due to the action of the surface tension of the solder H that has spread wetter to the second external electrode 15' prior to the first external electrode 14'.

[0051] In the multilayer ceramic capacitor 10' shown in FIG. 6, due to the occurrence of the tombstone phenomenon, the first external electrode 14' floats up from the first terminal 22 of the mounting substrate 20, resulting in the loss of electrical continuity between the first external electrode 14' and the first terminal 22 of the mounting substrate 20. Therefore, the multilayer ceramic capacitor 10' shown in FIG. 6 becomes a mounting defect.

[0052] Also, in the multilayer ceramic capacitor 10', when the solder H spreads wetter to the first external electrode 14' prior to the second external electrode 15', a tombstone phenomenon that rises on the first terminal 22 of the mounting substrate 20 also occurs. Thus, in the multilayer ceramic capacitor 10' according to the comparative example, mounting defects due to the tombstone phenomenon are likely to occur.

[0053] On the other hand, in the multilayer ceramic capacitor 10 according to the present embodiment, the surface tension of the solder H acts to prevent it from rising on the terminals 22 and 23 of the mounting substrate 20 with respect to the outer surfaces of the inner ends P1 and P2 of the inner layer portions 14a and 15a that protrude significantly. Thereby, in the multilayer ceramic capacitor 10, the occurrence of the tombstone phenomenon can be suppressed.

[0054] That is, in the first external electrode 14, the surface tension of the solder H acts in a direction opposite to the force that attempts to make the multilayer ceramic capacitor 10 rise on the first terminal 22 with respect to the outer surface of the first inner end P1 of the first inner layer portion 14a. Thereby, it becomes difficult for the multilayer ceramic capacitor 10 to rise on the first terminal 22.

[0055] Further, in the second external electrode 15, the surface tension of the solder H acts in a direction opposite to the force that attempts to raise the multilayer ceramic capacitor 10 on the second terminal 23 with respect to the outer surface of the second inner end portion P2 of the second inner layer portion 15a. As a result, it becomes difficult for the multilayer ceramic capacitor 10 to rise on the second terminal 23.

[0056] Therefore, in the multilayer ceramic capacitor 10, even when the solder H wets and spreads ahead of either one of the external electrodes 14 and 15, the tombstones phenomenon is less likely to occur, and it is easily maintained in a normal posture on the mounting substrate 20 during the mounting process. Therefore, in the multilayer ceramic capacitor 10, the occurrence of mounting defects can be suppressed.

[0057] Also, in the inner layer portions 14a and 15a of the external electrodes 14 and 15, regardless of the magnitude of the thickness t1, it is preferable that the thickness t2 is 3.5 μm or more. Thereby, in the multilayer ceramic capacitor 10, it becomes possible to more reliably receive the action of preventing it from rising on the terminals 22 and 23 of the mounting substrate 20 due to the surface tension of the solder H.

[0058] Furthermore, in the inner layer portions 14a and 15a, it is preferable to ensure the thickness t2 (μm) corresponding to the weight W (mg) of the multilayer ceramic capacitor 10. Specifically, it is preferable that the ratio t2 / W of the thickness t2 (μm) to the weight W (mg) is 35 or more. Thereby, in the multilayer ceramic capacitor 10, it becomes possible to more reliably receive the above effects.

[0059] In addition, in the multilayer ceramic capacitor 10, when the outer surfaces of the inner end portions P1 and P2 of the inner layer portions 14a and 15a wrap outward in the X-axis direction at the connection portions with respect to the main surfaces M1 and M2 and form a wedge-shaped space between the main surfaces M1 and M2, it becomes difficult for the solder to enter this wedge-shaped space during mounting. As a result, solder voids are likely to occur.

[0060] Therefore, in the cross sections shown in FIGS. 2 and 4, it is preferable that the inclination of the tangent line of the connecting portion with respect to the main surfaces M1 and M2 on the outer surfaces of the inner end portions P1 and P2 of the inner layer portions 14a and 15a is 90° or less. That is, it is preferable that the normal vector N of the connecting portion with respect to the main surfaces M1 and M2 on the outer surfaces of the inner end portions P1 and P2 of the inner layer portions 14a and 15a does not face inward in the Z-axis direction.

[0061] [Examples and Comparative Examples] As Examples 1 to 20 and Comparative Examples 1 to 19 of the above-described embodiment, samples of multilayer ceramic capacitors were produced such that the thicknesses t1 and t2 and the weight W had variously different configurations. In Examples 1 to 10 and Comparative Examples 1 to 18, the size of the sample was the 0402 size (0.4 ± 0.05 mm × 0.2 ± 0.05 mm × 0.2 ± 0.05 mm). In Examples 11 to 20 and Comparative Example 19, the size of the sample was the 0201 size (0.2 ± 0.015 mm × 0.1 ± 0.015 mm × 0.1 ± 0.015 mm). In the case of the 0402-size sample, the dimension in the X-axis direction of the ceramic element 11 was 0.365 mm, and the dimension in the Z-axis direction of the ceramic element 11 was 0.185 mm. In the case of the 0201-size sample, the dimension in the X-axis direction of the ceramic element 11 was 0.185 mm, and the dimension in the Z-axis direction of the ceramic element 11 was 0.080 mm. Further, the dimension D in the X-axis direction of the inner layer portions 14a and 15a shown in FIGS. 2 and 4 in the external electrodes 14 and 15 was 95 μm in the 0402-size sample and 70 μm in the 0201-size sample.

[0062] Also, for each sample, by mounting it on the mounting substrate 20 using the reflow method, the presence or absence of mounting defects was evaluated. Regarding the configurations of each of the examples and comparative examples, 1000 samples were evaluated for each. A configuration in which no mounting defect sample occurred was regarded as qualified, and a configuration in which one or more mounting defect samples occurred was regarded as unqualified. Note that the thicknesses t1, t2, and the weight W in each configuration of Examples 1 to 20 and Comparative Examples 1 to 19 were taken as the average values of the values obtained by extracting and measuring 10 samples for each configuration. The results for Examples 1 to 10 and Comparative Examples 1 to 18 where the sample is of 0402 size are shown in Table 1, and the results for Examples 11 to 20 and Comparative Example 19 where the sample is of 0201 size are shown in Table 2.

[0063]

Table 1

[0064]

Table 2

[0065] As shown in Tables 1 and 2, in all of Examples 1 to 20 where the ratio t2 / t1 of the thicknesses t1 and t2 is 0.4 or more, no mounting defect sample occurred, and it was evaluated as qualified. Note that the maximum value of the ratio t2 / t1 in Examples 1 to 20 was 0.57. On the other hand, in all of Comparative Examples 1 to 19 where the ratio t2 / t1 of the thicknesses t1 and t2 is less than 0.4, mounting defect samples mainly due to the two-moonstone phenomenon occurred, and it was evaluated as unqualified.

[0066] [Other Embodiments] As described above, the embodiments of the present invention have been explained, but the present invention is not limited only to the above-described embodiments, and it goes without saying that various modifications can be made.

[0067] For example, in the multilayer ceramic capacitor 10, it is not essential to configure the inner end portions P1 and P2 of the inner layer portions 14a and 15a as described above on both sides of the main surfaces M1 and M2. For example, at the inner end portions P1 and P2 of the inner layer portions 14a and 15a, the above configuration may not be adopted for the sides of the main surfaces M1 and M2 that are not opposed to the mounting substrate 20 during mounting.

[0068] Further, the base layers 14a1 and 15a1 of the external electrodes 14 and 15 do not have to be sintered films, and for example, may be sputtered films formed by sputtering. Also in this case, in the multilayer ceramic capacitor 10, by forming the outer surfaces of the intermediate layers 14a2 and 15a2 into the above shape, an effect of suppressing the occurrence of the two-tone phenomenon can be obtained.

[0069] Furthermore, the present invention is applicable not only to multilayer ceramic capacitors but also to all ceramic electronic components having a configuration including a pair of external electrodes. Examples of the ceramic electronic components to which the present invention is applicable include chip varistors, chip thermistors, multilayer inductors, etc., in addition to multilayer ceramic capacitors.

Explanation of Reference Numerals

[0070] 10... Multilayer ceramic capacitor 11... Ceramic body 12, 13... Internal electrodes 14, 15... External electrodes 14a, 15a... Inner layer portions 14a1, 15a1... Base layers 14a2, 15a2... Intermediate layers 14b, 15b... Surface layer portions P1, P2... Inner end portions E1, E2... End faces S1, S2... Side faces M1, M2... Main surfaces

Claims

1. A ceramic element body having first and second main surfaces perpendicular to a first axis, and first and second end surfaces perpendicular to a second axis orthogonal to the first axis, a first external electrode covering the first end surface and extending from the first end surface onto the main surface, and a second external electrode covering the second end surface and extending from the second end surface onto the main surface. The first and second external electrodes each include first and second surface layer portions made of Sn plating layers, Ni plating layers adjacent to the Sn plating layers, and first and second inner layer portions having first and second inner end portions rounded on the main surface. In a cross-section perpendicular to a third axis at the center in the third axis direction orthogonal to the first and second axes, the ratio t2 / t1 of the thickness t2 in the first axis direction of a portion where the inclination of the tangent to the outer surface at the first and second inner end portions with respect to the main surface is 45° to the maximum thickness t1 in the first axis direction of the first and second inner layer portions on the main surface is 0.4 or more. A ceramic electronic component.

2. The ceramic electronic component according to Claim 1, wherein the thickness t2 is 3.5 μm or more. A ceramic electronic component.

3. The ceramic electronic component according to Claim 1 or 2, wherein the ceramic electronic component has a size of 0.4 ± 0.05 mm × 0.2 ± 0.05 mm × 0.2 ± 0.05 mm or less. A ceramic electronic component.

4. The ceramic electronic component according to any one of Claims 1 to 3, wherein the ratio t2 / W of the thickness t2 (μm) to the weight W (mg) of the ceramic electronic component is 35 or more. A ceramic electronic component.

5. The ceramic electronic component according to any one of Claims 1 to 4, wherein the first and second inner layer portions further include a Cu underlayer adjacent to the inside of the Ni plating layer. A ceramic electronic component.

6. The ceramic electronic component according to any one of Claims 1 to 4, wherein the first and second inner layer portions further include a Cu plating layer adjacent to the inside of the Ni plating layer and a Ni underlayer adjacent to the inside of the Cu plating layer. A ceramic electronic component.

7. The ceramic electronic component according to any one of Claims 1 to 6, wherein the ratio t2 / t1 is 0.57 or less. A ceramic electronic component.

8. A ceramic electronic component and a mounting substrate. The ceramic electronic component includes a ceramic body having first and second main surfaces perpendicular to a first axis, and first and second end surfaces perpendicular to a second axis orthogonal to the first axis, a first external electrode covering the first end surface and extending from the first end surface onto the main surface, and a second external electrode covering the second end surface and extending from the second end surface onto the main surface. The mounting substrate has a substrate body, a first terminal provided on the substrate body and soldered to the first external electrode, and a second terminal provided on the substrate body and soldered to the second external electrode. The first and second external electrodes each include a Ni plating layer that contacts solder on the first and second terminals, and first and second inner layer portions having first and second inner end portions rounded on the main surface. In a cross section perpendicular to the third axis at the center in the third axis direction orthogonal to the first and second axes, the ratio t2 / t1 of the thickness t2 in the first axis direction of a portion where the inclination of the tangent to the outer surface at the first and second inner end portions with respect to the main surface is 45° to the maximum thickness t1 in the first axis direction of the first and second inner layer portions on the main surface is 0.4 or more. Circuit board.

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