Memory device

Abstract

To provide a memory device with a more suitable structure.SOLUTION: A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in the vertical direction. The first vertical transistor is electrically connected to the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly to a memory device including vertical transistors.

Background Art

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the form factor size of the memory cell approaches the lower limit, planar processes and manufacturing technologies become difficult and costly. As a result, the memory density of planar memory cells approaches the upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals between the memory arrays. As the dimensions of the memory device become smaller and the memory cell density becomes higher, the interconnection structure between the memory array and the peripheral devices becomes more complex, affecting the related circuit design and / or the related manufacturing process.

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device with a more suitable structure.

Means for Solving the Problems

[0005] The memory device is a memory device, comprising a semiconductor substrate, a first memory array including at least one first word line structure, at least one first vertical transistor, at least a part of the at least one first vertical transistor being disposed within the semiconductor substrate, and a word line contact structure disposed between the at least one first vertical transistor and the at least one first word line structure. The first memory array and the semiconductor substrate are joined together, and the at least one first word line structure is connected to the at least one first vertical transistor via the word line contact structure.

Brief Description of the Drawings

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and are further useful for enabling those skilled in the art to make and use the present disclosure.

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Mode for Carrying Out the Invention

[0007] [Summary of the Disclosure] In the present disclosure, a memory device is provided. In the memory device, a vertical transistor disposed in a substrate is electrically connected to a word line structure of a memory array disposed on another substrate. The area occupied by the vertical transistor on the substrate can be reduced, and accordingly, the connection structure between the vertical transistor and the word line structure can be simplified.

[0008] According to an embodiment of the present disclosure, a memory device is provided. The memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in the vertical direction. The first vertical transistor is electrically connected to the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.

[0009] In some embodiments, the at least one first vertical transistor includes a first semiconductor channel that vertically penetrates the second substrate.

[0010] In some embodiments, the at least one first vertical transistor is disposed in the second substrate and further includes a first gate electrode that horizontally surrounds the first semiconductor channel.

[0011] In some embodiments, the at least one first vertical transistor is disposed in the second substrate and further includes a first gate dielectric layer disposed between the first gate electrode and the first semiconductor channel.

[0012] In some embodiments, the first memory array includes a plurality of at least one first word line structure, and the memory device includes a plurality of at least one first vertical transistor electrically connected to the plurality of at least one first word line structure respectively.

[0013] In some embodiments, the first gate electrodes of the plurality of at least one first vertical transistor are physically and electrically connected to each other within the second substrate.

[0014] In some embodiments, the second substrate includes a semiconductor region, and the first gate electrode includes a doped region disposed within the second substrate.

[0015] In some embodiments, the memory device further includes a separation structure disposed within the second substrate, and the separation structure is disposed between the semiconductor region and the first gate electrode.

[0016] In some embodiments, the memory device further includes a word line contact structure disposed between at least one first vertical transistor and at least one first word line structure, and at least one first word line structure is electrically connected to at least one first vertical transistor via the word line contact structure.

[0017] In some embodiments, at least one first vertical transistor completely covers the word line contact structure in the vertical direction.

[0018] In some embodiments, the second substrate has a first surface and a second surface vertically opposite to the first surface, and the first memory array and the word line contact structure are disposed on the first surface of the second substrate.

[0019] In some embodiments, the memory device further includes conductive lines and connection structures. The conductive lines are disposed on a second surface of the second substrate, and the connection structures are disposed on the second surface of the second substrate and are disposed between the conductive lines and at least one first vertical transistor. The conductive lines are electrically connected to at least one first word line structure via the connection structures, at least one first vertical transistor, and a word line contact structure.

[0020] In some embodiments, the memory device further includes a third substrate, a second memory array, and at least one second vertical transistor. The first memory array is disposed between the first substrate and the third substrate in a vertical direction. The second memory array includes at least one second word line structure. At least one second vertical transistor is electrically connected to at least one second word line structure.

[0021] In some embodiments, the second memory array is disposed on the third substrate, and at least a portion of at least one second vertical transistor is disposed within the second substrate.

[0022] In some embodiments, at least one second vertical transistor includes a second semiconductor channel and a second gate electrode. The second semiconductor channel penetrates the second substrate in a vertical direction. The second gate electrode is disposed within the second substrate and surrounds the second semiconductor channel in a horizontal direction.

[0023] In some embodiments, at least one first vertical transistor includes a first gate electrode disposed within the second substrate, and the first gate electrode is physically and electrically connected to the second gate electrode.

[0024] In some embodiments, at least one first vertical transistor includes a first gate electrode disposed within the second substrate, and the first gate electrode is electrically separated from the second gate electrode.

[0025] In some embodiments, the third substrate is disposed between the first substrate and the second substrate in the vertical direction, and the second memory array is disposed between the second substrate and the third substrate in the vertical direction.

[0026] In some embodiments, the second substrate is disposed between the first substrate and the third substrate in the vertical direction, and the second memory array is disposed between the second substrate and the third substrate in the vertical direction.

[0027] In some embodiments, the second memory array is disposed on the second substrate, and at least a part of at least one second vertical transistor is disposed in the third substrate.

[0028] Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, claims, and drawings of the present disclosure.

[0029] These and other objects of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments shown in the various figures and drawings.

[0030] [Embodiments] Although specific configurations and arrangements will be described, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in various other applications.

[0031] References to "one embodiment", "an embodiment", "some embodiments", etc. in this specification indicate that the described embodiments may include a particular feature, structure, or characteristic, but it should be noted that not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in relation to an embodiment, achieving such a feature, structure, or characteristic in relation to other embodiments, whether or not explicitly described, is within the knowledge of those skilled in the art.

[0032] Generally, terms may be understood, at least in part, from their use in context. For example, the term "one or more" as used herein may be used, at least in part depending on the context, to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a", "an", or "the" may be understood, at least in part depending on the context, to convey a singular or plural usage. Further, the term "based on" may be understood not to necessarily convey an exclusive set of factors, and instead, may also, at least in part depending on the context, allow for the presence of additional factors that are not necessarily explicitly described.

[0033] Terms such as "first", "second", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, but it should be understood that these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or part from another. Thus, a first element, component, region, layer, or part described below could be termed a second element, component, region, layer, or part without departing from the teachings of the present disclosure.

[0034] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be construed most broadly such that "on" means not only "directly on" something, but also "on" something having intervening features or layers therebetween, and "above" or "over" means not only "above" or "over" something, but also can include the meaning of "above" or "over" something without intervening features or layers therebetween (i.e., directly above something).

[0035] Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein for ease of description to explain the relationship of one element or feature to another as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0036] The term "forming" or the term "disposing" is used hereinafter to describe the act of applying a layer of material to an object. Such terms are intended to describe any possible layer formation technique including, but not limited to, thermal growth, sputtering, vapor deposition, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0037] Refer to FIG. 1. FIG. 1 is a schematic diagram showing a memory device according to an embodiment of the present disclosure. As shown in FIG. 1, in the memory device, the NAND memory array 920 may be disposed on the substrate 910, and the planar transistor 950 configured to be electrically connected to the NAND memory array 920 may be disposed on another substrate 940. The NAND memory array 920 can include an alternating conductive / dielectric stack composed of dielectric layers 922 and conductive layers 924 alternately stacked in the vertical direction (such as the first direction D1 shown in FIG. 1), and each of the conductive layers 924 may be regarded as a word line in the NAND memory array 920. The alternating conductive / dielectric stack may have a stepped portion that exposes a part of each word line, and each word line may be electrically connected to a corresponding driving unit accordingly. For example, each of the planar transistors 950 may be electrically connected to one of the word lines via a wiring structure 930 for controlling the signal transmitted to the word line, and the planar transistor 950 may be regarded as the driving unit described above, but is not limited thereto. However, each of the planar transistors 950 occupies a specific area on the substrate 940, and most of the planar transistors 950 cannot be accurately positioned corresponding to the exposed portions of the word lines in the first direction D1, and accordingly the wiring structure 930 has to be complicated. Further, the layer of the word lines is limited to a specific range due to the total area occupied by the planar transistors 950 on the substrate 940, and the storage capacity of the memory device is limited accordingly.

[0038] Please refer to FIG. 2. FIG. 2 is a schematic diagram showing a memory device 301 according to a first embodiment of the present disclosure. As shown in FIG. 2, the memory device 301 includes a first substrate 100, a first memory array 110, a second substrate 150, and at least one first vertical transistor T1. The first memory array 110 is disposed on the first substrate 100. The first memory array 110 includes at least one first word line structure 114. The first memory array 110 is disposed between the first substrate 100 and the second substrate 150 in the vertical direction (for example, the first direction D1 shown in FIG. 2). The first vertical transistor T1 is electrically connected to the first word line structure 114. At least a part of the first vertical transistor T1 is disposed on the second substrate 150. The area occupied by the first vertical transistor T1 on the second substrate 150 may be relatively smaller than the area occupied by the planar transistor described above, which is beneficial in solving the related problems described above.

[0039] In some embodiments, the first memory array 110 can include a plurality of first word line structures 114, and the memory device 301 can correspondingly include a plurality of first vertical transistors T1, but is not limited thereto. The first vertical transistor T1 may be electrically connected to the first word line structure 114 respectively. In other words, each of the first word line structures 114 may be electrically connected to one of the first vertical transistors T1 in the second substrate 150. In some embodiments, the first memory array 110 can include an alternating conductive / dielectric stack composed of the first dielectric layer 112 and the first word line structure 114 alternately stacked in the first direction D1. The first memory array 110 can have a first stepped portion P1 for exposing a part of each of the first word line structures 114 at an end in the horizontal direction (such as the second direction D2 shown in FIG. 2) of the first memory array 110, but is not limited thereto. The first direction D1 may be regarded as the thickness direction of the first substrate 100, and / or the first direction D1 may be parallel to the normal direction of the surface of the first substrate 100, and the horizontal direction may be parallel to the surface of the first substrate 100, but is not limited thereto. In some embodiments, the memory device 301 can further include a plurality of first word line contact structures 122. Each of the first word line contact structures 122 may be disposed between one of the first vertical transistors T1 and one of the first word line structures 114 in the first direction D1 to electrically connect the first vertical transistor T1 and the first word line structure 114. In other words, each of the first word line structures 114 may be electrically connected to one of the first vertical transistors T1 through one of the first word line contact structures 122.

[0040] In some embodiments, since the area occupied by the first vertical transistor T1 on the second substrate 150 is relatively small, each of the first vertical transistors T1 may be arranged corresponding to the exposed portion of the corresponding first word line structure 114 in the first direction D1, and the connection structure between the first word line structure 114 and the first vertical transistor T1 may be simplified accordingly. For example, in some embodiments, each of the first word line contact structures 122 may be a pillar structure elongated in the first direction D1, and one end of each of the first word line contact structures 122 in the first direction D1 (such as the lower end of the first word line contact structure 122) may be in direct contact with the exposed portion of the corresponding first word line structure 114, and the other end of the first word line contact structure 122 in the first direction D1 (such as the upper end of the first word line contact structure 122) may be in direct contact with the corresponding first vertical transistor T1, but not limited thereto. In some embodiments, each of the first vertical transistors T1 may be able to completely cover the corresponding first word line contact structure 122 in the first direction D1, but not limited thereto.

[0041] In some embodiments, each of the first vertical transistors T1 can include a first semiconductor channel CH1, a first gate dielectric layer L1, and a first gate electrode G1. The first semiconductor channel CH1 may penetrate the second substrate 150 in the first direction D1, the first gate electrode G1 may be disposed in the second substrate 150, and may surround the first semiconductor channel CH1 in the horizontal direction (such as the second direction D2), and the first gate dielectric layer L1 may be disposed in the second substrate 150 and may be disposed between the first gate electrode G1 and the first semiconductor channel CH1, but is not limited thereto. In some embodiments, the first semiconductor channel CH1 may be elongated in the first direction D1, but is not limited thereto. In some embodiments, a plurality of first holes H1 may each penetrate the second substrate 150 in the first direction D1, and the first semiconductor channel CH1 and the first gate dielectric layer L1 of the same first vertical transistor T1 may be disposed in one of the first holes H1. Further, the second substrate 150 includes a semiconductor substrate, and each of the first gate electrodes G1 may include a first doped region DR1 disposed in the second substrate 150. In some embodiments, the first hole H1 may penetrate the first doped region DR1 in the first direction D1, and the first doped regions DR1 may be physically connected to each other, but are not limited thereto. In other words, in the second substrate 150, the first gate electrodes G1 of the first vertical transistors T1 may be physically and electrically connected to each other. However, in some embodiments, the first gate electrodes G1 may be electrically insulated from each other by a separation structure disposed in the second substrate 150. In some embodiments, each of the first vertical transistors T1 may be regarded as a surrounding gate transistor, but is not limited thereto. In some embodiments, the first gate electrode G1 can be formed by implanting a suitable dopant into the second substrate 150, and the second substrate 150 can include a semiconductor region (not shown in FIG. 2) without being doped by the dopant used to form the first gate electrode G1, but is not limited thereto.Note that the first vertical transistor T1 of the present disclosure is not limited to the above-described configuration, and other suitable types of vertical transistors may be used.

[0042] In some embodiments, the first substrate 100 may have a first surface S11 and a second surface S12 facing the first surface S11 in a first direction D1, and the second substrate 150 may have a first surface S21 and a second surface S22 facing the first surface S21 in the first direction D1. The first memory array 110 may be disposed on the first substrate 100, and the first memory array and the first word line contact structure 122 may be disposed on the second surface S12 of the first substrate 100 and may be disposed on the first surface S21 of the second substrate 150. Each first semiconductor channel CH1 of the first vertical transistor T1 may penetrate the second substrate 150 in the first direction D1 from the first surface S21 of the second substrate 150 to the second surface S22 of the second substrate 150, but is not limited thereto. In some embodiments, the memory device 301 may further include a plurality of first conductive lines GW1 and a plurality of first connection structures CS1. The first conductive lines GW1 and the first connection structures CS1 are disposed on the second surface S22 of the second substrate 150, and the first connection structures CS1 may be disposed between the first conductive lines GW1 and the second substrate 150 in the first direction D1. Each of the first conductive lines GW1 may be electrically connected to one of the first word line structures 114 through one of the first connection structures CS1, one of the first vertical transistors T1, and one of the first word line contact structures 122.

[0043] In some embodiments, the first conductive line GW1 may be regarded as a global word line routing for the first memory array 110, and the first vertical transistor T1 may be regarded as a pass gate transistor (or transmission gate transistor) for controlling a signal transmitted from the first conductive line GW1 to the first word line structure 114, but is not limited thereto. In some embodiments, two doped regions (not shown) may be disposed at two opposite ends of the first semiconductor channel CH1 in the first direction D1, the first word line contact structure 122 may contact one of the two doped regions, and the first connection structure CS1 may contact the other of the two doped regions, but is not limited thereto. In some embodiments, the first word line contact structure 122 and the first connection structure CS1 may each contact the corresponding first semiconductor channel CH1, and a part of the first word line contact structure 122 and a part of the first connection structure CS1 may be regarded as source / drain electrodes of the corresponding first vertical transistor T1, but is not limited thereto.

[0044] In some embodiments, the memory device 301 may further include a third substrate 200, a second memory array 210, a plurality of second gate contact structures 222, a plurality of second vertical transistors T2, a plurality of second connection structures CS2, and a plurality of second conductive lines GW2. The first memory array 110 is disposed between the first substrate 100 and the third substrate 200 in the first direction D1, the second substrate 150 is disposed between the first substrate 100 and the third substrate 200 in the first direction D1, the second memory array 210 and the second gate contact structures 222 are disposed between the third substrate 200 and the second substrate 150 in the first direction D1, and at least a part of each of the second vertical transistors T2 may be disposed on the second substrate 150, but is not limited thereto. In some embodiments, the third substrate 200 may have a first surface S31 and a second surface S32 facing the first surface S31 in the first direction D1, the second memory array 210 and the second gate contact structures 222 may be disposed on the third substrate 200 and may be disposed on the first surface S31 of the third substrate 200.

[0045] In some embodiments, the second memory array 210 may include a plurality of second word line structures 214, and the second vertical transistors T2 may each be electrically connected to a second word line structure 214. In other words, each of the second word line structures 214 may be electrically connected to one of the second vertical transistors T2 within the second substrate 150. In some embodiments, the second memory array 210 can include an alternating conductive / dielectric stack consisting of second dielectric layers 212 and second word line structures 214 alternately stacked in a first direction D1, and the second memory array 210 can have a second stepped portion P2 at an end in the horizontal direction (such as a second direction D2) of the second memory array 210 for exposing a part of each of the second word line structures 214, but is not limited thereto. In some embodiments, each of the second word line contact structures 222 may be disposed between one of the second vertical transistors T2 and one of the second word line structures 214 in the first direction D1 to electrically connect the second vertical transistor T2 and the second word line structure 214. In other words, each of the second word line structures 214 may be electrically connected to one of the second vertical transistors T2 through one of the second word line contact structures 222.

[0046] In some embodiments, each of the second vertical transistors T2 can include a second semiconductor channel CH2, a second gate dielectric layer L2, and a second gate electrode G2. In some embodiments, the second semiconductor channel CH2 may penetrate the second substrate 150 in the first direction D1, the second gate electrode G2 may be disposed in the second substrate 150, and may surround the second semiconductor channel CH2 in the horizontal direction (such as the second direction D2), the second gate dielectric layer L2 may be disposed in the second substrate 150 and may be disposed between the second gate electrode G2 and the second semiconductor channel CH2, but is not limited thereto. In some embodiments, the second semiconductor channel CH2 may be elongated in the first direction D1, but is not limited thereto. In some embodiments, a plurality of second holes H2 may each penetrate the second substrate 150 in the first direction D1, and the second semiconductor channel CH2 and the second gate dielectric layer L2 of the same second vertical transistor T2 may be disposed in one of the second holes H2. In some embodiments, each of the second gate electrodes G2 can include a second doped region DR2 disposed in the second substrate 150, the second hole H2 can penetrate the second doped region DR2 in the first direction D1, and the second doped regions DR2 can be physically connected to each other, but are not limited thereto. In other words, in the second substrate 150, the second gate electrodes G2 of the second vertical transistors T2 may be physically and electrically connected to each other, but are not limited thereto. In some embodiments, the second gate electrodes G2 may be electrically insulated from each other by a separation structure disposed in the second substrate 150. In some embodiments, each of the second vertical transistors T2 may be regarded as a surrounding gate transistor, but is not limited thereto. It should be noted that the second vertical transistor T2 of the present disclosure is not limited to the above-described configuration, and other suitable types of vertical transistors may be used.For example, a vertical transistor including a semiconductor channel extending in the vertical direction without penetrating the substrate, a gate electrode surrounding the semiconductor channel in the horizontal direction, and a connection structure that vertically penetrates a part of the substrate located below or above the semiconductor channel and contacts the semiconductor channel may be used as the first vertical transistor and / or the second vertical transistor in the present disclosure.

[0047] In some embodiments, the second gate electrode G2 may be formed by implanting a suitable dopant into the second substrate 150, and the composition of the second doped region DR2 may be the same as that of the first doped region DR1, but is not limited thereto. In particular, when the first vertical transistor T1 and the second vertical transistor T2 are arranged in the same substrate, the structure of the second vertical transistor T2 may be the same as that of the first vertical transistor T1 for process simplification, but is not limited thereto. In some embodiments, the structure of the second vertical transistor T2 may be different from that of the first vertical transistor T1 regardless of where the first vertical transistor T1 and the second vertical transistor T2 are arranged.

[0048] In some embodiments, the second conductive line GW2 and the second connection structure CS2 may be disposed on the first surface S21 of the second substrate 150 and may be disposed between the second substrate 150 and the first substrate 100 in the first direction D1. The second connection structure CS2 may be disposed between the second conductive line GW2 and the second substrate 150 in the first direction D1. Each of the second conductive lines GW2 may be electrically connected to one of the second word line structures 214 via one of the second connection structures CS2, one of the second vertical transistors T2, and one of the second word line contact structures 222. In some embodiments, the second conductive line GW2 may be regarded as global word line routing for the second memory array 210, and the second vertical transistor T2 may be regarded as a pass gate transistor (or transmission gate transistor) for controlling a signal transmitted from the second conductive line GW2 to the second word line structure 214, but is not limited thereto. In some embodiments, two doped regions (not shown) may be disposed at two opposite ends of the second semiconductor channel CH2 in the first direction D1, the second word line contact structure 222 may contact one of the two doped regions, and the second connection structure CS2 may contact another one of the two doped regions, but is not limited thereto. In some embodiments, the second word line contact structure 222 and the second connection structure CS2 may each contact the corresponding second semiconductor channel CH2, and a part of the second word line contact structure 222 and a part of the second connection structure CS2 may be regarded as source / drain electrodes of the corresponding second vertical transistor T2, but is not limited thereto.

[0049] In some embodiments, since the area occupied by the second vertical transistor T2 on the second substrate 150 is relatively small, each of the second vertical transistors T2 may be arranged corresponding to the exposed portion of the corresponding second word line structure 214 in the first direction D1, and the second word line contact structure 222 arranged between the second word line structure 214 and the second vertical transistor T2 may be simplified accordingly. For example, in some embodiments, each of the second word line contact structures 222 may be a pillar structure elongated in the first direction D1, one end of each of the second word line contact structures 222 in the first direction D1 may directly contact the exposed portion of the corresponding second word line structure 214, and the other end of the second word line contact structure 222 in the first direction D1 may directly contact the corresponding second vertical transistor T2, but is not limited thereto. In some embodiments, each of the second vertical transistors T2 may completely cover the corresponding second word line contact structure 222 in the first direction D1, but is not limited thereto.

[0050] In some embodiments, the memory device 301 may further include a first isolation structure 152 disposed within the second substrate 150, and at least a portion of the isolation structure 152 may be disposed between the first gate electrode G1 of the first vertical transistor T1 and the second gate electrode G2 of the second vertical transistor T2. In some embodiments, the first gate electrode G1 may be electrically isolated from the second gate electrode G2 by the first isolation structure 152, but is not limited thereto. In some embodiments, the first gate electrode G1 and the second gate electrode G2 may be disposed within the second substrate 150 and physically and electrically connected to each other. Further, the memory device 301 may further include a first interlayer dielectric 120 and a second interlayer dielectric 220. The first interlayer dielectric 120 may be disposed between the first substrate 100 and the second substrate 150 and may cover the first memory array 110, and the second interlayer dielectric 220 may be disposed between the third substrate 200 and the second substrate 150 and may cover the second memory array 210. The first word line contact structure 122, the second connection structure CS2, and the second conductive line GW2 may be disposed within the first interlayer dielectric 120. The second word line contact structure 222, the first connection structure CS1, and the first conductive line GW1 may be disposed within the second interlayer dielectric 220.

[0051] In some embodiments, the first substrate 100, the second substrate 150, and the third substrate 200 may each include a semiconductor substrate or a non-semiconductor substrate, such as a silicon substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or other suitable semiconductor substrates. In some embodiments, the second substrate 150 may be relatively thin for forming the first vertical transistor T1 and / or the second vertical transistor T2, but is not limited thereto. For example, the thickness TK2 of the second substrate 150 may be thinner than the thickness TK1 of the first substrate 100 and the thickness TK3 of the third substrate 200. The first dielectric layer 112 and the second dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The first word line structure 114, the second word line structure 214, the first word line contact structure 122, the second word line contact structure 222, the first connection structure CS1, the second connection structure CS2, the first conductive line GW1, and the second conductive line GW2 may each include a low-resistivity material and a barrier layer surrounding the low-resistivity material, but are not limited thereto. The above-mentioned low-resistivity materials may include materials having a relatively low resistivity such as copper, aluminum, cobalt, and tungsten, and the above-mentioned barrier layer may include titanium nitride, tantalum nitride, or other suitable barrier materials. The first gate dielectric layer L1 and the second gate dielectric layer L2 may include silicon oxide, silicon oxynitride, a high-k dielectric material, or other suitable dielectric materials. The first semiconductor channel CH1 and the second semiconductor channel CH2 may include amorphous silicon, polysilicon, or other suitable semiconductor materials. The first doped region DR1 and the second doped region DR2 may include n-type doped silicon or other suitable doped regions formed in the semiconductor substrate to enhance the conductivity of the first gate electrode G1 and the second gate electrode G2.The first interlayer dielectric 120 and the second interlayer dielectric 220 may each include a plurality of dielectric layers stacked in a first direction D1, and the material of the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, any suitable combination thereof, or other suitable dielectric materials. The first isolation structure 152 may include a single layer or a plurality of layers of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0052] In some embodiments, the manufacturing method of the memory device 301 may include, but is not limited to, the following steps. First, the first memory array 110, the first interlayer dielectric 120, the first word line contact structure 122, the second conductive line GW2, and the second connection structure CS2 may be formed on the first substrate 100, and the second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, the first conductive line GW1, and the first connection structure CS1 may be formed on the third substrate 200. The first vertical transistor T1, the second vertical transistor T2, and the first isolation structure 152 may be formed in the second substrate 150. Subsequently, the first substrate 100 on which the first memory array 110, the first interlayer dielectric 120, the first word line contact structure 122, the second conductive line GW2, and the second connection structure CS2 are formed, the third substrate 200 on which the second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, the first conductive line GW1, and the first connection structure CS1 are formed, and the second substrate 150 on which the first vertical transistor T1 and the second vertical transistor T2 are formed can be combined with each other by a direct bonding method such as a metal / dielectric hybrid bonding method or other suitable bonding techniques. Note that before the bonding process of thinning the thickness TK2 of the second substrate 150 and exposing the first vertical transistor T1 and the second vertical transistor T2 on the first surface S21 and the second surface S22 of the second substrate 150, a thinning process may be performed on the second substrate 150, but it is not limited thereto. In some embodiments, in order to reduce the total thickness of the memory device 301, other thinning processes may be performed on the first substrate 100 and / or the third substrate 200 before or after the above-described bonding process. In the present disclosure, in order to increase the total storage capacity of the memory device and simplify the related routing design, two or more memory arrays disposed on different substrates can be integrated by the above-described method.

[0053] In some embodiments, the above-described memory array is a 3D NAND memory array, 3D A NOR memory array, a dynamic random access memory (DRAM) array, 3D An XPoint memory array, or other suitable 3D memory structure can be included. In some embodiments, a memory string (not shown) can penetrate through an alternating conductive / dielectric stack of the memory array in a first direction D1. Each of the memory strings may have a cylindrical shape (e.g., pillar shape) that is long in the first direction D1, and each of the memory strings may include, but is not limited to, a channel layer, a tunnel layer, a memory layer, and a blocking layer arranged radially from the center of the pillar towards the outer surface in this order. The memory arrays in the present disclosure are not limited to the structure shown in FIG. 2 and / or the above-described structure, and other suitable memory array architectures can also be applied to the present disclosure.

[0054] Please refer to FIGS. 2 to 4. FIG. 3 is a schematic diagram showing a memory device according to an embodiment of the present disclosure, and FIG. 4 is a schematic diagram showing a top view of a part of the memory device according to an embodiment of the present disclosure. FIG. 3 may be regarded as a schematic diagram showing another part of the memory device 301 in the above-described first embodiment, and FIG. 4 may be regarded as a schematic diagram showing a top view of a part of a memory device similar to the memory device 301 in the above-described first embodiment, but is not limited thereto. As shown in FIGS. 2 and 3, in some embodiments, the memory device 301 may be disposed on the second surface S22 of the second substrate 150 and further include a third connection structure CS3 and a third conductive line GC disposed in the second interlayer dielectric 220. The third conductive line GC may be electrically connected to the first gate electrode G1 of the first vertical transistor T1 via a third connection structure CS3 for transmitting a signal to the first gate electrode G1 and controlling the switching condition of the first vertical transistor T1. In some embodiments, the third connection structure CS3 and the first connection structure CS1 may be formed of the same composition and / or formed by the same process, and the third conductive line GC and the first conductive line GW1 may be formed of the same composition and / or formed by the same process, but are not limited thereto. Further, in some embodiments, the second substrate 150 may include a semiconductor region 154, and at least a part of the first isolation structure 152 may be disposed between the semiconductor region 154 and the first gate electrode G1. Other circuit structures (not shown) may be formed on and / or within the semiconductor region 154, but are not limited thereto.

[0055] As shown in FIGS. 2 to 4, in some embodiments, the first memory array 110 may be divided into memory blocks 110A by a slit structure (not shown), and each of the first conductive lines GW1 may be elongated in another horizontal direction (such as the third direction D3 shown in FIG. 4) and overlap the first stepped portions P1 of different memory blocks 110A in the first direction D1. Further, the first gate electrodes G1 corresponding to different memory blocks 110A may be separated from each other by the first isolation structure 152, and the third conductive line GC may be elongated in the second direction D2 substantially orthogonal to the third direction D3, but is not limited thereto. In some embodiments, the semiconductor region 154 may be separated from the first gate electrode G1 by the first isolation structure 152, and the semiconductor region 154 may not overlap the first stepped portion P1 in the first direction D1 accordingly, but is not limited thereto. Note that components similar to the above-described third conductive line GC and third connection structure CS3 may be applied to the second memory array 210 of the present disclosure, and the features shown in FIGS. 3 and 4 may also be applied to other embodiments of the present disclosure.

[0056] The following description details different embodiments of the present disclosure. For the sake of simplicity, the same components in the following embodiments are denoted by the same reference numerals. In order to facilitate understanding of the differences between the embodiments, in the following description, the differences between different embodiments are described in detail, and the same features are not redundantly described.

[0057] Please refer to FIG. 5. FIG. 5 is a schematic diagram showing a memory device 302 according to a second embodiment of the present disclosure. As shown in FIG. 5, in the memory device 302, the second memory array 210 may be disposed on the second substrate 150, and a part of the second interlayer dielectric 220 may be disposed between the second memory array 210 and the third substrate 200 in the first direction D1. At least a part of each of the second vertical transistors T2 may be disposed within the third substrate 200. In some embodiments, the second semiconductor channel CH2 may penetrate the third substrate 200 in the first direction D1, the second gate electrode G2 may be disposed within the third substrate 200, and may horizontally surround the second semiconductor channel CH2. The second gate dielectric layer L2 may be disposed within the third substrate 200 and may be disposed between the second gate electrode G2 and the second semiconductor channel CH2, but is not limited thereto. In some embodiments, each of the second gate electrodes G2 may include a second doped region DR2 disposed within the third substrate 200, and the second hole H2 may penetrate the second doped region DR2 in the first direction D1, but is not limited thereto. In some embodiments, the second gate electrodes G2 of the second vertical transistors T2 may be physically and electrically connected to each other within the third substrate 150, and the second gate electrodes G2 of the second vertical transistors T2 may be separated from the first gate electrode G1 of the first vertical transistor T1. Further, the second connection structure CS2 and the second conductive line GW2 are disposed on the second surface S32 of the third substrate 200, and the protective layer 230 is disposed on the third substrate 200 and may cover the second connection structure CS2 and the second conductive line GW2. The protective layer 230 may include silicon oxide, silicon nitride, or other suitable insulating materials. In some embodiments, the second memory array 210 may be disposed on the semiconductor region 154, and a part of the first memory array 110 may overlap the second memory array 210 in the first direction D1, but is not limited thereto.

[0058] The manufacturing method of the memory device 302 can include, but is not limited to, the following steps. First, the first memory array 110, the first interlayer dielectric 120, and the first word line contact structure 122 may be formed on the first substrate 100, and the first vertical transistor T1 and the first isolation structure 152 may be formed in the second substrate 150. The second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, the first conductive line GW1, and the first connection structure CS1 may be formed on the third substrate 200, and the second vertical transistor T2 may be formed in the third substrate 200. The second conductive line GW2, the second connection structure CS2, and the protective layer 230 may be formed on the third substrate 200. Subsequently, the first substrate 100 on which the first memory array 110, the first interlayer dielectric 120, and the first word line contact structure 122 are formed, the second substrate 150 in which the first vertical transistor T1 is formed and on which the second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, the first conductive line GW1, and the first connection structure CS1 are formed, and the third substrate 200 in which the second vertical transistor T2 is formed and on which the second conductive line GW2, the second connection structure CS2, and the protective layer 230 are formed can be combined with each other by a direct bonding method such as a metal / dielectric hybrid bonding method or other appropriate bonding techniques. Note that before the bonding process of thinning the thickness TK2 of the second substrate 150 and the thickness TK3 of the third substrate 200 and exposing the first vertical transistor T1 on the first surface S21 and the second surface S22 of the second substrate 150 and exposing the second vertical transistor T2 on the first surface S31 and the second surface S32 of the third substrate 200, a thinning process may be performed on the second substrate 150 and / or the third substrate 200, but is not limited thereto. Therefore, the thickness TK2 of the second substrate 150 and the thickness TK3 of the third substrate 200 may be thinner than the thickness of the first substrate 100, but are not limited thereto.

[0059] Please refer to FIG. 6. FIG. 6 is a schematic diagram showing a memory device 303 according to a third embodiment of the present disclosure. As shown in FIG. 6, in the memory device 303, the third substrate 200 is disposed between the first substrate 100 and the second substrate 150 in the first direction D1, and the second memory array 210 may be disposed between the second substrate 150 and the third substrate 200 in the first direction D1. In some embodiments, the second memory array 210 may be disposed on the third substrate 200, on the second surface S32 of the third substrate 200 and the first surface S21 of the second substrate 150, and the first conductive line GW1, the second conductive line GW2, the first connection structure CS1, the second connection structure CS2, and the protective layer 230 may be disposed on the second substrate 150, on the second surface S22 of the second substrate 150. In some embodiments, the memory device 303 may further include a plurality of fourth connection structures CS4, a plurality of through-substrate connection structures TS, and a second isolation structure 240. The second isolation structure 240 may be disposed within the third substrate 200, each of the through-substrate connection structures TS may be disposed within the third substrate 200 and penetrate the second isolation structure 240 in the first direction D1, and each of the fourth connection structures CS4 may be disposed within the second interlayer dielectric 220 and disposed between one of the second vertical transistors T2 and one of the through-substrate connection structures TS in the first direction D1. Each of the through-substrate connection structures TS may be electrically connected to one of the first word line contact structures 122 and one of the fourth connection structures CS4, and each of the fourth connection structures CS4 may be electrically connected to one of the first vertical transistors T1. Accordingly, each of the first conductive lines GW1 may be electrically connected to one of the first word line structures 114 through one of the first connection structures CS1, one of the first vertical transistors T1, one of the fourth connection structures CS4, one of the through-substrate connection structures TS, and one of the first word line contact structures 122. The second isolation structure 240 may include a single layer or a plurality of layers of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.The fourth connection structure CS4 and the through-substrate connection structure TS may include, but are not limited to, a low resistivity material and a barrier layer surrounding the low resistivity material. The aforementioned low resistivity material can include materials having a relatively low resistivity such as copper, aluminum, cobalt, and tungsten, and the aforementioned barrier layer can include titanium nitride, tantalum nitride, or other suitable barrier materials.

[0060] The manufacturing method of the memory device 303 can include, but is not limited to, the following steps. First, the first memory array 110, the first interlayer dielectric 120, and the first word line contact structure 122 may be formed on the first substrate 100, the through-substrate connection structure TS and the second isolation structure 240 may be formed in the third substrate 200, the second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, and the fourth connection structure CS4 may be formed on the third substrate 200, the first vertical transistor T1, the second vertical transistor T2, and the first isolation structure 152 may be formed in the second substrate 150, and the first connection structure CS1, the second connection structure CS2, the first conductive line GW1, the second conductive line GW2, and the protection layer 230 may be formed on the second substrate 150. Subsequently, the first substrate 100 on which the first memory array 110, the first interlayer dielectric 120, and the first word line contact structure 122 are formed, the third substrate 200 in which the through-substrate connection structure TS and the second isolation structure 240 are formed and on which the second memory array 210, the second interlayer dielectric 220, the second word line contact structure 222, and the fourth connection structure CS4 are formed, and the second substrate 150 in which the first vertical transistor T1, the second vertical transistor T2, and the first isolation structure 152 are formed and on which the first connection structure CS1, the second connection structure CS2, the first conductive line GW1, the second conductive line GW2, and the protection layer 230 are formed can be combined with each other by a direct bonding method such as a metal / dielectric hybrid bonding method or other suitable bonding techniques. Note that before the bonding process of thinning the thickness TK2 of the second substrate 150 and exposing the first vertical transistor T1 and the second vertical transistor T2 on the first surface S21 and the second surface S22 of the second substrate 150, a thinning process may be performed on the second substrate 150, but it is not limited thereto.

[0061] Please refer to FIG. 7. FIG. 7 is a schematic diagram showing a memory device 304 according to a fourth embodiment of the present disclosure. As shown in FIG. 7, in the memory device 304, the first conductive line GW1, the second conductive line GW2, the first connection structure CS1, the second connection structure CS2, and the protection layer 230 may be disposed on the third substrate 200 and may be disposed on the second surface S32 of the third substrate 200. Further, the second separation structure 240 and the through-substrate connection structure TS may be disposed within the third substrate 200, and each of the first vertical transistors T1 within the second substrate 150 may be electrically connected to one of the first conductive lines GW1 through one of the fourth connection structures CS4, one of the through-substrate connection structures TS, and one of the first connection structures CS1.

[0062] Please refer to FIG. 8. FIG. 8 is a schematic diagram showing a memory device 305 according to a fifth embodiment of the present disclosure. As shown in FIG. 8, in the memory device 305, the first gate electrode G1 of the first vertical transistor T1 may be physically and electrically connected to the second gate electrode G2 of the second vertical transistor T2. In some embodiments, the first gate electrode G1 and the second gate electrode G2 may be formed in the same doped region (such as the first doped region DR1, etc.) within the second substrate 150, but are not limited thereto.

[0063] Please refer to FIG. 9. FIG. 9 is a schematic diagram showing the memory device 306 according to the sixth embodiment of the present disclosure. As shown in FIG. 9 and the above-mentioned FIG. 5, the difference between the memory device 306 of the present embodiment and the above-mentioned memory device 302 is that in the memory device 306, the second memory array 210 may not overlap with the first memory array 110 in the first direction D1, and in the top view of the memory device 306, the second stepped portion P2 of the second memory array 210 may be arranged adjacent to the first stepped portion P1 in the second direction D2, but is not limited thereto. In the top view of the memory device 306, the shape of the second memory array 210 may be the same as the mirror image of the shape of the first memory array 110, and the shape of the first memory array 110 and the shape of the second memory array 210 may be a mirror-symmetric pattern in some embodiments, but is not limited thereto. Note that the relative arrangement of the first memory array 110 and the second memory array 210 may also be applied to other embodiments of the present disclosure.

[0064] Please refer to FIG. 10. FIG. 10 is a schematic diagram showing the memory device 307 according to the seventh embodiment of the present disclosure. As shown in FIG. 9 and the above-mentioned FIG. 6, the difference between the memory device 307 of the present embodiment and the above-mentioned memory device 303 is that in the memory device 307, the second memory array 210 may not overlap with the first memory array 110 in the first direction D1, and in the top view of the memory device 307, the second stepped portion P2 of the second memory array 210 may be arranged adjacent to the first stepped portion P1 in the second direction D2, but is not limited thereto. In the top view of the memory device 307, the shape of the second memory array 210 may be the same as the mirror image of the shape of the first memory array 110, and the shape of the first memory array 110 and the shape of the second memory array 210 may be a mirror-symmetric pattern in some embodiments, but is not limited thereto.

[0065] To summarize the above description, in the memory device of the present disclosure, the vertical transistor disposed in the substrate is electrically connected to the word line structure of the memory array disposed on another substrate. The area occupied by the vertical transistor on the substrate can be reduced, and accordingly, the word line contact structure located between the vertical transistor and the word line structure can be simplified.

[0066] Those skilled in the art will readily understand that numerous modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the boundaries of the appended claims.

Claims

1. A memory device, comprising: a semiconductor substrate; a first memory array including at least one first word line structure; at least one first vertical transistor, at least a part of the at least one first vertical transistor being disposed within the semiconductor substrate; a word line contact structure disposed between the at least one first vertical transistor and the at least one first word line structure; the first memory array and the semiconductor substrate being joined together, and the at least one first word line structure being connected to the at least one first vertical transistor via the word line contact structure; each of the word line contact structures extending through an interlayer dielectric facing an exposed portion of the corresponding at least one first word line structure; a memory device.

2. A second memory array including at least one second word line structure; and at least one second vertical transistor connected to the at least one second word line structure. The memory device according to claim 1.

3. The semiconductor substrate is a second substrate, and the memory device further comprises: a first substrate on which the first memory array is disposed in a vertical direction on the first substrate between the first substrate and the second substrate; a third substrate on which the first memory array is disposed in a vertical direction between the first substrate and the third substrate; the second memory array being disposed on the third substrate; at least a part of the at least one second vertical transistor being disposed within the second substrate. The memory device according to claim 2.

4. The at least one first vertical transistor includes a first semiconductor channel penetrating the semiconductor substrate in a vertical direction. The memory device according to any one of claims 1 to 3.

5. The at least one first vertical transistor is disposed within the semiconductor substrate and further includes a first gate electrode surrounding the first semiconductor channel in a horizontal direction. The memory device according to claim 4.

6. The at least one first vertical transistor is disposed within the semiconductor substrate and further includes a first gate dielectric layer disposed between the first gate electrode and the first semiconductor channel. The memory device according to claim 5.

7. The first memory array includes a plurality of the at least one first word line structure, and the memory device includes a plurality of the at least one first vertical transistor electrically connected to the plurality of the at least one first word line structure respectively. The memory device according to claim 5.

8. The first gate electrodes of the plurality of the at least one first vertical transistor are physically and electrically connected to each other within the semiconductor substrate. The memory device according to claim 7.

9. The semiconductor substrate includes a semiconductor region, and the first gate electrode includes a doped region disposed within the semiconductor substrate. The memory device according to claim 5.

10. A separation structure disposed within the semiconductor substrate and disposed between the semiconductor region and the first gate electrode is further included. The memory device according to claim 9.

11. The word line contact structure is a vertically long pillar structure. One end of each of the word line contact structures in the vertical direction directly contacts an exposed portion of the corresponding at least one first word line structure. The other end of the word line contact structure in the vertical direction directly contacts the corresponding at least one first vertical transistor. The exposed portion of the at least one first word line structure is aligned with the at least one first vertical transistor in the vertical direction. The memory device according to any one of claims 1 to 3.

12. The at least one first vertical transistor completely covers the word line contact structure in the vertical direction. The memory device according to claim 11.

13. The semiconductor substrate has a first surface and a second surface facing the first surface in the vertical direction. The first memory array and the word line contact structure are disposed on the first surface of the semiconductor substrate. The memory device according to claim 11.

14. A conductive line disposed on the second surface of the semiconductor substrate, A connection structure disposed on the second surface of the semiconductor substrate and disposed between the conductive line and the at least one first vertical transistor, wherein the conductive line is electrically connected to the at least one first word line structure through the connection structure, the at least one first vertical transistor, and the word line contact structure, and further comprising a connection structure. The memory device according to claim 13.

15. The at least one second vertical transistor includes a second semiconductor channel penetrating the semiconductor substrate in the vertical direction, and a second gate electrode disposed in the semiconductor substrate and surrounding the second semiconductor channel in the horizontal direction. The memory device according to claim 2 or 3.

16. The at least one first vertical transistor includes a first gate electrode disposed in the semiconductor substrate, and the first gate electrode is physically and electrically connected to the second gate electrode. The memory device according to claim 15.

17. The at least one first vertical transistor includes a first gate electrode disposed in the semiconductor substrate, and the first gate electrode is electrically separated from the second gate electrode. The memory device according to claim 15.

18. The third substrate is disposed between the first substrate and the second substrate in the vertical direction, and the second memory array is disposed between the second substrate and the third substrate in the vertical direction. The memory device according to claim 3.

19. The second substrate is disposed between the first substrate and the third substrate in the vertical direction, and the second memory array is disposed between the second substrate and the third substrate in the vertical direction. The memory device according to claim 3.

20. The second memory array is disposed on the second substrate, and at least a part of the at least one second vertical transistor is disposed in the third substrate. The memory device according to claim 19.

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