Semiconductor Structure and Method of Manufacturing the Same

Abstract

To provide a semiconductor structure that enables a device to have higher capability of resisting the moisture.SOLUTION: A semiconductor structure 100 includes a substrate 110, a semiconductor epitaxial layer 120 provided on the substrate 110, an active area 121 and a terminal area 123 in the semiconductor epitaxial layer 120, a field oxide layer 130 provided in the semiconductor epitaxial layer 120, an anode layer 140 provided extending from the active area 121 to a part of the field oxide layer 130 and including a top wall surface 142, a side wall surface 143 connected to the field oxide layer 130, and a connection surface 144 that connects between the side wall surface 143 and the top wall surface 142, and a passivation layer 150 provided extending along the side wall surface 143 so as to cover the field oxide layer 130 and the connection surface 144. The connection surface 144 is formed in an arch shape so that the side wall surface 143 and the top wall surface 142 of the anode layer 140 are connected smoothly.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background Art

[0002] Silicon carbide, as an important third-generation semiconductor material, has advantages such as a high band gap, a high critical breakdown electric field, and a high thermal conductivity. Therefore, compared with conventional silicon power devices, silicon carbide power devices have advantages such as a higher breakdown voltage, a faster switching speed, and a higher operating temperature. With the maturity of silicon carbide diode technology, the application areas have become wider, including areas such as photovoltaic inverters, on-board chargers, and communication power supplies.

[0003] Depending on the application area, the reliability requirements for the device are different. For example, in coastal areas or in high-temperature, high-salt, and high-humidity environments, the requirements for the High Temperature and High Humidity Reverse Bias (H3TRB) test for the device are special and more stringent than the AEC-Q101 (Automotive Electronics Council-Q101) standard for conventional silicon power devices.

[0004] Current power devices prevent moisture erosion through a silicon oxide silicon nitride laminated construction or a silicon oxynitride passivation layer. However, during actual operation, the device often undergoes repeated cycles of high and low temperatures, as disclosed in Patent Document 1 for example. Moreover, conventional etching techniques, as disclosed in Non-Patent Document 1 for example, etch only along the direction perpendicular to the surface of the silicon sheet, and the etched structure always has a vertical cutting surface.

[0005] Therefore, in the bent corner portion of the etched metal, stress concentration is likely to occur in the passivation layer or the material layer, resulting in cracks. Due to the action of a high electric field, the ingress and egress of moisture through the cracks are accelerated, thereby causing the device to malfunction.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] An object of the present invention is to provide a semiconductor structure and a method for manufacturing the semiconductor structure that reduce the problem of stress concentration and crack formation at the bent corner of the metal layer, and improve the moisture resistance of the device.

Means for Solving the Problems

[0009] To achieve the above object, the present invention provides a substrate, an epitaxial layer provided on the substrate, active regions and termination regions provided in the epitaxial layer, a field oxide layer provided in the epitaxial layer so as to extend from the periphery of the active region to the termination region, an anode layer provided so as to extend from a part of the active region to a part of the field oxide layer, and including a top wall surface on a side opposite to the active region, a side wall surface connected to the field oxide layer, and a connecting surface connecting between the side wall surface and the top wall surface, a passivation layer provided so as to extend along the side wall surface so as to cover at least the connecting surface while covering the field oxide layer, wherein the connecting surface is formed in an arc shape so that the side wall surface and the top wall surface of the anode layer are smoothly connected, and provides a semiconductor structure characterized by this.

[0010] In addition, the present invention provides Step a of providing a base structure including a substrate, an epitaxial layer provided on the substrate, active regions and termination regions provided in the epitaxial layer, and a field oxide layer provided in the epitaxial layer so as to extend from the peripheral portion of the active region to the termination region, A step of forming an anode layer on the active region and the field oxide layer, wherein the anode layer is disposed to extend from the active region to a part of the field oxide layer, and the anode layer includes a top wall surface on a side opposite to the active region, a side wall surface connected to the field oxide layer, and a connecting surface connecting between the side wall surface and the top wall surface, and the connecting surface is formed in an arch shape so that the side wall surface and the top wall surface of the anode layer are smoothly connected; step b A step of forming a passivation layer on the field oxide layer and the anode layer, wherein the passivation layer is disposed to extend along the side wall surface so as to cover at least the connecting surface while covering the field oxide layer; step c, provided is a method for manufacturing a semiconductor structure, characterized by including the above.

Effects of the Invention

[0011] The semiconductor structure and the method for manufacturing a semiconductor structure provided by the present invention make the upper bending angle of the side wall surface of the anode layer of the semiconductor structure, that is, the connecting surface between the side wall surface and the top wall surface, in an arch shape, so that the side wall surface and the top wall surface of the anode layer are smoothly connected without sharp parts and other obstructive parts (wherein, in this specification and the claims of the present application, "smoothly connected" means "smoothly connected without sharp parts and other obstructive parts"), thus avoiding a sudden change in the inclination angle and preventing stress from concentrating on the part located at the upper bending angle of the side wall surface in the passivation layer, and greatly improving the reliability of the device. Compared with the prior art, the semiconductor structure provided by the present invention reduces the crack problem caused by stress concentration at the bending angle due to the steep side surface of the anode layer, and improves the moisture resistance of the device.

Brief Description of the Drawings

[0012] To clearly explain the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly described below. The following drawings only show some embodiments of this application and do not limit the scope. It should be understood that those with ordinary knowledge in the technical field can obtain other related drawings according to these drawings without creative effort.

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Embodiments for Carrying Out the Invention

[0013] To more clearly explain the objectives, technical solutions, and advantages of the embodiments of this application, hereinafter, in combination with the accompanying drawings of the embodiments of the present invention, the technical solutions in the embodiments of this application will be clearly and completely described. It will be apparent that the described embodiments are only some of the embodiments of this application and not all of them. Usually, the components of the embodiments of this application depicted and shown in the accompanying drawings can be arranged and designed in various different layouts.

[0014] Therefore, hereinafter, the detailed description of the embodiments of this application provided in the accompanying drawings does not constitute any limitation to the protection scope of this application and merely shows the selected embodiments of this application. Based on the embodiments of this application, all other embodiments obtained on the premise that those skilled in the art do not perform creative work belong to the scope of the claims related to this application.

[0015] Before describing the present invention in more detail, it should be noted that, if considered appropriate, reference numerals or the end portions of reference numerals are repeated between figures to indicate corresponding or similar elements, and these can optionally have the same characteristics.

[0016] In the description of the present invention, terms indicating orientation and positional relationships such as "upper", "lower", "inner", "outer", etc. are based on the orientation and positional relationships shown in the drawings or the orientation and positional relationships habitually placed when using the products of the present invention for the purpose of more simply and clearly explaining, and do not teach or imply that the corresponding devices and devices have specific orientations, structures, operations, etc. in a specific orientation, and are not limitations to the present invention.

[0017] Also, in the description of the present invention, terms such as "first", "second", etc. are used only for the purpose of distinction and do not teach or imply relative importance.

[0018] The present invention provides a new semiconductor structure and a method for manufacturing the semiconductor structure. If there is no conflict, the features of each embodiment of the present invention can be combined.

[0019] As shown in FIGS. 1 and 2, an embodiment of the present invention provides a semiconductor structure 100. The semiconductor structure 100 reduces the crack problem caused by stress concentration at the bending angle due to the sharpness of the anode layer 140 by optimizing the conditions of photolithography and etching, for example, by optimizing the conditions of photolithography and dry etching, and improves the moisture resistance of the device by making the bending angle of the anode layer 140 gentler.

[0020] This embodiment provides a semiconductor structure 100 including a substrate 110, a semiconductor epitaxial layer 120, a field oxide layer 130, an anode layer 140, and a passivation layer 150. The semiconductor epitaxial layer 120 is disposed on the substrate 110. And active regions 121 and termination regions 123 are disposed in the semiconductor epitaxial layer 120. The active regions 121 and the termination regions 123 extend away from the surface (top surface) of the substrate 110 where the semiconductor epitaxial layer 120 is formed within the semiconductor epitaxial layer 120. The field oxide layer 130 is disposed on the semiconductor epitaxial layer 120 so as to extend from the periphery of the active region 121 to the termination region 123. The anode layer 140 is disposed so as to extend from the active region 121 to a part of the field oxide layer 130. That is, the anode layer 140 is disposed on the field oxide layer 130. And the anode layer 140 includes a top wall surface 142 on the side opposite to the active region 121, a side wall surface 143 connected to the field oxide layer 130, and a connecting surface 144. The side wall surface 143 of the anode layer 140 and the top wall surface 142 of the anode layer 140 are connected by the connecting surface 144. The connecting surface 144 is formed in an arch shape so that the side wall surface 143 and the top wall surface 142 of the anode layer 140 are smoothly connected. The passivation layer 150 is disposed so as to extend along the side wall surface 143 so as to cover at least the connecting surface 144 while covering the field oxide layer 130.

[0021] During actual operation, since the device always goes through the process of high and low temperature cycling, the thermal expansion coefficients of the passivation layer, anode layer, and protective layer are different. Therefore, the shear force is too large and the passivation layer fractures. In particular, the passivation layer at the bending angle of the anode layer (i.e., the part corresponding to the connection surface 144) is prone to fracture due to stress concentration. Also, through the cracks caused by this fracture, the ingress and egress of moisture are accelerated by the action of a high electric field, thereby causing the device to malfunction.

[0022] In this embodiment, due to the arched connection surface 144 between the side wall surface 143 and the top wall surface 142 of the anode layer 140, the connection between the side wall surface 143 and the top wall surface 142 of the anode layer 140 is smooth, and the angle between the side wall surface 143 and the top wall surface 142 of the anode layer 140 changes abruptly, so the generation of stress concentration at the part located at the bending angle of the upper passivation layer 150 can be reduced, and the malfunction of the device caused by moisture entering the device can be reduced.

[0023] The passivation layer 150 is installed so as to extend while covering the connection surface 144 while covering the field oxide layer 130. Therefore, the range in which the passivation layer 150 covers the anode layer 140 can be limited, cracks due to thermal expansion can be suppressed, and the moisture resistance of the device is further improved.

[0024] Also, compared with the prior art where a power device prevents moisture erosion through a silicon oxide or silicon nitride laminated structure or a silicon oxynitride passivation layer, the present invention only changes the bending angle structure of the anode layer itself, and there is no need for methods such as adding a buffer material layer disclosed in Patent Document 1. Therefore, the present invention can not only reduce the stress concentration of the passivation layer, but also reduce the layer structure of the device, reduce the package height of the device, and is beneficial for the miniaturization design of the device.

[0025] Since the connection between the side wall surface 143 and the top wall surface 142 is smooth, when depositing the passivation layer 150, it is advantageous for the upward extension of the passivation layer 150. Thereby, it is advantageous for solving the problem of the passivation layer 150 climbing above the anode layer 140, the molding quality of the passivation layer 150 is better, and the reliability of the device is improved.

[0026] In some embodiments, as shown in FIG. 3, a recess 141a is provided on the top wall surface 142 of the anode layer 140. The periphery of the recess 141a and the side wall surface 143 of the anode layer 140 are connected by a joint 146. A part of the joint 146 is a connection surface 144.

[0027] The field oxide layer 130 is provided on the semiconductor epitaxial layer 120, and a first window 131 for exposing the active region 121 is formed.

[0028] For example, in the anode layer 140, a protrusion 141 is formed at a portion corresponding to the periphery of the first window 131, and the recess 141a is formed between the protrusions 141 on both sides. The side wall surface 143 of the anode layer 140 extends from the protrusion 141 to the field oxide layer 130, and the portion where the surface of the protrusion 141 and the side wall surface 143 of the anode layer 140 are joined is the above-mentioned joint 146. The passivation layer 150 extends to the protrusion 141 so as to cover the protrusion 141 while covering the side wall surface 143.

[0029] In some embodiments, as shown in FIGS. 1 and 4, the periphery of the recess 141a and the side wall surface 143 of the anode layer 140 are connected by a joint 146. The joint 146 can be an arched connection surface 144.

[0030] In some other embodiments, a part of the joint 146 is the connection surface 144, and the other part is a part of the top wall surface 142 of the anode layer 140. That is, the top wall surface 142 of the anode layer 140 includes the recess 141a and the remaining part of the joint 146 excluding the connection surface 144.

[0031] In some other embodiments, as shown in FIGS. 1, 3, and 4, while covering the side wall surface 143 of the anode layer 140, the passivation layer 150 extends to the joint portion 146 so as to cover the joint portion 146.

[0032] In some other embodiments, as shown in FIGS. 1 and 3, in the first direction T1 from the active region 121 to the termination region 123, the length of the portion of the passivation layer 150 covering the joint portion 146 is in the range of 2 μm to 100 μm. That is, the joint width range (i.e., the above length) of the passivation layer 150 at the joint portion 146 of the anode layer 140 is in the range of 2 μm to 100 μm.

[0033] Here, the joint width of the passivation layer 150 covering the joint portion 146 of the anode layer 140 refers to the width of the surface of the portion where the passivation layer 150 and the anode layer 140 are joined, that is, the width of the partial surface in the anode layer 140 for depositing the passivation layer 150. Of course, the joint width may be understood as the length extending from the portion (i.e., the portion connecting the arc-shaped connection surface 144 and the inclined straight side wall surface 143 in FIG. 1) connecting the connection surface 144 and the side wall surface 143 of the passivation layer 150 to the portion where the joint portion 146 (i.e., the connection surface 144) and the inclined straight top wall surface 142 are connected.

[0034] For example, the joint width of the passivation layer 150 covering the joint portion 146 of the anode layer 140 can be 50 μm.

[0035] In the above embodiments, the passivation layer 150 is installed to extend and cover the joint portion 146 of the anode layer 140, and by setting a certain joint width, it is possible to avoid the situation that the covering range of the passivation layer 150 is too wide, and further suppress the problem that the shear force is too large due to the different coefficients of thermal expansion between different materials, resulting in cracks in the passivation layer 150.

[0036] The protrusion 141 of this embodiment is installed in the peripheral area of the top wall surface 142 of the anode layer 140, and the top wall surface 142 and the side wall surface 143 of the anode layer 140 are connected by a joint 146. The joint 146 can be entirely in an arch shape, that is, as shown in FIG. 1, the connecting surface 144 is in an arch shape and is directly connected to the top wall surface 142 and the side wall surface 143.

[0037] In some other embodiments, as shown in FIG. 3, the joint 146 can include a connecting surface 144 and a transition surface. The connecting surface 144 is in an arch shape, and the transition surface is in a planar shape. That is, after the passivation layer 150 passes through the arch, it becomes gentle at the transition surface. This transition surface is the remaining part of the joint 146 excluding the connecting surface 144, or can also be said to be a part of the top wall surface 142 of the anode layer 140.

[0038] Here, since the top wall surface 142 of the anode layer 140 has a recess 141a, the anode layer 140 has an upper bending angle and a lower bending angle. And since a part of the joint 146 connecting the periphery of the recess 141a and the side wall surface 143 of the anode layer 140 is the arch-shaped connecting surface 144, the upper bending angle and the lower bending angle of the anode layer 140 are in a state of gentle transition. That is, the transition between the side wall surface 143 of the anode layer 140 and the top wall surface 142 of the anode layer 140 is in an arch shape. Thereby, the part where the passivation layer 150 has a smooth bending angle is less likely to crack, and the moisture resistance ability of the device is improved.

[0039] Also, due to the smooth bending angle, it can contribute to solving the climbing problem of the passivation layer 150, and the molding quality of the passivation layer 150 becomes better.

[0040] In addition, the passivation layer 150 extends to the top end of the protrusion 141 so as to cover the top end, and corresponds to the position of the peripheral area of the first window 131. Specifically speaking, the passivation layer 150 climbs to the top end of the protrusion 141 while extending from the field oxide layer 130 toward the side wall surface 143 of the anode layer 140, brings about a good passivation effect without affecting the electrical connection with the outside of the anode layer 140, and completely covers the upper bending angle and the lower bending angle of the side wall surface 143 of the anode layer 140 by the passivation layer 150. The passivation layer 150 may be a two-layer medium of silicon oxide and silicon nitride, or may be a silicon oxynitride medium. The thickness of the passivation layer 150 is in the range of 8000 Å to 15000 Å (1 Å is 10 -10 m). Of course, the material and thickness of the above-mentioned passivation layer 150 are merely illustrative and do not limit the present invention.

[0041] In some other embodiments, as shown in FIG. 2, the top wall surface 142 of the anode layer 140 can also be planar (i.e., without the recess 141a), specifically, the portion above the active area 121 in the anode layer 140 has a planar structure.

[0042] In some embodiments, as shown in FIGS. 1 and 2, the side wall surface 143 of the anode layer 140 is in an inclined shape that extends so as to be inclined from the field oxide layer 130 to the active area 121.

[0043] In some embodiments, the angle formed between the side wall surface 143 of the anode layer 140 and the top surface on the side opposite to the end area 123 of the field oxide layer 130 may be smaller than the angle usually required in the advanced integrated circuit applications described in Non-Patent Document 1, and side walls of 88° to 89° are usually required for advanced integrated circuit applications. Therefore, in this embodiment, the angle formed between the side wall surface 143 of the anode layer 140 and the top surface on the side opposite to the end area 123 of the field oxide layer 130 (i.e., the second angle α in FIG. 1 for example) is in the range of 0° to 88°.

[0044] In this embodiment, the side wall surface 143 of the anode layer 140 is installed to be non-vertical and inclined to the field oxide layer 130, so that the connection between the side wall surface 143 and the top wall surface 142 of the anode layer 140 is smooth, and the inclination angle between the side wall surface 143 and the top wall surface 142 of the anode layer 140 changes abruptly (the angle formed in between is too large), thereby reducing the occurrence of stress concentration in the passivation layer 150 located in that part, and reducing the failure of the device caused by moisture entering the device interior.

[0045] In some embodiments, the projection of one end of the arch shape close to the top wall surface 142 of the connection surface 144 in the figure in the direction towards the semiconductor epitaxial layer 120 intersects (i.e., the positions correspond) with the projection on one side away from the semiconductor epitaxial layer 120 of the field oxide layer 130.

[0046] That is, the projection of the intersection point of the arch shape of the connection surface 144 and the top wall surface 142 along the direction from the semiconductor epitaxial layer 120 towards the substrate 110 is on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120.

[0047] In some embodiments, as shown in FIGS. 1 and 4, the connection surface 144 includes a first point A1 connected to the top wall surface 142 and a second point A2 connected to the side wall surface 143. The point where the first point A1 is projected onto the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120 along the direction from the semiconductor epitaxial layer 120 towards the substrate 110 is defined as the third point A3. The first angle θ, which is the angle formed by the line connecting the third point A3 and the second point A2 and the line connecting the third point A3 and the first point A1, exceeds 5°.

[0048] If the first angle θ is less than 5°, stress will still concentrate on the portion located at the bend angle of the side wall surface 143 in the passivation layer 150. Therefore, in order to solve the problem that stress concentrates on the portion located at the upward bend angle of the side wall surface 143 in the passivation layer 150 and reduce the problem of cracks occurring in the portion located at the bend angle of the side wall surface 143 in the passivation layer 150 due to the concentration of such stress, by setting the first angle θ to be greater than 5°, it is possible to reduce the problem that the first angle θ is too small and the arch length of the connection surface 140 becomes short, resulting in stress concentration and cracks occurring in the portion located at the bend angle of the side wall surface 143 in the passivation layer 150. As a result, the moisture resistance of the device is improved, and furthermore, the reliability of the device is improved.

[0049] In some embodiments, as shown in FIGS. 1 and 4, the connection surface 144 includes a first point A1 connected to the top wall surface 142 and a second point A2 connected to the side wall surface 143. The point where the first point A1 is projected onto the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120 along the direction from the semiconductor epitaxial layer 120 towards the substrate 110 is defined as the third point A3. The first angle θ, which is the angle formed by the line connecting the third point A3 and the second point A2 and the line connecting the third point A3 and the first point A1, is less than 45°.

[0050] If the first angle θ is too large, for example, 45° or more, the downward bend angle of the side wall surface 143 that bends downward along the arch shape of the connection surface 144 becomes sharp, and the portion at the connection part between the side wall surface 143 and the field oxide layer 130 in the passivation layer 150 also becomes sharp and is prone to cracking. Therefore, in order to reduce the sharpness of the passivation layer 150 at the downward bend angle of the side wall surface 143, the first angle θ is set to be less than 45°. Thereby, the side wall surface 143 that bends downward along the arch shape of the connection surface 144 becomes a gentle slope, and it is possible to reduce the concentration of stress and the occurrence of cracks in the portion located at the downward bend angle of the side wall surface 143 of the anode layer 140 in the passivation layer 150.

[0051] Furthermore, since the first angle θ is set to be less than 45°, the side wall surface 143 that bends downward along the arch shape of the connection surface 144 becomes a gentle slope (a tangent line downward from the arch shape). Thereby, the passivation layer 150 can grow along the gentle slope, which is advantageous for the uniform growth of the passivation layer 150.

[0052] In order to reduce the problem that stress concentrates at the portions located at the upward bending angle and the downward bending angle of the side wall surface 143 in the passivation layer 150 and cracks are generated, and to improve the moisture resistance ability of the device, in some embodiments, the connection surface 144 includes a first point A1 connected to the side wall surface 143 and a second point A2 connected to the top wall surface 142. The point where the first point A1 is projected onto the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120 along the direction from the semiconductor epitaxial layer 120 to the substrate 110 is the third point A3. The first angle θ, which is the angle formed by the line connecting the third point A3 and the second point A2 and the line connecting the third point A3 and the first point A1, is greater than 5° and less than 45°.

[0053] In this way, by setting the first angle θ to be greater than 5° and less than 45°, the problem that stress concentrates at the portions located at the upward bending angle and the downward bending angle of the side wall surface 143 in the passivation layer 150 and cracks are generated can be reduced simultaneously.

[0054] In order to further reduce the problem that stress concentrates at the portions located at the upward bending angle and the downward bending angle of the side wall surface 143 in the passivation layer 150 and cracks are generated, and to improve the moisture resistance ability of the device, in some embodiments, the first angle θ is within the range of 15° to 30°.

[0055] In some embodiments, as shown in FIG. 1, in the second direction T2 from the semiconductor epitaxial layer 120 to the substrate 110, in the arch shape of the connection surface 144, from the side close to the top wall surface 142, the distance from the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120 is the distance a. In an ideal situation, the arch shape of the connection surface 144 is part of or close to a perfect circle, and the arc length of the connection surface 144 can be arranged to be a*2πθ / 360. In other situations, when the arch shape of the connection surface 144 is not part of a perfect circle, the arc length can be calculated based on other calculation methods, so the calculation method of the arc length is not particularly limited.

[0056] The length of the distance a is the distance from the first point A1 connecting the connection surface 144 and the top wall surface 142 to the third point A3 where the first point A1 is projected onto the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120.

[0057] In some embodiments, as shown in FIG. 1, the line connecting the first point A1 and the third point A3 intersects the top surface of the field oxide layer 130. That is, the connection surface 144 of the anode layer 140 is completely located above the top surface of the field oxide layer 130, thus reducing the stress at the bend angle of the anode layer 140. For example, the anode layer 140 is an anode layer 140 with a uniform thickness, and when the top surface of the field oxide layer 130 is parallel to the surface of the semiconductor epitaxial layer 120, in the direction from the semiconductor epitaxial layer 120 to the substrate 110, the sum of the thickness of the anode layer 140 and the thickness of the field oxide layer 130 can be a.

[0058] In some other embodiments, as shown in FIG. 4, since the side surface of the field oxide layer 130 close to the active region 121 is inclined towards the termination region 123 of the semiconductor epitaxial layer 120, the line connecting the first point A1 and the third point A3 intersects the side surface of the field oxide layer 130, that is, at least a part of the connection surface 144 of the anode layer 140 is above the side surface of the field oxide layer 130.

[0059] Of course, in some embodiments, as shown in FIG. 5, the line connecting the first point A1 and the third point A3 does not intersect the field oxide layer 130, that is, the arched connection surface 144 is not completely located above the field oxide layer 130.

[0060] In some embodiments, the second angle α, which is the angle formed by the side wall surface 143 of the anode layer 140 and the surface of the field oxide layer 130, is in the range of 30° to 60°.

[0061] In this embodiment, through the optimization of photolithography and etching conditions, for example, through the optimization of photolithography and dry etching conditions, the second angle α, which is the angle formed by the side wall surface 143 and the surface of the field oxide layer 130, is made to be within the range of 30° to 60°. Since the side wall surface 143 of the anode layer 140 is inclined toward the active region 121 and the angle formed with the surface of the field oxide layer 130 is, for example, within the range of 30° to 60°, the passivation layer 150 extends more smoothly between the side wall surface 143 and the top wall surface 142. Therefore, it is possible to reduce the occurrence of stress concentration in the upper passivation layer 150 due to a sudden change in the angle between the side wall surface 143 and the top wall surface 142 of the anode layer 140, and reduce the failure of the device caused by moisture entering the device.

[0062] Also, since the side wall surface 143 of the anode layer 140 is inclined toward the active region 121 and the angle formed with the surface of the field oxide layer 130 is, for example, within the range of 30° to 60°, the passivation layer 150 can grow so as to climb more along the side wall surface 143 of the anode layer 140. Therefore, the formation of the passivation layer 150 is further optimized, and the reliability of the device is also optimized.

[0063] As an example, the angle formed by the side wall surface 143 and the surface of the field oxide layer 130 can be 45°.

[0064] Note that the angle formed by the side wall surface 143 and the surface of the field oxide layer 130 is an acute angle formed by the side wall surface 143 and the top surface (upper surface) on the side opposite to the end region 123 of the field oxide layer 130, that is, the inclination angle of the side wall surface 143.

[0065] The semiconductor structure 100 in this embodiment mainly refers to a silicon carbide diode structure. That is, the present invention provides a highly reliable silicon carbide diode structure. Through a metal etching method after the angle of the photoresist is optimized, the upper bending angle of the front side metal (i.e., the anode layer 140, front side metal) is formed in an arc shape, and the lower bending angle is controlled between 30° and 60°. By doing so, the problem that the stress concentrates at the bending angle due to the steep metal side wall of the anode layer and the passivation layer cracks is reduced, and the moisture resistance ability of the device is improved.

[0066] Furthermore, by forming the upper bending angle of the front side metal (i.e., the anode layer 140) in an arc shape and controlling the lower bending angle between 30° and 60°, the climbing angle of the passivation layer 150 becomes gentle, the climbing problem of the passivation layer 150 is successfully solved, and the reliability of the device is greatly improved.

[0067] In some embodiments, the connecting surface 144 includes a first point A1 connected to the top wall surface 142 and a second point A2 connected to the side wall surface 143. The point where the first point A1 is projected onto the surface on the side opposite to the substrate 110 of the semiconductor epitaxial layer 120 along the direction from the semiconductor epitaxial layer 120 to the substrate 110 is defined as the third point A3. The first angle θ, which is the angle formed by the line connecting the third point A3 and the second point A2 and the line connecting the third point A3 and the first point A1, is greater than 5° and less than 45°. And the second angle α, which is the angle formed by the side wall surface 143 of the anode layer 140 and the top surface on the side opposite to the end region 123 of the field oxide layer 130, is within the range of 30° to 60°.

[0068] By setting the first angle θ to be greater than 5° and less than 45° and setting the second angle α within the range of 30° to 60°, it is possible to reduce the stress concentration at the portions located at the upward bending angle and the downward bending angle of the side wall surface 143 in the passivation layer 150, and further reduce the problem of cracks caused by stress concentration at the portions located at the upward bending angle and the downward bending angle of the side wall surface 143 in the passivation layer 150.

[0069] In some embodiments, as shown in FIGS. 1 and 2, both the substrate 110 and the semiconductor epitaxial layer 120 can be silicon carbide. The substrate 110 has a crystal type of 4H-SiC, a thickness range of 250 μm to 350 μm, and a doping concentration in the range of 1E19 to 5E20 / cm 3 is in the range. The silicon carbide epitaxy has a thickness in the range of 5 μm to 40 μm and a concentration range of 5E15 to 5E16 / cm 3 is in.

[0070] The substrate 110 can be made of materials such as silicon (Si) and sapphire, and is used to form the semiconductor epitaxial layer 120 by heteroepitaxial growth. The deposition methods of the substrate 110 can include Chemical Vapor Deposition (CVD), Vapour Phase Epitaxy (VPE), Metal-organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Pulsed Laser Deposition (PLD), atomic layer epitaxy, Molecular Beam Epitaxy (MBE), sputtering, vapor deposition, etc. Here, the deposition method of the substrate 110 is not specifically limited.

[0071] The semiconductor epitaxial layer 120 can also achieve epitaxial growth through processes such as chemical vapor deposition, vapor phase epitaxy, metal-organic chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy. The specific structures and forming methods of the substrate 110 and the semiconductor epitaxial layer 120 can refer to the conventional semiconductor structures.

[0072] In some embodiments, as shown in FIGS. 1 and 2, the field oxide layer 130 includes a side surface adjacent to the active region 121 and a top surface on the side opposite to the termination region 123. The top surface of the field oxide layer 130 is parallel to the surface on which the field oxide layer 130 of the termination region 123 is disposed. The side surface of the field oxide layer 130 is inclined from the field oxide layer 130 towards the termination region 123.

[0073] In some embodiments, as shown in FIGS. 1 and 2, a third angle β, which is the angle formed by the side surface of the field oxide layer 130 and the surface of the termination region 123, is within the range of 30° to 60°, that is, the inclination angle of the side surface of the field oxide layer 130 is within the range of 30° to 60°.

[0074] The angle formed by the side surface of the field oxide layer 130 and the surface of the termination region 123 is an acute angle formed by the side surface of the field oxide layer 130 and the upper surface of the termination region 123, that is, the inclination angle of the side surface of the field oxide layer 130.

[0075] In some embodiments, as shown in FIGS. 1 and 2, the anode layer 140 covers the top surface of the field oxide layer 130. Specifically, the anode layer 140 covers a part of the top surface of the field oxide layer 130 while completely covering the first window 131.

[0076] In some embodiments, as shown in FIGS. 1 and 2, an implantation region (the shaded region in the figure) that contacts the anode layer 140 is provided in at least a part of the active region 121. Specifically, after forming the semiconductor epitaxial layer 120, it is necessary to simultaneously form the source area and the termination region 123 by high-energy ion injection. The implantation region can be a P-type doping structure, and the implantation concentration range is 1E17~5E18 / cm 3 and the shape of the implantation region in the active region 121 as viewed from above includes, but is not limited to, a rod shape, a square shape, a hexagonal shape or other combined structures, and the shape of the implantation region is not specifically limited here.

[0077] The semiconductor device can be a JBS device (junction barrier Schottky diode) or an MPS device (merged PIN Schottky diode) in which the anode layer 140 makes an ohmic contact with the P+ region of the active region 121 and a Schottky contact with the N region. As shown in FIG. 1, the surface of the P+ region and the surface of the N region are connected to each other, and the P+ region is one implanted region that extends to the substrate 110 along the surface of the N region.

[0078] In some other embodiments, as shown in FIG. 4, the semiconductor device is an SBD device (Schottky barrier diode) in which the metal contact method between the anode layer 140 and the active region 121 is a Schottky contact.

[0079] For the specific structures and principles of the JBS device, the MPS device, and the SBD device, reference can be made to the related descriptions of the known technologies.

[0080] The anode layer 140 can be formed by sputtering or depositing a Schottky metal and a front metal for electrode thickening. The sputtering temperature is in the range of 400°C to 500°C, and the sputtering time is in the range of 5 minutes to 10 minutes. Moreover, the specific material of the Schottky metal includes, but is not limited to, Ti, TiN, TiW, W, Mo, Ta, Ni, Al, or combinations thereof, and the thickness range is within 500 Å to 3000 Å. The specific material of the front metal for electrode thickening includes, but is not limited to, Al, Ag, Cu, or combinations thereof.

[0081] The anode layer 140 in this embodiment can be a multilayer structure, that is, it can include a Schottky metal and a front metal for electrode thickening. Of course, in other embodiments, the anode layer 140 can be a single-layer structure, such as a copper layer.

[0082] In some embodiments, the anode layer 140 is disposed to extend from the active region 121 to the top surface of the field oxide layer 130.

[0083] In some embodiments, the extension length L in the first direction T1 of the portion of the anode layer 140 located on the top surface of the field oxide layer 130 is in the range of 0 μm to 50 μm, and the first direction T1 is the direction from the active region 121 to the termination region 123. For example, the anode layer 140 is joined to the field oxide layer 130, and the passivation layer 150 overlaps the field oxide layer 130 and the anode layer 140 simultaneously.

[0084] The extension length L in the first direction T1 of the portion of the anode layer 140 located on the top surface of the field oxide layer 130 can define the length by which the passivation layer 150 overlaps the top surface of the field oxide layer 130. Thereby, by covering a certain area of the field oxide layer 130 with the anode layer 140, the risk of the active region 121 being directly exposed is reduced, and the reliability of the device is improved. Also, by covering a certain area of the field oxide layer 130 with the anode layer 140, a gap can be opened between the anode layer 140 and the periphery of the field oxide layer 130, so that the passivation layer 150 can overlap the top surface of the field oxide layer 130, and it becomes easier for the passivation layer 150 to cover the sidewall surfaces 143 of the field oxide layer 130 and the anode layer 140 simultaneously. When depositing the passivation layer 150, it is advantageous for the passivation layer 150 to climb along the sidewall surface 143 of the anode layer 140, and the forming quality of the passivation layer 150 is better.

[0085] For example, the length by which the passivation layer 150 overlaps the top surface of the field oxide layer 130 is 30 μm.

[0086] In the above embodiments, the thickness of the field oxide layer 130 is in the range of 6000 Å to 12000 Å. After the field oxide layer 130 is formed, the first window 131 can be formed by a wet etching process, and when the etching angle is in the range of 30° to 60°, the side surface of the field oxide layer 130 slopes from bottom to top and towards the termination region 123. That is, the first window 131 is trapezoidal in reverse, and the inclination angle of the periphery of the first window 131 is in the range of 30° to 60°.

[0087] In some embodiments, as shown in FIGS. 1 to 5, the semiconductor structure 100 further includes a protective layer 160. The protective layer 160 is installed to cover the entire passivation layer 150 and extend to and cover a part of the top wall surface 142 of the anode layer 140.

[0088] For example, a second window 161 penetrating through to the anode layer 140 may be formed in the protective layer 160. In this case, the anode layer 140 can be further installed to have a pad region extending from the periphery of the protective layer 160 to the active region 121. The protective layer 160 can be polyimide. After the anode layer 140 and the passivation layer 150 are formed, polyimide is spin-coated on the passivation layer 150, and after exposure and baking, the second window 161 is formed. Also, the protective layer 160 covers the entire passivation layer 150 and a part of the anode layer 140, enclosing the passivation layer 150 inside. Also, the periphery of the second window 161 is inclined to form a trapezoidal structure in reverse. By setting the thickness range of the protective layer 160 to be 3.5 μm to 12 μm, a good protective effect can be achieved.

[0089] This embodiment further provides a method for manufacturing the semiconductor structure 100 for manufacturing the above semiconductor structure 100, and the manufacturing method includes the following steps.

[0090] S1: Provide a base structure.

[0091] In some embodiments, the base structure includes a substrate 110, a semiconductor epitaxial layer 120 disposed on the substrate 110, an active region 121 and a termination region 123 disposed on the semiconductor epitaxial layer 120, and a field oxide layer 130 disposed on the semiconductor epitaxial layer 120 so as to extend from the periphery of the active region 121 to the termination region 123. The active region 121 and the termination region 123 extend away from the surface of the substrate 110 where the semiconductor epitaxial layer 120 of the substrate 110 is formed, from within the semiconductor epitaxial layer 120.

[0092] Step S1 can be performed, for example, by the following steps.

[0093] S11: Provide the substrate 110.

[0094] For example, as shown in FIG. 6, the substrate 110 can be a silicon carbide substrate 110 and is used for heteroepitaxial growth. The substrate 110 has a crystal type of 4H-SiC, a thickness range of 250 μm to 350 μm, and a doping concentration in the range of 1E19 to 5E20 / cm 3 . The deposition method of the substrate 110 can include chemical vapor deposition, vapor phase epitaxy, metal organic chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, evaporation, etc. Here, the deposition method of the substrate 110 is not specifically limited. In addition, the substrate 110 may be made of materials such as silicon and sapphire, and the material of the substrate 110 is not specifically limited either.

[0095] S12: Form a semiconductor epitaxial layer 120 on the substrate 110.

[0096] For example, as shown in FIG. 7, the semiconductor epitaxial layer 120 can be silicon carbide, and the silicon carbide epitaxy has a thickness in the range of 5 μm to 40 μm and a concentration range of 5E15 to 5E16 / cm 3It is located therein. The semiconductor epitaxial layer 120 can be epitaxially grown on the substrate 110 by processes such as chemical vapor deposition, vapor phase epitaxy, metalorganic chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, etc.

[0097] Epitaxial growth using the silicon carbide substrate 110 is a basic process, and the silicon carbide substrate 110 and silicon carbide epitaxy are obtained by S11 and S12. After forming the structure of the semiconductor epitaxial layer 120, it is necessary to form the active region 121 and the termination region 123 by implantation in the semiconductor epitaxial layer 120. The active region 121 and the termination region 123 extend away from the surface of the semiconductor epitaxial layer 120 of the substrate 110 within the semiconductor epitaxial layer 120. Specifically, the P-type doping implantation regions of the active region 121 and the termination region 123 can be simultaneously formed by high-energy ion implantation, and the implantation concentration range is 1E17~5E18 / cm 3 Therein, the shape of the implantation region in the active region 121 includes, but is not limited to, a rod shape, a square shape, a hexagonal shape, or other combined structures.

[0098] S13: Form a field oxide layer 130 on the semiconductor epitaxial layer 120.

[0099] For example, as shown in FIG. 8, the field oxide layer 130 can be grown and formed on the semiconductor epitaxial layer 120 by a CVD method (chemical vapor deposition), and the thickness range of the field oxide layer 130 is 6000A~12000A.

[0100] S14: Etch the field oxide layer 130 to form a first window 131 that exposes the active region 121.

[0101] For example, as shown in FIG. 9, the first window 131 can be formed to penetrate up to the semiconductor epitaxial layer 120 by a wet etching process. The etching angle is within the range of 30° to 60°, whereby the first window 131 is an inverted trapezoid, and the inclination angle of the periphery of the first window 131 is within the range of 30° to 60°. In actual production, the field oxide layer 130 in the active region 121 is etched at an etching angle inclined 30° to 60° from the terminal region 123 by a wet etching process, and the active region 121 is surrounded and defined by the side surface of the field oxide layer 130 that has become 30° to 60° with respect to the surface of the terminal region 123, thereby forming the first window 131 that exposes the active region 121.

[0102] S2: Form an anode layer 140 on the active region 121 and the field oxide layer 130.

[0103] In some embodiments, as shown in FIGS. 10 to 12, the anode layer 140 is disposed to extend from the active region 121 to a part of the field oxide layer 130, and the anode layer 140 includes a top wall surface 142 on the side opposite to the active region 121 and a side wall surface 143 connected to the field oxide layer 130. The side wall surface 143 of the anode layer 140 and the top wall surface 142 of the anode layer 140 are connected by a connecting surface 144, and the connecting surface 144 is formed in an arc shape so that the side wall surface 143 and the top wall surface 142 of the anode layer 140 are smoothly connected.

[0104] In some embodiments, when manufacturing the anode layer 140, an anode layer 140 having a recess 141a can be formed on the active region 121 and the field oxide layer 130. The recess 141a is disposed on the top wall surface 142 of the anode layer 140, and the periphery of the recess 141a and the side wall surface 143 of the anode layer 140 are connected by a joint portion 146. At least a part of the joint portion 146 is the connecting surface 144.

[0105] In actual production, as shown in FIG. 10, first, a metal layer 145 can be formed on the field oxide layer 130 and the semiconductor epitaxial layer 120 by sputtering or evaporation. Then, as shown in FIG. 11, a photoresist is applied to the metal layer 145, and the photoresist is exposed and developed at an angle planned to be inclined toward the active region 121 to form a photoresist layer 147. The planned angle is within the range of 30° to 60°, whereby the peripheral inclination angle of the photoresist layer 147 is within the range of 30° to 60°. Finally, as shown in FIG. 12, using the photoresist layer 147 as a mask, the metal layer 145 is etched to form an anode layer 140 having an arch-shaped connection surface 144.

[0106] Since the photoresist layer 147 is manufactured early, the anode layer 140 can be formed into a metal form with a curvature by etching. The side wall surface 143 of the anode layer 140 has an arc-shaped upper bending angle, and the inclination angle of the lower bending angle is within the range of 30° to 60°. And since the periphery of the anode layer 140 needs to overlap the field oxide layer 130, as shown in FIG. 13, the distance between the periphery of the anode layer 140 and the periphery of the passivation layer 150 is within the range of 0 μm to 50 μm.

[0107] For example, when etching the metal layer 145, such as when etching the metal layer 145 by dry etching, etching along the periphery of the photoresist layer 147 can form a side wall surface 143 of the anode layer 140 whose angle formed with the top surface on the side opposite to the terminal region 123 of the field oxide layer 130 is within the range of 30° to 60°. Specifically, by etching along the periphery of the photoresist layer 147, an anode layer 140 can be formed that is installed to extend from the active region 121 to the top surface of the field oxide layer 130, and the extension length in the first direction T1 from the active region 121 to the terminal region 123 is 0 μm to 50 μm.

[0108] In some embodiments, after forming the anode layer 140 by etching, the photoresist layer 147 can be removed, and a protrusion 141 is formed at a portion corresponding to the periphery of the first window 131 of the anode layer 140. The protrusion 141 can surround and define a concave portion 141a. The side wall surface 143 of the anode layer 140 extends from the protrusion 141 to the field oxide layer 130, and the connecting portion between the surface of the protrusion 141 and the side wall surface 143 of the anode layer 140 is an arc.

[0109] S3: Form a passivation layer 150 on the field oxide layer 130 and the anode layer 140.

[0110] For example, as shown in FIG. 13, the passivation layer 150 is installed to extend while covering a part of the top wall surface 142 of the anode layer 140 while covering the field oxide layer 130. During manufacturing, first, a high resistance material layer is deposited on the field oxide layer 130 and the anode layer 140, and then the high resistance material layer is etched to form a passivation layer 150 that covers the side wall surface 143 of the anode layer 140 and extends to the connection surface 144 to cover the connection surface 144.

[0111] In actual manufacturing, the passivation layer 150 is deposited by CVD, and the passivation layer 150 extends to the protrusion 141 to cover the protrusion 141 while covering the side wall surface 143. The passivation layer 150 may be a two-layer medium of silicon oxide and silicon nitride, or may be a silicon oxynitride medium. The thickness of the passivation layer 150 is in the range of 8000 Å to 15000 Å.

[0112] When depositing the passivation layer 150, the width by which the passivation layer 150 covers the joint surface 144 of the anode layer 140 should not be too large. For example, the joint width range by which the passivation layer 150 covers the joint surface 144 of the anode layer 140 is within the range of 2 μm to 100 μm, so as to avoid the passivation layer 150 covering too wide a range, and further suppress the problem that the shear force is too large due to different coefficients of thermal expansion, resulting in cracks in the passivation layer 150. Of course, in some embodiments, when the joint 146 includes the joint surface 144 and the transition surface, as shown in FIG. 3, the joint width range by which the passivation layer 150 covers the joint 146 of the anode layer 140 should also not be too large and should be within the range of 2 μm to 100 μm.

[0113] S4: Form a protective layer 160 on the passivation layer 150.

[0114] For example, as shown in FIG. 1, the protective layer 160 covers the passivation layer 150 and the anode layer 140. The protective layer 160 is formed by spin-coating polyimide on the passivation layer 150, followed by exposure and baking, and a second window 161 is formed. Also, the thickness range of the protective layer 160 is from 3.5 μm to 12 μm.

[0115] According to the above content, for the semiconductor structure 100 provided in this embodiment, a first window 131 is formed in the field oxide layer 130, and the anode layer 140 is formed to cover the first window 131, so that a protrusion 141 is formed at a portion corresponding to the periphery of the first window 131 of the anode layer 140. The side wall surface 143 of the anode layer 140 extends from the protrusion 141 to the field oxide layer 130. The joint portion between the surface of the protrusion 141 and the side wall surface 143 of the anode layer 140 is arc-shaped. The passivation layer 150 extends to the protrusion 141 so as to cover the protrusion 141 while covering the side wall surface 143 of the anode layer 140. By making the upper bending angle of the side wall surface 143 of the anode layer 140, that is, the joint portion between the side wall surface 143 and the protrusion 141, arc-shaped, the connection between the side wall surface 143 of the anode layer 140 and the protrusion 141 is made smooth, avoiding a sudden change in the inclination angle, and preventing stress from concentrating at a portion of the passivation layer 150 located at the upper bending angle of the side wall surface 143. Compared with the prior art, the semiconductor structure 100 of this embodiment reduces the crack problem caused by stress concentration at the bending angle due to the sharpness of the anode layer 140, and improves the moisture resistance of the device.

[0116] At the same time, by reasonably regulating the width of the passivation layer 150, it is possible to avoid the situation that the coverage range of the passivation layer 150 is too wide, and further suppress the problem that cracks occur in the passivation layer 150 due to too large a shear force caused by different thermal expansion coefficients.

[0117] Since the connection between the side wall surface 143 and the top wall surface 142 is smooth, it is beneficial for the upward extension of the passivation layer 150 when depositing the passivation layer 150. Thereby, the creeping problem of the passivation layer 150 is well solved, the forming quality of the passivation layer 150 is better, and the reliability of the device is improved.

[0118] The present invention has been described in connection with what is considered to be exemplary embodiments. However, it is understood that the present disclosure is not limited to the disclosed embodiments, but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation that includes all such modifications and equivalent arrangements.

[0119] The above embodiments are illustrative of the principles and effects of the present invention and do not limit the present invention. Those skilled in the art can make some changes and modifications to the above embodiments on the premise of not departing from the spirit and scope of the present invention. Therefore, all changes and modifications made on the premise that those skilled in the art do not depart from the gist of the present invention should be included in the protection scope of the present invention.

Industrial Applicability

[0120] The semiconductor structure and the method of manufacturing the semiconductor structure of the present invention are suitable for providing a highly reliable semiconductor structure.

Explanation of Signs

[0121] 100 Semiconductor structure 110 Substrate 120 Semiconductor epitaxial layer 121 Active region 123 Terminal region 130 Field oxide layer 131 First window 140 Anode layer 141 Protrusion 141a Recess 142 Top wall surface 143 Side wall surface 144 Connection surface 145 Metal layer 146 Junction 147 Photoresist layer 150 Passivation layer 160 Protection layer 161 Second window A1 First point A2 Second point Point 3 of A3 Distance a Extended length L First direction T1 Second direction T2 First angle θ Second angle α Third angle β

Claims

1. A substrate, a semiconductor epitaxial layer disposed on the substrate, an active region and a termination region disposed within the semiconductor epitaxial layer, a field oxide layer disposed on the semiconductor epitaxial layer so as to extend from a periphery of the active region to the termination region, an anode layer including a top wall surface disposed on a side opposite to the active region and extending from a part of the active region to a part of the field oxide layer, a side wall surface connected to the field oxide layer, and a connection surface connecting between the side wall surface and the top wall surface; and a passivation layer disposed along the side wall surface so as to cover at least the connection surface while covering the field oxide layer, wherein the connection surface is formed in an arc shape such that the side wall surface and the top wall surface of the anode layer are smoothly connected, the field oxide layer includes a side surface proximate to the active region and a top surface on a side opposite to the termination region, the top surface of the field oxide layer is parallel to a surface on which the field oxide layer of the termination region is disposed, the side surface of the field oxide layer is inclined from the periphery of the active region to the termination region, and a third angle, which is an angle formed by the side surface of the field oxide layer and the surface of the termination region, is in a range of 30° to 60°. A semiconductor structure characterized by this.

2. The semiconductor structure according to claim 1, wherein the side wall surface of the anode layer is in a slope shape extending so as to be inclined from the field oxide layer to the active region.

3. The connection surface includes a first point connected to the top wall surface and a second point connected to the side wall surface. When a point where the first point is projected onto a surface on a side opposite to the substrate of the semiconductor epitaxial layer along a direction from the semiconductor epitaxial layer to the substrate is defined as a third point, a first angle, which is an angle formed by a line connecting the third point and the second point and a line connecting the third point and the first point, exceeds 5°. The semiconductor structure according to claim 2, characterized by this.

4. The semiconductor structure according to claim 3, wherein the first angle is less than 45°.

5. The semiconductor structure according to claim 4, wherein the first angle is in a range of 15° to 30°.

6. The second angle, which is the angle formed by the side wall surface of the anode layer and the top surface on the side opposite to the terminal region of the field oxide layer, is within the range of 30° to 60°. The semiconductor structure according to claim 4, wherein the semiconductor structure is characterized in that.

7. The anode layer covers at least a part of the top surface of the field oxide layer. The semiconductor structure according to claim 1, wherein the semiconductor structure is characterized in that.

8. The extension length in the first direction from the active region to the terminal region of the portion of the anode layer covering the top surface of the field oxide layer is 0 μm to 50 μm. The semiconductor structure according to claim 1, wherein the semiconductor structure is characterized in that.

9. A recess is provided on the top wall surface of the anode layer. The periphery of the recess and the side wall surface of the anode layer are connected by a joint. At least a part of the joint is the connection surface. The semiconductor structure according to claim 1, wherein the semiconductor structure is characterized in that.

10. The entire joint is the connection surface. The semiconductor structure according to claim 9, wherein the semiconductor structure is characterized in that.

11. The joint is composed of the connection surface and a part of the top wall surface. The passivation layer extends to the joint so as to cover the joint while covering the side wall surface of the anode layer. The semiconductor structure according to claim 9, wherein the semiconductor structure is characterized in that.

12. The length of the portion of the passivation layer covering the joint is 2 μm to 100 μm. The semiconductor structure according to claim 11, wherein the semiconductor structure is characterized in that.

13. The semiconductor structure according to claim 1, further comprising a protective layer installed so as to extend and cover a part of the top wall surface of the anode layer while covering the entire passivation layer.

14. Step a of providing a base structure including a substrate, a semiconductor epitaxial layer installed on the substrate, an active region and a terminal region installed in the semiconductor epitaxial layer, and a field oxide layer installed in the semiconductor epitaxial layer so as to extend from the peripheral portion of the active region to the terminal region. Forming an anode layer on the active region and the field oxide layer, wherein the anode layer is disposed to extend from a part of the active region to the field oxide layer, and the anode layer includes a top wall surface on a side opposite to the active region, a side wall surface connected to the field oxide layer, and a connection surface connecting between the side wall surface and the top wall surface, and the connection surface is formed in an arch shape so that the side wall surface and the top wall surface of the anode layer are smoothly connected; step b Forming a passivation layer on the field oxide layer and the anode layer, wherein the passivation layer is disposed to extend along the side wall surface so as to cover at least the connection surface while covering the field oxide layer; step c In step b Step b-1 of forming a metal layer on the field oxide layer and the semiconductor epitaxial layer Step b-2 of applying a photoresist to the metal layer Exposing and developing the photoresist at a predetermined angle inclined toward the active region from the metal layer to form a photoresist layer inclined at the predetermined angle; step b-3 Etching the metal layer to form the anode layer; step b-4, a method for manufacturing a semiconductor structure, characterized by the above

15. In step a Step a-1 of forming the semiconductor epitaxial layer on the substrate Forming the active region and the termination region on the semiconductor epitaxial layer using an implantation technique, wherein the active region and the termination region extend away from the surface of the substrate where the semiconductor epitaxial layer is formed within the semiconductor epitaxial layer; step a-2 Step a-3 of forming the field oxide layer on the semiconductor epitaxial layer Etching the field oxide layer to form a first window for exposing the active region; step a-4, a method for manufacturing a semiconductor structure according to claim 14, characterized by the above

16. The predetermined angle is within the range of 30° to 60° In step b-4 Etching along the periphery of the photoresist layer to form a sidewall surface of the anode layer, the angle formed by the top surface on the side opposite to the terminal region of the field oxide layer being within the range of 30° to 60°, the manufacturing method of the semiconductor structure according to claim 14, characterized in that it includes this.

17. In step b-4, Etching along the periphery of the photoresist layer to form the anode layer, The anode layer is installed on the top surface so as to extend from the active region to the top surface on the side opposite to the terminal region of the field oxide layer, and The manufacturing method of the semiconductor structure according to claim 14, characterized in that the extension length in the first direction from the active region to the terminal region of the portion of the anode layer installed on the top surface of the field oxide layer is 0 μm to 50 μm.

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