Substrate for semiconductor packaging, semiconductor package, and method for manufacturing substrate for semiconductor packaging

Abstract

To provide a substrate for semiconductor packaging, a semiconductor package, and a method for manufacturing a substrate for semiconductor packaging that ensure thermal stability while not substantially increasing the thickness of the semiconductor package.SOLUTION: A substrate for semiconductor packaging includes a substrate 100 including one surface 110, another surface 140 opposite the one surface, a surface 120 with one surface recessed, and a sidewall 130 connecting the one surface and the recessed surface, and a plurality of first vias 121 penetrating the recessed surface and the other surface, and the plurality of first vias contain thermally conductive material, thereby the substrate has an excellent heat release effect and prevents the warping phenomenon of the substrate surface due to thermal expansion.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments relate to semiconductors, and more specifically, to a substrate for semiconductor packaging, a semiconductor package, and a method of manufacturing a substrate for semiconductor packaging.

Background Art

[0002] In fabricating an electronic component, forming a circuit on a semiconductor wafer is referred to as a front-end (FE) process, and assembling the wafer into a state where it can be used as an actual product is referred to as a back-end (BE) process, and this back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nanometer line widths, tens of millions of cells, high-speed operation, and a large amount of heat dissipation. However, relatively, there is no technology that perfectly packages this.

[0004] In particular, in a semiconductor package on which a heat-generating element is mounted, if heat dissipation is not performed well, a warpage phenomenon may occur due to the difference in the coefficient of thermal expansion between the components of the package. This increases the defect rate of the semiconductor package. Therefore, conventional semiconductor packages have tried to dissipate heat by separately providing an interposer layer or a heat dissipation layer between packages, but this has the problem of increasing the thickness of the semiconductor package.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] An object of an embodiment is to provide a substrate for semiconductor packaging, a semiconductor package, and a method for manufacturing a substrate for semiconductor packaging, which ensure thermal stability while not substantially increasing the thickness of the semiconductor package.

[0007] The technical problems of the embodiment are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] To achieve the above object, a substrate for semiconductor packaging according to an embodiment includes a substrate including one surface, another surface facing the one surface, a surface where the one surface is recessed, and sidewalls connecting the one surface and the recessed surface, and a plurality of first vias penetrating the recessed surface and the another surface, wherein the plurality of first vias include thermal vias containing a thermally conductive material.

[0009] The substrate may include a glass substrate.

[0010] The substrate may include an insulator substrate.

[0011] The surface roughness (Ra) of the one surface and the another surface may each be 10 Å or less.

[0012] The substrate may further include a plurality of second vias penetrating the one surface and the another surface.

[0013] The area of the recessed surface may be 10% or more of the one surface.

[0014] To achieve the above object, a semiconductor package according to an embodiment includes a substrate including one surface, another surface facing the one surface, a surface in which the one surface is recessed, and sidewalls connecting the one surface and the recessed surface, a plurality of first vias penetrating the recessed surface and the other surface, and an element portion disposed on the recessed surface. The plurality of first vias include thermal vias containing a thermally conductive material.

[0015] The substrate may include a glass substrate.

[0016] The substrate may include an insulator substrate.

[0017] The surface roughness (Ra) of the one surface and the other surface may each be 10 Å or less.

[0018] The substrate may further include a plurality of second vias penetrating the one surface and the other surface.

[0019] The element portion may include active elements.

[0020] The semiconductor package may further include a filler covering the element portion.

[0021] The filler may have a lower coefficient of thermal expansion than the substrate.

[0022] The angle between the sidewall and the recessed surface may be an obtuse angle.

[0023] To achieve the above object, a method of manufacturing a substrate for semiconductor packaging according to an embodiment includes a preparation step of forming defects at a predetermined position on one surface of the substrate, another surface facing the one surface, or both of these surfaces, a via formation step of adding an etching solution to the substrate to form a plurality of vias and a recessed surface, including a filling step of filling the plurality of vias with a thermally conductive material.

Advantages of the Invention

[0024] The semiconductor packaging substrate, semiconductor package, and semiconductor packaging substrate produced by the manufacturing method of the embodiment have excellent heat dissipation effects.

[0025] In addition, the semiconductor packaging substrate, semiconductor package, and semiconductor packaging substrate produced by the manufacturing method of the embodiment have the effect of being able to relieve the warping phenomenon of the substrate surface due to thermal expansion.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0027] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the embodiments belong can easily implement them. However, the embodiments can be realized in various different forms and are not limited to the embodiments described herein. The same reference numerals are assigned to similar parts throughout the specification.

[0028] Throughout this specification, the term "these combinations" included in the Markush-form expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-form expression, and means including one or more selected from the group consisting of the said components.

[0029] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. Also, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0030] In this specification, the "~" system may mean including a compound corresponding to "~" or a derivative of "~" in the compound.

[0031] In this specification, the meaning that B is located on A means that B is located directly in contact with A or B is located on A while another layer is located between them, and is not construed as being limited to B being located in contact with the surface of A.

[0032] In this specification, the meaning that B is connected to A means that A and B are directly connected or A and B are connected via other components between them, and is not construed as being limited to A and B being directly connected unless otherwise specified.

[0033] In this specification, unless otherwise specified, singular expressions are construed in a sense that includes singular or plural as construed in the context.

[0034] In this specification, a substrate on which no element is mounted is referred to as a substrate for semiconductor packaging, and a substrate on which an element is mounted is referred to as a semiconductor package. However, additional elements can be further mounted on the semiconductor package.

[0035] In the process of developing a semiconductor device that is more integrated and can exhibit high performance with a thin thickness, the inventors of the embodiments recognized that not only the element itself but also the part related to packaging is an important factor in improving performance. Conventionally, packaging substrates of two or more layers such as an interposer and an organic substrate have been applied on a motherboard. However, the inventors attempted to apply a single-layer packaging substrate. And in that process, when forming a thermal via in a recess of the packaging substrate, it was confirmed that it can assist in heat dissipation of the semiconductor device and prevent the warping phenomenon of the substrate surface due to thermal expansion, and embodiments are presented.

[0036] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0037] FIG. 1 is a conceptual diagram of a substrate for a semiconductor package according to an embodiment. FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1. FIGS. 3 and 4 are schematic cross-sectional views of semiconductor packages according to other embodiments taken along line A-A' of FIG. 1.

[0038] Referring to FIGS. 1 and 2, substrates for semiconductor packaging according to some embodiments include a substrate 100 and a first via 121.

[0039] The substrate 100 can include a first surface 110, a second surface 140 opposite to the first surface, a recessed surface 120 where the first surface is recessed, and a sidewall 130 connecting the first surface and the recessed surface.

[0040] The substrate 100 may be, for example, a ceramic substrate or a glass substrate.

[0041] Exemplarily, a silicon-based ceramic substrate, a glass-based ceramic substrate, etc. may be applied as the ceramic substrate. The silicon-based ceramic substrate may be a substrate that partially or entirely includes a silicon substrate, a silicon carbide substrate, etc. The glass-based ceramic substrate may be a substrate that partially or entirely includes a quartz substrate, a sapphire substrate, etc.

[0042] Exemplarily, an alkali borosilicate plate glass, a non-alkali alkaline earth borosilicate plate glass, etc. may be applied as the glass substrate, and any plate glass applicable as a component of an electronic product is applicable.

[0043] The glass substrate can be manufactured in the form of a large panel. Therefore, when applying a glass substrate to the substrate 100, mass production is relatively easy and the processability can be improved. In this case, it is relatively easy to increase the area of the recessed surface 120 described later.

[0044] The plate glass that is a glass substrate is an insulator by itself. Therefore, when applying a glass substrate to the substrate 100, coating of an insulating layer on the inner diameter surfaces of the plurality of first vias 121 and the plurality of second vias 122 described later is not essential. Through this, the manufacturing process of the semiconductor package can be further simplified.

[0045] The substrate 100 may have a thickness (h1) of 30 μm or more, 50 μm or more, 100 μm or more, 250 μm or more, 400 μm or more, or 500 μm or more. The substrate may have a thickness of 3000 μm or less, 1000 μm or less, 300 μm or less, 200 μm or less, or 150 μm or less. When the substrate is applied within such a thickness range, it can have excellent usability as a substrate for semiconductor packaging.

[0046] When applying a glass substrate to the substrate 100, one surface 110 and the other surface 140 of the substrate can have flat surface characteristics.

[0047] Specifically, the surface roughness (Ra) of one surface and the other surface of the substrate may be 10 Å or less, 5 Å or less, or 2 Å or less. In this case, it may be relatively easy to form a fine pattern on the substrate 100. The surface roughness (Ra) may be 0.1 Å or more.

[0048] For the measurement of the surface roughness (Ra), a normal method for measuring the surface roughness of a substrate can be applied. Exemplarily, it can be measured by a method conforming to SEMI D7-97 "Method for Measuring the Surface Roughness of FPD Glass Substrates".

[0049] When applying a glass substrate as the substrate 100, the recessed surface can have a very low surface roughness.

[0050] Specifically, the surface roughness (Ra) of the recessed surface 120 may be 10 Å or less, 5 Å or less, or 2 Å or less. The surface roughness (Ra) may be 0.1 Å or more.

[0051] Further, the recessed surface 120 may have a slight difference between the area of the recessed surface as seen from above the opening of the recessed surface 120 and the area measured along the actual recessed surface. Specifically, the recessed surface 120 is generally more uneven than the surface before being recessed, and thus can have a relatively larger surface area.

[0052] In an embodiment, when the entire area of the recessed surface as seen from above the opening is taken as 100%, the difference from the area measured along the recessed surface may be 0.1 to 10%, may be only 0.1 to 5%, or may be only 0.1 to 3%. Since the surface of the substrate tends to show a larger area measured along the recessed surface, the area measured along the recessed surface may be 100.1% to 110%, 100.1% to 105%, or 100.1% to 103% of the area of the recessed surface as seen from above the opening.

[0053] This is a characteristic that is difficult to obtain in a conventional prepreg-based substrate, and the surface roughness of the recessed surface can be further reduced by applying a process including etching to the recessed surface.

[0054] When applying a glass substrate to the substrate 100, it is easy to increase the area of the recessed surface 120. The recessed surface 120 may be 10% or more, 20% or more, 30% or more, or 40% or more of the total area of one surface before being recessed. The recessed surface 120 may be 70% or less, 60% or less, or 50% or less of the total area of one surface before being recessed. When applying the recessed surface 120 within such an area range to the substrate 100, a large number of elements can be arranged to be embedded inside the substrate, so that a more integrated semiconductor package can be obtained.

[0055] The plurality of first vias 121 include thermal vias.

[0056] The plurality of first vias 121 may include conductive vias that electrically connect the element portion 200 and the printed circuit board 500.

[0057] The plurality of first vias 121 may include thermal vias and conductive vias.

[0058] The thermal via can be connected to a separate heat-generating structure. The yorbia can be grounded. The thermal via can be configured not to transmit an electrical signal to the element portion.

[0059] The thermal via may include a thermally conductive material. The above-mentioned thermally conductive material is applicable as long as it is a thermally conductive material applicable to the packaging substrate. For example, the thermally conductive material may be gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), or a combination thereof. The thermally conductive material may have a thermal conductivity of 200 W / m·K or more, 300 W / m·K or more, or 400 W / m·K or more. The upper limit of the thermal conductivity of the thermally conductive material is not particularly limited, but may be, for example, 5000 W / m·K or less.

[0060] At least a part of the plurality of first vias 121 may be arranged to overlap with a part of the element portion 200 described later in the third direction Z. The plurality of first vias 121 can transfer the heat generated when a heating element is included in the element portion 200 in the third direction Z. Therefore, the plurality of first vias 121 can reduce the thermal resistance of the substrate. Thereby, the plurality of first vias 121 can prevent or mitigate the warpage phenomenon that may occur on the surface of the substrate and improve the performance of the semiconductor package.

[0061] Referring to FIG. 3, a semiconductor packaging substrate according to some embodiments may include a plurality of second vias 122 that penetrate one surface 110 and the other surface 140 of the substrate 100.

[0062] The plurality of second vias 122 may be, for example, conductive vias. When the plurality of second vias 122 are conductive vias, the plurality of second vias 122 may include a conductive material. The plurality of second vias 122 can enable an upper layer 400 disposed on one surface 110 of the substrate 100 described below and a printed circuit board 500 disposed on the other surface 140 described below to exchange electrical signals.

[0063] Since other descriptions of the substrate for semiconductor packaging overlap with the above descriptions, the description thereof is omitted.

[0064] Referring to FIG. 4, a semiconductor package according to some embodiments may further include an element part 200 on the substrate for semiconductor packaging described above.

[0065] The upper surface of the element part 200 may be formed lower than the upper surface of the one surface 110. In this case, the recess may further include a filler 300 covering the element part, making it relatively easy to compensate for the step between the one surface and the recessed surface.

[0066] Alternatively, the upper surface of the element part 200 may also be formed substantially on the same plane as the upper surface of the one surface 110 (not shown). In this case, the recess can fill the empty space using a relatively small amount of the filler 300. Specifically, the element part 200 may be disposed so as to be embedded inside the substrate 100. That is, the semiconductor package 1 may be an embedded package in which the element part 200 is disposed so as to be embedded inside the substrate 100.

[0067] In the drawings such as FIGS. 1, 4 to 8, the element part 200 is shown as having one element disposed therein, but the embodiments are not limited thereto.

[0068] That is, two or more elements may be stacked in the third direction Z. In some other embodiments, two or more semiconductor chips may be spaced apart in the first direction X or the second direction Y.

[0069] The element portion 200 can include an active element. For example, it can include any one of an Application Processor (AP), a Power Management Integrated Circuit (PMIC), a Central Processing Unit (CPU), a controller, and an Application Specific Integrated Circuit (ASIC).

[0070] The element portion 200 can include a passive element. For example, it can include any one of a capacitor, a resistor, and an inductor.

[0071] The element portion 200 can include both an active element and a passive element.

[0072] The element portion 200 can be electrically connected to the substrate 100. Although not shown in the figure, for example, the element portion 200 and the substrate 100 may be connected through a Wire Bonding method. Also, the element portion 200 and the substrate 100 may be connected through a method using ball-shaped bumps (Flip Chip, FC). However, the connection method is not limited thereto.

[0073] Other descriptions of the substrate for semiconductor packaging are repetitive with the above descriptions, so the description thereof is omitted.

[0074] Referring to FIG. 5, semiconductor packages according to some embodiments may include a plurality of second vias 122 that penetrate through one surface 110 and the other surface 140 of the substrate 100.

[0075] The plurality of second vias 122 may be, for example, conductive vias. When the plurality of second vias 122 are conductive vias, the plurality of second vias 122 may include a conductive material. The plurality of second vias 122 may be electrically connected to the upper layer 400.

[0076] Referring to FIG. 6, semiconductor packages according to some embodiments may further include a filler 300. Specifically, the filler 300 may be disposed to surround the element portion 200. If the height of the element portion is h4 and the depth of the recessed surface is h3, the filler can be disposed to enclose the difference therebetween. The filler can flatten the recessed surface. Although not shown in the drawings, a redistribution layer can be disposed in the above-mentioned filler. In FIG. 6, the side wall 130 of the substrate 100 is shown as being separated from the element portion 200, but it is not limited thereto. In some other embodiments, the side wall 130 of the substrate 100 can be at least partially in direct contact with the element portion 200. In this case, the filler can be disposed to cover the upper surface of the element portion 200 and fill the space between the side wall of the substrate and the element portion.

[0077] The filler 300 may be a thermosetting material, a thermoplastic material, a UV curable material, etc. The filler 300 may be a silicon-based material, an epoxy-based material, an acrylic-based material, etc. The filler 300 may be a polymer material, or an organic-inorganic composite material in which inorganic particles are dispersed in a polymer material. The filler 300 may be ABF (Ajinomoto Build-up Film, ABF), EMC (Epoxy Molding Compound), or LCP (liquid crystal polymer, LCP). However, the filler is not limited to those mentioned above.

[0078] Since other descriptions of the substrate for semiconductor packaging and the semiconductor package overlap with the above descriptions, the description thereof will be omitted.

[0079] Referring to FIG. 7, in some embodiments, the angle between the side wall 130 and the recessed surface 120 of the semiconductor package may be an obtuse angle. Exemplarily, the obtuse angle can be 91 degrees or more, 93 degrees or more, or 95 degrees or more. Also, the obtuse angle can be 130 degrees or less, 120 degrees or less, or 110 degrees or less. In this case, the amount of the filler 300 required for the process can be reduced. Since other descriptions of the substrate for semiconductor packaging and the semiconductor package overlap with the above descriptions, the description thereof will be omitted.

[0080] Referring to FIG. 8, in some embodiments, the semiconductor device may further include an upper layer 400 and a printed circuit board 500 on the above-described semiconductor package.

[0081] The upper layer 400 may have a layer capable of exchanging electrical signals disposed thereon. For example, it may include a redistribution layer (RDL), a layer in which one or more semiconductor packages are stacked. However, it is not limited thereto as long as it is a structure that can be stacked on the substrate for semiconductor packaging. For example, the upper layer may include a silkscreen layer that does not exchange electrical signals.

[0082] The printed circuit board 500 may be electrically connected to the upper layer 400 via the second via 122.

[0083] Hereinafter, a method for manufacturing a substrate for semiconductor packaging according to still another embodiment of the embodiment will be described.

[0084] The manufacturing method of the substrate for semiconductor packaging of the embodiment includes a preparation step of forming defects at predetermined positions on one surface of the substrate, the other surface facing the one surface, or both of them; a via formation step of adding an etching solution to the predetermined positions to form vias and recessed surfaces; and a filling step of filling the vias with a substance, thereby manufacturing the substrate for semiconductor packaging described above.

[0085] In the via formation step, on one surface and the other surface of the substrate, any one selected from the group consisting of i) a via formation defect penetrating the substrate, ii) a recessed surface formation defect, iii) a via formation defect penetrating the recessed surface and the other surface, and combinations thereof is formed. After the formation of i) and ii), iii) may be formed separately. Also, after the formation of ii), both i) and iii) may be formed. In the etching, after masking the surface that is not to be etched, an etching solution is added so that a selectively predetermined portion (the unmasked portion) can be etched, and the etching rate of the portion where the defect is formed is made to be etched faster than the portion where no defect is formed, so that a recessed surface and vias can be formed.

[0086] Among the plurality of vias, a via overlapping with the recess in the third direction Z can form a first via.

[0087] Among the plurality of vias, a via not overlapping with the recess in the third direction Z can form a second via.

[0088] The filling step can include a thermal via filling step of filling at least a part of the vias with a thermally conductive material and a conductive via filling step of filling at least a part of the vias with a conductive material. The thermal via filling step and the conductive via filling step can be performed simultaneously. In this case, more efficient progress of the process is possible.

[0089] The manufacturing method of the substrate for semiconductor packaging will be described in more detail. 1) Preparation Step (Glass Defect Formation Process): Prepare a substrate having a flat one surface and the other surface, and form a defect at a predetermined position of the substrate for the formation of vias. The glass substrate may be applied to the substrate. For example, alkali borosilicate plate glass, non-alkali alkaline earth borosilicate plate glass, etc. may be applied, and any plate glass applicable as a component of an electronic product is applicable. As a commercially available product, products manufactured by manufacturing manufacturers such as Corning, Schott, AGC, etc. may be applied. For the formation of the defect (groove), methods such as mechanical etching, laser irradiation, etc. may be applied.

[0090] 2) Via Formation Step: The substrate with the defect formed forms a plurality of vias and / or recesses through a physical or chemical etching process. When applying a glass substrate to the substrate, the substrate itself with the defect can be etched.

[0091] For the etching, after masking a part of the target surface before the etching process, an etching solution can be added so that a predetermined part (the unmasked part) is selectively etched.

[0092] The etching can form a recessed surface and / or a via by etching the part where the defect is formed at a faster etching rate than the part where the defect is not formed.

[0093] In this case, the annoyance of the process of applying and removing the masking film, etc. can be eliminated, and the process can be simplified. In such a case, the thickness of the substrate with vias may be slightly thinner than the thickness of the original substrate.

[0094] 3) Filling Step: The inner diameter surfaces of the plurality of vias can be coated with an insulating layer. However, when applying a glass substrate to the substrate, the coating of the insulating layer can be omitted. In this case, the surface of the substrate and the inner diameter surfaces of the plurality of vias can be sputtered with a glass-metal adhesive or the like having excellent adhesion to glass (not shown). On the other hand, a conductive material or a thermally conductive material can be sputtered on the glass-metal adhesive to form a seed layer (not shown). Thereafter, a current is applied to the seed layer with the vias filled with a conductive material or a thermally conductive material (not shown). After a sufficient time has elapsed, the vias filled with the conductive material or the thermally conductive material are formed through chemical-mechanical polishing (CMP) on one surface and the other surface of the substrate (not shown).

[0095] On the other hand, a first via at a predetermined position among the vias can be filled with a thermally conductive material through a first via filling process. Exemplarily, the thermally conductive material may be gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), or a combination thereof. However, the thermally conductive material is not limited thereto as long as it is a thermally conductive material applicable to a packaging substrate. A second via at a predetermined position can be filled with a conductive material through a second via filling process. Also, the thermally conductive material and the conductive material can include the same substance. Exemplarily, copper (Cu) can be included as a filling material for the first via and the second via because of its high thermal conductivity and electrical conductivity. In this case, the first via filling process and the second via filling process can be performed simultaneously.

[0096] As described in detail above with respect to the preferred embodiments, the scope of the rights is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concepts defined in the appended claims also belong to the scope of the rights.

Description of Reference Numerals

[0097] 10 Defect 100 Substrate 110 One Surface 120 Recessed surface 121 First via 122 Second via 130 Side wall 140 Other surface 200 Element part 300 Filling material 400 Upper layer 500 Printed circuit board

Claims

1. A substrate including one surface, another surface facing the one surface, a surface recessed in the one surface, and sidewalls connecting the one surface and the recessed surface; a plurality of first vias penetrating the recessed surface and the another surface; wherein the plurality of first vias are thermal vias including a thermally conductive material; a substrate for semiconductor packaging, wherein a surface roughness of the recessed surface is from 0.1 Å to 10 Å.

2. The substrate for semiconductor packaging according to claim 1, wherein the substrate includes a glass substrate.

3. The substrate for semiconductor packaging according to claim 1, wherein the substrate includes an insulator substrate.

4. The substrate for semiconductor packaging according to claim 1, wherein surface roughnesses (Ra) of the one surface and the another surface are each 10 Å or less.

5. The substrate for semiconductor packaging according to claim 1, wherein the substrate further includes a plurality of second vias penetrating the one surface and the another surface.

6. The substrate for semiconductor packaging according to claim 1, wherein an area of the recessed surface is 10% or more of the one surface.

7. A substrate including one surface, another surface facing the one surface, a surface recessed in the one surface, and sidewalls connecting the one surface and the recessed surface; a plurality of first vias penetrating the recessed surface and the another surface; an element portion disposed on the recessed surface; wherein the plurality of first vias are thermal vias including a thermally conductive material; a semiconductor package, wherein a surface roughness of the recessed surface is from 0.1 Å to 10 Å.

8. The semiconductor package according to claim 7, wherein the element portion includes an active element.

9. further including a filler covering the element portion; the semiconductor package according to claim 7, wherein the filler has a lower coefficient of thermal expansion than the substrate.

10. The semiconductor package according to claim 7, wherein an angle between the sidewall and the recessed surface is an obtuse angle.

11. A preparation step of forming a defect at a predetermined position on one surface of the substrate, another surface facing the one surface, or both of them; a via formation step of adding an etching solution to the substrate to form a plurality of vias and a recessed surface; a filling step of filling the plurality of vias with a thermally conductive material; a method for manufacturing a semiconductor package, wherein a surface roughness of the recessed surface is from 0.1 Å to 10 Å.

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