A package comprising an integrated device configured for a plurality of possible power resources

Abstract

A package including a substrate and an integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where when the switch is turned on, the switch is configured to allow at least a portion of the power resource from the second power resource to contribute to the first core of the integrated device.

Description

Priority Claim

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 17 / 162,621, filed on January 29, 2021, the entire contents of which are hereby incorporated by reference herein as if fully set forth below and for all applicable purposes.

Technical Field

[0002]

[0002] Various features relate to packages and substrates, and more particularly to packages that include a substrate and an integrated device.

Background Art

[0003]

[0003] A package may include a substrate and an integrated device. Power to the integrated device may be provided through interconnects of the substrate. How power to the integrated device is routed through the substrate can affect the performance of the integrated device and the package. There is a continuing need to provide packages that fully utilize the capabilities of the integrated device.

Summary of the Invention

[0004]

[0004] Various features relate to packages and substrates, and more particularly to packages that include a substrate and an integrated device.

[0005]

[0005] One example provides a package that includes a substrate and an integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power supply to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power supply to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where when the switch is turned on, the switch is configured to enable at least a portion of the power from the second power supply to proceed to the first core of the integrated device.

[0006]

[0006] Another example provides a package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes a first power interconnect configured to provide a first electrical path for a first power supply to the first integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power supply to the second integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where when the switch is turned on, the switch is configured to enable at least a portion of the power from the second power supply to proceed to the first integrated device.

[0007]

[0007] Another example provides a method comprising operating an integrated device that includes a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core. The method determines that the first core of the integrated device requires more power. The method turns on at least one switch to re-route a portion of the second power resource to the first core of the integrated device.

[0008]

[0008] Another example provides a method comprising operating a first integrated device, where a first power resource is directed to the first integrated device. The method operates a second integrated device, where a second power resource is directed to the second integrated device. The method determines that the first integrated device requires more power. The method turns on at least one switch to re - route a portion of the second power resource to the first integrated device.

[0009]

[0009] Various features, properties, and advantages may become apparent from the following detailed description when read in conjunction with the drawings in which like reference numerals generally refer to like elements throughout.

Brief Description of the Drawings

[0010]

Figure 1

[0010] Side view of a package including a substrate and an integrated device having a plurality of cores with a shareable power resource.

Figure 2

[0011] Plan view of an exemplary substrate having various power planes configured for a shareable power resource.

Figure 3

[0012] Diagram showing an exemplary package having possible electrical paths for a substrate and an integrated device having a plurality of cores with a shareable power resource.

Figure 4

[0013] Diagram showing an exemplary package having possible electrical paths for a substrate and an integrated device having a plurality of cores with a shareable power resource.

Figure 5

[0014] Electrical circuit diagram of a package including a substrate and an integrated device having a plurality of cores with a shareable power resource.

Figure 6

[0015] Diagram showing an exemplary integrated device having a plurality of cores with a shareable power resource.

Figure 7

[0016] A diagram showing an exemplary package having possible electrical paths for a substrate and an integrated device having a sharable power resource.

Figure 8

[0017] A diagram showing an exemplary package having possible electrical paths for a substrate and an integrated device having a sharable power resource.

Figure 9

[0018] An exemplary flowchart of a method for providing a sharable power resource for a package including a plurality of cores.

Figure 10A

[0019] A diagram showing an exemplary sequence for fabricating a substrate including at least one switch for controlling a sharable power resource.

Figure 10B

Figure 10C

Figure 11

[0020] An exemplary flowchart of a method for fabricating a substrate including at least one switch for controlling a sharable power resource.

Figure 12

[0021] A diagram showing various electronic devices that can integrate the dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits and / or PCBs described herein.

DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0022] In the following description, specific details are provided in order to give a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects with unnecessary details. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the present disclosure.

[0012]

[0023] The present disclosure describes a package that includes a substrate and an integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to proceed to the first core of the integrated device. Sharing of the power resource helps enable the integrated device to perform optimally by providing additional power to one or more cores that may need and / or desire additional power when another core may not need as much power. Exemplary package comprising an integrated device configured for a shareable power resource

[0024] FIG. 1 shows a package 100 that includes a substrate 102, an integrated device 104, and a encapsulation layer 110. As will be further described below, the integrated device 104 is configured for shared power resources. The package 100 is coupled to a board 190 through a plurality of solder interconnects 130. The integrated device 104 is coupled to the substrate 102 through a plurality of solder interconnects 105. The encapsulation layer 110 is coupled to the substrate 102. The encapsulation layer 110 is located on the substrate 102 and the integrated device 104. The encapsulation layer 110 encapsulates the integrated device 104. A passive device 109 is coupled to the substrate 102. The passive device 109 may include a capacitor. An interconnect 112 may extend through the encapsulation layer 110. The interconnect 112 may include a through mold via (TMV). The interconnect 112 may be coupled to the substrate 102.

[0013]

[0025] The integrated device 104 is coupled to the substrate 102 through a plurality of solder interconnects 105. In some implementations, the integrated device 104 may be coupled to the substrate 102 through a plurality of solder interconnects 105 and pillar interconnects. An underfill 106 is located between the integrated device 104 and the substrate 102. The underfill 106 may be located around the plurality of solder interconnects 105. The integrated device 104 includes at least two cores. For example, the integrated device 104 includes a first core 140 and a second core 142. A core may be a processing unit of the integrated device configured to read and execute program instructions. Each core of the integrated device may be a separate processing unit of the integrated device. In some implementations, each core may be configured to perform separate and / or different functions for the integrated device 104.

[0014]

[0026] The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. As will be further described below, at least in FIG. 2, the plurality of interconnects 122 includes interconnects configured to provide an electrical path for power resources to the core of the integrated device 104. The substrate 102 also includes at least one switch 107. The at least one switch 107 may include at least one transistor. The at least one switch 107 includes a gate interconnect 170, a source interconnect 172, a drain interconnect 174, a gate dielectric layer 176, and a channel 178. When a voltage is applied at the gate interconnect 170, current may be induced from the source interconnect 172 through the channel 178 to the drain interconnect 174. The at least one switch 107 may be used to provide a shareable power resource to the core of the integrated device 104. The at least one switch 107 may be located within different portions of the substrate 102. In some implementations, the at least one switch 107 may be located near an upper metal layer of the substrate 102 (e.g., a metal layer near the integrated device coupled to the substrate 102). In some implementations, the at least one switch 107 may be located near a lower metal layer of the substrate 102 (e.g., a metal layer coupled to a solder interconnect (e.g., a ball grid array)). In some implementations, the at least one switch 107 may be located within the substrate 102, near which a passive device 109 is coupled to the substrate 102.

[0015]

[0027] The plurality of interconnections 122 may include several power interconnections (e.g., power planes) configured to provide an electrical path for a power resource (e.g., power) to one or more integrated devices (e.g., the cores of the integrated devices). For example, a first power interconnection (e.g., a first power plane) may be used to provide an electrical path for power to a first core 140, and a second power interconnection (e.g., a second power plane) may be used to provide an electrical path for power to a second core 142. Various power resources may be coupled to one or more power management integrated devices (e.g., a power management integrated circuit (PMIC)). Thus, various power resources may travel through one or more power management integrated devices. Various power resources may be part of a power grid resource. The power grid resource may include at least one power resource and a ground. Although not shown, one or more power management integrated devices may be coupled to the substrate 102, the package 100, another substrate, and / or the board 190. In one example, a power source (e.g., a battery) may be coupled to one or more power management integrated devices. Energy (e.g., current) from the power source may travel through one or more power management integrated devices and may be redistributed to various integrated devices and / or the cores of the integrated devices through a power grid resource that includes several power resource electrical paths (e.g., a first power resource electrical path, a second power resource electrical path, a third power resource electrical path). In another example, a first power resource may be from a first power source (e.g., a first battery), and a second power resource may be from a second power source (e.g., a second battery).

[0016]

[0028] Different implementation forms may use different materials for package 100. At least one dielectric layer 120 may include glass, polyimide, oxides, and / or combinations thereof. The gate dielectric layer 176 may include HfO2 (hafnium oxide), SiO2 (silicon dioxide), Al2O3 (aluminum oxide), and / or combinations thereof. The channel 178 may include polycrystalline SiGe (silicon germanium), CdSe (cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-doped In2O3 (indium oxide), and / or combinations thereof. The gate interconnect 170, source interconnect 172, and drain interconnect 174 may include copper, cobalt, tungsten (W), and / or combinations thereof.

[0017]

[0029] Packages for high-performance devices need to incorporate redundancy and high-grade robustness into the package. From a design perspective, the power interconnects (e.g., power planes) in the package substrate need to be separated to optimize the power consumption of the integrated devices in the package. However, separating the power planes of the package weakens the power distribution network (PDN). This can result in the reallocation of power resources for different integrated devices and / or parts of the integrated device. The end result is that the integrated device may not be able to perform optimally. To help provide optimal integrated device performance in the package, switches may be implemented in the substrate to enable the sharing of power resources.

[0018]

[0030] FIG. 2 shows a plan view of the metal layer of the substrate 102. The substrate 102 includes a first power plane 201, a second power plane 203, a third power plane 205, a fourth power plane 207, a fifth power plane 209, and a sixth power plane 211. The first power plane 201, the second power plane 203, the third power plane 205, the fourth power plane 207, the fifth power plane 209, and the sixth power plane 211 are examples of interconnections. Each of the power planes is configured to provide an electrical path for an integrated device (e.g., the core of an integrated device). For example, the first power plane 201 may be configured to be coupled to the first core 140 of the integrated device 104, and the second power plane 203 may be configured to be coupled to the second core 142 of the integrated device 104. Each particular power plane is configured to be electrically coupled to a particular power resource. The power planes may be located on any metal layer of the substrate 102. In some implementations, the power planes may be located on the metal layer of the substrate 102 closest to the integrated device 104. Each of the power planes may be configured to be electrically coupled to one or more power management integrated devices. Thus, each of the power planes may be configured as an electrical path for a particular current through one or more power management integrated devices.

[0019]

[0031] FIG. 2 shows a substrate 102 including a plurality of switches 107. The plurality of switches 107 are coupled to a first power plane 201 and a second power plane 203. The plurality of switches 107 are configured to allow current traveling through the second power plane 203 to be shared with the first power plane 201. When the switch is off / case, current may not flow through that particular switch. When the switch is on / case, current may flow through that particular switch. The more switches that are turned on, the more current can flow from the second power plane 203 to the first power plane 201. Thus, the amount of power shared can be controlled by controlling the number of switches from the plurality of switches 107 that are turned on. When all switches are off, there is no sharing from the second power plane 203 to the first power plane 201. FIG. 2 shows that the switches are coupled to the first power plane 201 (e.g., the first interconnect) and the second power plane 203 (e.g., 203). However, the switches can be coupled between any of the different power planes shown and described in the present disclosure. Moreover, the substrate 102 may include power rails, and the switches can be coupled between the power planes and / or power rails. The plurality of interconnects 122 may include power planes (e.g., 201, 203, 205, 207, 209, 211) and / or power rails.

[0020]

[0032] Figure 3 shows an exemplary electrical path in package 100 with switch 107 turned off. As shown in Figure 3, electrical path 301 is coupled to core 140 of integrated device 104, and electrical path 303 is coupled to core 142 of integrated device 104. Electrical path 301 (e.g., the first electrical path) includes a first solder interconnect from a plurality of solder interconnects 130, a first plurality of interconnects from a plurality of interconnects 122 (including the first power plane 201 (e.g., the first power interconnect)), a first solder interconnect from a plurality of solder interconnects 105, and the first core 140. Electrical path 303 (e.g., the second electrical path) includes a second solder interconnect from a plurality of solder interconnects 130, a second plurality of interconnects from a plurality of interconnects 122 (including the second power plane 203 (e.g., the second power interconnect)), a second solder interconnect from a plurality of solder interconnects 105, and the second core 142. Electrical path 303 may also include passive device 109.

[0021]

[0033] Figure 4 shows an exemplary electrical path in package 100 with switch 107 turned on. Switch 107 may be part of electrical path 303. Switch 107 may be coupled to a plurality of interconnects 122. Switch 107 may be coupled to integrated device 104 (e.g., configured to be electrically coupled to core 140 of the integrated device). When / if switch 107 is turned on, some power from a second power resource traveling through electrical path 303 is shared with and transferred to the first core 140 through switch 107. Some power from the second power resource may travel through the second power plane 203 and the first power plane 201. Switch 107 is controllable by integrated device 104 (e.g., controllable by the first core 140 and / or the second core 142). Thus, switch 107 can be turned on and off by integrated device 104. By turning on additional switches, more power can be shared with the first power plane 201 and the first core 140, which provides additional electrical paths for power to reach the first core 140.

[0022]

[0034] FIG. 5 shows an electrical circuit diagram 500 for package 100. The electrical circuit diagram 500 includes a first circuit 501 and a second circuit 503. The first circuit 501 may be an electrical representation of electrical path 301. The second circuit 503 may be an electrical representation of electrical path 303. The first circuit 501 is configured to be electrically coupled to the second circuit 503 through at least one switch 107. The first circuit 501 may include a board 190, a first power plane 201, and a first interconnect from the first core 140. The second circuit 503 may include a board 190, a second power plane 203, a passive device 109, and a second interconnect from the second core 142. At least one switch 107 is part of the second circuit 503 located in the substrate 102. At least one switch 107 may be located near a solder interconnect 130 (e.g., a ball grid array). At least one switch 107 may be part of the substrate 102 where the passive device 109 is coupled to the substrate 102.

[0023]

[0035] FIG. 6 shows an example of an integrated device 104 that includes a first core 140, a second core 142, a third core 143, a fourth core 144, a fifth core 145, a sixth core 146, a seventh core 147, and an eighth core 148. The first core 140 is coupled to a first electrical path 301 that is coupled to a first power resource. The second core 142 is coupled to a second electrical path 303 that is coupled to a second power resource. The second power resource is a shareable power resource. The third core 143 is coupled to a third electrical path 603 that is coupled to a third power resource. The fourth core 144 is coupled to a fourth electrical path 604 that is coupled to a fourth power resource. The second power resource is shareable with the first core 140, the third core 143, and / or the fourth core 144. Some switches (e.g., 107) may be used to enable the second power resource to be shareable with the first core 140, the third core 143, and / or the fourth core 144.

[0024]

[0036] The fifth core 145 is coupled to a fifth electrical path 605 that is coupled to a fifth power resource. The sixth core 146 is coupled to a sixth electrical path 606 that is coupled to a sixth power resource. The seventh core 147 is coupled to a seventh electrical path 607 that is coupled to a seventh power resource. The eighth core 148 is coupled to an eighth electrical path 608 that is coupled to an eighth power resource. The eighth power resource is a shareable power resource. The eighth power resource is shareable with the fifth core 145, the sixth core 146, and / or the seventh core 147. Some switches (e.g., 107) may be used to enable the eighth power resource to be shareable with the fifth core 145, the sixth core 146, and / or the seventh core 147.

[0025]

[0037] Different implementations may have different numbers of cores with different configurations and designs for the power resources. Any of the cores (e.g., processing cores) may be replaced with memory (e.g., memory units). The use of shared power resources may be applicable between the memory and / or cores of an integrated device (e.g., between two memories, between the memory and a core of an integrated device). The use of shareable power resources may be applicable between the integrated devices of a package. For example, a power resource allocated for use by a first integrated device may be shared with a second integrated device. An integrated device (e.g., 104, 740, 742) may include dies (e.g., semiconductor bare dies). An integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. An integrated device (e.g., 104, 740, 742) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An exemplary package comprising an integrated device configured for a total possible power resource

[0038] Figures 7 and 8 show a package 700 including a first integrated device 740 and a second integrated device 742. Package 700 is similar to package 100 of Figures 1 and 3 - 4, and thus may include the same components and / or similar components as package 100. The first integrated device 740 may include at least one core. The second integrated device 742 may include at least one core. The first integrated device 740 and the second integrated device 742 are coupled to a substrate 102. The first integrated device 740 is coupled to the substrate 102 through a plurality of solder interconnects 105. In some implementations, the first integrated device 740 may be coupled to the substrate 102 through a plurality of solder interconnects 105 and pillar interconnects. The second integrated device 742 is coupled to the substrate 102 through a plurality of solder interconnects 705. In some implementations, the second integrated device 742 may be coupled to the substrate 102 through a plurality of solder interconnects 705 and pillar interconnects.

[0026]

[0039] Figure 7 shows an exemplary electrical path in package 700 with switch 107 turned off. As shown in Figure 7, electrical path 701 is coupled to the first integrated device 740, and electrical path 703 is coupled to the second integrated device 742. Electrical path 701 (e.g., the first electrical path) includes a first solder interconnect from a plurality of solder interconnects 130, a first plurality of interconnects from a plurality of interconnects 122 (including the first power plane 201 (e.g., the first power interconnect)), a first solder interconnect from a plurality of solder interconnects 105, and the first integrated device 740. Electrical path 703 (e.g., the second electrical path) includes a second solder interconnect from a plurality of solder interconnects 130, a second plurality of interconnects from a plurality of interconnects 122 (including the second power plane 203 (e.g., the second power interconnect)), a second solder interconnect from a plurality of solder interconnects 705, and the second integrated device 742. Electrical path 703 may also include a passive device 109.

[0027]

[0040] FIG. 8 shows an exemplary electrical path in package 700 with switch 107 turned on. Switch 107 can be part of electrical path 703. Switch 107 can be coupled to a plurality of interconnects 122. Switch 107 can be coupled to integrated device 740 (e.g., configured to be electrically coupled to integrated device 740 of the integrated device). When / If switch 107 is turned on, some power from a second power resource traveling through electrical path 703 is shared with and transferred to first integrated device 740 through switch 107. Some power from the second power resource can travel through second power plane 203 and first power plane 201. Switch 107 can be controllable by first integrated device 740 and / or second integrated device 742. Thus, switch 107 can be turned on and off by first integrated device 740 and / or second integrated device 742. By turning on additional switches, more power can be shared with first power plane 201 and first integrated device 740, which provides an additional electrical path for power to travel to first core 140. Exemplary flowchart of a method for sharing power resources

[0041] FIG. 9 shows an exemplary flowchart of a method 900 for sharing power resources in a package. Method 900 can be implemented by one or more integrated devices. Method 900 can be implemented by one or more cores of an integrated device. For example, method 900 can be implemented by integrated device 104 of package 100. In another example, method 900 can be implemented by integrated devices 740 and / or 742 of package 700.

[0028]

[0042] The method operates one or more cores (e.g., 140, 142) of an integrated device (e.g., 104) (at 905). Operating one or more cores includes reading and executing instructions. Each core may perform distinct and / or different functions. In some implementations, a core may be part of a separate integrated device. Operating one or more cores may also include utilizing one or more memories.

[0029]

[0043] The method determines (at 910) that at least one core of the integrated device requires and / or desires more power. Different implementations may have different one or more criteria for determining whether one or more cores require and / or desire more power. For example, when the amount of power provided to a core is less than a maximum allowable power, the method may determine that the core requires and / or desires more power. Whether a core requires more power may mean whether the core desires more power and / or may benefit from more power. For example, a core may require and / or desire more power when the core is operating at a frequency lower than its maximum frequency. In some implementations, two or more cores may require and / or desire more power. In addition to determining that a core may require and / or desire more power, method 900 may also determine whether there is available shareable power allocated for another core. Note that not all power allocated to a core may be shareable with another core. In some implementations, power allocated to a particular core may be shareable with another core when the particular core is operating below its maximum capacity and / or when the particular core is not being utilized. Thus, even when one or more cores may require and / or desire more power, there may be no power to share from the power resources allocated to another core.

[0030]

[0044] The method turns on at least one switch to share the power resources allocated to a particular core (at 915) with another core of the integrated device. The switch may include a transistor. In some implementations, turning on the switch may include applying a voltage to the gate interconnect of the transistor. In some implementations, the more switches that are turned on, the more power is shared with another core of the integrated device. In some implementations, the number of switches that are turned on may vary in real time. That is, the number of switches that are turned on may be different during different times of the operation of one or more cores of the integrated device. Note that when there is no available power to be shared, none of the switches may be turned on. As described above, in some implementations, even if a core needs and / or desires more power, the method may determine that no additional power to be shared from another core is available. In such cases, the method may not turn on the switch and / or additional switches. As an example, the method may turn on a first switch and a second switch. The first switch and the second switch are coupled to a first power interconnect and a second power interconnect of the substrate. The first power interconnect may be coupled to a first core and the second power interconnect may be coupled to a second core. Turning on the first switch and the second switch may result in a portion of the second power resource traveling from the second power interconnect to the first power interconnect through the first switch and the second switch. Accordingly, a portion of the power from the second power resource allocated to the second core may be redirected to the first core through the first switch and the second switch. In some implementations, turning on at least one switch includes turning on some and / or all of the switches between two different power interconnects (e.g., power planes).

[0031]

[0045] The method may turn off at least one switch to stop (at 920) sharing of power resources and / or to reduce sharing of power resources. The switch may include a transistor. In some implementations, turning off the switch may include stopping a voltage from being applied to the gate interconnect of the transistor. Turning off a particular switch may mean that power may not flow through that particular switch. However, power may still flow between different power interconnects through another switch that remains on. In some implementations, method 900 may continuously and repeatedly inspect in real time the power requirements of the integrated device and / or the cores of the integrated device and turn one or more switches on and off as needed to provide power resources to the various integrated devices and / or the various cores of the integrated device. One or more criteria for determining whether an integrated device (e.g., a core of the integrated device) needs and / or desires additional power may vary in different implementations. Examples of what may be used to determine whether more power is needed for an integrated device include the strength of the voltage, the strength of the current of the power provided to the integrated device, and / or the operating frequency of the (one or more) cores.

[0032]

[0046] For example, method 900 can operate an integrated device that includes a first core and a second core, where a first power resource is directed to the first core and a second power resource is directed to the second core. Method 900 can determine that the first core of the integrated device needs and / or desires more power. Method 900 can turn on at least one switch to re-route a portion of the second power resource to the first core of the integrated device when there is available power from the second power resource. In some implementations, turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to the second core. Method 900 can further determine that the first core of the integrated device does not need more power (e.g., does not need all of the power provided by the first power resource and a portion of the power from the second power resource). Method 900 can turn off at least one switch to stop re-routing a portion of the second power resource to the first core of the integrated device. Method 900 can further determine that the first core of the integrated device needs additional power (e.g., needs more power than that already provided by the first power resource and a portion of the power from the second power resource). Method 900 can turn on more or all of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to the second core to re-route more of the second power resource to the first core of the integrated device.

[0033]

[0047] Method 900 may be applicable to cores of the same integrated device, cores of different integrated devices, and / or different integrated devices. Method 900 may also be applicable to the memory of an integrated device (e.g., between two memories, between the memory and the core of an integrated device). Thus, one or more cores described above in FIG. 9 may be applicable to one memory. Method 900 may be applicable to two or more integrated devices.

[0034]

[0048] For example, method 900 may operate a first integrated device and a second integrated device, where a first power resource is directed to the first integrated device and a second power resource is directed to the second integrated device. Method 900 may determine that the first integrated device requires and / or desires more power. Method 900 may turn on at least one switch to re - route a portion of the second power resource to the first integrated device. In some implementations, turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device. Method 900 may further determine that the first integrated device does not require more power (e.g., does not require all of the power provided by the first power resource and a portion of the power from the second power resource). Method 900 may turn off at least one switch to stop re - routing a portion of the second power resource to the first integrated device. Method 900 may further determine that the first integrated device requires additional power (e.g., requires more power than that already provided by the first power resource and a portion of the power from the second power resource). Method 900 may turn on more or all of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device to re - route more of the second power resource to the first integrated device. Exemplary sequence for fabricating a substrate with switches

[0049] In some implementations, fabricating a substrate includes several processes. FIGS. 10A - 10C show an exemplary sequence for providing or fabricating a substrate that includes switches for sharing power resources. In some implementations, the sequence of FIGS. 10A - 10C can be used to provide or fabricate a substrate 102 that includes at least one switch.

[0035]

[0050] Note that the sequence of FIGS. 10A - 10C can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the spirit of the present disclosure.

[0036]

[0051] Step 1 shows the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000, as shown in FIG. 10A. The metal layer can be patterned to form interconnects 1001. A plating process can be used to form the metal layer and the interconnects. Some of the interconnects 1001 can define a gate interconnect 170, a source interconnect 172, and / or a drain interconnect 174.

[0037]

[0052] Step 2 shows the state after a dielectric layer 1002 is formed over the carrier 1000 and the interconnects. The dielectric layer 1002 can include polyimide. A deposition process can be used to form the dielectric layer 1002.

[0038]

[0053] Stage 3 shows the state after the gate dielectric layer 176 is formed over the interconnect 1001. A deposition process may be used to form the gate dielectric layer 176. Different implementations may use different materials for the gate dielectric layer 176. For example, the gate dielectric layer 176 may include HfO2 (hafnium oxide), SiO2 (silicon dioxide), Al2O3 (aluminum oxide), and / or combinations thereof.

[0039]

[0054] Stage 4 shows the state after a portion of the gate dielectric layer 176 is removed. Removing a portion of the gate dielectric layer 176 may expose the source interconnect 172 and the drain interconnect 174. The source interconnect 172 and the drain interconnect 174 may be formed from portions of the interconnect 1001.

[0040]

[0055] Stage 5 shows the state after the channel 178 is formed over the gate dielectric layer 176, the source interconnect 172, and the drain interconnect 174. Different implementations may use different materials for the channel 178. The channel 178 may include polycrystalline SiGe (silicon germanium), CdSe (cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-doped In2O3 (indium oxide), and / or combinations thereof. The material used for the channel 178 may be formed using low temperatures (e.g., less than 200 degrees Celsius). Stage 5 may show the switch 107 including the gate interconnect 170, the source interconnect 172, the drain interconnect 174, the gate dielectric layer 176, and the channel 178. The switch 107 may be configured as a transistor.

[0041]

[0056] Stage 6 shows the state after the dielectric layer 1020 is formed over the carrier 1000, the switch 107, and the interconnect 1001. The dielectric layer 1020 may include polyimide. However, different implementations may use different materials for the dielectric layer 1020. The dielectric layer 1020 may include the dielectric layer 1002. A deposition process may be used to form the dielectric layer 1020.

[0042]

[0057] Stage 7 shows the state after a plurality of cavities 1011 are formed in the dielectric layer 1020, as shown in FIG. 10B. The plurality of cavities 1011 can be formed using an etching process or a laser process.

[0043]

[0058] Stage 8 shows the state after the interconnect 1013 is formed in and on the dielectric layer 1020. For example, vias, pads and / or traces can be formed. A plating process can be used to form the interconnect.

[0044]

[0059] Stage 9 shows the state after another dielectric layer 1022 is formed on the dielectric layer 1020. A deposition process can be used to form the dielectric layer 1022.

[0045]

[0060] Stage 10 shows the state after the cavity 1021 is formed in the dielectric layer 1022, as shown in FIG. 10C. An etching process or a laser process can be used to form the cavity 1021.

[0046]

[0061] Stage 11 shows the state after the interconnect 1023 is formed in and on the dielectric layer 1022. For example, vias, pads and / or traces can be formed. A plating process can be used to form the interconnect.

[0047]

[0062] Stage 12 shows the situation after carrier 1000 is separated from dielectric layer 1020 (e.g., removed, ground), leaving substrate 102 (e.g., a coreless substrate). In certain implementations, the coreless substrate is an embedded trace substrate (ETS). Stage 11 shows substrate 102 including dielectric layer 1020 and dielectric layer 1022. In some implementations, dielectric layer 1020 and dielectric layer 1022 can be regarded as one dielectric layer (e.g., a single dielectric layer). Substrate 102 includes a plurality of interconnects 1001, a plurality of interconnects 1013, and a plurality of interconnects 1023. The plurality of interconnects 1001, the plurality of interconnects 1013, and the plurality of interconnects 1023 can be represented by a plurality of interconnects 122. Some of the interconnects from substrate 102 can be configured as power interconnects (e.g., power planes) as described in this disclosure.

[0048]

[0063] Different implementations can use different processes to form the (one or more) metal layers. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes for forming the (one or more) metal layers. For example, sputtering processes, spray coating processes, and / or plating processes can be used to form the (one or more) metal layers. Exemplary flowchart of a method for fabricating a substrate with switches

[0064] FIG. 11 shows an exemplary flowchart of a method 1100 for providing or fabricating a substrate with switches. In some implementations, method 1100 of FIG. 11 can be used to provide or fabricate the substrate of FIG. 1. For example, the method of FIG. 11 can be used to fabricate substrate 102.

[0049]

[0065] Note that the sequence of FIG. 11 can combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes can be changed or modified.

[0050]

[0066] The method provides a carrier (at 1105). The method forms a metal layer over the carrier (at 1110). The metal layer can be patterned to form interconnects 1001. Some of the interconnects 1001 can define gate interconnects 170, source interconnects 172, and / or drain interconnects 174. A plating process can be used to form the metal layer and the interconnects. A dielectric layer can be formed after the interconnects 1001 are formed. Step 1 of FIG. 10A shows and describes an example of providing a carrier and forming interconnects.

[0051]

[0067] The method forms at least one switch 107 that includes a gate dielectric layer 176 and a channel 178 (at 1115). One or more deposition processes can be used to form the gate dielectric layer 176 and the channel 178. The gate dielectric layer 176 can include HfO2 (hafnium oxide), SiO2 (silicon dioxide), Al2O3 (aluminum oxide), and / or combinations thereof. The channel 178 can include polycrystalline SiGe (silicon germanium), CdSe (cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-doped In2O3 (indium oxide), and / or combinations thereof. In some implementations, the source interconnects 172 and / or the drain interconnects 174 can be doped. The switch can include a transistor. Steps 3 - 5 of FIG. 10A show and describe an example of forming a channel and a gate dielectric layer.

[0052]

[0068] The method forms a dielectric layer 1020 over a carrier 1000, an interconnection 1001, and a switch 107 (at 1120). The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1011) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process or a laser process. Stages 56 of FIG. 10A and 7 of FIG. 10B illustrate and describe an example of forming the dielectric layer and the cavities.

[0053]

[0069] The method forms an interconnection in and over the dielectric layer (at 1125). For example, an interconnection 1113 may be formed. An electroplating process may be used to form the interconnection. Forming the interconnection may include providing a patterned metal layer over and / or in the dielectric layer. Stage 8 of FIG. 10B illustrates and describes an example of forming the interconnection.

[0054]

[0070] The method forms a dielectric layer 1022 over the dielectric layer 1020 and the interconnection 1113 (at 1130). The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1021) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 9 of FIG. 10B and 10 of FIG. 10C illustrate and describe an example of forming the dielectric layer and the cavities.

[0055]

[0071] The method forms an interconnection in and / or over the dielectric layer (at 1135). For example, an interconnection 1023 may be formed. An electroplating process may be used to form the interconnection. Forming the interconnection may include providing a patterned metal layer over and in the dielectric layer. Stage 11 of FIG. 10C illustrates and describes an example of forming the interconnection.

[0056]

[0072] The method can form (one or more) additional dielectric layers and additional interconnects as described at 1130 and 1135.

[0057]

[0073] Once all (one or more) dielectric layers and additional interconnects are formed, the method can separate (e.g., remove, grind) carriers (e.g., 1100) from the dielectric layer 1020, leaving the substrate. In some implementations, the coreless substrate is an embedded trace substrate (ETS). Step 12 of FIG. 10C shows and describes an example after the substrate is separated from the carrier.

[0058]

[0074] Different implementations can use different processes to form (one or more) metal layers. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes for forming (one or more) metal layers. For example, sputtering processes, spray coating processes, and / or plating processes can be used to form (one or more) metal layers. Exemplary Electronic Device

[0075] FIG. 12 shows various electronic devices that can be integrated with any of the above-described devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, mobile phone device 1202, laptop computer device 1204, fixed location terminal device 1206, wearable device 1208, or automotive vehicle 1210 may include device 1200 described herein. Device 1200 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1202, 1204, 1206, and 1208 and vehicle 1210 shown in FIG. 12 are merely exemplary. Other electronic devices can also include, but are not limited to, mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS)-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that may store or retrieve data or computer instructions, or any combination thereof, a group of devices (e.g., electronic devices) that can characterize device 1200.

[0059]

[0076] One or more of the components, processes, features, and / or functions shown in FIGS. 1-9, FIGS. 10A-10C, and / or FIGS. 11-12 may be reconfigured and / or combined into a single component, process, feature, or function and / or may be implemented in some of the components, processes, or functions. Also, additional elements, components, processes, and / or functions may be added without departing from the present disclosure. Note that FIGS. 1-9, FIGS. 10A-10C, and / or FIGS. 11-12 in the present disclosure, and their corresponding descriptions are not limited to dies and / or ICs. In some implementations, FIGS. 1-9, FIGS. 10A-10C, and / or FIGS. 11-12, and their corresponding descriptions may be used to manufacture, create, provide, and / or generate devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, a heat dissipation device, and / or an interposer.

[0060]

[0077] Note that the figures in the present disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the positions, locations, sizes, and / or shapes of various parts and / or components in the figures may be exemplary. In some implementations, the various components and / or parts in the figures may be optional.

[0061]

[0078] One or more processors (e.g., cores, integrated devices) in a processing system may execute software. Software is broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., regardless of the name such as software, firmware, middleware, microcode, hardware description language. Software may be present on a computer-readable medium.

[0062]

[0079] The computer-readable medium may be a non-transitory computer-readable medium. Non-transitory computer-readable media include, by way of example, magnetic storage devices (e.g., hard disks, floppy (registered trademark) disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., cards, sticks, or key drives), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM (registered trademark)), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The computer-readable medium may be present within the processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer-readable medium may be implemented in a computer program product. In some examples, the computer-readable medium may be part of the memory. By way of example, a computer program product may include the computer-readable medium in a packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and overall design constraints imposed on the overall system.

[0063]

[0080] The term "exemplary" is used in this specification to mean "an example, instance, or serving as an illustration." Any implementation form or aspect described as "exemplary" in this specification should not necessarily be construed as being more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not necessarily require that all aspects of the present disclosure include the features, advantages, or modes of operation being described. The term "coupled" is used in this specification to refer to a direct or indirect coupling (e.g., a mechanical coupling) between two objects. For example, if object A physically contacts object B and object B contacts object C, objects A and C can be considered to be coupled to each other even if they do not directly physically contact each other. The term "electrically coupled" can mean that two objects are directly or indirectly coupled to each other such that an electric current (e.g., a signal, power, ground) can flow between the two objects. Two objects that are electrically coupled may or may not have an electric current flowing between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything beyond the fourth) is optional. Any of the components being described can be the first component, the second component, the third component, or the fourth component. For example, a component called the second component can be the first component, the second component, the third component, or the fourth component. The term "encapsulate" means that an object can partially or completely encapsulate another object. The terms "upper" and "lower" are optional. A component located above the upper can be located above a component located below the lower. An upper component can be considered a lower component, and vice versa. As described in the present disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component depending on how the upper and lower are arbitrarily defined.In another example, the first component may be located on (e.g., above) the first surface of the second component, the third component may be located on (e.g., below) the second surface of the second component, and the second surface is opposite to the first surface. It should be further noted that the term "over" used in this application in the context of one component being located over another component can be used to mean a component that is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component that is over a second component may (1) mean that the first component is over the second component but not in direct contact with the second component, (2) the first component is on the second component (e.g., on its surface), and / or (3) the first component is in the second component (e.g., embedded therein). A first component that is located "in" a second component may be partially located in the second component or may be completely located in the second component. The term "about 'value X'" or "approximately value X" used in this disclosure means within 10 percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value within the range of 0.9 to 1.1.

[0064]

[0081] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect can include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under bump metallization (UBM) layers / interconnects. In some implementations, an interconnect can include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect can include two or more elements or components. An interconnect can be defined by one or more interconnects. An interconnect can include one or more metal layers. An interconnect can be part of a circuit. Different implementations can use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process can be used to form an interconnect.

[0065]

[0082] Also, note that the various disclosures included herein can be described as a process shown as a flowchart, a flow diagram, a structural diagram, or a block diagram. A flowchart can describe operations as a sequential process, but many of the operations can be performed in parallel or simultaneously. Further, the order of the operations can be rearranged. A process ends when its operations are completed.

[0066]

[0083] In the following, additional examples are described to facilitate understanding of the present invention.

[0067]

[0084] Aspect 1: A package comprising an integrated device and a substrate coupled to the integrated device. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device, a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device, a switch coupled to the first power interconnect and the second power interconnect, and wherein when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first core of the integrated device.

[0068]

[0085] Aspect 2: The package according to aspect 1, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first core through the switch.

[0069]

[0086] Aspect 3: The package according to aspects 1 to 2, wherein the switch includes at least one transistor.

[0070]

[0087] Aspect 4: The package according to aspect 3, wherein the at least one transistor includes a source interconnect, a drain interconnect, a channel, and a gate interconnect.

[0071]

[0088] Aspect 5: The package according to aspects 1 to 4, wherein the first power interconnect includes a first power plane and the second power interconnect includes a second power plane.

[0072]

[0089] Aspect 6: The package according to aspect 5, wherein the first power plane and the second power plane are located on the same metal layer of the substrate.

[0073]

[0090] Aspect 7: The package according to aspects 1 to 6, wherein the switch is configured to be controlled by the integrated device.

[0074]

[0091] Aspect 8: The package according to any one of Aspects 1 to 7, further comprising a second switch coupled to the first power interconnection and the second power interconnection, wherein when the second switch is turned on, the second switch is configured to enable at least a portion of the power resources from the second power resource to contribute to the first core of the integrated device.

[0075]

[0092] Aspect 9: The package according to any one of Aspects 1 to 7, wherein the integrated device further comprises a third core, and wherein the substrate comprises a third power interconnection configured to provide a third electrical path for a third power resource to the third core of the integrated device, a second switch coupled to the third power interconnection and the second power interconnection, and wherein when the second switch is turned on, the second switch is configured to enable at least a portion of the power resources from the second power resource to contribute to the third core of the integrated device.

[0076]

[0093] Aspect 10: The package according to any one of Aspects 1 to 9, wherein the first power resource and the second power resource are part of a power grid resource configured to be coupled to one or more power management integrated devices.

[0077]

[0094] Aspect 11: The package according to any one of Aspects 1 to 10, wherein the first power resource includes a first current from a power management integrated device, and the second power resource includes a second current from the power management integrated device.

[0078]

[0095] Aspect 12: The package according to any one of Aspects 1 to 11, wherein the integrated device is configured to determine whether the first core of the integrated device requires more power, and when it is determined that the first core requires more power, to turn on a switch to re-route a portion of the second power resource to the first core of the integrated device.

[0079]

[0096] Aspect 13: The integrated device is further configured to determine whether a first core of the integrated device requires more power, and if it is determined that the first core does not require more power, to turn off a switch to stop rerouting a portion of a second power resource to the first core of the integrated device through the switch. The package according to Aspect 12.

[0080]

[0097] Aspect 14: The integrated device is further configured to determine whether a first core of the integrated device requires additional power, and if it is determined that the first core requires additional power, to turn on a second switch coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to a second core to reroute more of a second power resource to the first core of the integrated device. The package according to Aspect 13.

[0081]

[0098] Aspect 15: A package comprising a first integrated device, a second integrated device, and a substrate coupled to the first integrated device and the second integrated device, the substrate comprising a first power interconnect configured to provide a first electrical path for a first power resource to the first integrated device, a second power interconnect configured to provide a second electrical path for a second power resource to the second integrated device, a switch coupled to the first power interconnect and the second power interconnect, wherein when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first integrated device.

[0082]

[0099] Aspect 16: The package according to Aspect 15, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first integrated device through the switch.

[0083]

[0100] Aspect 17: The package according to any one of Aspects 15 to 16, wherein the switch includes at least one transistor.

[0084]

[0101] Aspect 18: The package according to Aspect 17, wherein the at least one transistor comprises a source interconnect, a drain interconnect, a channel, and a gate interconnect.

[0085]

[0102] Aspect 19: The package according to any one of Aspects 15 to 18, wherein the switch is configured to be controlled by a first integrated device and / or a second integrated device.

[0086]

[0103] Aspect 20: The package according to any one of Aspects 15 to 19, which is part of a power grid resource configured such that a first power resource and a second power resource are coupled to one or more power management integrated devices.

[0087]

[0104] Aspect 21: The package according to any one of Aspects 15 to 19, wherein the first power resource includes a first current from a power management integrated device and the second power resource includes a second current from the power management integrated device.

[0088]

[0105] Aspect 22: The package according to any one of Aspects 15 to 21, wherein the first integrated device is configured to determine whether the first integrated device requires more power and, if it is determined that the first integrated device requires more power, to turn on the switch to reroute a portion of the second power resource to the first integrated device.

[0089]

[0106] Aspect 23: The package according to Aspect 22, wherein the first integrated device is further configured to determine whether the first integrated device does not require more power and, if it is determined that the first integrated device does not require more power, to turn off the switch to stop rerouting a portion of the second power resource to the first integrated device through the switch.

[0090]

[0107] Aspect 24: The first integrated device is further configured to determine whether the first integrated device requires additional power, and if it is determined that the first integrated device requires additional power, to turn on a second switch coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to a second integrated device to reroute more of a second power resource to the first integrated device, the package according to aspect 23.

[0091]

[0108] Aspect 25: The package according to aspects 15 to 24, incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0092]

[0109] Aspect 26: Operating an integrated device including a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core, determining that the first core of the integrated device requires more power, and turning on at least one switch to reroute a portion of the second power resource to the first core of the integrated device.

[0093]

[0110] Aspect 27: Further comprising determining that the first core of the integrated device does not require more power and turning off at least one switch to stop rerouting a portion of the second power resource to the first core of the integrated device through the at least one switch, the method according to aspect 26.

[0094]

[0111] Aspect 28: The method according to aspects 26 to 27, wherein turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to a first core and a second power interconnect coupled to a second core.

[0095]

[0112] Aspect 29: The method according to aspect 28, further comprising determining that a first core of an integrated device requires additional power and turning on all of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to a second core to re - route more of a second power resource through at least one switch to the first core.

[0096]

[0113] Aspect 30: The method according to aspects 26 to 29, wherein the first power resource and the second power resource proceed through a power management integrated device.

[0097]

[0114] Aspect 31: A method comprising operating a first integrated device, wherein a first power resource is directed to the first integrated device, operating a second integrated device, wherein a second power resource is directed to the second integrated device, determining that the first integrated device requires more power, and turning on at least one switch to re - route a portion of the second power resource to the first integrated device through at least one switch.

[0098]

[0115] Aspect 32: The method according to aspect 31, further comprising determining that the first integrated device does not require more power and turning off at least one switch to stop re - routing a portion of the second power resource to the first integrated device through at least one switch.

[0099]

[0116] Aspect 33: The method according to Aspects 31 to 32, wherein turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to a first integrated device and a second power interconnect coupled to a second integrated device.

[0100]

[0117] Aspect 34: The method according to Aspect 33, further comprising determining that the first integrated device requires additional power and turning on all of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device to reroute more of a second power resource through at least one switch to the first integrated device.

[0101]

[0118] Aspect 35: The method according to Aspects 31 to 34, wherein the first power resource and the second power resource proceed through a power management integrated device.

[0102]

[0119] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is illustrative and does not limit the scope of the claims. Accordingly, the present teachings can be readily applied to other types of devices, and many alternative forms, modifications, and variations will be apparent to those skilled in the art. The invention described in the claims of the present application at the time of filing is appended below. [C1] An integrated device including a first core and a second core, A substrate coupled to the integrated device, A package comprising: wherein the substrate A first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device; A second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device; A switch coupled to the first power interconnect and the second power interconnect, wherein when the switch is turned on, the switch is configured to allow at least a portion of the power resources from the second power resource to contribute to the first core of the integrated device; A package comprising. [C2] The package according to C1, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first core through the switch. [C3] The package according to C1, wherein the switch includes at least one transistor. [C4] The package according to C3, wherein the at least one transistor comprises a source interconnect, a drain interconnect, a channel, and a gate interconnect. [C5] The first power interconnect includes a first power plane, The second power interconnect includes a second power plane, The package according to C1. [C6] The package according to C5, wherein the first power plane and the second power plane are located on the same metal layer of the substrate. [C7] The package according to C1, wherein the switch is configured to be controlled by the integrated device. [C8] The package according to C1, further comprising a second switch coupled to the first power interconnect and the second power interconnect, wherein when the second switch is turned on, the second switch is configured to allow at least a portion of the power resources from the second power resource to contribute to the first core of the integrated device. [C9] The integrated device further comprises a third core, The substrate is, A third power interconnect configured to provide a third electrical path for a third power resource to the third core of the integrated device; A second switch coupled to the third power interconnect and the second power interconnect, wherein when the second switch is turned on, the second switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the third core of the integrated device; The package according to C1, further comprising. [C10] The package according to C1, wherein the first power resource and the second power resource are part of a power grid resource configured to be coupled to one or more power management integrated devices. [C11] The first power resource includes a first current from a power management integrated device. The second power resource includes a second current from the power management integrated device. The package according to C1. [C12] The integrated device is Determining whether the first core of the integrated device requires more power; When it is determined that the first core requires more power, turning on the switch to re-route a portion of the second power resource to the first core of the integrated device; The package according to C1, configured to perform. [C13] The integrated device is Determining whether the first core of the integrated device does not require more power; When it is determined that the first core does not require more power, turning off the switch to stop re-routing a portion of the second power resource to the first core of the integrated device through the switch; The package according to C12, further configured to perform. [C14] The integrated device is Determining whether the first core of the integrated device requires additional power; When it is determined that the first core requires additional power, turning on a second switch coupled between the first power interconnect coupled to the first core and the second power interconnect coupled to the second core to re-route more of the second power resource to the first core of the integrated device; The package according to C13, further configured to perform [C15] A first integrated device, and A second integrated device, and A substrate coupled to the first integrated device and the second integrated device, A package comprising, wherein the substrate is A first power interconnect configured to provide a first electrical path for a first power resource to the first integrated device, A second power interconnect configured to provide a second electrical path for a second power resource to the second integrated device, A switch coupled to the first power interconnect and the second power interconnect, wherein when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first integrated device, A package comprising [C16] The package according to C15, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first integrated device through the switch. [C17] The package according to C15, wherein the switch includes at least one transistor. [C18] The package according to C17, wherein the at least one transistor comprises a source interconnect, a drain interconnect, a channel, and a gate interconnect. [C19] The package according to C15, wherein the switch is configured to be controlled by the first integrated device and / or the second integrated device. [C20] The package according to C15, wherein the first power resource and the second power resource are part of a power grid resource configured to be coupled to one or more power management integrated devices. [C21] The first power resource includes a first current from a power management integrated device, The second power resource includes a second current from the power management integrated device, The package according to C15. [C22] The first integrated device is Determining whether the integrated device requires more power, and Turning on the switch to re-route a portion of the second power resource to the first integrated device when it is determined that the first integrated device requires more power, The package according to C15, configured to perform [C23] The first integrated device is Determining whether the first integrated device requires more power; If it is determined that the first integrated device does not require more power, turning off the switch to stop rerouting a portion of the second power resource to the first integrated device through the switch; The package according to C22, further configured to perform. [C24] The first integrated device is Determining whether the first integrated device requires additional power; If it is determined that the first integrated device requires additional power, turning on a second switch coupled between the first power interconnect coupled to the first integrated device and the second power interconnect coupled to the second integrated device to reroute more of the second power resource to the first integrated device; The package according to C23, further configured to perform. [C25] The package according to C15, incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle. [C26] Operating an integrated device including a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core; Determining that the first core of the integrated device requires more power; Turning on at least one switch to reroute a portion of the second power resource to the first core of the integrated device; A method comprising. [C27] Determining that the first core of the integrated device does not require more power; Turning off the at least one switch to stop rerouting a portion of the second power resource to the first core of the integrated device; The method according to C26, further comprising. [C28] Turning on at least one switch includes turning on some, but not all, of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to the second core, the method of C26. [C29] Determining that the first core of the integrated device requires additional power and turning on all of the switches coupled between the first power interconnect coupled to the first core and the second power interconnect coupled to the second core to re - route more of the second power resources to the first core. The method of C28, further comprising. [C30] The method of C26, wherein the first power resource and the second power resource pass through a power management integrated device. [C31] Operating a first integrated device, wherein a first power resource is directed to the first integrated device. Operating a second integrated device, wherein a second power resource is directed to the second integrated device. Determining that the first integrated device requires more power. Turning on at least one switch to re - route a portion of the second power resources to the first integrated device. A method comprising. [C32] Determining that the first integrated device does not require more power. Turning off the at least one switch to stop re - routing a portion of the second power resources to the first integrated device. The method of C31, further comprising. [C33] Turning on at least one switch includes turning on some, but not all, of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device, the method of C31. [C34] Determining that the first integrated device requires additional power. Turning on all of the switches coupled between the first power interconnect coupled to the first integrated device and the second power interconnect coupled to the second integrated device to re - route more of the second power resources to the first integrated device. The method according to C33, further comprising. [C35] The method according to C31, wherein the first power resource and the second power resource proceed through a power management integrated device.

Claims

1. An integrated device comprising a first core and a second core; and A substrate coupled to the integrated device, A package comprising: wherein the substrate is A first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device; A second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device; A switch coupled to the first power interconnect and the second power interconnect, wherein when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first core of the integrated device; A package comprising.

2. The package according to claim 1, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first core through the switch.

3. The first power interconnect includes a first power plane, The second power interconnect includes a second power plane, The first power plane and the second power plane are located on the same metal layer of the substrate. The package according to claim 1.

4. The package according to claim 1, wherein the switch is configured to be controlled by the integrated device.

5. The package according to claim 1, further comprising a second switch coupled to the first power interconnect and the second power interconnect, wherein when the second switch is turned on, the second switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first core of the integrated device.

6. The package according to claim 1, wherein the first power resource and the second power resource are part of a power grid resource configured to be coupled to one or more power management integrated devices.

7. The first power resource includes a first current from a power management integrated device, The second power resource includes a second current from the power management integrated device. The package according to claim 1.

8. The integrated device is Determining whether the first core of the integrated device requires more power; If it is determined that the first core requires more power, turning on the switch to re - route a portion of the second power resource to the first core of the integrated device; configured to perform; The integrated device, Determining whether the first core of the integrated device does not require more power; If it is determined that the first core does not require more power, turning off the switch to stop re - routing a portion of the second power resource to the first core of the integrated device through the switch; The package according to claim 1, further configured to perform.

9. The integrated device, Determining whether the first core of the integrated device requires additional power; If it is determined that the first core requires additional power, turning on a second switch coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to a second core to re - route more of the second power resource to the first core of the integrated device; The package according to claim 8, further configured to perform.

10. A first integrated device; A second integrated device; A substrate coupled to the first integrated device and the second integrated device, A package comprising: wherein the substrate, A first power interconnect configured to provide a first electrical path for a first power resource to the first integrated device; A second power interconnect configured to provide a second electrical path for a second power resource to the second integrated device; A switch coupled to the first power interconnect and the second power interconnect, wherein when the switch is turned on, the switch is configured to enable at least a portion of the power resource from the second power resource to contribute to the first integrated device; A package comprising.

11. The package according to claim 10, wherein when the switch is turned off, the switch is configured such that power from the second power resource does not contribute to the first integrated device through the switch.

12. The package according to claim 10, wherein the switch is configured to be controlled by the first integrated device and / or the second integrated device.

13. The first integrated device determines whether the integrated device requires more power, and when it is determined that the first integrated device requires more power, turns on the switch to re-route a portion of the second power resource to the first integrated device, and is configured to perform The first integrated device determines whether the first integrated device does not require more power, and when it is determined that the first integrated device does not require more power, turns off the switch to stop re-routing a portion of the second power resource to the first integrated device through the switch, and is further configured to perform The first integrated device determines whether the first integrated device requires additional power, and when it is determined that the first integrated device requires additional power, turns on a second switch coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device to re-route more of the second power resource to the first integrated device, and is further configured to perform, the package according to claim 10.

14. operating an integrated device including a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core, determining that the first core of the integrated device requires more power, and turning on at least one switch to re-route a portion of the second power resource to the first core of the integrated device. A method comprising.

15. Operating the first integrated device, wherein a first power resource is directed to the first integrated device, Operating the second integrated device, wherein a second power resource is directed to the second integrated device, Determining that the first integrated device requires more power, Turning on at least one switch to reroute a portion of the second power resource to the first integrated device, A method comprising.

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