Semiconductor device

Abstract

To provide a semiconductor device which has a novel structure using an oxide semiconductor layer of a novel structure.SOLUTION: A semiconductor device has: a first oxide semiconductor layer which is formed on a substrate having an insulating surface and has a crystalline region grown from the surface toward the inside of the first semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer, which contact the second oxide semiconductor layer; a gate insulation layer which covers the second oxide semiconductor layer, the source electrode layer and the drain electrode layer; and a gate electrode layer on the gate insulation layer in a region which overlaps the second oxide semiconductor layer, in which the second oxide semiconductor layer is a layer having crystal grown from the crystalline region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field of the disclosed invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same. Here, the semiconductor device refers to an element and a device in general that function by utilizing semiconductor characteristics. For example, power devices, thyristors, converters, image sensors, memories, semiconductor integrated circuits including these, electro-optical devices typified by liquid crystal display panels, and light-emitting display devices having organic light-emitting elements are widely included in semiconductor devices.

Background Art

[0002] The field-effect transistor is one of the most widely used semiconductor elements. The materials used for field-effect transistors vary depending on their applications, and in particular, semiconductor materials containing silicon are widely used.

[0003] Field-effect transistors using silicon satisfy the characteristics required for many applications. For example, for applications such as integrated circuits that require high-speed operation, single-crystalline silicon is used to meet the requirements. Also, for large-area applications such as display devices, amorphous silicon can be used to meet the requirements.

[0004] As described above, silicon has high versatility and can be used for various applications. However, in recent years, there has been a tendency to require further performance as well as versatility for semiconductor materials. For example, from the viewpoint of high performance of large-area display devices, in order to realize high-speed operation of switching elements, a semiconductor material that is easy to form into a large area and has performance exceeding that of amorphous silicon is required.

[0005] ​​​​​​​​​​​​​ Among metal oxides, some exhibit semiconductor characteristics. For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. are known. Thin film transistors having such metal oxides exhibiting semiconductor characteristics as a channel formation region are already known (Patent Documents 1 to 4, Non-Patent Document 1).

[0006] Metal oxides are known not only as single-component oxides but also as multi-component oxides. For example, InGaO3(ZnO) having a homologous m (m: natural number) is known as a multi-component oxide semiconductor containing In, Ga, and Zn (Non-Patent Documents 2 to 4).

[0007] Under such circumstances, technologies related to field effect transistors (also called FETs) using oxide semiconductors have attracted attention, and it has been confirmed that oxide semiconductors composed of the above-mentioned In-Ga-Zn-based oxides can be applied as the channel layer of thin film transistors (Non-Patent Documents 5 and 6).

[0008]

[0009] For example, Patent Document 5 discloses a transparent thin film field effect transistor using a homologous compound InMO3(ZnO) m (M = In, Fe, Ga, or Al, m is an integer of 1 or more and less than 50).

[0009] In addition, Patent Document 6 discloses a field effect transistor using an amorphous oxide semiconductor containing In, Ga, and Zn and having an electron carrier concentration of less than 10 18 / cm 3 . In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn = 1:1:m (m < 6). ​

[0010] Furthermore, Patent Document 7 discloses a field-effect transistor having an amorphous oxide semiconductor containing microcrystals as an active layer. [Prior Art Documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 60-198861 [Patent Document 2] Japanese Patent Application Laid-Open No. 8-264794 [Patent Document 3] Japanese Patent Application Laid-Open No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Patent Document 6] International Publication No. 05 / 088726 [Patent Document 7] Japanese Patent Application Laid-Open No. 2006-165529 [Non-Patent Documents]

[0012] [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650 - 3652 [Non-Patent Document 2] ​M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m = 3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m = 7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Masanoki Nakamura, Noboru Kimizuka, Hisahiko Mohri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phases, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492

Summary of the Invention

Problems to be Solved by the Invention

[0013] In Patent Document 3, there is a disclosure that the composition in the crystalline state is InGaO3(ZnO) m (m < 6 as an integer). Further, in Example 1 of Patent Document 3, the case of InGaO3 (ZnO)4 is disclosed. However, in fact, even when such an oxide semiconductor is used, sufficient characteristics have not been obtained.

[0014] In view of the above problems, one of the objects is to provide a semiconductor device having a new structure using an oxide semiconductor layer with a new structure.

Means for Solving the Problems

[0015] In the disclosed invention, a semiconductor device is configured using an oxide semiconductor layer that is highly purified and has a crystal region. The crystal region is, for example, a region having electrical anisotropy. Or, it is a region that suppresses the intrusion of impurities.

[0016] One aspect of the disclosed invention is a first oxide semiconductor layer having a crystal region grown from the surface of the first oxide semiconductor layer on a substrate having an insulating surface toward the inside, and the first oxide semiconductor ​​​A second oxide semiconductor layer on a layer, a source electrode layer and a drain in electrode layer in contact with the second oxide semiconductor layer, and a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer in a region overlapping with the second oxide semiconductor layer on the gate insulating layer and, the second oxide semiconductor layer is a semiconductor device having a layer having crystals grown from a crystal region.

[0017] Another aspect of the disclosed invention is a first gate electrode layer on a substrate having an insulating surface, a first gate insulating layer covering the first gate electrode layer, and a first oxide semiconductor layer having a crystal region grown from the surface of the first oxide semiconductor layer inward on the first gate insulating layer and, a second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode layer and a drain electrode layer in contact with the second oxide semiconductor layer, and a second gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer in a region overlapping with the second oxide semiconductor layer on the second gate insulating layer and, the second oxide semiconductor layer is a semiconductor device having a layer having crystals grown from a crystal region. In the above, the height difference on the surface of the second oxide semiconductor layer is 1 nm or less (preferably 0.2 nm or less) in a region overlapping with the gate electrode layer (channel formation region), and it is a semiconductor device.

[0018] In the above, the crystal region of the first oxide semiconductor layer has a c-axis orientation perpendicular to the surface of the first oxide semiconductor layer. Also, the c-axis direction of the crystal coincides with the depth direction.

[0019]

[0020] ​​​​​​​​In the above configuration, the substrate having an insulating surface is a semiconductor device having an oxide or a nitride. It is.

[0021] In the above configuration, the crystal region of the first oxide semiconductor layer is a semiconductor device having an average film thickness of 2 nm or more and 10 nm or less. It is.

[0022] In the above configuration, the first oxide semiconductor layer or the second oxide semiconductor layer is a semiconductor device having any one metal oxide selected from In-Sn -Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and In-Z n-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-M g-O, In-O, Sn-O, Zn-O. It is.

[0023] In the above configuration, the first oxide semiconductor layer or the second oxide semiconductor layer is a semiconductor device which is a highly purified oxide semiconductor layer. It is.

[0024] In the above configuration, the first oxide semiconductor layer and the second oxide semiconductor layer are semiconductor devices made of materials containing the same main component. It is.

[0025] In the above configuration, the first oxide semiconductor layer and the second oxide semiconductor layer are semiconductor devices made of different materials. It is.

[0026] In the above configuration, the first oxide semiconductor layer and the second oxide semiconductor layer are semiconductor devices having the same electron affinity. It is.

[0027] In the above configuration, the second oxide semiconductor layer is a semiconductor device having a recess.

[0028] In the above configuration, the second oxide semiconductor layer is a semiconductor device having a high-purity crystal region. .

[0029] In the above configuration, the carrier density of the first oxide semiconductor layer or the second oxide semiconductor layer is less than 1.0×10 12 cm -3 , preferably less than 1.45×10 10 cm -3 . It is a semiconductor device.

[0030] In the above configuration, the crystal region of the first oxide semiconductor layer is a semiconductor device made of a polycrystalline oxide semiconductor material. Also, the second oxide semiconductor layer is a semiconductor device made of a polycrystalline oxide semiconductor material.

[0031] In the above configuration, both the first oxide semiconductor layer and the second oxide semiconductor layer are semiconductor devices made of a polycrystalline oxide semiconductor material. In the above configuration, the sum of the thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is 3 nm or more and 50 nm or less. It is a semiconductor device.

[0032] In the above configuration, it is a semiconductor device having an insulating layer substantially the same shape as the source electrode layer and the drain electrode layer on the source electrode layer and the drain electrode layer.

[0033] In the above configuration, it is a semiconductor device having a source electrode layer and a drain electrode layer made of a material with low affinity for oxygen in the portion in contact with the second oxide semiconductor layer.

[0034] Also, another aspect of the disclosed invention is to provide a first oxide semiconductor layer on a substrate having an insulating surface. Form and perform a first heat treatment to cause crystal growth from the surface to the interior of the first oxide semiconductor layer, and form a crystal region in the first oxide semiconductor layer in which the c-axis is oriented in a direction substantially perpendicular to the surface. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a gate electrode layer in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. toward the interior, a crystal region in which crystal growth occurs from the surface of the first oxide semiconductor layer toward the interior and the c-axis is oriented in a direction substantially perpendicular to the surface is formed in the first oxide semiconductor layer. A second oxide semiconductor layer is formed on the first oxide semiconductor layer, and a second heat treatment is performed to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. A conductive layer is formed on the second oxide semiconductor layer, and a source electrode layer and a drain electrode layer are formed by etching the conductive layer. A gate insulating layer is formed so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer is formed in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a gate electrode layer in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a gate electrode layer in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a gate electrode layer in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. and form a drain electrode layer. Form a gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a gate electrode layer in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. A gate insulating layer is formed so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer is formed in a region overlapping the second oxide semiconductor layer on the gate insulating layer. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device.

[0035] Also, another aspect of the disclosed invention is to form a first gate electrode layer on a substrate having an insulating surface, form a first gate insulating layer so as to cover the first gate electrode layer, form a first oxide semiconductor layer on the first gate insulating layer, and perform a first heat treatment to cause crystal growth from the surface of the first oxide semiconductor layer toward the interior, and form a crystal region in the first oxide semiconductor layer in which the c-axis is oriented in a direction substantially perpendicular to the surface. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Form a first gate insulating layer so as to cover the first gate electrode layer, form a first oxide semiconductor layer on the first gate insulating layer, and perform a first heat treatment to cause crystal growth from the surface of the first oxide semiconductor layer toward the interior, and form a crystal region in the first oxide semiconductor layer in which the c-axis is oriented in a direction substantially perpendicular to the surface. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Form a first oxide semiconductor layer on the first gate insulating layer, and perform a first heat treatment to cause crystal growth from the surface of the first oxide semiconductor layer toward the interior, and form a crystal region in the first oxide semiconductor layer in which the c-axis is oriented in a direction substantially perpendicular to the surface. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Perform a first heat treatment to cause crystal growth from the surface of the first oxide semiconductor layer toward the interior, and form a crystal region in the first oxide semiconductor layer in which the c-axis is oriented in a direction substantially perpendicular to the surface. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Form a second oxide semiconductor layer on the first oxide semiconductor layer, and perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Perform a second heat treatment to cause crystal growth from the crystal region to crystallize the second oxide semiconductor layer. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. Form a conductive layer on the second oxide semiconductor layer, and form a source electrode layer and a drain electrode layer by etching the conductive layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. and form a drain electrode layer. Form a second gate insulating layer so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and form a second gate electrode layer in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. A second gate insulating layer is formed so as to cover the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a second gate electrode layer is formed in a region overlapping the second oxide semiconductor layer on the second gate insulating layer. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device.

[0036] In the above configuration, a method for manufacturing a semiconductor device is provided, where the film thickness of the first oxide semiconductor layer is 3 nm or more and 15 nm or less.

[0037] In the above configuration, a method for manufacturing a semiconductor device is provided, where a polycrystalline region is formed as the crystal region of the first oxide semiconductor layer.

[0038] In the above configuration, a method for manufacturing a semiconductor device is provided, where the second oxide semiconductor layer is polycrystallized by a second heat treatment.

[0039] In the above configuration, a method for manufacturing a semiconductor device is provided, where both the first oxide semiconductor layer and the second oxide semiconductor layer are polycrystallized by a first heat treatment and a second heat treatment.

[0040] In the above configuration, a method for manufacturing a semiconductor device is provided, where crystal growth is performed by a second heat treatment such that the c-axis is oriented in a direction substantially perpendicular to the surface of the second oxide semiconductor layer.

[0041] In the above configuration, the second oxide semiconductor layer is formed by a sputtering method, and the composition ratio of the metal oxide target is In:Ga:Zn = 1:x:y (x is 0 or more and 2 or less, and y is 1 or more and 5 or less).

[0042] In the above configuration, a method for manufacturing a semiconductor device is provided, where the composition of the metal oxide target is In:Ga:Zn = 1:x:y ( x = 1, y = 1).

[0043] In the above configuration, a method for manufacturing a semiconductor device is provided, where the composition of the metal oxide target is In:Ga:Zn = 1:x:y ( x = 0, y = 1).

[0044] ​​​​​​In the above configuration, a method for manufacturing a semiconductor device is provided, in which an insulating layer having substantially the same shape as the source electrode layer and the drain electrode layer is formed on the source electrode layer and the drain electrode layer.

[0045] In the above configuration, a method for manufacturing a semiconductor device is provided, in which a material having a low affinity for oxygen is used to form the source electrode layer and the drain electrode layer in a portion in contact with the second oxide semiconductor layer.

[0046] In the above manufacturing method, annealing is performed after the formation of the first oxide semiconductor layer, and the second oxide semiconductor layer is formed on the upper surface thereof. Thereafter, crystal growth is caused toward the surface of the second oxide semiconductor layer above the surface of the first oxide semiconductor layer. The first oxide semiconductor layer corresponds to a seed crystal for the second oxide semiconductor layer. It is important that a second oxide semiconductor layer having crystallinity (for example, polycrystalline) is formed on the upper side of the first oxide semiconductor layer.

[0047] As the crystallinity of the oxide semiconductor layer increases, the amount of change in the threshold voltage of the transistor before and after the BT test can be suppressed, and high reliability can be achieved. In addition, a transistor using an oxide semiconductor layer having a c-axis oriented polycrystalline layer can reduce the amount of change in the threshold voltage of the transistor even before and after the BT test in which light is continuously irradiated on the transistor, and a transistor having stable electrical characteristics can be manufactured.

[0048] Further, the higher the crystallinity of the oxide semiconductor layer, the more the temperature dependence of the electrical characteristics of the transistor, for example, the amount of change in the on-current and off-current from -30°C to 120°C can be suppressed. Although the operating temperature range of a normal display panel is 0°C or higher and 40°C or lower, for example, for an in-vehicle display ​​​​​​​​​​​​When it comes to a panel, heat resistance of -30°C or higher up to 85°C, and even up to 105°C is required. Not limited to display panels, by using a highly crystalline oxide semiconductor layer in switching elements, drive circuits, etc. a device that can withstand various harsh environments can be realized, which is useful because it can expand the usage applications and fields of use.

[0049] Also, the higher the crystallinity of the oxide semiconductor layer, the higher the field-effect mobility transistor that can be realized.

[0050] All of the above oxide semiconductor layers have metal oxides, such as In-Sn-G a-Zn-O film, which is a quaternary metal oxide, or In-Ga-Zn-O film, which is a ternary metal oxide, In-Sn-Zn -O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O system, or In-Zn-O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, or I n-O film, Sn-O film, Zn-O film, etc., and metal oxide films can be used.

[0051] The above oxide semiconductor layer can use a thin film represented by InMO3(ZnO) m (m > 0, and m is not a natural number). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Also, a material represented by InGa Mn, or Ga and Co, etc. Also, a material represented by InGa x Zn y O z can be used. Here, x, y, z are arbitrary numbers. Also, x, y, z are integers. And x, y, z are integers. There is no need for it to be an integer, and it may be a non-integer. Note that x may be 0, but y should not be 0. This is desirable. For example, this notation includes In-Zn-O where x is 0. Also, The oxide semiconductor material denoted as In-Ga-Zn-O in this specification is InGaO3( ZnO) m (m > 0, and m is not a natural number), and the fact that m is not a natural number can be confirmed by using ICP -MS analysis or RBS analysis. Also, it includes cases such as when it is denoted as x = 1, y = 1, or when it is denoted as x = 1, y = 0.5. Also, when the carrier density is less than 1×10 1×10 12 cm -3 less than, preferably less than 1.45×10 10 cm -3 a highly purified oxide semiconductor is preferably used.

[0052] The metal oxides reported so far have been in an amorphous state, or in a polycrystalline state , or those that obtain single crystals by treatment at a high temperature of about 1400 °C. However, as shown above, after forming a flat polycrystal of the metal oxide, a thin-film polycrystal can be formed at a relatively low temperature by a method of crystal growth using the flat polycrystal of the metal oxide as a seed, and further a thick-film poly crystal can be formed, which opens up a wider industrial application. Note that in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even a slight unevenness of the substrate becomes a deviation of the local c-axis, and as the crystal growth progresses, it becomes a defect such as a crystal transition different from the c-axis direction of adjacent crystals. Note that the flat crystals in the oxide semiconductor layer are crystals of InGaZnO4 (In:Ga:Zn:O = 1:1:1:4). is suitable. Or, it is preferably a crystal of In2Ga2ZnO7 (In:Ga:Zn:O = 2:2:1:7). is preferably a crystal. Further, a crystal having a c-axis orientation in a direction perpendicular to the surface of the oxide semiconductor layer , for example, is polycrystalline.

[0053] In addition, in this specification and the like, the terms "upper" and "lower" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode layer on the gate insulating layer" , other components are excluded between the gate insulating layer and the gate electrode layer except. Further, the terms "upper" and "lower" are merely expressions used for convenience of explanation, and especially when not specifically mentioned , those with the upper and lower reversed are also included.

[0054] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components . For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0055] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are adopted or , when the direction of current changes in the circuit operation. Therefore , in this specification, the terms "source" and "drain" may be used interchangeably.

[0056] In addition, in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" ​​​" is not particularly limited as long as it enables the exchange of electrical signals between connection targets.

[0057] For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors resistive elements, inductors, capacitors, and other elements having various functions. etc. are included.

Advantages of the Invention

[0058] In the disclosed invention, a highly purified oxide semiconductor layer is used in a semiconductor device. High purification means excluding hydrogen, which is a factor in the n-type conversion of the oxide semiconductor, from the oxide semiconductor layer as much as possible, or supplying oxygen lacking in the oxide semiconductor layer to reduce defects caused by oxygen deficiency in the oxide semiconductor layer, which is a concept including at least one of these.

[0059] The high purification is performed to make the oxide semiconductor layer intrinsic (i-type). Since the oxide semiconductor is generally n-type, the off-current is high. When the off-current is high, the switching characteristics are insufficient and it is not suitable as a semiconductor device. Therefore, in one aspect of the present invention, the oxide semiconductor layer is highly purified to be i-type or close to it.

[0060] Also, in the disclosed invention, an oxide semiconductor layer having a crystal region is used in a semiconductor device.

[0061] In an oxide semiconductor layer having a crystal region, the electrical characteristics of the oxide semiconductor layer are different compared to an oxide semiconductor layer without a crystal region. For example, in an oxide semiconductor layer having a crystal region in which the c-axis is oriented in a direction substantially perpendicular to the surface, the conductivity in a direction parallel to the surface of the oxide semiconductor layer is improved, and the insulation in a direction perpendicular to the surface of the oxide semiconductor layer is improved. oriented in a direction substantially perpendicular to the surface, the conductivity in a direction parallel to the surface of the oxide semiconductor layer is improved, and the insulation in a direction perpendicular to the surface of the oxide semiconductor layer is improved. electricity is improved, and the insulation in a direction perpendicular to the surface of the oxide semiconductor layer is improved.

[0062] Thus, by using an oxide semiconductor layer having a crystal region in a semiconductor device, semiconductor devices with excellent electrical characteristics can be realized.

[0063] In addition, in an oxide semiconductor layer having a crystal region, compared with an oxide semiconductor layer not having a crystal region the intrusion of impurities into the oxide semiconductor layer is suppressed. For example, in an oxide semiconductor layer having a crystal region the intrusion of water, hydrogen, etc., which have an adverse effect on the oxide semiconductor layer, is suppressed thereby.

[0064] Thereby, it is possible to suppress the oxide semiconductor layer from being n-type after the fact. That is the reliability of the semiconductor device can be improved.

[0065] Thus, according to one aspect of the disclosed invention, a highly reliable semiconductor device with excellent characteristics is provided thereby.

[0066] As described above, by using an oxide semiconductor, particularly a highly purified and crystallized oxide semiconductor, it is understood that various effects can be obtained. And, like the disclosed invention, by realizing a crystallized oxide semiconductor layer in a crystal structure a new semiconductor device with excellent characteristics is realized.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0068] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0069] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0070] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0071] (Embodiment 1) In the present embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described​​ This will be described with reference to FIGS. 1 to 4.

[0072] (Configuration of Semiconductor Device) FIG. 1 is a cross-sectional view showing a transistor 150, which is an example of a configuration of a semiconductor device. The transistor 150 is an n-channel IGFET (insulator-type field effect transistor) in which the carriers are electrons. ed Gate Field Effect Transistor) As will be described, it is also possible to fabricate a p-channel IGFET.

[0073] The transistor 150 is formed of a first oxide semiconductor layer provided on a substrate 100 with an insulating layer 102 interposed therebetween. A conductor layer 104a and a second oxide semiconductor layer provided on the first oxide semiconductor layer 104a. 106a and a source electrode layer or a drain electrode layer electrically connected to the second oxide semiconductor layer 106a. A drain electrode layer 108a, a source electrode layer or a drain electrode layer 108b, and a second oxide a source or drain electrode layer 108a; and a source electrode A gate insulating layer 112 covering the gate electrode layer 108b and a gate insulating layer 112 on the gate insulating layer 112. and a gate electrode layer 114 (see FIGS. 1A and 1B).

[0074] In addition, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components. , may be omitted as appropriate.

[0075] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are made of a quaternary metal oxide. Materials such as In-Sn-Ga-Zn-O, which is an oxide of In-Ga -Zn-O-based materials, In-Sn-Zn-O-based materials, In-Al-Zn-O-based materials, Sn-Ga-Zn-O-based materials, Al-Ga-Zn-O-based materials, Sn-Al-Zn-O -based materials, and binary metal oxide In-Zn-O-based materials, Sn-Zn-O-based materials , Al-Zn-O-based materials, Zn-Mg-O-based materials, Sn-Mg-O-based materials, In- Mg-O-based materials, and monovalent metal oxide In-O-based materials, Sn-O-based materials, Z n-O-based materials, etc. are used.

[0076] Also, an oxide semiconductor material represented by In-A-B-O may be used. Here, A is one or more elements selected from Group 13 elements such as gallium (Ga) and aluminum (Al), and Group 14 elements represented by silicon (Si) and germanium (Ge). Also, B represents one or more elements selected from Group 12 elements represented by zinc (Zn). Note that the contents of In, A, and B are arbitrary, including the case where the content of A is zero. On the other hand, the contents of In and B are not zero. That is, the above notations include In-Ga -Zn-O and In-Zn-O, etc.

[0077] Among them, the In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material for use in semiconductor devices.

[0078] Typical examples of the In-Ga-Zn-O-based oxide semiconductor material include those represented by InGaO3(ZnO) m (m > 0). Also, using M instead of Ga, InMO3(Zn O) mThere are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M is Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn The above composition is derived from the crystal structure. It should be noted that the above is merely an example.

[0079] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are free of impurities such as hydrogen. It is desirable that the water be highly purified by sufficiently removing all substances and supplying oxygen. Specifically, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a The hydrogen concentration is 5×10 19 / cm 3 Less than 5×10 18 / cm 3 More hopes below Preferably 5 x 10 17 / cm 3 In addition, the hydrogen concentration is sufficiently reduced and oxygen is supplied. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are purified by the above-mentioned The conductor layer 106a is made of a silicon wafer (containing trace amounts of impurity elements such as phosphorus and boron) The carrier density in the doped silicon wafer (1×10 14 / cm 3 Compared to Then, a sufficiently small carrier density value (e.g., 1×10 12 / cm 3 Less than, more preferred For example, 1.45×10 10 / cm 3 In this way, i-type or essentially i By using a patterned oxide semiconductor, a transistor 15 with extremely excellent off-current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is in the range from -5V to -20V, the off-current is 1×10 -13 A or less. Note that the hydrogen concentration in the above-described first oxide semiconductor layer 104a and second oxide semiconductor layer 106 a is measured by secondary ion mass spectrometry (SIMS).

[0080] Here, the first oxide semiconductor layer 104a has a crystalline region, and the crystalline region is a region including the surface of the first oxide semiconductor layer 104a, that is, a region including the interface with the second oxide semiconductor layer 106a, and it is desirable that the crystalline region has a crystal in which the c-axis is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer 104a. For example, the crystalline region can be a region including crystal grains in which the c-axis is oriented in a direction substantially perpendicular to the surface of the first oxide semiconductor layer 104a. Here, "substantially perpendicular" means a state within ±10° from the perpendicular direction. Note that the crystalline region may be only in the vicinity of the surface of the first oxide semiconductor layer 104a (for example, the distance (depth) from the surface is 2 nm or more and 10 nm or less), or may reach the back surface of the first oxide semiconductor layer 104a.

[0081] Also, it is desirable that the crystalline region is a plate-like crystal. Here, the plate-like crystal means a crystal that is developed in a planar manner and has a shape like a thin plate. Also, it is preferable that the crystalline region is polycrystalline.

[0082] Further, the second oxide semiconductor layer 106a is formed of crystals grown from the crystal region of the first oxide semiconductor layer 104a.

[0083] Here, since the second oxide semiconductor layer 106a is formed of crystals grown from the crystal region of the first oxide semiconductor layer 104a, the c-axis is oriented in a direction substantially perpendicular to the interface with the first oxide semiconductor layer 104a, similar to the crystal region of the first oxide semiconductor layer 104a. That is, it is composed of crystals in which the c-axis is oriented in a direction substantially perpendicular to the interface with the first oxide semiconductor layer 104a. Here, "substantially perpendicular" means a state within ±10° from the vertical direction.

[0084] Further, the second oxide semiconductor layer 106a is preferably composed of plate-like crystals (plate-shaped crystals), similar to the crystal region of the first oxide semiconductor layer 104a. Also, the second oxide semiconductor layer 106a is preferably polycrystalline.

[0085] Further, the second oxide semiconductor layer 106a may contain not only crystals grown from the crystal region of the first oxide semiconductor layer 104a but also crystals grown from the surface of the second oxide semiconductor layer 106a.

[0086] Also, when the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are the same (so-called homo-epitaxial growth), the boundary between the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a may become indistinguishable, so it is shown by a dotted line in Fig. 1(A). Therefore, in Fig. 1(A), there are cases where the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a can be regarded as the same layer (see Fig. 1(A)). Also, both the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are polycrystalline.

[0087] ​​​​​​​​​​Of course, the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a may be different (see Fig. 1(B)). When the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are different (in the case of so-called hetero-epitaxial growth), for example, a binary metal oxide In-Zn-O-based material may be used for the first oxide semiconductor layer 104a, and a ternary metal oxide In-Ga-Zn-O-based material may be used for the second oxide semiconductor layer 106a, and a configuration such as this can be adopted. By forming the second oxide semiconductor layer 106a by crystal growth from the crystal region of the first oxide semiconductor layer 104a, electrical anisotropy is imparted to the second oxide semiconductor layer 106a. For example, since the c-axis is oriented in a direction substantially perpendicular to the interface between the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the conductivity in the direction parallel to the surface of the second oxide semiconductor layer 106a is increased. On the other hand, with respect to the direction perpendicular to the surface of the second oxide semiconductor layer 106a, the insulating property is increased. Of the oxide semiconductor layers, the region that becomes the channel formation region preferably has at least a flat surface. Also, the first oxide semiconductor layer and the second oxide semiconductor layer are polycrystals having the same c-axis orientation. Note that the height difference on the surface of the second oxide semiconductor layer is preferably 1 nm or less (preferably 0.2 nm or less) in the region (channel formation region) that overlaps with the gate electrode layer. As described above, crystal growth is performed from the crystal region of the highly purified first oxide semiconductor layer 104a.

[0088]

[0089]

[0090] ​​​​​​​​​​​​​​By using the formed second oxide semiconductor layer 106a, a semiconductor device having good electrical characteristics can be realized.

[0091] In addition, since the second oxide semiconductor layer 106a is relatively stable, it is possible to suppress the intrusion of impurities (e.g., water, etc.) into the second oxide semiconductor layer 106a. Therefore, the reliability of the second oxide semiconductor layer 106a can be improved.

[0092] Hereinafter, the significance of purifying and intrinsicizing (i - type conversion) an oxide semiconductor, and the merits of constructing a semiconductor device using such an oxide semiconductor, etc. will be briefly described .

[0093] 〈Intrinsicization of Oxide Semiconductor〉 In the study of physical properties of oxide semiconductors, such as DOS (density of state), many studies have been conducted , but these studies do not include the idea of sufficiently reducing the defect levels themselves. In one aspect of the disclosed invention, by removing water and hydrogen that can cause an increase in DOS from the oxide semiconductor , a highly purified and intrinsicized (i - type converted) oxide semiconductor is fabricated. This is based on the idea of sufficiently reducing DOS itself. And by this , it enables the production of extremely excellent industrial products.

[0094] Note that when removing hydrogen, water, etc., oxygen may be removed simultaneously. For this reason, it is preferable to supply oxygen to the unbonded hands of the metal generated due to oxygen deficiency and reduce DOS caused by oxygen defects to further purify and intrinsicize (i - type convert) the oxide semiconductor . For example, an oxygen - rich oxide film is formed in close contact with the channel formation region, 20 ​​​By performing heat treatment under temperature conditions of 0°C or higher and 400°C or lower, typically around 250°C, the supply of oxygen from the oxide film into the oxide semiconductor can reduce the DOS caused by oxygen vacancies. Also, during the heat treatment, the inert gas may be switched to a gas containing oxygen. Subsequent to the heat treatment, it is also possible to supply oxygen into the oxide semiconductor by going through a temperature reduction process in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed.

[0095] The factors that deteriorate the characteristics of the oxide semiconductor are considered to be due to shallow energy levels of 0.1 to 0.2 eV below the conduction band formed by excessive hydrogen, deep energy levels formed by oxygen vacancies, etc. To eliminate these defects, the technical concept of thoroughly removing hydrogen and sufficiently supplying oxygen would be correct.

[0096] Note that although the oxide semiconductor is generally of the n-type, in one aspect of the disclosed invention, by removing impurities such as water and hydrogen and supplying oxygen, which is a constituent element of the oxide semiconductor, p-type conversion is achieved. In this regard, it can be said that this is not p-type conversion by adding impurity elements like silicon, etc., but includes a novel technical concept.

[0097] Also, by making the oxide semiconductor p-type, the temperature characteristics of the transistor become good. Typically, in the temperature range from -25°C to 150°C, in the current-voltage characteristics of the transistor, there is almost no variation in the on-current, off-current, field-effect mobility, S value, and threshold voltage, and almost no deterioration of the current-voltage characteristics due to temperature.

[0098] Note that the transistor using the oxide semiconductor shown in this embodiment uses silicon carbide. Compared with the transistors used, the mobility is about two orders of magnitude lower, but the drain voltage is increased, and the channel width (W) is increased to increase the current value of the transistor and improve the device characteristics. It can be made possible.

[0099] The technical idea of this embodiment is to intentionally remove impurities such as water and hydrogen that are inadvertently present in the oxide semiconductor without adding any impurities, thereby purifying the oxide semiconductor itself to a high purity. That is, by removing water or hydrogen that constitutes the donor level and further supplying sufficient oxygen, which is the main component material of the oxide semiconductor, the oxygen deficiency is reduced, and the oxide semiconductor is purified to a high purity. At the time of forming the oxide semiconductor film, hydrogen at a level of 1×10 cm

[0100] is measured to be present in the oxide semiconductor by SIMS (secondary ion mass spectrometry). By intentionally removing the water or hydrogen that causes this donor level and further adding oxygen, which also decreases simultaneously with the removal of water or hydrogen (one of the components of the oxide semiconductor), to the oxide semiconductor, the oxide semiconductor 20 cm -3 is purified to a high purity and made an electrically intrinsic (i-type) semiconductor. is measured by SIMS (secondary ion mass spectrometry). By intentionally removing the water or hydrogen that causes this donor level and further adding oxygen, which also decreases simultaneously with the removal of water or hydrogen (one of the components of the oxide semiconductor), to the oxide semiconductor, the oxide semiconductor is purified to a high purity and made an electrically intrinsic (i-type) semiconductor. is purified to a high purity and made an electrically intrinsic (i-type) semiconductor. is purified to a high purity and made an electrically intrinsic (i-type) semiconductor.

[0101] Also, in this embodiment, the smaller the amount of water and hydrogen in the oxide semiconductor, the better, and the smaller the number of carriers, the better. That is, the carrier density is 1×10 1 2 cm cm -3 less than, and more preferably less than the measurement limit of 1.4×10 10 cm -3 is required. Furthermore, in terms of the technical idea of this embodiment, being close to zero or zero is ideal. is required. Furthermore, in terms of the technical idea of this embodiment, being close to zero or zero is ideal. In particular, oxide semiconductors are treated with oxygen, nitrogen, or ultra-dry air (water content of 20 ppm or less, Preferably, the concentration is 1 ppm or less, and more preferably 10 ppb or less, in air. By performing a heat treatment at 50°C or less, preferably 550°C to 750°C, The pure water or hydrogen can be removed to achieve high purification. By removing impurities such as ZnO, the oxide semiconductor can be highly purified, and the carrier density can be increased. 1×10 12 cm -3 less than 1.4 × 10 10 cm -3 It can be less than.

[0102] Furthermore, the heat treatment is performed at a high temperature of 450°C to 850°C, preferably 600°C to 700°C. In this case, the oxide semiconductor can be highly purified and crystallized. Crystal growth occurs from the surface of the semiconductor toward the inside, forming a polycrystalline layer with the c-axis oriented.

[0103] In the present invention, the polycrystalline layer having the c-axis direction is used as a seed crystal, and a second oxide semiconductor is grown thereon. and performing a heat treatment at 450°C to 850°C, preferably 550°C to 750°C. By this, the second oxide semiconductor is made into a polycrystalline layer in which the c-axis is oriented similarly to the seed crystal. That is, an ideal axial alignment is achieved in which the c-axes of the seed crystal and the second oxide semiconductor are coaxial. The thin film can be grown by deposition or epitaxial growth.

[0104] In addition, the second oxide semiconductor, which is coaxial with the seed crystal, can be grown by solid phase growth only by heat treatment after film formation. The second oxide semiconductor is formed while being heated at a temperature of 200° C. to 600° C., typically. By sputtering, crystal growth can be achieved while depositing.

[0105] Furthermore, by reducing and preferably eliminating the carriers of the oxide semiconductor, in the transistor, the oxide semiconductor functions as a path for carriers to pass through. As a result, the oxide semiconductor is a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, and in the off state of the transistor, the off current can be made extremely low. This is the technical idea of this embodiment. Also, when the oxide semiconductor functions as a path and is made into a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, the carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. Moreover, by making the oxide semiconductor function as a path and making it a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. This is the technical idea of this embodiment.

[0106] In addition, when the oxide semiconductor functions as a path and the oxide semiconductor itself has no carriers or has extremely few carriers and is made into a highly purified intrinsic (i-type), carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. Moreover, by making the oxide semiconductor function as a path and making it a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. Furthermore, by reducing and preferably eliminating the carriers of the oxide semiconductor, in the transistor, the oxide semiconductor functions as a path for carriers to pass through. As a result, the oxide semiconductor is a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, and in the off state of the transistor, the off current can be made extremely low. This is the technical idea of this embodiment. Moreover, by making the oxide semiconductor function as a path and making it a highly purified intrinsic (i-type) semiconductor with no carriers or extremely few carriers, carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. In addition, when the oxide semiconductor functions as a path and the oxide semiconductor itself has no carriers or has extremely few carriers and is made into a highly purified intrinsic (i-type), carriers are supplied by the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source electrode and the drain electrode, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated. This is the technical idea of this embodiment.

[0107] By the way, in a lateral transistor in which the channel is formed substantially parallel to the substrate, in addition to the channel, it is necessary to provide a source and a drain, which increases the occupied area of the transistor on the substrate and hinders miniaturization. However, in a vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, miniaturization of the transistor is possible. By the way, in a lateral transistor in which the channel is formed substantially parallel to the substrate, in addition to the channel, it is necessary to provide a source and a drain, which increases the occupied area of the transistor on the substrate and hinders miniaturization. However, in a vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, miniaturization of the transistor is possible. By the way, in a lateral transistor in which the channel is formed substantially parallel to the substrate, in addition to the channel, it is necessary to provide a source and a drain, which increases the occupied area of the transistor on the substrate and hinders miniaturization. However, in a vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, miniaturization of the transistor is possible. By the way, in a lateral transistor in which the channel is formed substantially parallel to the substrate, in addition to the channel, it is necessary to provide a source and a drain, which increases the occupied area of the transistor on the substrate and hinders miniaturization. However, in a vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, miniaturization of the transistor is possible. By the way, in a lateral transistor in which the channel is formed substantially parallel to the substrate, in addition to the channel, it is necessary to provide a source and a drain, which increases the occupied area of the transistor on the substrate and hinders miniaturization. However, in a vertical transistor, since the source, the channel, and the drain are stacked, the occupied area on the substrate surface can be reduced. As a result, miniaturization of the transistor is possible.

[0108] In this way, by purifying the oxide semiconductor film to a high purity so as to minimize the inclusion of impurities other than the main component, typically hydrogen, water, hydroxyl groups, or hydrides, etc., and forming a polycrystalline region, the operation of the transistor can be made good. In particular, the breakdown voltage can be increased, the short-channel effect can be reduced, and the on / off ratio can be increased. Also, the change amount of the threshold voltage of the transistor before and after the BT test can be suppressed, and high reliability can be achieved. Also, the temperature dependence of the electrical characteristics can be suppressed. Also, a transistor using an oxide semiconductor layer having a c-axis oriented polycrystalline layer can reduce the change amount of the threshold voltage of the transistor even before and after the BT test performed while irradiating the transistor with light, and a transistor having

[0109] stable electrical characteristics can be fabricated. Semiconductor materials that can be a comparison target with the oxide semiconductor include silicon carbide (e.g., 4H-Si C), etc. The oxide semiconductor and 4H-SiC have some common points. The carrier density is one example. According to the Fermi-Dirac distribution, the minority carriers of the -7 oxide semiconductor are estimated to be about 10 3 / cm , which is an extremely low value similar to 6.7× -11 / cm 3 in 4H-SiC. Compared with the intrinsic carrier density of silicon (about 1.4 ×10 10 / cm 3 ), it can be well understood that the degree is far from comparable.

[0110] Also, the energy bandgap of the oxide semiconductor is 3.0 to 3.5 eV, and 4H-S​ Since the energy band gap of iC is 3.26 eV, it can be said that in this regard, oxide semiconductors and silicon carbide have something in common as wide-gap semiconductors. On the other hand, there are extremely large differences between oxide semiconductors and silicon carbide. That is the

[0111] processing temperature. Since silicon carbide generally requires heat treatment at 1500°C to 2000°C, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because at such high temperatures, semiconductor substrates, semiconductor elements, etc. will be destroyed. On the other hand, oxide semiconductors can be fabricated by heat treatment at 300°C or higher and 800°C or lower. After forming an integrated circuit using other semiconductor materials, it becomes possible to form semiconductor elements using oxide semiconductors.

[0112] Also, different from the case of silicon carbide, it has the advantage that it is possible to use substrates with low heat resistance, such as glass substrates. Furthermore, in terms of not requiring heat treatment at high temperatures, it has the advantage that the energy cost can be made sufficiently low compared to silicon carbide. Furthermore, silicon carbide has the problem that crystal defects and trace amounts of unintentionally incorporated impurities become factors for generating carriers. Theoretically, a carrier density as low as that of the oxide semiconductor of the present invention can be obtained with silicon carbide, but in reality, due to the reasons described above, it is difficult to obtain a carrier density of 10 / cm 12 / cm 3 or less. The above also applies to the comparison between gallium nitride, which is also known as a wide-gap semiconductor, and oxide semiconductors.

[0113] 〈Conduction mechanism of transistors using oxide semiconductors〉 The conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 18 to 21. In the following description, an ideal situation is assumed for ease of understanding, and not all of it reflects the actual situation. Also, it should be noted that the following description is merely a consideration. FIG. 18 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. FIG. 19 shows an energy band diagram (schematic diagram) of the A-A' cross-section of FIG. 18. The black circles (●) in FIG. 19 represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. FIG. 20 shows an energy band diagram (schematic diagram) of the B-B' cross-section in FIG. 18. FIG. 20(A) shows an on state where a positive potential (V>0) is applied to the gate electrode (GE) and carriers (electrons) flow between the source electrode and the drain electrode.

[0114] FIG. 18 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. FIG. 19 shows an energy band diagram (schematic diagram) of the A-A' cross-section of FIG. 18. The black circles (●) in FIG. 19 represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. FIG. 20 shows an energy band diagram (schematic diagram) of the B-B' cross-section in FIG. 18. FIG. 20(A) shows an on state where a positive potential (V>0) is applied to the gate electrode (GE) and carriers (electrons) flow between the source electrode and the drain electrode.

[0115] FIG. 19 shows an energy band diagram (schematic diagram) of the A-A' cross-section of FIG. 18. The black circles (●) in FIG. 19 represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. In FIG. 19, the black circles (●) represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. In FIG. 19, the black circles (●) represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. D After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. In FIG. 19, the black circles (●) represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. G In FIG. 19, the black circles (●) represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. G >0 In FIG. 19, the black circles (●) represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V>0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V = 0), and the solid line indicates the case where a positive voltage (V>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. When a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows.

[0116] FIG. 20 shows an energy band diagram (schematic diagram) of the B-B' cross-section in FIG. 18. FIG. 20(A) shows an on state where a positive potential (V>0) is applied to the gate electrode (GE) and carriers (electrons) flow between the source electrode and the drain electrode. FIG. 20 shows an energy band diagram (schematic diagram) of the B-B' cross-section in FIG. 18. FIG. 20(A) shows an on state where a positive potential (V>0) is applied to the gate electrode (GE) and carriers (electrons) flow between the source electrode and the drain electrode. G >0 FIG. 20 shows an energy band diagram (schematic diagram) of the B-B' cross-section in FIG. 18. FIG. 20(A) shows an on state where a positive potential (V>0) is applied to the gate electrode (GE) and carriers (electrons) flow between the source electrode and the drain electrode. Also, FIG. 20(B) shows a state where a negative potential (V G <0) is applied to the gate electrode (GE). This indicates the off state (a state where minority carriers do not flow).

[0117] FIG. 21 shows the relationship between the vacuum level, the work function (φ M ) of the metal, and the electron affinity (χ) of the oxide semiconductor. It shows.

[0118] At room temperature, electrons in the metal are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located near the conduction band, away from the intrinsic Fermi level (E ) located at the center of the bandgap. Note that it is known that part of hydrogen in the oxide semiconductor acts as a donor and is one of the factors for n-type conversion. i ) Also, oxygen deficiency is known to be one of the factors for n-type conversion. In contrast, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor for n-type conversion, from the oxide semiconductor, purifies it to be as free as possible from elements (impurity elements) other than the main components of the oxide semiconductor, and makes it intrinsic (i-type) or attempts to make it intrinsic by removing oxygen deficiency. That is, instead of adding impurity elements to make it i-type, by removing impurities such as hydrogen and water and oxygen deficiency as much as possible, it is characterized by being highly purified i-type (intrinsic semiconductor ) or approaching it. As a result, the Fermi level (E

[0119] ) can be made comparable to the intrinsic Fermi level (E ) ) ) ) or approaching it. As a result, the Fermi level (E ) can be made comparable to the intrinsic Fermi level (E F ) ) i )

[0120] The bandgap (E g ​​​​​) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that. The work function of titanium (Ti) constituting the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface no Schottky-type barrier is formed for electrons.

[0121] At this time, as shown in Fig. 20(A), electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor).

[0122] Also, as shown in Fig. 20(B), when a negative potential is applied to the gate electrode (GE), since the number of minority carriers, holes, is substantially zero, the current becomes a value approaching zero infinitely.

[0123] By highly purifying the oxide semiconductor so that elements other than the main component of the oxide semiconductor (impurity elements) are not contained as much as possible, it becomes intrinsic (i-type) or substantially intrinsic, so the interface characteristics with the gate insulating layer are manifested. Therefore, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. By highly purifying the oxide semiconductor and making the interface between the oxide semiconductor and the gate insulating layer good, for example, when the channel width (W) of the transistor is 1×10

[0124] μm and the channel length (L) is 3 μm, an off-current of 10 A or less and a subthreshold slope of 0.1 V / dec. 4 μm, the channel length (L) is 3 μm, an off-current of 10 -13 A or less and a subthreshold slope of 0.1 V / dec. The characteristics of the threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be realized. It can be achieved.

[0125] In this way, by highly purifying so that elements other than the main component of the oxide semiconductor (impurity elements) are not contained as much as possible, the operation of the transistor can be made good. It can be achieved.

[0126] 〈Hot carrier degradation resistance of transistors using oxide semiconductors〉 Next, the hot carrier degradation resistance of transistors using oxide semiconductors will be described with reference to FIGS. 22 and FIG. 23. In the following description, an ideal situation is assumed for ease of understanding, and not all of it reflects the actual situation. Also, it should be noted that the following description is only a consideration. It is only a consideration at most.

[0127] The main causes of hot carrier degradation are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). In the following, for simplicity, only electrons are considered. For simplicity, only electrons are considered.

[0128] CHE injection refers to the phenomenon in which electrons having energy higher than the barrier of the gate insulating layer in the semiconductor layer are injected into the gate insulating layer or the like. The imparting of energy to electrons is performed by accelerating the electrons in a low electric field. is performed by accelerating the electrons in a low electric field.

[0129] DAHC injection refers to the phenomenon in which new electrons generated by the collision of electrons accelerated by a high voltage are injected into the gate insulating layer or the like. The difference between DAHC injection and CHE injection lies in whether or not avalanche breakdown due to impact ionization is involved. In DAHC injection, the valence of the semiconductor is involved. Electrons with kinetic energy above the energy gap are required.

[0130] Figures 22 and 23 show the energy required for various hot carrier injections estimated from the band structures of silicon (Si) and an In-Ga-Zn-O-based oxide semiconductor (I GZO). In Figures 22 and 23, the left represents CHE injection and the right represents DAHC injection.

[0131] In silicon, degradation due to DAHC injection is more serious than that due to CHE injection. This is because the band gap of silicon is small and avalanche breakdown is likely to occur. Since the number of carriers (e.g., electrons) that are accelerated without collision in silicon is very small, the probability of CHE injection itself due to that is low. However, the number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases, easily exceeding the probability of CHE injection.

[0132] In an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not very different from that in the case of silicon, but the energy required for DAHC injection is about the same as the energy required for CHE injection due to the wide band gap. That is, the probability of DAHC injection is low.

[0133] On the other hand, similar to silicon, the number of carriers (e.g., electrons) that are accelerated without collision is also very small, so the probability of CHE injection itself due to that is low. That is, the resistance to hot carrier degradation is high compared to silicon.

[0134] <Short-channel effect in a transistor using an oxide semiconductor> Next, the short-channel effect in a transistor using an oxide semiconductor will be described with reference to FIG. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the above necessarily reflect the actual situation. Also, the following explanation is only a guide. Please note that this is merely speculation.

[0135] The short channel effect becomes evident as transistors become smaller (as the channel length (L)) The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and S value. Increase in leakage current, etc.

[0136] Here, a structure capable of suppressing the short channel effect is developed using device simulation. Specifically, the carrier density and the thickness of the oxide semiconductor layer were varied. We prepared four types of models and confirmed the relationship between channel length (L) and threshold voltage (Vth). The model used a bottom-gate transistor with a carrier density of 1. 7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 The oxide semiconductor The thickness of the layer was set to either 1 μm or 30 nm. A Ga-Zn-O oxide semiconductor is used as the gate insulating layer, and a 100 nm thick silicon oxynitride layer is used as the gate insulating layer. A bare membrane was used.

[0137] There is no significant difference in the calculation results between the top gate structure and the bottom gate structure.

[0138] The calculation results are shown in Figures 24 and 25. Figure 24 shows the case where the carrier density is 1.7 × 10 -8 / c m 3 In the case of Figure 25, the carrier density is 1.0×10 15 / cm 3 This is the case. As a result, in a transistor including an oxide semiconductor, the thickness of an oxide semiconductor layer is reduced. This shows that the short channel effect can be suppressed by using In the case of an oxide semiconductor layer having a sufficiently low carrier density, the thickness of the oxide semiconductor layer is about 3 μm. nm to 50 nm, preferably 3 nm to 20 nm, typically about 20 nm. It is understood that the short channel effect can be sufficiently suppressed if

[0139] <Carrier density in oxide semiconductors> One of the technical ideas of the disclosed invention is to sufficiently reduce the carrier density in the oxide semiconductor layer. The aim is to obtain a carrier density as close as possible to the intrinsic (i-type) state. Regarding the method of measuring the carrier density in the oxide semiconductor layer, the following is a description of the method of measuring the carrier density in the oxide semiconductor layer. 7 for further explanation.

[0140] The carrier density in the oxide semiconductor layer was measured by fabricating a MOS capacitor using the oxide semiconductor layer. , CV measurement of the MOS capacitor (Capacitance Voltage Mea This can be obtained by evaluating the results of the confirmation (CV characteristics).

[0141] The carrier density is measured in the following steps (1)-(3). (1) MOS capacitor gate (2) Obtain the CV characteristics by plotting the relationship between the gate voltage Vg and the capacitance C. From the V characteristics, the gate voltage Vg and (1 / C) 2Obtain a graph representing the relationship with the graph In the weak inversion region in (1 / C) 2 Find the derivative value. (3) Substitute the obtained derivative value into the following equation (1) representing the carrier density N carrier density N d In Equation (1), e is the elementary charge , ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor

[0142]

Equation

[0143] As a sample for measurement, a MOS capacitor with the following structure was used. Structure of the MOS capacitor On a glass substrate, it has a titanium layer with a thickness of 300 nm, and on the titanium layer, it has a titanium nitride layer with a thickness of 100 nm On the titanium nitride layer, it has an oxide semiconductor layer with a thickness of 2 μm using an In-Ga-Zn-O-based oxide semiconductor ( a-IGZO), and on the oxide semiconductor layer, it has a silicon oxynitride layer with a thickness of 30 0 nm, and on the silicon oxynitride layer, it has a silver layer with a thickness of 300 nm

[0144] Note that the oxide semiconductor layer was formed by sputtering using a target for forming an oxide semiconductor containing In, Ga, and Zn ( In:Ga:Zn = 1:1:0.5 [atom%]) The formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio was Ar:O2 = 30 (sccm):15 (sccm))

[0145] Figure 26 shows the C-V characteristics, and Figure 27 shows the relationship between Vg and (1 / C) 2 respectively. In the weak inversion region of Figure 27, the carrier density obtained from the derivative value of (1 / C) 2 using Equation (1) is 6.0×10 / cm 10 / cm3 It was.

[0146] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, an oxide semiconductor having a carrier density of 1×10 12 / cm 3 Less than 1.45×10 10 / cm 3 (less than) By using such a gate insulating film, it is possible to obtain a transistor with excellent off-state current characteristics.

[0147] As described above, by using an oxide semiconductor, in particular, a highly purified and intrinsic oxide semiconductor, It is understood that various effects can be obtained. By realizing a crystalline oxide semiconductor layer, a new semiconductor device with excellent characteristics can be developed. The placement is realized.

[0148] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the transistor 150 will be described with reference to FIGS.

[0149] First, an insulating layer 102 is formed on a substrate 100. Then, a first oxide film is formed on the insulating layer 102. A first oxide semiconductor layer is formed, and a first heat treatment is performed to form a first oxide semiconductor layer including a surface of the first oxide semiconductor layer. The region including the oxide semiconductor layer 104 is crystallized to form the first oxide semiconductor layer 104 (see FIG. 2A).

[0150] The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate can be used for mass production of the semiconductor device according to one embodiment of the present invention. It is preferable that the glass substrate is a non-alkali glass substrate. The glass substrate may be, for example, aluminosilicate glass, aluminoborosilicate glass, or The substrate 100 may be made of a glass material such as borosilicate glass. Insulating substrates such as insulating substrates, quartz substrates, and sapphire substrates; semiconductor substrates such as silicon The surface of a semiconductor substrate made of a conductive material is covered with an insulating material. A conductive substrate made of a material having a surface covered with an insulating material can be used. A plastic substrate can also be used, provided that it can withstand a heat treatment of about 1000 nm.

[0151] The insulating layer 102 functions as a base and is formed by using a CVD method, a sputtering method, or the like. The insulating layer 102 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or nitride. The oxide layer is formed to include silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 102 may have a single layer structure or a stacked layer structure. The thickness of the insulating layer 102 is not particularly limited, but is, for example, 10 nm or more and 500 nm or less. Here, since the insulating layer 102 is not an essential component, the insulating layer 10 It is also possible to adopt a configuration in which no. 2 is provided.

[0152] Note that if hydrogen, water, or the like is contained in the insulating layer 102, hydrogen may enter the oxide semiconductor layer, and water may be released from the insulating layer 102. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 102 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0153] For example, when using a sputtering method, remove any residual moisture in the processing chamber. It is desirable to form an insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, , it is desirable to use adsorption-type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps. It is also possible to use a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump or the like has sufficiently removed hydrogen, water, etc., so that the concentration of impurities contained in the insulating layer 102 can be reduced.

[0154] In addition, when forming the insulating layer 102, it is desirable to use a high-purity gas in which impurities such as hydrogen and water have been reduced to a concentration of about several ppm (preferably, about several ppb).

[0155] The first oxide semiconductor layer is made of a quaternary metal oxide In-Sn-Ga-Zn-O-based material or a ternary metal oxide In-Ga-Zn-O-based material, In-Sn-Zn-O-based material, In-Al-Zn-O-based material, Sn-Ga-Zn-O-based material, Al-Ga-Z n-O-based material, Sn-Al-Zn-O-based material, or a binary metal oxide In-Zn -O-based material, Sn-Zn-O-based material, Al-Zn-O-based material, Zn-Mg-O-based material, Sn-Mg-O-based material, In-Mg-O-based material, In-O-based material, Sn- O-based material, Zn-O-based material, etc. It can be formed using these.

[0156] Alternatively, an oxide semiconductor material represented by In-A-B-O may be used. Here, A is one or more elements selected from Group 13 elements such as gallium (Ga) and aluminum (Al), Group 14 elements represented by silicon (Si) and germanium (Ge), etc. Also, B is one or more types selected from Group 12 elements represented by zinc (Zn). represents an element. The contents of In, A, and B are arbitrary, including the case where the content of A is zero. . On the other hand, the contents of In and B are not zero. That is, the above notations include In-Ga -Zn-O, In-Zn-O, and the like.

[0157] Among them, the In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices.

[0158] Typical examples of the In-Ga-Zn-O-based oxide semiconductor material include InGaO3(ZnO) m (m>0). Also, there is an oxide semiconductor material represented by using M instead of Ga, InMO3(Zn O) m (m>0). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn , Ga and Co, etc. can be applied. It should be noted that the above composition is derived from the crystal structure and is only an example.

[0159] In this embodiment, the first oxide semiconductor layer is formed by sputtering using a target for an In-Ga-Zn-O-based oxide semiconductor film.

[0160] As a target for fabricating the first oxide semiconductor layer by sputtering, for example , a target made of a metal oxide mainly composed of zinc oxide can be used. Also, for the composition ratio of the target for forming an oxide semiconductor film containing In, Ga, and Zn, In:Ga:Zn = 1:x:y (x is 0 or more and 2 or less, y is 1 or more and 5 or less). For example, In:Ga:Zn = 1:1:1 [atom ratio] (x = 1, y = 1) (that is, In2O3:Ga2O3: ZnO = 1:1:2 [mole ratio]) targets having such a composition ratio may also be used. Also, as a target for forming an oxide semiconductor film, a target having a composition ratio of In:Ga:Zn = 1:1:0.5 [ato m ratio], or a target having a composition ratio of In:Ga:Zn = 1:1:2 [atom ratio , or a target having a composition ratio of In:Ga:Zn = 1:0:1 [atom ratio] (x = 0, y = 1) can also be used. In this embodiment, since heat treatment is performed later to intentionally crystallize it, it is preferable to use a target for forming an oxide semiconductor film in which crystallization is likely to occur.

[0161] The relative density of the oxide semiconductor in the target for forming an oxide semiconductor film is 80% or more, preferably 9 5% or more, more preferably 99.9% or more. By using a target for forming an oxide semiconductor film having a high relative density, a dense first oxide semiconductor layer is formed. Also, in this embodiment , since heat treatment is performed later to intentionally crystallize the first oxide semiconductor layer, it is preferable to use a target for forming an oxide semiconductor film in which crystallization is likely to occur.

[0162] The formation atmosphere of the first oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. ​​. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of about several ppm (preferably about several ppb), and it is preferable to use a high-purity gas atmosphere .

[0163] When forming the first oxide semiconductor layer, for example, a substrate is placed in a processing chamber maintained in a reduced-pressure state and heated to a substrate temperature of 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower . Then, while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and a first oxide semiconductor layer is formed using a metal oxide as a target. By forming the oxide semiconductor layer while heating the substrate , impurities contained in the first oxide semiconductor layer can be reduced . Also, damage due to sputtering is reduced. Before, during, or after forming the first oxide semiconductor layer, it is preferable to remove water and the like remaining in the sputtering apparatus. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump . For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used . Also, a turbo pump with a cold trap added may be used . Since hydrogen, water, etc. are removed from the processing chamber evacuated using a cryopump, the impurity concentration of the first oxide semiconductor layer can be reduced . . .

[0164] As the formation conditions of the first oxide semiconductor layer, for example, conditions such as a distance between the substrate and the target of 1 70 mm, a pressure of 0.4 Pa, a DC power of 0.5 kW, and an atmosphere of oxygen (oxygen flow rate ratio 100%) atmosphere can be applied ) When using a power supply, dust (powder or flake-like substances formed during film formation) can be reduced which is preferable because the film thickness distribution becomes uniform. The thickness of the first oxide semiconductor layer is preferably 3 nm or more and 1 5 nm or less, and in this embodiment, it is 5 nm as an example. However, since the appropriate thickness varies depending on the oxide semiconductor material and application used, etc., the thickness may be selected according to the material and application used, etc.

[0165] Before forming the first oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering by introducing argon gas to generate plasma and remove the deposits on the surface of the insulating layer 102. Here, reverse sputtering means that in normal sputtering, ions are collided with the sputtering target, whereas, conversely, it refers to a method of modifying the surface by colliding ions with the processing surface. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate, etc. In addition, an atmosphere of nitrogen, helium, oxygen, etc. may be applied instead of the argon atmosphere.

[0166] Before forming the first oxide semiconductor layer, it is good to perform a preheating treatment to remove the moisture or hydrogen remaining in the inner wall of the sputtering apparatus, on the target surface, or in the target material. As the preheating treatment, there are methods such as heating the inside of the film formation chamber to 200 °C to 600 °C under reduced pressure, or methods of repeatedly introducing and exhausting nitrogen or inert gas while heating. After the preheating treatment is completed, the substrate or the sputtering apparatus is cooled and then the oxide semiconductor layer is formed without being exposed to the atmosphere. In this case, the target coolant should preferably be grease or the like instead of water. Yes. A certain effect can be obtained by repeating the introduction and exhaust of nitrogen without heating, but it is better to perform the operation while heating. It is even better to perform the operation while heating.

[0167] Next, a first heat treatment of the first oxide semiconductor layer is performed to crystallize a region including at least the surface of the first oxide semiconductor layer, thereby forming the first oxide semiconductor layer 104. Further, by this first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer can be removed. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. The heating time is 1 minute or longer and 24 hours or shorter. In the present embodiment, as the first heat treatment, heat treatment is performed at 700°C for 1 hour in a dry air atmosphere. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. The heating time is 1 minute or longer and 24 hours or shorter. In the present embodiment, as the first heat treatment, heat treatment is performed at 700°C for 1 hour in a dry air atmosphere. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. The heating time is 1 minute or longer and 24 hours or shorter. In the present embodiment, as the first heat treatment, heat treatment is performed at 700°C for 1 hour in a dry air atmosphere. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized.

[0168] In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized. In the first heat treatment, it is preferable that nitrogen, oxygen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen, oxygen, or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the first heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 104 can be removed. Therefore, impurities can be reduced, and a first oxide semiconductor layer 104 that is i-type or substantially i-type can be formed, so that a transistor 150 with extremely excellent characteristics can be realized.

[0169] Also, during the temperature increase of the first heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and during cooling, the atmosphere inside the furnace may be switched to an oxygen atmosphere. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, by switching the atmosphere to an oxygen atmosphere, oxygen can be supplied to the inside of the first oxide semiconductor layer to make it an i-type.

[0170] A first oxide semiconductor layer 104 having a crystal region in a region including at least the surface is formed by the first heat treatment. The crystal region formed in the region including the surface is formed by crystal growth from the surface toward the inside. The crystal region includes plate-like crystals having an average film thickness of 2 nm or more and 10 nm or less. Also, the crystal region is a region having crystals in which the c-axis is oriented in a direction substantially perpendicular to the surface. Here, substantially perpendicular means a state within ±10° from the vertical direction.

[0171] In this embodiment, an example is shown in which the entire first oxide semiconductor layer is crystallized by the first heat treatment, but it is not limited to this. As long as a crystal region is formed in a region including at least the surface of the first oxide semiconductor layer 104. For example, the first oxide semiconductor layer 104 may have an amorphous region on the lower surface of the first oxide semiconductor layer 104, that is, at the interface with the insulating layer 102. By having an amorphous region at the interface with the insulating layer 102, carriers flowing through the crystal region do not directly receive the influence of the interface with the insulating layer 102, which is preferable.

[0172] Note that the heat treatment apparatus used for the first heat treatment is not particularly limited, and an apparatus that heats an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element can be used. For example ​​​​​​​​​For example, electric furnaces and GRTA (Gas Rapid Thermal Anneal) equipment. , LRTA (Lamp Rapid Thermal Anneal) equipment and other RTA ( A Rapid Thermal Anneal (LRTA) device can be used. Halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps The radiation of light (electromagnetic waves) emitted from lamps such as high-pressure sodium lamps and high-pressure mercury lamps. The GRTA device uses high-temperature gas to heat the object to be treated. It is a device that performs processing.

[0173] Next, a first oxide semiconductor layer 104 having a crystalline region at least in a region including a surface thereof is formed with A second oxide semiconductor layer 105 is formed (see FIG. 2B).

[0174] The second oxide semiconductor layer 105 is a quaternary metal oxide similar to the first oxide semiconductor layer. Materials based on the In-Sn-Ga-Zn-O system, which is a material with a ternary metal oxide, In-Ga-Zn- O-based materials, In-Sn-Zn-O-based materials, In-Al-Zn-O-based materials, Sn-G a-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al- Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O Materials based on In-O, Sn-O, and Zn-O are single-element metal oxides. The material may be selected from the group consisting of fluorine, fluorine-containing ...

[0175] Among them, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to make the leakage current sufficiently small, and since the field-effect mobility is also high, it is suitable as a semiconductor material for use in semiconductor devices.

[0176] As a representative example of an In-Ga-Zn-O-based oxide semiconductor material, there is one represented by InGaO3(ZnO) m (m > 0). Also, in the above, using M instead of Ga, it can be expressed as I nMO3(ZnO) m (m > 0). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn) , cobalt (Co), etc. For example , as M, Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and M n, Ga and Co, etc. can be applied. It should be noted that the above composition is derived from the crystal structure and is merely an example.

[0177] Note that the second oxide semiconductor layer 105 may use a material having the same main component as the first oxide semiconductor layer 104, or preferably have the same crystal structure and a close lattice constant (mismatch of 1% or less). Or it may be formed using a material with a different main component.

[0178] When using a material with the same main component, in the crystallization of the second oxide semiconductor layer 105 performed later, crystal growth is likely to occur using the crystal region of the first oxide semiconductor layer 104 as a seed. Also , since the substantial film thickness can be increased, it is suitable for applications such as power devices. Furthermore, when using the same main component material, the interfacial physical properties such as adhesion and electrical properties are also good.

[0179] When using materials with different main components, the electrical characteristics of each layer can be made different. Thus for example, by using a material with high electrical conductivity for the second oxide semiconductor layer and a material with low electrical conductivity for the first oxide semiconductor layer, a semiconductor device with reduced influence of the underlying interface can be realized. Also, by using a material that is easy to crystallize for the first oxide semiconductor layer to form good seed crystals, and then forming and crystallizing the second oxide semiconductor layer, regardless of the ease of crystallization of the second oxide semiconductor layer, the second oxide semiconductor layer can be made to have good crystallinity.

[0180] In this embodiment, the second oxide semiconductor layer 105 is formed by sputtering using a target for forming an In-Ga-Zn-O-based oxide semiconductor film. The formation of the second oxide semiconductor layer 105 by sputtering may be performed in the same manner as the formation of the first oxide semiconductor layer by sputtering described above. However, the thickness of the second oxide semiconductor layer 105 is preferably made thicker than the thickness of the first oxide semiconductor layer 104. Also, the second oxide semiconductor layer 105 is preferably formed such that the sum of the thicknesses of the first oxide semiconductor layer 104 and the second oxide semiconductor layer 105 is 3 nm or more and 50 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material and application to be used, so the thickness may be selected according to the material and application to be used.

[0181] Next, a second heat treatment is performed on the second oxide semiconductor layer 105 to cause crystal growth using the crystal region of the first oxide semiconductor layer 104 as a seed, thereby forming the second oxide semiconductor layer 106 (see Fig. 2( C)).

[0182] ​​​​​​​​​​​​​​ The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heating time of the second heat treatment is 1 hour or longer and 100 hours or shorter, preferably 5 hours or longer and 20 hours or shorter, and typically 10 hours.

[0183] In the second heat treatment as well, it is preferable that nitrogen, oxygen, or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen, oxygen, or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). Further, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or lower, and more preferably in ultra-dry air with H2O of 1 ppm or lower. By such a second heat treatment, water (including hydroxyl groups) and hydrogen in the second oxide semiconductor layer 106 can be removed. Therefore, impurities can be reduced, and an i-type or substantially i-type second oxide semiconductor layer 106 can be formed, so that a transistor 150 with extremely excellent characteristics can be realized.

[0184] Also, during the temperature increase of the second heat treatment, the inside of the furnace may be set to a nitrogen atmosphere, and during cooling, the atmosphere may be switched to an oxygen atmosphere. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, the atmosphere can be switched to an oxygen atmosphere to supply oxygen to the inside of the second oxide semiconductor layer 106 to make it i-type.

[0185] In this way, by performing the second heat treatment for a long time, the second oxide semiconductor layer 105 and the first ​​​​​​​​​​​​​From the crystal region formed at the interface of the oxide semiconductor layer 104, the entire second oxide semiconductor layer 105 can be crystallized to form the second oxide semiconductor layer 106. Further, by the second heat treatment, the first oxide semiconductor layer 104 composed of a crystal layer having a higher degree of orientation and can be obtained.

[0186] The second oxide semiconductor layer 106 is composed of a crystal in which the c-axis is oriented in a direction substantially perpendicular to the interface with the first oxide semiconductor layer 104, similar to the crystal region of the first oxide semiconductor layer 104. Here ,"substantially perpendicular" means a state within ±10° from the vertical direction.

[0187] For example, when an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 106 , it may contain crystals represented by InGaO3(ZnO) m (m > 0 and m is not a natural number), or crystals represented by In2Ga2ZnO7 (In:Ga:Zn:O = 2:2:1:7). Such crystals are oriented by the second heat treatment so that their c-axis takes a direction substantially perpendicular to the surface of the oxide semiconductor layer 106.

[0188] Here, the above-mentioned crystals contain any of In, Ga, and Zn and can be regarded as a laminated structure of layers parallel to the a-axis (a-axis) and the b-axis. Specifically , the above-mentioned crystals have a structure in which a layer containing In and a layer not containing In (a layer containing Ga or a layer containing Zn) are laminated in the c-axis direction.

[0189] In an In-Ga-Zn-O-based oxide semiconductor crystal, the conductivity in the direction parallel to the a-axis and the b-axis of the layer containing In is good. This is because in the In-Ga-Zn-O-based acid ​ In controls the electrical conduction mainly in the oxide semiconductor crystal, and the 5s orbit of one In forms a carrier path by overlapping with the 5s orbit of adjacent In. On the other hand, regarding the direction perpendicular to the layer (i.e., the c-axis direction), the insulation is improved.

[0190] Also, when the first oxide semiconductor layer 104 has an amorphous region near the interface with the insulating layer 102, by performing the second heat treatment, crystal growth occurs from the crystal region formed on the surface of the first oxide semiconductor layer 104 toward the lower surface of the first oxide semiconductor layer, and the amorphous region may be crystallized. Depending on the material constituting the insulating layer 102 and the conditions of the heat treatment, etc., the amorphous region may remain.

[0191] When using an oxide semiconductor material with the same main component for the first oxide semiconductor layer 104 and the second oxide semiconductor layer 105, as shown in Fig. 2(C), as the seed for the crystal growth of the first oxide semiconductor layer 104, crystal growth occurs upward toward the surface of the second oxide semiconductor layer 105, and the second oxide semiconductor layer 106 is formed, and the first oxide semiconductor layer 104 and the second oxide semiconductor layer 105 have the same crystal structure. Therefore, although shown by a dotted line in Fig. 2(C), the boundary between the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 cannot be distinguished, and the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 may be regarded as the same layer.

[0192] Thus, by forming the second oxide semiconductor layer 106 by crystal growth from the crystal region of the first oxide semiconductor layer 104, the second oxide semiconductor layer 106 has electrical anisotropy. is provided. In the above example, the conductivity in the direction parallel to the surface of the second oxide semiconductor layer 106 increases, while the insulation increases in the direction perpendicular to the surface of the second oxide semiconductor layer 106. Therefore, by using the second oxide semiconductor layer 106 crystal-grown from the crystal region of the first oxide semiconductor layer 104 with high purity, a semiconductor device having good electrical characteristics can be realized.

[0193] Note that the heat treatment apparatus used for the second heat treatment is not particularly limited, and it may be provided with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA apparatus such as a GRTA apparatus or an LRTA apparatus can be used.

[0194] Next, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 104a and second oxide semiconductor layer 106a (see FIG. 2(D)).

[0195] For the etching of the oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both of them can also be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the oxide semiconductor layer can be etched into a desired shape.

[0196] As dry etching, a parallel plate type RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) etching method, or the like can be used. Also in this case, the etching conditions ​​​​​​​​​(The amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the electrode on the substrate side such as temperature) needs to be set as appropriate.

[0197] Etching gases that can be used for dry etching include, for example, gases containing chlorine ( chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases , such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), tri fluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), gases with noble gases such as helium (He) and argon (Ar) added thereto, etc. may also be used. .

[0198] Etching liquids that can be used for wet etching include a solution of phosphoric acid, acetic acid, and nitric acid mixed together, aqueous ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% aqueous ammonia: water = 5 :2:2), etc. Also, etching liquids such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used. .

[0199] Next, a conductive layer 108 is formed so as to be in contact with the second oxide semiconductor layer 106a (see Fig. 2(E ).

[0200] The conductive layer 108 can be formed using PVD methods such as sputtering, and CVD methods such as plasma CVD. Also, the conductive layer 108 can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components. Manganese, magnesium, zirconium A material containing any one or more of mu and beryllium may be used. Also, aluminum may be used with a material containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium.

[0201] Further, the conductive layer 108 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO) can be used, an indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), an indium zinc oxide alloy (In2O3 - ZnO), or a material obtained by adding silicon or silicon oxide to these metal oxide materials.

[0202] As the conductive layer 108, a three - layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three - layer laminated structure in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Also, a two - layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two - layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two - layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can be used as the metal conductive film. Of course, it may be a single layer or a laminated structure of four or more layers as the metal conductive film. In the case of a single - layer structure, for example, a single - layer structure of a titanium layer is preferably used. When using a single - layer structure of a titanium layer, etching that can form a good taper shape during subsequent etching can be realized. Here, a three - layer structure of a titanium film, an aluminum film, and a titanium film will be applied. When using a single - layer structure of a titanium layer, etching that can form a good taper shape during subsequent etching can be realized.

[0203] In addition, when a material that can extract oxygen from the second oxide semiconductor layer 106a (a material with a high affinity for oxygen), such as titanium, is used in a portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a, the contact region between the conductive layer 108 and the second oxide semiconductor layer 106a is n-type due to oxygen deficiency. By utilizing this, the low resistance of the source region or the drain region can be achieved. On the other hand, an oxide conductor layer may be formed between the second oxide semiconductor layer 106a and the conductive layer 108 without using a material that can extract oxygen from the second oxide semiconductor layer 106a. Even when such an oxide conductive layer is provided, the low resistance of the source region or the drain region can be achieved. When n-type conversion of the contact region between the second oxide semiconductor layer 106a and the conductive layer 108 is not required, it is advisable to use a material with a low oxygen extraction effect (a material with a low affinity for oxygen) in the portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a. Examples of such materials include titanium nitride. The structure of the conductive layer 108 may be a single-layer structure or a laminated structure as described above. When the conductive layer 108 has a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, a two-layer structure of a titanium nitride film and a copper-molybdenum alloy film, a two-layer structure of a tantalum nitride film and a tungsten film, a two-layer structure of a tantalum nitride film and a copper film, a three-layer structure of a titanium nitride film, a tungsten film, and a titanium film, etc. can be adopted. By using a material with a low oxygen extraction effect as described above in the conductive layer 108, the oxide semiconductor

[0204] When a material that can extract oxygen from the second oxide semiconductor layer 106a is used in a portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a, the contact region between the conductive layer 108 and the second oxide semiconductor layer 106a is n-type due to oxygen deficiency. By utilizing this, the low resistance of the source region or the drain region can be achieved. On the other hand, an oxide conductor layer may be formed between the second oxide semiconductor layer 106a and the conductive layer 108 without using a material that can extract oxygen from the second oxide semiconductor layer 106a. Even when such an oxide conductive layer is provided, the low resistance of the source region or the drain region can be achieved. When n-type conversion of the contact region between the second oxide semiconductor layer 106a and the conductive layer 108 is not required, it is advisable to use a material with a low oxygen extraction effect (a material with a low affinity for oxygen) in the portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a. Examples of such materials include titanium nitride. The structure of the conductive layer 108 may be a single-layer structure or a laminated structure as described above. When the conductive layer 108 has a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, a two-layer structure of a titanium nitride film and a copper-molybdenum alloy film, a two-layer structure of a tantalum nitride film and a tungsten film, a two-layer structure of a tantalum nitride film and a copper film, a three-layer structure of a titanium nitride film, a tungsten film, and a titanium film, etc. can be adopted.

[0205] When n-type conversion of the contact region between the second oxide semiconductor layer 106a and the conductive layer 108 is not required, it is advisable to use a material with a low oxygen extraction effect (a material with a low affinity for oxygen) in the portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a. Examples of such materials include titanium nitride. The structure of the conductive layer 108 may be a single-layer structure or a laminated structure as described above. When the conductive layer 108 has a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, a two-layer structure of a titanium nitride film and a copper-molybdenum alloy film, a two-layer structure of a tantalum nitride film and a tungsten film, a two-layer structure of a tantalum nitride film and a copper film, a three-layer structure of a titanium nitride film, a tungsten film, and a titanium film, etc. can be adopted. By using a material with a low oxygen extraction effect as described above in the conductive layer 108, the oxide semiconductor When a material that can extract oxygen from the second oxide semiconductor layer 106a is used in a portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a, the contact region between the conductive layer 108 and the second oxide semiconductor layer 106a is n-type due to oxygen deficiency. By utilizing this, the low resistance of the source region or the drain region can be achieved. On the other hand, an oxide conductor layer may be formed between the second oxide semiconductor layer 106a and the conductive layer 108 without using a material that can extract oxygen from the second oxide semiconductor layer 106a. Even when such an oxide conductive layer is provided, the low resistance of the source region or the drain region can be achieved. When n-type conversion of the contact region between the second oxide semiconductor layer 106a and the conductive layer 108 is not required, it is advisable to use a material with a low oxygen extraction effect (a material with a low affinity for oxygen) in the portion of the conductive layer 108 that contacts the second oxide semiconductor layer 106a. Examples of such materials include titanium nitride. The structure of the conductive layer 108 may be a single-layer structure or a laminated structure as described above. When the conductive layer 108 has a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, a two-layer structure of a titanium nitride film and a copper-molybdenum alloy film, a two-layer structure of a tantalum nitride film and a tungsten film, a two-layer structure of a tantalum nitride film and a copper film, a three-layer structure of a titanium nitride film, a tungsten film, and a titanium film, etc. can be adopted. By using a material with a low oxygen extraction effect as described above in the conductive layer 108, the oxide semiconductor

[0206] By using a material with a low oxygen extraction effect as described above in the conductive layer 108, the oxide semiconductor Prevent n-type formation by extracting oxygen from the layer, and suppress adverse effects on transistor characteristics caused by non-uniform n-type formation or the like.

[0207] Also, as described above, by using a material with high barrier properties such as a titanium nitride film or a tantalum nitride film for the conductive layer 108 in the portion in contact with the second oxide semiconductor layer 106a, intrusion of impurities into the second oxide semiconductor layer 106a can be suppressed, and adverse effects on transistor characteristics can be suppressed. It is possible.

[0208] Next, the conductive layer 108 is selectively etched to form a source electrode layer or a drain electrode layer 10 8a, a source electrode layer or a drain electrode layer 108b (see FIG. 3(A)). Note that an insulating layer is formed on the conductive layer 108, and the insulating layer is etched to form an insulating layer having substantially the same shape as the source electrode layer or the drain electrode layer on the source electrode layer or the drain electrode layer. In this case, the capacitance (so-called gate capacitance) between the source electrode layer or the drain electrode layer and the gate electrode can be reduced. Note that in this specification and the like, the expression "substantially the same" is used in the sense that it does not necessarily have to be exactly the same, and includes a range that can be regarded as the same. For example, differences when formed by a single etching process are acceptable. Also, it does not have to be the same in terms of thickness. When performing exposure for mask formation used in etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. In particular, when performing exposure with a channel length (L) of less than 25 nm it is preferable to perform exposure for mask formation using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. Exposure with extreme ultraviolet light has high resolution.

[0209] For exposure during mask formation used in etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. In particular, when performing exposure with a channel length (L) of less than 25 nm it is preferable to perform exposure for mask formation using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. Exposure with extreme ultraviolet light has high resolution. , it is preferable to perform exposure for mask formation using extreme ultraviolet light (Extreme Ultraviolet let) with a wavelength as short as several nm to several tens of nm. Exposure with extreme ultraviolet light has high resolution. is highly focused and has a large depth of focus. Therefore, the channel length (L) of the transistor formed later can be set to 10 nm or more and 1000 nm (1 μm) or less. By reducing the channel length in this way, the operating speed can be improved. Also, since the transistor using the above oxide semiconductor has a very small off-current, an increase in power consumption due to miniaturization can be suppressed. When etching the conductive layer 108, the second oxide semiconductor layer 106a is not removed, and the respective materials and etching conditions are appropriately adjusted. Depending on the materials and etching conditions, a part of the second oxide semiconductor layer 106a may be etched in this process, resulting in an oxide semiconductor layer having a groove (recess). Also, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, the source electrode layer or drain electrode layer 108b, the crystal layer in contact therewith may be in an amorphous state. In order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed.

[0210] When etching the conductive layer 108, the second oxide semiconductor layer 106a is not removed, and the respective materials and etching conditions are appropriately adjusted. Depending on the materials and etching conditions, a part of the second oxide semiconductor layer 106a may be etched in this process, resulting in an oxide semiconductor layer having a groove (recess). Also, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, the source electrode layer or drain electrode layer 108b, the crystal layer in contact therewith may be in an amorphous state. When etching the conductive layer 108, the second oxide semiconductor layer 106a is not removed, and the respective materials and etching conditions are appropriately adjusted. Depending on the materials and etching conditions, a part of the second oxide semiconductor layer 106a may be etched in this process, resulting in an oxide semiconductor layer having a groove (recess). Also, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, the source electrode layer or drain electrode layer 108b, the crystal layer in contact therewith may be in an amorphous state.

[0211] Also, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, the source electrode layer or drain electrode layer 108b, the crystal layer in contact therewith may be in an amorphous state. When etching the conductive layer 108, the second oxide semiconductor layer 106a is not removed, and the respective materials and etching conditions are appropriately adjusted. Depending on the materials and etching conditions, a part of the second oxide semiconductor layer 106a may be etched in this process, resulting in an oxide semiconductor layer having a groove (recess). Also, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, the source electrode layer or drain electrode layer 108b, the crystal layer in contact therewith may be in an amorphous state.

[0212] Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Also, in order to reduce the number of masks used and the number of processes, a resist mask may be formed by a multi-tone mask, which is an exposure mask that transmits light having a plurality of intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing, so it can be used for a plurality of etching processes. That is, with a single multi-tone mask, a resist mask corresponding to at least two or more different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced. As a result, the process can be simplified.

[0213] Here, a heat treatment (third heat treatment) may be performed on the second oxide semiconductor layer 106a. By the third heat treatment, a high-purity crystal region is formed in a region including the surface of the exposed second oxide semiconductor layer 106a without overlapping with the source electrode layer or the drain electrode layer 108a, 108b. Here, the high-purity crystal region is a region where the crystallinity is enhanced compared to other regions of the second oxide semiconductor layer 106a. Note that the range of the high-purity crystal region varies depending on the material constituting the second oxide semiconductor layer 106a, the heat treatment conditions, and the like. For example, it is also possible to form a high-purity crystal region up to the lower interface of the second oxide semiconductor layer 106a. it is possible to form a high-purity crystal region up to the lower interface of the second oxide semiconductor layer 106a.

[0214] For the third heat treatment, the same heat treatment as the first heat treatment can be applied. That is, heat treatment using an electric furnace, heat treatment using heat conduction from a medium such as a heated gas, heat treatment by heat radiation, etc. can be applied.

[0215] For example, GRTA treatment at a temperature of 400°C or higher and 900°C or lower using a high-temperature inert gas (such as nitrogen or a noble gas) can be applied. Regarding the upper limit of the heat treatment temperature, although there is no requirement from the essential part of the invention, when the heat resistance of the substrate 100 is low, the upper limit of the heat treatment temperature needs to be within the range of its heat resistance.

[0216] When applying GRTA treatment, the heat treatment time is preferably 1 minute or more and 100 minutes or less. For example, it is good to perform GRTA treatment at 650°C for about 3 to 6 minutes. As described above,​​​​​​ By applying the GRTA process, heat treatment can be performed in a short time, so that the influence of heat on the substrate 100 can be reduced. That is, compared with the case of performing heat treatment for a long time , it is possible to raise the upper limit of the heat treatment temperature. In addition, it is easy to form a high-purity crystal region in the region including the surface of the second oxide semiconductor layer 106 a.

[0217] In the third heat treatment, it is desirable that the treatment atmosphere does not contain hydrogen (including water), etc. For example, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%, that is, the impurity concentration is 1 ppm or less), preferably 7N (99.99999%, that is, the impurity concentration is 0.1 ppm or less) or more. Also, instead of the inert gas, oxygen gas, N2O gas, ultra-dry air (dew point is -40 °C or lower, preferably - 60 °C or lower), etc. in which hydrogen (including water) is sufficiently reduced may be used.

[0218] In the present embodiment, the GRTA process is applied as the third heat treatment, but the third heat treatment is not limited to the GRTA process. For example, heat treatment by an electric furnace, LRTA process, etc. can also be applied.

[0219] Thus, by performing the third heat treatment, a high-purity crystal region, which is a crystal region with higher purity, can be recrystallized in the second oxide semiconductor layer 106 a having crystals. Also , when the surface of the second oxide semiconductor layer 106a is damaged during the formation of the source electrode layer or drain electrode layers 108a, 108b, it is possible to recover the damaged portion.

[0220] Even in the high-purity crystal region formed in this way, like the above-described crystal, the structure of the oxide semiconductor ​The crystal is oriented such that its c-axis is substantially perpendicular to the surface of the oxide semiconductor layer. Here, "substantially perpendicular" means a state within ±10° from the perpendicular direction.

[0221] By including such a high-purity crystal region, the electrical anisotropy imparted to the second oxide semiconductor layer 106a can be improved. The electrical anisotropy imparted to the second oxide semiconductor layer 106a can be improved.

[0222] By providing such a high-purity crystal region in the second oxide semiconductor layer 106a, the electrical characteristics of the semiconductor device can be further improved. The electrical characteristics of the semiconductor device can be further improved.

[0223] Next, a gate insulating layer 112 in contact with a part of the second oxide semiconductor layer 106a is formed without exposing it to the atmosphere (see Fig. 3(B)). The gate insulating layer 112 can be formed using a method such as CVD or sputtering. The gate insulating layer 112 can be formed using a method such as CVD or sputtering. Also, the gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less.

[0224] Note that an i-type or substantially i-type oxide semiconductor (high-purity oxide semiconductor) obtained by removing impurities is extremely sensitive to interface levels and interface charges, so high quality is required for the gate insulating layer 112. Note that an i-type or substantially i-type oxide semiconductor (high-purity oxide semiconductor) obtained by removing impurities is extremely sensitive to interface levels and interface charges, so high quality is required for the gate insulating layer 112. Note that an i-type or substantially i-type oxide semiconductor (high-purity oxide semiconductor) obtained by removing impurities is extremely sensitive to interface levels and interface charges, so high quality is required for the gate insulating layer 112.

[0225] In this embodiment, the gate insulating layer 112 is formed using a high-density plasma device. Here, the high-density plasma device refers to a device that can achieve a plasma density of 1×10 11 / cm 3 or higher. For example, microwave power of 3 kW to 6 kW is applied to generate plasma for forming an insulating film. For example, the high-density plasma CVD method using microwaves (e.g., 2.45 GHz) is suitable in that it can form a high-quality gate insulating layer 112 that is dense and has high breakdown voltage. By closely contacting the highly purified oxide semiconductor layer with the high-quality gate insulating layer, the interface states can be reduced and the interface characteristics can be made good.

[0226] Silane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into the chamber as material gases, and high-density plasma is generated under a pressure of 10 Pa to 30 Pa to form the gate insulating layer 1 12. Then, the supply of silane gas is stopped, and nitrous oxide (N2O) and a rare gas may be introduced without exposing to the atmosphere to perform plasma treatment on the surface of the insulating film. At least the plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N2O) and a rare gas is performed after the formation of the insulating film. The insulating film that has undergone the above process sequence is an insulating film with a thin film thickness, for example, less than 100 nm, and can ensure reliability.

[0227] When forming the gate insulating layer 112, the flow rate ratio of silane gas (SiH4) to nitrous oxide (N2O) introduced into the chamber is in the range of 1:10 to 1:200. Also, as the rare gas introduced into the chamber, helium, argon, krypton, xenon, etc. can be used , but it is preferable to use argon, which is inexpensive among them.

[0228] ​​​​​​​​​

[0229] In addition, the insulating film obtained by the high-density plasma device can form a film with a constant thickness, so it has excellent step coverage. Also, the insulating film obtained by the high-density plasma device can precisely control the thickness of a thin film.

[0230] The insulating film obtained through the above process sequence is significantly different from the insulating film obtained by a conventional parallel-plate PCVD device. When comparing the etching rates using the same etchant, it is 10% or more, or 20% or more slower than the insulating film obtained by the parallel-plate PCVD device. The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0231] In this embodiment, a silicon oxynitride film (also referred to as SiOxNy, where x > y > 0) with a film thickness of 100 nm obtained by a high-density plasma device is used as the gate insulating layer 112.

[0232] Of course, if a high-quality insulating layer can be formed as the gate insulating layer 112, other methods such as sputtering or plasma CVD can also be applied. Also, an insulating layer whose film quality and interface characteristics are modified by heat treatment after formation may be applied. In any case, an insulating layer with good film quality as the gate insulating layer 112 and capable of reducing the interface state density with the oxide semiconductor layer and forming a good interface may be provided.

[0233] By improving the interface characteristics with the gate insulating layer 112 in this way and removing impurities in the oxide semiconductor, especially hydrogen and water, even for a gate bias - thermal stress test (BT test: for example, 85°C, 2 × 10 V / cm, 12 hours, etc.), the threshold voltage (Vt 6 It is possible to obtain a stable transistor in which (h) does not vary.

[0234] Thereafter, it is desirable to perform a fourth heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. For example, a heat treatment at 250°C for 1 hour may be performed in a nitrogen atmosphere. Performing the fourth heat treatment can reduce the variation in the electrical characteristics of the transistor. Also, it is possible to supply oxygen to the oxide semiconductor layer 106a by the fourth heat treatment.

[0235] In this embodiment, the fourth heat treatment is performed after the formation of the gate insulating layer 112. However, the timing of the fourth heat treatment is not particularly limited as long as it is after the third heat treatment. Also, the fourth heat treatment is not an essential step.

[0236] Next, a gate electrode layer 114 is formed in a region overlapping the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a on the gate insulating layer 112 (see FIG. 3(C)). The gate electrode layer 114 can be formed by forming a conductive layer on the gate insulating layer 112 and then selectively patterning the conductive layer.

[0237] The above conductive layer can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Also, the conductive layer can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components. Also, it may be formed using a nitride of the above-described elements, such as titanium nitride or tantalum nitride. Manganese, magnesium, zirconium , a material containing any one or more of beryllium may be used. Also, on aluminum , a material containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

[0238] Further, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3—ZnO), or those obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0239] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a nitride film containing tantalum and silicon, a two-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Here, a material containing titanium is used to form the conductive layer and processed into the gate electrode layer 114.

[0240] Next, an interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the gate insulating layer 112 and the gate electrode layer 114 (see Fig. 3(D)). The interlayer insulating layer 116 and the interlayer insulating layer 118 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide, nitride Materials containing inorganic insulating materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide can be used for formation. In this embodiment, although a laminated structure of the interlayer insulating layer 116 and the interlayer insulating layer 118 is adopted, one aspect of the disclosed invention is not limited thereto. It may be a single layer or a laminated structure of three or more layers. For example, the interlayer insulating layer 118 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the interlayer insulating layer 118, such as a sputtering method. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the interlayer insulating layer 118 by using a sputtering method. The substrate temperature during film formation may be from room temperature to 300 °C or less, and in this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a mixture of a rare gas (typically argon) and oxygen.

[0241] Moreover, a silicon target or a silicon oxide target can be used as the target. For example, silicon oxide can be formed by the sputtering method in an atmosphere of oxygen and nitrogen using a silicon target. The interlayer insulating layer 118 provided on the low-resistance oxide semiconductor layer uses an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH− and blocks the intrusion of these from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. Furthermore, a protective insulating layer such as a silicon nitride film or an aluminum nitride film may be formed on the interlayer insulating layer 118. In addition, the interlayer insulating layer 118 is not limited to the above structure. For example, the interlayer insulating layer 118 may be formed by a chemical vapor deposition method (CVD method) or a plasma enhanced chemical vapor deposition method (PECVD method). In this case, the film formation conditions such as the gas flow rate, the reaction temperature, and the reaction pressure need to be adjusted according to the type of the insulating film to be formed. In addition, the interlayer insulating layer 118 may be formed by a spin coating method or a spray coating method using an organic insulating material. In this case, the viscosity of the organic insulating material solution, the spin speed, and the spray pressure need to be adjusted according to the type of the insulating film to be formed. However, when an organic insulating material is used, it is necessary to pay attention to the influence of impurities such as moisture and hydrogen ions on the device performance. Therefore, in this embodiment, an inorganic insulating film is preferably used for the interlayer insulating layer 118. In addition, the interlayer insulating layer 116 and the interlayer insulating layer 118 may be formed integrally or separately. When formed separately, the formation order and the formation conditions of the two insulating layers need to be optimized according to the device structure and the performance requirements. In addition, in order to improve the adhesion between the interlayer insulating layer 118 and the underlying layer, a buffer layer or a primer layer may be provided between them. This buffer layer or primer layer can be made of a material such as titanium nitride, titanium oxide, or silicon nitride, and its thickness and composition can be adjusted according to the specific situation.

[0242] In addition, before the formation of the interlayer insulating layer 118, the inner wall of the sputtering device, the surface of the target, and the It is advisable to perform a preheat treatment to remove any moisture or hydrogen remaining in the material. After the preheating process is completed, cool the substrate or sputtering device and then store it in a cool place without exposing it to the air. In this case, the target cooling liquid is not water but oil or the like. Repeated nitrogen introduction and evacuation without heating can produce a certain effect, but It's even better if you do it while it's hot.

[0243] After the interlayer insulating layer 118 is formed, a silicon nitride film is formed by a sputtering method without exposure to the air. Alternatively, a laminated structure may be formed.

[0244] In addition, the interlayer insulating layer 118 and the interlayer insulating layer 116 are provided with a contact that reaches the gate electrode layer 114. A contact hole is formed, electrically connected to the gate electrode layer 114, and a contact for applying a gate potential is formed. A contact electrode may be formed on the interlayer insulating layer 118. Also, after the interlayer insulating layer 116 is formed, the gate A contact hole is formed to reach the source electrode layer 114, and a source electrode layer or a drain electrode layer is formed thereon. A connection electrode is formed using the same material as the contact electrode layer, and an interlayer insulating layer 118 is formed on the connection electrode. After forming a contact hole in the insulating layer 118 that reaches the connection electrode, the insulating layer 118 is electrically connected to the connection electrode. An electrode for providing a gate potential by forming an electrode connected to the interlayer insulating layer 118 may be formed on the interlayer insulating layer 118 .

[0245] It is preferable that the interlayer insulating layer 118 is formed so that its surface is flat. By forming the interlayer insulating layer 118 so as to have a flat surface, a conductive layer is formed on the interlayer insulating layer 118. This is because electrodes, wiring, etc. can be formed suitably.

[0246] As described above, the second oxide semiconductor layer 106a grown from the crystal region of the first oxide semiconductor layer 104a is used to complete the transistor 150.

[0247] By manufacturing the transistor 150 by the method as described above, good electrical characteristics are realized by the crystal of the second oxide semiconductor layer 106a.

[0248] By performing crystallization by the first heat treatment and the second heat treatment, hydrogen which is an n-type impurity is removed from the oxide semiconductor, and high purity is achieved so that impurities other than the main component of the oxide semiconductor are not contained as much as possible, thereby making it intrinsic (i-type) or making it intrinsic type. That is, instead of adding impurities to make it i-type, by removing impurities such as hydrogen and water as much as possible, it is made into a highly purified i-type (intrinsic semiconductor) or brought close to it. By highly purifying the oxide semiconductor layer, the threshold voltage value of the transistor can be made positive, and a so-called normally-off transistor 150 can be realized.

[0249] Also, when the transistor 150 is manufactured by the method as described above, the hydrogen concentration of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a is 5×10 / cm 18 3 or less, and the off-current of the transistor 150 is 1×10 -13 A or less at the measurement limit. In this way, by sufficiently reducing the hydrogen concentration and supplying oxygen to highly purify the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, a transistor 150 with excellent characteristics can be obtained.

[0250] Conventional oxide semiconductors are generally n-type, and so-called normally-on, where current flows between the source electrode and the drain electrode even when the gate voltage is 0V, is likely to occur. Even if the field-effect mobility is high, it is difficult to control the transistor as a circuit when it is normally-on. When the oxide semiconductor is n-type, the Fermi level (Ef) is located away from the intrinsic Fermi level (Ei) at the center of the bandgap and is positioned closer to the conduction band. Note that it is known that a part of hydrogen in the oxide semiconductor is one of the factors that act as a donor and cause n-type doping. Therefore, in order to make the oxide semiconductor layer i-type, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor, and high purity is achieved so that impurities other than the main components of the oxide semiconductor are not contained as much as possible. That is, it is made intrinsic (i-type) or substantially intrinsic type, not by adding impurities to make it i-type, but by removing impurities such as hydrogen and water as much as possible, thereby achieving high purity i-type (intrinsic semiconductor) or approaching it. By doing so, the Fermi level (Ef) can be brought to the same level as the intrinsic Fermi level (Ei). By purifying the oxide semiconductor layer, the threshold voltage value of the transistor can be made positive, and a so-called normally-off switching element can be realized. As one of the processes for high purification, it is preferable to remove moisture and the like remaining in the sputtering apparatus before, during, or after forming the oxide semiconductor film. In order to remove the residual moisture in the sputtering apparatus, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is used.

[0251]

[0252]

[0253] ​ It is preferable. As the exhaust means, a cold trap may be added to the turbo pump. Even a sputtering apparatus evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and compounds containing compounds containing hydrogen atoms such as water (H2O) are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. Further, the relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 95 % or more, and more preferably 99.9% or more. Using a target with a high relative density can reduce the impurity concentration in the formed oxide semiconductor film. When impurities are mixed into the formed oxide semiconductor film, there is a risk of inhibiting one-way crystal growth, that is, crystal growth from the surface downward, during the subsequent heat treatment for crystallization. Therefore, it is ideal to have a state where there are no impurities in the oxide semiconductor film, and high purification is extremely important.

[0254] If impurities are mixed into the formed oxide semiconductor film, there is a risk of inhibiting one-way crystal growth, that is, crystal growth from the surface downward, during the subsequent heat treatment for crystallization. Therefore, it is ideal to have a state where there are no impurities in the oxide semiconductor film, and high purification is extremely important. When performing the film formation of the oxide semiconductor film, it is also possible to perform a preheating treatment to remove moisture or hydrogen remaining on the inner wall of the sputtering apparatus, the target surface, or the target material. As the preheating treatment, there are methods such as heating the inside of the film formation chamber to 200°C to 600°C under reduced pressure, or methods such as repeatedly introducing and exhausting nitrogen or inert gas while heating. In this case

[0255] for the target coolant, it is preferable to use grease or the like instead of water. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform it while heating. After the preheating treatment is completed, the substrate or the sputtering apparatus is cooled, and the film formation of the oxide semiconductor film is performed. It is also possible to perform a preheating treatment to remove moisture or hydrogen remaining on the inner wall of the sputtering apparatus, the target surface, or the target material. As the preheating treatment, there are methods such as heating the inside of the film formation chamber to 200°C to 600°C under reduced pressure, or methods such as repeatedly introducing and exhausting nitrogen or inert gas while heating. In this case for the target coolant, it is preferable to use grease or the like instead of water. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform it while heating. After the preheating treatment is completed, the substrate or the sputtering apparatus is cooled, and the film formation of the oxide semiconductor film is performed. After completing the preheating treatment, cool the substrate or the sputtering apparatus and perform film formation of the oxide semiconductor film.

[0256] Also, when forming an oxide semiconductor film or a material film formed in contact therewith, the sputtering gas used should also be a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to a concentration of about several ppm (preferably about several ppb).

[0257] Also, during the formation of the oxide semiconductor film by sputtering, the substrate may be heated to a temperature equal to or higher than room temperature and lower than the strain point of the substrate.

[0258] Also, as one of the processes for high-purity purification, a first heat treatment is performed in an atmosphere containing almost no hydrogen and moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, for moisture, the dew point is -40 °C or lower, preferably -50 °C or lower), etc.). This first heat treatment can also be called dehydration or dehydrogenation to desorb H, OH, etc. from the oxide semiconductor layer. When heating is performed while raising the temperature in an inert atmosphere and then switching to an atmosphere containing oxygen in the middle, or when heat treatment is performed in an oxygen atmosphere, it can also be called an oxidation treatment. The first heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas, or an instantaneous heating method such as an LRTA (Lamp

[0259] Rapid Thermal Anneal) method using lamp light. Also, the first heat treatment may be performed simultaneously with heating by irradiating light with a wavelength of 450 nm or less. The oxide semiconductor layer subjected to the first heat treatment for high-purity purification should have, when measured up to 450 °C by TDS (Thermal Desorption Spe ctroscopy) on the oxide semiconductor layer after the first heat treatment, at least one of the two peaks of water ctroscopy), less than ​​​​​​​The heat treatment conditions are such that one peak that appears around 300°C is not detected. Therefore, , for a transistor using an oxide semiconductor layer that has undergone heat treatment for purification, when measuring up to 450°C with T DS, at least a peak of water that appears around 300°C is not detected .

[0260] For the first heat treatment, since crystal growth is performed without a polycrystalline layer that serves as a seed for crystal growth, it is preferable to perform heating at a high temperature for a short time so that only crystal growth from the surface occurs. Also, , when the surface of the oxide semiconductor layer is flat, a good plate-like polycrystalline layer can be obtained. Therefore , it is desirable that the base member, for example, the insulating layer or the substrate, has as high flatness as possible. By increasing the flatness , it becomes easier to form a polycrystalline layer that contacts the entire surface of the base member, which is useful . For example, the flatness is about the same as that of a commercially available silicon wafer. For example, the height difference in AFM measurement in a region with a surface roughness of 1 μ m square is 1 nm or less, preferably 0.2 nm .

[0261] The polycrystalline layer increases the electrical conductivity σ by the overlapping and connection of the electron clouds of In in the oxide semiconductor. Therefore, a transistor having a polycrystalline layer can achieve a high field-effect mobility .

[0262] One method of further performing crystal growth using the flat plate-like polycrystalline layer formed by the first heat treatment as a seed is shown below with reference to FIGS. 14(A), 14(B), and 14(C).

[0263] To briefly explain the order of steps, after forming the first oxide semiconductor layer on the base member, a first heat treatment for purification is performed, and by the same process as the first heat treatment for purification ​ A polycrystalline layer with aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, and a second oxide semiconductor layer is laminated thereon. Further, by performing a second heat treatment for crystallization, the second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first

[0264] oxide semiconductor layer as a seed. The first heat treatment causes crystal growth to occur from the surface in a state where there is no crystal layer serving as a seed for crystal growth. In contrast, in the second heat treatment, since there is a flat polycrystalline layer serving as a seed, heating can be performed for a long time at the lowest temperature at which crystal growth is possible, and good crystallinity can be obtained, which is preferable. The crystal direction achieved by the second heat treatment is from bottom to top, from the substrate side to the surface side (also referred to as the recrystallization direction), and is different from the crystal direction in the first heat treatment. Also, since the polycrystalline layer obtained by the first heat treatment is heated again in the second heat treatment, the crystallinity is further improved.

[0265]

[0265] FIG. 14(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500.

[0266] Also, FIG. 14(B) is a cross-sectional view immediately after the formation of the second oxide semiconductor layer 502. The second oxide semiconductor layer 502 is formed by sputtering, and as the metal oxide target, a metal oxide target with In: Ga:Zn = 1:1:1 [atomic ratio] or a metal oxide target with In:Ga:Zn = 1:1:2 may be used.

[0267] 1 oxide crystal layer's polycrystalline layer (the first oxide crystal layer 501) as a seed, the second oxide semiconductor Crystal growth occurs upward toward the surface of the layer 502, and a second oxide crystal layer 503b is formed. The crystal members have the same crystal structure.

[0268] Note that a structure corresponding to Fig. 14(B) was actually fabricated, and a TEM photograph of the cross section is shown in Fig. 15 (A). A schematic diagram is shown in Fig. 15(B). The TEM photograph is a high-magnification photograph (8 million times) observed with a high-resolution transmission electron microscope (Hitachi, Ltd. "H9000-NAR": TEM ) at an acceleration voltage of 3 00 kV. The sample for which Fig. 15(A) was taken was obtained by forming an insulating layer on a glass substrate, forming a first In-Ga-Zn-O film with a film thickness of 5 nm thereon, and performing a heat treatment at 700 °C for 1 hour in a dry air atmosphere. In Fig. 15(A ), it can be confirmed that the first In-Ga-Zn-O film is c-axis oriented in the direction perpendicular to the surface of the first In-Ga-Zn-O film, and that the interface between the first In-Ga-Zn-O film and the insulating layer is also crystallized and c-axis oriented in the direction perpendicular to the surface. As shown in Fig. 14( A), a first oxide crystal layer 501 containing a flat polycrystal is formed on the base member. This flat polycrystal is a crystal of InGaZnO4 (In:Ga:Zn:O = 1:1:1: 4). Also, the c-axis direction of the crystal coincides with the depth direction.

[0269] In addition, the first In-Ga-Zn-O film of the sample for which Fig. 15(A) was taken was formed using a sputtering device and an oxide semiconductor film-forming target (In-Ga-Zn-O-based oxide semiconductor film-forming target (In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio], In:Ga :Zn = 1:1:1 [atom ratio])), at a substrate temperature of 200 °C and a film-forming rate of 4 nm / m It is formed by film formation in in. Also, it is not limited to the material and composition of this target. For example, In When using a target of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio], I t is easy to obtain polycrystals of n2Ga2ZnO7.

[0270] The crystal structure of In2Ga2ZnO7 contains any of In, Ga, and Zn and can be regarded as a laminated structure of layers parallel to the a-axis (a-axis) and the b-axis (b-axis). It can be captured as a laminated structure of layers parallel to the a-axis and b-axis. Since the electrical conduction of the crystal of In2Ga2ZnO7 is mainly controlled by In, the electrical properties of the layer containing In in the directions parallel to the a-axis and b-axis are good. The crystal of In2Ga2ZnO7 has overlapping and connected electron clouds of In, forming a carrier path.

[0271] Alternatively, instead of the above target, a metal oxide target of In2O3:Ga2O3:ZnO = 2:1:8 [mol e ratio] may be used.

[0272] Alternatively, a metal oxide target of In2O3:ZnO = 1:2 [mole ratio] that does not contain Ga may be used. When making a bottom gate type transistor, since the oxide of Ga is an insulator, using an In-Zn-O film can increase the field effect mobility more than using the first In-Ga-Zn-O film.

[0273] Also, since the polycrystals obtained by the first heat treatment are heated again by the second heat treatment, it becomes a third oxide crystal layer 503a with improved crystallinity.

[0274] Also, in the structure shown in Fig. 14(C), in contact with the base member 500, the third oxide crystal It can be said that it has a two-layer structure in which the crystal layer 503a and the second oxide crystal layer 503b are stacked in this order. The first The materials of the oxide crystal layer 501 and the second oxide semiconductor layer 502 are not particularly limited as long as polycrystals with a c axis orientation perpendicular to the surface can be obtained, and different materials may be used or materials with the same main component may be used.

[0275] When using an oxide semiconductor material with the same main component, as shown by the dotted line in Fig. 14(C), the boundary between the third oxide crystal layer 503a and the second oxide crystal layer 503b becomes unclear, and it can be regarded as a single-layer structure.

[0276] In this way, the polycrystalline layer composed of the stacked third oxide crystal layer 503a and the second oxide crystal layer 503b can be crystallized in two heat treatments.

[0277] In addition, in Fig. 14(A), the polycrystalline layer with relatively aligned crystal orientations formed on at least the surface of the first oxide semiconductor layer grows in the depth direction from the surface, so it can be formed without being affected by the shadow of the base member.

[0278] Actually, after the formation of the second In-Ga-Zn-O film, heat treatment at 650°C for 6 minutes was performed in a nitrogen atmosphere, and the TEM photograph of the cross section taken is shown in Fig. 16(A). In addition, the schematic diagram is shown in Fig. 16( B). In Fig. 16(A), it can be confirmed that the entire second In-Ga-Zn-O film is crystallized. Also, it can be confirmed that the crystals of the second In-Ga-Zn-O film are c-axis oriented perpendicular to the surface of the second In-Ga-Z n-O film. In addition, it can be confirmed that the vicinity of the interface between the first In-Ga-Zn-O film and the insulating layer is not crystallized even after the second heat treatment. ​​​

[0279] The mechanism by which a crystal layer with relatively aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, for example, an In-Ga-Zn-O film, will be described. By heat treatment, zinc contained in the In-Ga-Zn-O film diffuses and accumulates near the surface, serving as seeds for crystal growth. Crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat polycrystalline layer is formed. This is inferred from the fact that in TDS measurements up to 450 °C, In and Ga are not detected, while Zn shows a peak especially around 300 °C under vacuum heating conditions. Note that the TDS measurement is performed in a vacuum, and it has been confirmed that zinc has been detected from around 200 °C. By heat treatment, zinc contained in the In-Ga-Zn-O film diffuses and accumulates near the surface, serving as seeds for crystal growth. Since crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), a flat polycrystalline layer is formed. This is inferred from the fact that in TDS measurements up to 450 °C, In and Ga are not detected, while Zn shows a peak especially around 300 °C under vacuum heating conditions. Note that the TDS measurement is performed in a vacuum, and it has been confirmed that zinc has been detected from around 200 °C.

[0280] Also, as a comparative example, a TEM photograph of the cross-section of a sample obtained by forming an In-Ga-Zn-O film with a thickness of 50 nm and then heating it at 700 °C for 1 hour is shown in Fig. 17(A). A schematic diagram is shown in Fig. 17(B). The TEM photograph according to Fig. 17(A) is a high-magnification photograph (2 million times) observed with a high-resolution transmission electron microscope (Hitachi, Ltd.'s "H9000-NAR": TEM) with an acceleration voltage of 300 kV. From Fig. 17(A), it can be confirmed that about 5 nm from the surface of the In-Ga-Zn-O film is crystallized, and there are many amorphous portions and a plurality of randomly oriented crystals inside the In-Ga-Zn-O film. From this, it can be said that even if heat treatment at 700 °C, which is higher than 650 °C, and for 1 hour, which is longer than 6 minutes, is performed once after forming a film as thick as 50 nm, it is difficult to make the entire thick film into a crystal layer with high orientation.

[0281] ​​​​​​​​​​​​​From these experimental results, it can be said that by forming a film in two steps to form a polycrystalline layer that serves as a seed for crystal growth and then growing the crystal after forming the film again, a thick polycrystalline layer can be formed, indicating that the method disclosed in this specification is extremely useful. By forming a film in two steps and performing two heat treatments, a crystal layer with a high orientation, that is, a polycrystalline layer with a c-axis orientation perpendicular to the surface of the oxide semiconductor layer, can be obtained thickly for the first time. After that, it can be said that by growing the crystal after forming the film again, a thick polycrystalline layer can be formed, indicating that the method disclosed in this specification is extremely useful. By forming a film in two steps and performing two heat treatments, a crystal layer with a high orientation, that is, a polycrystalline layer with a c-axis orientation perpendicular to the surface of the oxide semiconductor layer, can be obtained thickly for the first time. Also, devices using metal oxides, typically In-Ga-Zn-O films, are completely different from devices using single-crystalline Si , devices using SiC, or devices using GaN.

[0282] Wide-gap semiconductors such as SiC (3.26 eV) and GaN (3.39 eV) are known. However, SiC and GaN are expensive materials. Also, for SiC, in order to selectively form a low-resistance region, a temperature of 1700 °C or higher is required for activation after doping with phosphorus or aluminum. Also, GaN has an epitaxial growth process that requires heating at 1200 °C or higher for a long time. That is, SiC and GaN require a processing temperature of 1000 °C or higher, and thinning on a glass substrate is substantially impossible. Moreover, SiC and GaN are only single crystals, require control in PN junctions, and need to be more perfect single crystals. Therefore, due to the incorporation of an unintended trace amount of impurities in the manufacturing process, it becomes a donor or acceptor, so there is a limit to the lower limit of the carrier density. On the other hand, metal oxides can have all crystal structures of amorphous, polycrystalline, or single-crystalline.

[0283] Wide-gap semiconductors such as SiC (3.26 eV) and GaN (3.39 eV) are known. However, SiC and GaN are expensive materials. Also, for SiC, in order to selectively form a low-resistance region, a temperature of 1700 °C or higher is required for activation after doping with phosphorus or aluminum. Also, GaN has an epitaxial growth process that requires heating at 1200 °C or higher for a long time. That is, SiC and GaN require a processing temperature of 1000 °C or higher, and thinning on a glass substrate is substantially impossible. Moreover, SiC and GaN are only single crystals, require control in PN junctions, and need to be more perfect single crystals. Therefore, due to the incorporation of an unintended trace amount of impurities in the manufacturing process, it becomes a donor or acceptor, so there is a limit to the lower limit of the carrier density. On the other hand, metal oxides can have all crystal structures of amorphous, polycrystalline, or single-crystalline. That is, SiC and GaN require a processing temperature of 1000 °C or higher, and thinning on a glass substrate is substantially impossible.

[0284] Moreover, SiC and GaN are only single crystals, require control in PN junctions, and need to be more perfect single crystals. Therefore, due to the incorporation of an unintended trace amount of impurities in the manufacturing process, it becomes a donor or acceptor, so there is a limit to the lower limit of the carrier density. On the other hand, metal oxides can have all crystal structures of amorphous, polycrystalline, or single-crystalline. However, SiC and GaN are expensive materials. Also, for SiC, in order to selectively form a low-resistance region, a temperature of 1700 °C or higher is required for activation after doping with phosphorus or aluminum. Also, GaN has an epitaxial growth process that requires heating at 1200 °C or higher for a long time. That is, SiC and GaN require a processing temperature of 1000 °C or higher, and thinning on a glass substrate is substantially impossible. Moreover, SiC and GaN are only single crystals, require control in PN junctions, and need to be more perfect single crystals. Therefore, due to the incorporation of an unintended trace amount of impurities in the manufacturing process, it becomes a donor or acceptor, so there is a limit to the lower limit of the carrier density. On the other hand, metal oxides can have all crystal structures of amorphous, polycrystalline, or single-crystalline.​​ can be utilized. This is because, without using the control of the PN junction, φ MS versus χ OS + 1 / 2Eg OS , φ MD versus χ OS +1 / 2Eg OS and the work functions of the source and drain ( φ MS and φ MD ), the electron affinity (χ OS ) of the metal oxide, and the energy bandgap (Eg OS ) are utilized to perform band control equivalent to the control of the PN junction. These are one of the characteristics of metal oxides.

[0285] The bandgap of metal oxides, typically the In-Ga-Zn-O film, is also about three times wider than that of single-crystalline silicon, and the manufacturing cost can be made lower than that of SiC, so it is an inexpensive material.

[0286] The bandgap of In-Ga-Zn-O is 3.05 eV, and based on this value, the intrinsic carrier density is calculated. The energy distribution f(E) of electrons in a solid is known to follow the Fermi-Dirac statistics shown by the following equation. It is known to follow the Fermi-Dirac statistics.

[0287] [Equation]

[0288] For an ordinary semiconductor where the carrier density is not extremely high (not degenerate), the following relational expression holds .

[0289] [Equation]

[0290] Therefore, the Fermi-Dirac distribution of Equation (1) is approximated by the Boltzmann distribution equation shown below. Approximated.

[0291]

Number

[0292] Using Equation (3) to calculate the intrinsic carrier density (n i ), the following equation is obtained.

[0293]

Number

[0294] Then, the effective density of states (Nc, Nv) of Si and In-Ga-Zn-O and the value of the band gap (Eg) were substituted into Equation (4) to calculate the intrinsic carrier density. The results are shown in Table 1. .

[0295]

Table 1

[0296] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. When 3.05 eV is selected as the bandgap of IGZO, in Si and In-Ga-Zn- O, assuming that the Fermi-Dirac distribution law is approximately correct for the intrinsic carrier density, it can be said that the former has a carrier density about 10 17 times larger than the latter.

[0297] In addition, the oxide semiconductor can form a thin film by sputtering at a heating temperature from room temperature to 400 °C, and the maximum process temperature can be less than 850 °C, typically 450 °C or higher and 700 °C or lower. When the maximum process temperature is set below the strain point of the glass, a large-area glass It is also possible to form it on a glass substrate. Therefore, for industrialization, the maximum process temperature is 850 ℃ or less, typically 450℃ or more and 700℃ or less, and it is important to be able to fabricate a metal oxide with a wide bandgap.

[0298] Also, when three-dimensionally integrating silicon integrated circuits, since the temperature for processing the oxide semiconductor is less than the temperature (1050℃) at which the bonding on the lower side (silicon side) is broken, it is also applicable to three-dimensional integrated circuits with silicon integrated circuits.

[0299] As described above, a semiconductor device with a new structure having excellent characteristics is realized by the disclosed invention.

[0300] 〈Modification Example〉 Next, a modification example of the semiconductor device shown in FIGS. 1 to 3 will be described with reference to FIGS. 4 to 6. Note that since many of the components of the semiconductor device shown in FIGS. 4 to 6 are common to the semiconductor device shown in FIGS. 1 to 3, only the differences will be described here.

[0301] The transistor 150 shown in FIG. 4(A) includes an oxide semiconductor layer 106a having a concave portion (groove portion). Note that the concave portion is formed by etching when forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b. Therefore, the concave portion is formed in a region overlapping with the gate electrode layer 114. The concave portion makes it possible to reduce the thickness of the semiconductor layer related to the channel formation region, which contributes to suppressing the short-channel effect.

[0302] The transistor 150 shown in FIG. 4(B) includes an oxide semiconductor layer having a high-purity crystal region 110 It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device. It includes 106a. Note that the high-purity crystal region 110 is formed after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and then performing a third heat treatment. Therefore, the high-purity crystal region 110 does not overlap with the source electrode layer or drain electrode layers 108a and 108b, and is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystal region 110 is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystal region 110 can improve the electrical anisotropy imparted to the second oxide semiconductor layer 106a, and can further improve the electrical characteristics of the semiconductor device.

[0303] The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B). The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B). The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B). The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B). The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B). The transistor 150 shown in FIG. 4(C) includes an oxide semiconductor layer 106a having a recess (groove), and has a high-purity crystal region 110 in a region including the exposed surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or drain electrode layers 108a and 108b. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 4(B). The effects resulting from this configuration are the same as those in the cases of FIGS. 4(A) and 4(B).

[0304] The transistor 150 shown in FIG. 5(A) has insulating layers 109a and 109b having substantially the same shape as the source electrode layer or drain electrode layers 108a and 108b and the source electrode layer or drain electrode layer 108b on them. In this case, the capacitance (so-called gate capacitance) between the source electrode layer or drain electrode layer and the gate electrode layer can be reduced. The transistor 150 shown in FIG. 5(A) has insulating layers 109a and 109b having substantially the same shape as the source electrode layer or drain electrode layers 108a and 108b and the source electrode layer or drain electrode layer 108b on them. In this case, the capacitance (so-called gate capacitance) between the source electrode layer or drain electrode layer and the gate electrode layer can be reduced. The transistor 150 shown in FIG. 5(A) has insulating layers 109a and 109b having substantially the same shape as the source electrode layer or drain electrode layers 108a and 108b and the source electrode layer or drain electrode layer 108b on them. In this case, the capacitance (so-called gate capacitance) between the source electrode layer or drain electrode layer and the gate electrode layer can be reduced. The transistor 150 shown in FIG. 5(A) has insulating layers 109a and 109b having substantially the same shape as the source electrode layer or drain electrode layers 108a and 108b and the source electrode layer or drain electrode layer 108b on them. In this case, the capacitance (so-called gate capacitance) between the source electrode layer or drain electrode layer and the gate electrode layer can be reduced. has the following advantages. In this specification and the like, the expression "substantially the same" is used in the sense that it does not need to be exactly the same, and includes the range that can be regarded as the same. For example, differences in the case of being formed by one etching process are allowed. Also, it does not need to be the same up to the thickness. 。 。

[0305] The transistor 150 shown in FIG. 5(B) includes an oxide semiconductor layer 106a having a concave portion (groove portion), and on the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, there are an insulating layer 109a and an insulating layer 109b having substantially the same shape as these. That is, it has the characteristics of the transistor 150 according to FIG. 4(A) and the characteristics of the transistor 150 according to FIG. 5 (A). The effects resulting from this configuration are also the same as in the cases of FIGS. 4(A) and 5(A). (A). 。

[0306] The transistor 150 shown in FIG. 5(C) has a high-purity crystal region 110 in a region including the surface of the exposed second oxide semiconductor layer 106a without overlapping with the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, and on the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, there are an insulating layer 109a and an insulating layer 109b having substantially the same shape as these. That is, it has the characteristics of the transistor 150 according to FIG. 4(B) and the characteristics of the transistor 150 according to FIG. 5(A). The effects resulting from this configuration are also the same as in the cases of FIGS. 4(B) and 。 。 drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, 。 5(A). 50. 。

[0307] The transistor 150 shown in Fig. 6(A) has a source electrode layer or a drain electrode layer with a single-layer structure 108a, and a source electrode layer or a drain electrode layer 108b. Specifically, for example, a single-layer structure of a titanium layer can be adopted. When the source electrode layer or the drain electrode layer has a single-layer structure, as compared with the case of having a stacked structure, an etching that forms a good tapered shape can be realized .

[0308] In the transistor 150 shown in Fig. 6(B), in the portion of the source electrode layer or the drain electrode layer 108a , and the oxide semiconductor layer 106a of the source electrode layer or the drain electrode layer 108b that is in contact , there are conductive layers 1 07a and 107b made of a material with a low effect of extracting oxygen (a material with low affinity for oxygen). By having such a conductive layer with a low effect of oxygen extraction , the n-type conversion of the oxide semiconductor layer due to oxygen extraction can be prevented, and the adverse effects on the transistor characteristics caused by non-uniform n-type conversion of the oxide semiconductor layer can be suppressed .

[0309] Note that in Fig. 6(B), a two-layer source electrode layer or drain electrode layer 108a and , a source electrode layer or a drain electrode layer 108b are adopted, but one aspect of the disclosed invention is not limited to this. A single-layer structure of a conductive layer made of a material with a low effect of extracting oxygen is also acceptable, or a stacked structure of three or more layers is also acceptable. In the case of a single-layer structure, for example, a single-layer structure of a titanium nitride film can be applied . In the case of a stacked structure, for example, a two-layer structure of a titanium nitride film and a titanium film can be adopted .

[0310] The transistor 150 shown in Fig. 28(A) has a first oxide semiconductor with amorphous remaining at the lower part It has a layer 104a. Here, the region including the first oxide semiconductor layer 104a in Fig. 28(A) is shown enlarged in Fig. 28(B). As shown in Fig. 28(B), the first oxide semiconductor layer 104a is characterized in that it is composed of a lower amorphous region 104aa and an upper crystalline region 104ab. Thus, by leaving an amorphous region below the crystalline region that functions as the channel formation region of the transistor 150, carriers flowing through the crystalline region are preferably not affected by the interface with the insulating layer 102. are not affected by the interface with the insulating layer 102, which is preferable. are not affected by the interface with the insulating layer 102, which is preferable.

[0311] Fig. 29 is a cross-sectional view showing an example of the configuration of a semiconductor device. The semiconductor device shown in Fig. 29 has a transistor 250 using a material other than an oxide semiconductor (for example, silicon) at the lower part and has a transistor 150 using an oxide semiconductor at the upper part. The transistor 150 using an oxide semiconductor is the transistor 150 shown in Fig. 1(A). Note that both the transistor 250 and the transistor 150 are described as n-type transistors here, but a p-type transistor may be employed. In particular, it is easy to make the transistor 250 p-type

[0312] The transistor 250 includes a channel formation region 21 6 provided in a substrate 200 containing a semiconductor material, impurity regions 214 and high-concentration impurity regions 220 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 216, a gate insulating layer 208a provided on the channel formation region 21 6, a gate electrode layer 210a provided on the gate insulating layer 208a, and a source electrode layer or a drain electrode electrically connected to the impurity region 214 6, a gate insulating layer 208a provided on the channel formation region 216, a gate electrode layer 210a provided on the gate insulating layer 208a, and a source electrode layer or a drain electrode electrically connected to the impurity region 214 6, a gate insulating layer 208a provided on the channel formation region 216, a gate electrode layer 210a provided on the gate insulating layer 208a, and a source electrode layer or a drain electrode electrically connected to the impurity region 214 ​It has a polar layer 230a and a source electrode layer or a drain electrode layer 230b (see Fig. 29). See.

[0313] Here, a sidewall insulating layer 218 is provided on the side surface of the gate electrode layer 210a. Also, in a region of the substrate 200 that does not overlap with the sidewall insulating layer 218 when viewed in plan, it has a high-concentration impurity region 220 and a metal compound region 224 in contact with the high-concentration impurity region 220. An element isolation insulating layer 206 is provided on the substrate 200 so as to surround the transistor 250, and an interlayer insulating layer 226 and an interlayer insulating layer 228 are provided so as to cover the transistor 250. The source electrode layer or the drain electrode layer 230a and the source electrode layer or the drain electrode layer 230b are electrically connected to the metal compound region 224 through openings formed in the interlayer insulating layer 226, the interlayer insulating layer 228, and the insulating layer 234. That is, the source electrode layer or the drain electrode layer 230a and the source electrode layer or the drain electrode layer 230b are electrically connected to the high-concentration impurity region 220 and the impurity region 214 through the metal compound region 224. The transistor 150 includes an oxide semiconductor layer 106a provided on the insulating layer 102, a source electrode layer or a drain electrode layer 108a provided on the oxide semiconductor layer 106a and electrically connected to the oxide semiconductor layer 106a, and a source electrode layer or a drain electrode layer 108b. And a gate insulating layer 112 provided so as to cover the oxide semiconductor layer 106a, the source electrode layer or the drain electrode layer 108a, and the source electrode layer or the drain electrode layer 108b, and a gate electrode provided in a region overlapping with the oxide semiconductor layer 106a on the gate insulating layer 112.

[0314] ​​​​​​​​having layer 114 (see FIG. 29).

[0315] Also, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Here, openings reaching the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b are provided in the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118. Through the openings, the electrodes 254d and 254e are respectively formed in contact with the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b. Also, in the same manner as the electrodes 254d and 254e, electrodes 254a, 254b, and 254c in contact with the electrodes 236a, 236b, and 236c are formed through the openings provided in the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118. , source electrode layer or drain electrode layer 108a, source electrode layer or drain electrode layer 10 8b are provided, and through the openings, the electrodes 254d, 254 e are respectively formed in contact with the source electrode layer or drain electrode layer 108a and the source electrode layer or drain ing electrode layer 108b. Also, in the same manner as the electrodes 254d and 254e, through the openings provided in the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118, electrodes 254a, 25 4b, and 254c in contact with the electrodes 236a, 236b, and 236c are formed.

[0316] Here, it is desirable that the oxide semiconductor layer 106a is highly purified by sufficiently removing impurities such as hydrogen and supplying oxygen. Specifically, the hydrogen concentration in the oxide semiconductor layer 106a is 5×10 / cm 06a is 5×10 19 / cm 3 or less, desirably 5×10 18 / cm 3 or less, more desirably 5×10 17 / cm 3 or less. Note that in the oxide semiconductor layer 106a in which the hydrogen concentration is sufficiently reduced and highly purified by supplying oxygen, the carrier density value is sufficiently small compared to that in a general silicon wafer (a silicon wafer doped with a small amount of impurity elements such as phosphorus and boron) (about 1×10 / cm ). carrier density (about 1×10 14 / cm 3 ). (For example, less than 1×10 12 / cm 3 and desirably, less than 1.45×10 10 / cm 3 is adopted.) By using an i-type or substantially i-type oxide semiconductor in this way, a transistor 150 with extremely excellent off-current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V and the gate voltage Vg is in the range from -5V to -20V the off-current is 1×10 -13 A or less. In this way, by applying an oxide semiconductor layer 106a with a sufficiently low hydrogen concentration and a high purity to reduce the off-current of the transistor 150, a semiconductor device with a new configuration can be realized. Note that the hydrogen concentration in the above-mentioned oxide semiconductor layer 106a is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy).

[0317] Note that the oxide semiconductor constituting the oxide semiconductor layer is not particularly limited as long as it has a non-single crystal structure For example, various structures can be applied, such as an amorphous structure, a microcrystalline (microcrystal, nanocrystal, etc.) structure, a polycrystalline structure, a structure in which microcrystals or polycrystals are included in an amorphous material, and a structure in which microcrystals or polycrystals are formed on the surface of an amorphous structure.

[0318] Also, an insulating layer 256 is provided on the interlayer insulating layer 118, and electrodes 258a, 258b, 258c, and 258d are provided so as to be embedded in the insulating layer 256. Here, the electrode 258a is in contact with the electrode 254a, the electrode 258b is in contact with the electrode 254 b, the electrode 258c is in contact with the electrodes 254c and 254d, and the electrode 2 b, the electrode 258c is in contact with the electrodes 254c and 254d, and the electrode 2 58d is in contact with the electrode 254e. Also, it is preferable to use a material containing copper for the electrodes 258a, 258b, 258c, and a part of the electrode 258d. By using a material containing copper for the electrodes 258a, 258b, 258c, and a part of the electrode 258d, the conductivity can be improved. , that is, the source electrode layer or the drain electrode layer 108a of the transistor 150 is electrically connected to other elements (such as transistors using materials other than oxide semiconductors) via the electrodes 230c, 236c, 254c, 258c, 254d (see Fig. 29). Furthermore, the source electrode layer or the drain electrode layer 108b of the transistor 150 is electrically connected to other elements via the electrodes 254e and 258d. Note that the configuration of the electrodes related to the connection (such as the electrodes 230c, 236c, 254c, 258c, 254d, etc.) is not limited to the above, and additions, omissions, etc. can be made as appropriate. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected.

[0319] As described above, one aspect of the disclosed invention can be used in various modified forms. Also, the modified examples are not limited to the above examples. For example, Figs. 4(A), 4(B), 4(C), 5(A), 5(B), 5(C), 6(A), 6(B), 28, and 29 can be appropriately combined and used as another modified example. Of course, those described in the specification, etc. 0c, electrode 236c, electrode 254c, electrode 258c, electrode 254d are electrically connected to other elements (such as transistors using materials other than oxide semiconductors) (see Fig. 29). Reference). Furthermore, the source electrode layer or the drain electrode layer 108b of the transistor 150 is electrically connected to other elements via the electrodes 254e and 258d. Note that the configuration of the electrodes related to the connection (such as the electrodes 230c, 236c, 254c, 258c, 254d, etc.) is not limited to the above, and additions, omissions, etc. can be made as appropriate. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected.

[0320] In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected. In the above, one example of a typical connection relationship has been shown, but one aspect of the disclosed invention is not limited to this. For example, the gate electrode layer 210a of the transistor 250 and the source electrode layer or the drain electrode layer 108a of the transistor 150 may be electrically connected.

[0321] As described above, one aspect of the disclosed invention can be used in various modified forms. Also, the modified examples are not limited to the above examples. For example, Figs. 4(A), 4(B), 4(C), 5(A), 5(B), 5(C), 6(A), 6(B), 28, and 29 can be appropriately combined and used as another modified example. Of course, those described in the specification, etc. As described above, one aspect of the disclosed invention can be used in various modified forms. Also, the modified examples are not limited to the above examples. For example, Figs. 4(A), 4(B), 4(C), 5(A), 5(B), 5(C), 6(A), 6(B), 28, and 29 can be appropriately combined and used as another modified example. Of course, those described in the specification, etc. As described above, one aspect of the disclosed invention can be used in various modified forms. Also, the modified examples are not limited to the above examples. For example, Figs. 4(A), 4(B), 4(C), 5(A), 5(B), 5(C), 6(A), 6(B), 28, and 29 can be appropriately combined and used as another modified example. Of course, those described in the specification, etc. As described above, one aspect of the disclosed invention can be used in various modified forms. Also, the modified examples are not limited to the above examples. For example, Figs. 4(A), 4(B), 4(C), 5(A), 5(B), 5(C), 6(A), 6(B), 28, and 29 can be appropriately combined and used as another modified example. Of course, those described in the specification, etc. Within the scope, it is also possible to freely make changes, omissions, etc.

[0322] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0323] (Embodiment 2) In this embodiment, a semiconductor device having a configuration different from that of the semiconductor device according to the previous embodiment and its manufacturing method will be described with reference to FIGS. 7 to 12. Note that the configuration shown in this embodiment has many common points with the configuration shown in the previous embodiment, so hereinafter mainly only the differences will be described.

[0324] <Configuration of Semiconductor Device> FIG. 7 is a cross-sectional view showing a transistor 150 which is an example of the configuration of a semiconductor device.

[0325] The difference from the configuration shown in FIG. 1 is that a gate electrode layer 101 a is provided below the first oxide semiconductor layer 104a. That is, the transistor 150 shown in FIG. 7 includes a gate electrode layer 101a on a substrate 100, an insulating layer 102 covering the gate electrode layer 101a, a first oxide semiconductor layer 104a on the insulating layer 102, a second oxide semiconductor layer 106a provided on the first oxide semiconductor layer 104a, a source electrode layer or drain electrode layer 108a that is electrically connected to the second oxide semiconductor layer 106a, and a source electrode layer or drain electrode layer 108 b, a gate insulating layer 112 covering the second oxide semiconductor layer 106a, the source electrode layer or drain electrode layer 108a, and the source electrode layer or drain electrode layer 108b, and a gate electrode layer 114 on the gate insulating layer 112 (see FIGS. 7(A) and 7(B)). Here, the insulating layer 102 also functions as a gate insulating layer.

[0326] Also, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that since the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components, they may be omitted as appropriate.

[0327] As shown in Embodiment 1, the first oxide semiconductor layer 104a has a crystal region including the surface, and the second oxide semiconductor layer 106a is formed by crystal growth from the crystal region of the first oxide semiconductor layer 104a.

[0328] The gate electrode layer 101a shown in FIGS. 7(A) and 7(B) can function as a so-called back gate. The potential of the back gate can be a fixed potential, for example, 0 V or a ground potential, and can be determined as appropriate by the implementer. Also, by providing gate electrodes above and below the oxide semiconductor layer, in a bias - thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin - film transistor, the change amount of the threshold voltage of the thin - film transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, the threshold voltage can be controlled. Also, the threshold voltage can be made positive to function as an enhancement - type transistor. Also, the threshold voltage can be made negative to function as a depletion - type transistor. For example, an enhancement - type transistor and a depletion - type transistor can be combined. to form an inverter circuit (hereinafter referred to as an EDMOS circuit) and use it for a drive circuit is possible. The drive circuit includes at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit.

[0329] Note that in the oxide semiconductor layer, the region overlapping the unevenness of the insulating layer 102 has grain boundaries and becomes polycrystals. Also, in the oxide semiconductor layer, the region that becomes the channel formation region has at least a flat surface, and the first oxide semiconductor layer and the second oxide semiconductor layer have the same C-axis orientation and are polycrystals. Note that the height difference on the surface of the second oxide semiconductor layer is 1 nm or less (preferably 0.2 nm or less) in the region (channel formation region) overlapping with the gate electrode layer. This is preferable.

[0330] Details of each component can be referred to the previous embodiments and are thus omitted.

[0331] As shown in the configuration of FIG. 7, by using the second oxide semiconductor layer 106a crystal-grown from the crystal region of the highly purified first oxide semiconductor layer 104a, a semiconductor device having good electrical characteristics can be realized.

[0332] Further, when the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are the same (in the case of so-called homo-epitaxial growth), the boundary between the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a cannot be distinguished, and the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a may be regarded as the same layer (see FIG. 7(A)).

[0333] Of course, when the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are different​​ may also be used (see FIG. 7(B)). When the materials of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are different (in the case of so-called hetero-epitaxial growth), for example, a configuration may be adopted in which In-Zn-O, which is a binary metal oxide, is used for the first oxide semiconductor layer 104a, and In-Ga-Zn-O, which is a ternary metal oxide, is used for the second oxide semiconductor layer 106a. For example, a configuration using In-Zn-O for the first oxide semiconductor layer 104a and In-Ga-Zn-O for the second oxide semiconductor layer 106a can be adopted. etc.

[0334] Further, since the second oxide semiconductor layer 106a is relatively stable, it is possible to suppress the intrusion of impurities (such as moisture) into the second oxide semiconductor layer 106a. Therefore, the reliability of the second oxide semiconductor layer 106a can be improved. etc.

[0335] Furthermore, by having the gate electrode layer 101a, which is a so-called back gate, it becomes easy to adjust the electrical characteristics of the transistor 150. Note that the gate electrode layer 101a may be given the same potential as the gate electrode layer 114, or a potential different from that of the gate electrode layer 114. It may also be floating. etc. etc.

[0336] <Manufacturing Method of Semiconductor Device> Next, a method for manufacturing the transistor 150, which is an example of the configuration of the semiconductor device, will be described with reference to FIGS. 8 to 10.

[0337] First, a conductive layer 101 is formed on the substrate 100 (see FIG. 8(A)). Details of the substrate 100 can be referred to the previous embodiments and will be omitted. etc.

[0338] The conductive layer 101 can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. It can be formed using a method. Further, the conductive layer 101 is made of aluminum, chromium, copper, an element selected from tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as a component can be used. A material containing any one or more of manganese, magnesium, zirconium, beryllium, and thorium may also be used. Further, a material in which aluminum contains one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may also be used.

[0339] Further, the conductive layer 101 may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), an indium zinc oxide alloy (In2O3—ZnO), or a material obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0340] The conductive layer 101 may have a single-layer structure or a laminated structure of two or more layers. In one aspect of the disclosed invention, since heat treatment is performed at a relatively high temperature after the formation of the conductive layer 101, it is desirable to form the conductive layer 101 using a material with high heat resistance. Examples of materials with high heat resistance include, for example, titanium, tantalum, tungsten, and molybdenum. Polysilicon with enhanced conductivity by adding impurity elements can also be used.

[0341] Next, the conductive layer 101 is selectively etched to form a gate electrode layer 101a, and an insulating layer 102 covering the gate electrode layer 101a is formed (see FIG. 8(B)). ​

[0342] For the exposure during mask formation used for etching, it is preferable to use ultraviolet rays, KrF laser light, or ArF laser light. In particular, when performing exposure with a channel length (L) of less than 25 nm, it is preferable to perform the exposure for mask formation using extreme ultraviolet rays with a very short wavelength of several nm to several tens of nm. Exposure with extreme ultraviolet rays is suitable for miniaturization because it has high resolution and a large depth of focus.

[0343] The gate electrode layer 101a is a so-called back gate. By having the gate electrode layer 101a, it is possible to control the electric field in the oxide semiconductor layer 106a, and thereby, the electrical characteristics of the transistor 150 can be controlled. Note that the gate electrode layer 101a may be electrically connected to other wirings, electrodes, etc. and given some potential, or may be insulated and in a floating state.

[0344] Note that a "gate electrode" usually refers to something that can intentionally control the potential. However, in this specification, etc., even when the potential is not intentionally controlled, the term "gate electrode" is used. For example, as described above, a conductive layer that is insulated and in a floating state may also be referred to as a "gate electrode layer".

[0345] The insulating layer 102 functions as a base and also functions as a gate insulating layer. The insulating layer 102 can be formed using a CVD method, a sputtering method, or the like. Also, the insulating layer 102 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 102 It may be a single-layer structure or a laminated structure. The thickness of the insulating layer 102 is not particularly limited, but for example, it can be set to be 10 nm or more and 500 nm or less.

[0346] However, if the insulating layer 102 contains hydrogen, water, etc., the intrusion of hydrogen into the oxide semiconductor layer, the extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, and the characteristics of the transistor may deteriorate. Therefore, it is desirable to form the insulating layer 102 so as to contain as little hydrogen and water as possible.

[0347] For example, when using a sputtering method or the like, it is desirable to form the insulating layer 102 in a state where the residual moisture in the processing chamber has been removed. In addition, in order to remove the residual moisture in the processing chamber, it is desirable to use an adsorption type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. It is also possible to use a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump or the like has had hydrogen, water, etc. sufficiently removed, so the concentration of impurities contained in the insulating layer 102 can be reduced.

[0348] In addition, when forming the insulating layer 102, it is desirable to use a high-purity gas in which impurities such as hydrogen and water have been reduced to a concentration of about ppm (preferably, a concentration of about ppb).

[0349] Note that, similar to the gate insulating layer 112, high quality is required for the insulating layer 102. Therefore, it is desirable to form the insulating layer 102 by a method similar to that of the gate insulating layer 112. Details can be referred to the previous embodiments and are thus omitted.

[0350] Next, a first oxide semiconductor layer 104 is formed on the insulating layer 102, and at least the region including the surface of the first oxide semiconductor layer is crystallized by a first heat treatment to form the first oxide semiconductor layer 104 (see Fig. 8(C)). For the method of forming the first oxide semiconductor layer, the conditions of the first heat treatment, and the details of the first oxide semiconductor layer 104, refer to the previous embodiments. Among the first oxide semiconductor layer 104, the region overlapping the unevenness of the gate insulating layer has crystal grain boundaries and becomes polycrystalline. Also, among the first oxide semiconductor layer 104, the region that becomes the channel formation region has at least a flat surface and is a polycrystalline body in which the first oxide semiconductor layer and the second oxide semiconductor layer have the same C-axis orientation. Next, a second oxide semiconductor layer is formed on the first oxide semiconductor layer 104 having a crystal region in at least the region including the surface, and crystal growth is performed using the crystal region of the first oxide semiconductor layer 104 as a seed by a second heat treatment to form the second oxide semiconductor layer 106 (see Fig. 8(D)). For the method of forming the second oxide semiconductor layer, the conditions of the second heat treatment, and the details of the second oxide semiconductor layer 106, refer to the previous embodiments. Next, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 104a and second oxide semiconductor layer 106a (see Fig. 9(A)). Here, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are regions that overlap with the gate electrode layer 101a. This is possible.

[0351] Among the first oxide semiconductor layer 104, the region overlapping the unevenness of the gate insulating layer has crystal grain boundaries and becomes polycrystalline. Also, among the first oxide semiconductor layer 104, the region that becomes the channel formation region has at least a flat surface and is a polycrystalline body in which the first oxide semiconductor layer and the second oxide semiconductor layer have the same C-axis orientation.

[0352] Next, a second oxide semiconductor layer is formed on the first oxide semiconductor layer 104 having a crystal region in at least the region including the surface, and crystal growth is performed using the crystal region of the first oxide semiconductor layer 104 as a seed by a second heat treatment to form the second oxide semiconductor layer 106 (see Fig. 8(D)). For the method of forming the second oxide semiconductor layer, the conditions of the second heat treatment, and the details of the second oxide semiconductor layer 106, refer to the previous embodiments. This is possible. Next, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 104a and second oxide semiconductor layer 106a (see Fig. 9(A)). Here, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are regions that overlap with the gate electrode layer 101a.

[0353] Next, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 104a and second oxide semiconductor layer 106a (see Fig. 9(A)). Here, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are regions that overlap with the gate electrode layer 101a. Next, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 104a and second oxide semiconductor layer 106a (see Fig. 9(A)). Here, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are regions that overlap with the gate electrode layer 101a. Attention should be paid to the points to be formed. For details, the previous embodiments can be referred to.

[0354] Next, a conductive layer 108 is formed so as to be in contact with the second oxide semiconductor layer 106a (see Fig. 9(B) ). Then, the conductive layer 108 is selectively etched to form a source electrode layer or a drain electrode layer 108a and a source electrode layer or a drain electrode layer 108b (see Fig. 9(C) ). Regarding the conductive layer 108, the source electrode layer or the drain electrode layer 108a, the source electrode layer or the drain electrode layer 108b, the etching process, and other details, the previous embodiments can be referred to.

[0355] Also, as shown in Fig. 9(C), the gate electrode layer 101a has a region overlapping with the source electrode layer or the drain electrode layer 108a (or the source electrode layer or the drain electrode layer 108b). One of the features is also that the end portion of the source electrode layer or the drain electrode layer 108a and the step of the insulating layer 102, that is, in the cross-sectional view, the region between the flat surface of the gate insulating layer and the point where it becomes a tapered surface (here, the L OV region shown in Fig. 9(C)). The L OV region is important to prevent carriers from flowing into the grain boundaries generated by the unevenness at the end of the gate electrode layer.

[0356] Next, similar to the previous embodiments, the second oxide semiconductor layer 106a may be heat-treated (third heat treatment ). By the third heat treatment, a high-purity crystal region is formed in a region including the surface of the second oxide semiconductor layer 106a that does not overlap with the source electrode layer or the drain electrode layers 10 8a and 108b and is exposed. Note that the range of the high-purity crystal region is the second oxide semiconductor This varies depending on the material constituting the conductor layer 106a, the conditions of the heat treatment, etc. For example, It is also possible to form a high-purity crystalline region up to the lower interface of the second oxide semiconductor layer 106a. For details of the third heat treatment and other details, the above embodiment can be referred to. .

[0357] Next, without exposing the gate electrode to the air, the gate electrode was removed from the gate electrode in contact with a part of the second oxide semiconductor layer 106a. An insulating layer 112 is formed (see FIG. 10(A)). Then, a first A gate electrode is provided in a region overlapping with the oxide semiconductor layer 104a and the second oxide semiconductor layer 106a. Then, the gate insulating layer 112 and the gate electrode 114 are formed (see FIG. 10(B)). An interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the electrode layer 114 (see FIG. 10(C)). For details of the above steps, the above embodiment can be referred to.

[0358] By the method described in this embodiment, crystal growth occurs from the crystalline region of the first oxide semiconductor layer 104a. Therefore, the second oxide semiconductor layer 106a can be formed by etching the oxide semiconductor layer 106a. A conductor device can be realized.

[0359] In addition, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are formed by the method described in this embodiment. The hydrogen concentration in the semiconductor layer 106a is 5×10 19 / cm 3 The following is also true for the transistor The off current is 1×10 -13 In this way, the hydrogen concentration is sufficiently reduced and the oxygen concentration is The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are purified by supplying By using the semiconductor layer 106a, a semiconductor device with excellent characteristics can be realized.

[0360] Furthermore, by having a gate electrode layer which is a so-called back gate, it becomes easy to adjust the electrical characteristics of the semiconductor device.

[0361] As described above, a semiconductor device with a new structure having excellent characteristics is realized by the disclosed invention. is realized.

[0362] <Modification Example> Next, a modification example of the semiconductor device shown in FIGS. 7 to 10 will be described with reference to FIGS. 11 to 13. Note that many of the components of the semiconductor device shown in FIGS. 11 to 13 are common to the semiconductor device shown in FIGS. 7 to 10. Therefore, only the differences will be described here. to 10, and therefore only the differences will be described here. will be described.

[0363] The transistor 150 shown in FIG. 11(A) includes an oxide semiconductor layer 106 a having a concave portion (groove portion). Note that the concave portion is formed by etching when forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b. Therefore, the concave portion is formed in a region overlapping with the gate electrode layer 114. Due to the concave portion, it is possible to reduce the thickness of the semiconductor layer related to the channel formation region, which contributes to suppression of the short channel effect. is possible, which contributes to suppression of the short channel effect. and contributes to suppression of the short channel effect.

[0364] The transistor 150 shown in FIG. 11(B) includes an oxide semiconductor layer 106a having a high-purity crystal region 110. Note that the high-purity crystal region 110 is formed by performing a third heat treatment after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b. Therefore, the high-purity crystal region 1 is formed by performing a third heat treatment after forming the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b. 10 does not overlap with the source electrode layer or the drain electrode layer 108a, 108b, and will be formed in a region including the surface of the exposed second oxide semiconductor layer 106a. Here, the high-purity crystalline region is a region with higher crystallinity than other regions of the second oxide semiconductor layer 106a and becomes. With the high-purity crystalline region 110, the electrical anisotropy imparted to the second oxide semiconductor layer 106a can be improved, and the electrical characteristics of the semiconductor device can be further improved .

[0365] The transistor 150 shown in FIG. 11(C) includes an oxide semiconductor layer 106 a having a concave portion (groove portion), and does not overlap with the source electrode layer or the drain electrode layer 108a, 108b, and has a high-purity crystalline region 110 in a region including the surface of the exposed second oxide semiconductor layer 106a. That is, it has the characteristics of the transistor 150 according to FIG. 11(A) and the characteristics of the transistor 150 according to FIG. 11(B). The effects resulting from the said configuration are also the same as in the cases of FIGS. 11( A) and FIG. 11(B).

[0366] The transistor 150 shown in FIG. 12(A) has insulating layers 109a and 109b having substantially the same shape as the source electrode layer or the drain electrode layer 108a and the source electrode layer or the drain electrode layer 108b on them. In this case, there is an advantage that the capacitance (so-called gate capacitance) between the source electrode layer or the drain electrode layer and the gate electrode layer can be reduced. In this specification etc., the expression "substantially the same" is used with the meaning that it does not need to be exactly the same, and the range that can be regarded as the same is included . For example, differences in the case of being formed by one etching process are allowed. Also, thickness ​ They do not have to be the same.

[0367] The transistor 150 shown in FIG. 12(B) includes an oxide semiconductor layer 106 having a concave portion (groove portion) a, and on the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, there are insulating layers 109a and insulating layer 109b having substantially the same shape as these. That is, it has the characteristics of the transistor 150 according to FIG. 11(A) and the characteristics of the transistor 150 according to FIG. 12(A). The effects resulting from this configuration are also the same as those in the cases of FIGS. 11(A) and 12(A).

[0368] The transistor 150 shown in FIG. 12(C) has a high-purity crystal region 110 in a region including the surface of the exposed second oxide semiconductor layer 106a without overlapping with the source electrode layer or drain electrode layers 108a and 108b, and on the source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b, there are insulating layers 10 9a and insulating layer 109b having substantially the same shape as these. That is, it has the characteristics of the transistor 150 according to FIG. 11(B) and the characteristics of the transistor 150 according to FIG. 12(A). The effects resulting from this configuration are also the same as those in the cases of FIGS. 11(B) and 12(A).

[0369] In the transistor 150 shown in FIG. 13, in the portions of the source electrode layer or drain electrode layers 108a and the source electrode layer or drain electrode layer 108b that are in contact with the oxide semiconductor layer 106a, there are conductive layers 107 a and conductive layer 107b made of a material having a low oxygen-extracting effect (a material having a low affinity for oxygen). Having such a conductive layer with a low oxygen-extracting effect ​ By doing so, the n-type conversion of the oxide semiconductor layer due to the extraction of oxygen can be prevented, and the adverse effects on the transistor characteristics caused by non-uniform n-type conversion and the like can be suppressed.

[0370] Note that in FIG. 13, the two-layer source electrode layer or drain electrode layer 108a and the source electrode layer or drain electrode layer 108b are employed, but one aspect of the disclosed invention is not limited to this. A single-layer structure of a conductive layer made of a material with a low oxygen-extracting effect may also be used, and a laminated structure of three or more layers may also be used. In the case of a single-layer structure, for example, a single-layer structure of a titanium nitride film can be applied. In the case of a laminated structure, for example, a two-layer structure of a titanium nitride film and a titanium film can be employed.

[0371] As described above, one aspect of the disclosed invention can be used in various modified forms. . Also, the modified examples are not limited to the above examples. For example, FIGS. 11(A), 11(B), 11 (C), FIGS. 12(A), 12(B), 12(C), and FIG. 13 can be appropriately combined and used as another modified example. Of course, within the scope described in the specification and the like, changes, omissions, and the like can be freely made.

[0372] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0373] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment will be described with reference to FIG. 30. The semiconductor device obtained in the previous embodiment has excellent characteristics that are unprecedented. It has characteristics. Therefore, it is possible to provide an electronic device with a new configuration using the semiconductor device.

[0374] FIG. 30(A) is a notebook personal computer including the semiconductor device according to the previous embodiment, which is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is mounted inside the housing 302. Also, the semiconductor device according to the disclosed invention can be applied to the display unit 303. By applying the semiconductor device according to the disclosed invention to an integrated circuit board or the like, high-speed operation of the circuit can be realized. Also, by applying the semiconductor device according to the disclosed invention to the display unit 303, high-quality images can be displayed. In this way, by applying the semiconductor device according to the disclosed invention to a personal computer, a personal computer with excellent performance can be provided.

[0375] FIG. 30(B) is a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. The main body 311 is provided with a display unit 313, an external interface 315, operation buttons 314, etc. Also, there is a stylus 312 as an accessory for operation. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is mounted on the main body 311. Also, the semiconductor device according to the disclosed invention can be applied to the display unit 313. By applying the semiconductor device of the disclosed invention to an integrated circuit board or the like, high-speed operation of the circuit can be realized. Also, by applying the semiconductor device according to the disclosed invention to the display unit 313, ​​​​​​​​​​​​​​As a result, high-quality images can be displayed. Thus, by applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a PDA with excellent performance can be provided. By applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a PDA with excellent performance can be provided.

[0376] In FIG. 30(C), as an example of an electronic paper including the semiconductor device according to the previous embodiment, an electronic book 320 is shown. The electronic book 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337 and can perform an opening / closing operation about the shaft portion 337. With such a configuration, the electronic book 320 can be used like a paper book. 320 can be used like a paper book.

[0377] A display portion 325 is incorporated in the housing 321, and a display portion 327 is incorporated in the housing 323. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is mounted inside the housing 323 or the housing 321. The semiconductor device according to the disclosed invention can be applied to the display portion 327. The display portion 325 and the display portion 327 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, text can be displayed on the right display portion (the display portion 325 in FIG. 30(C)), and an image can be displayed on the left display portion (the display portion 327 in FIG. 30(C)). By applying it to an integrated circuit board or the like, high-speed operation of the circuit can be realized. By applying the semiconductor device according to the disclosed invention to the display portion 327, high-quality images can be displayed. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is mounted inside the housing 323 or the housing 321. The semiconductor device according to the disclosed invention can be applied to the display portion 327. The display portion 325 and the display portion 327 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, text can be displayed on the right display portion (the display portion 325 in FIG. 30(C)), and an image can be displayed on the left display portion (the display portion 327 in FIG. 30(C)). By adopting a configuration for displaying different screens, for example, text can be displayed on the right display portion (the display portion 325 in FIG. 30(C)), and an image can be displayed on the left display portion (the display portion 327 in FIG. 30(C)). text can be displayed on the right display portion (the display portion 325 in FIG. 30(C)), and an image can be displayed on the left display portion (the display portion 327 in FIG. 30(C)). By applying it to an integrated circuit board or the like, high-speed operation of the circuit can be realized. By applying it to an integrated circuit board or the like, high-speed operation of the circuit can be realized. By applying the semiconductor device according to the disclosed invention to the display portion 327, high-quality images can be displayed.

[0378] Also, in FIG. 30(C), an example in which the housing 321 is provided with an operation portion or the like is shown. For example, the housing​​ The body 321 is provided with a power supply 331, operation keys 333, a speaker 335, etc. With the operation keys 333, pages can be sent. Note that it may be configured to include a keyboard, a pointing device, etc. on the same surface as the display portion of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, etc. may be provided. Further, the electronic book 320 may be configured to have a function as an electronic dictionary.

[0379] Also, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0380] Note that the electronic paper can be applied to any field as long as it can display information. For example, in addition to electronic books, it can be applied to posters, in-vehicle advertisements on vehicles such as trains, displays on various cards such as credit cards, etc. Thus, by applying the semiconductor device according to the disclosed invention to the electronic paper, an electronic paper with excellent performance can be provided.

[0381] Figure 30(D) is a mobile phone including the semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, a housing 340 and a housing 341. The housing 341 is provided with a display panel 342, a speaker 343, a microphone 344, a pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 It includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built inside the housing 341. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is mounted inside the housings 340 and 341.

[0382] The display panel 342 has a touch panel function, and a plurality of operation keys 345 shown by dotted lines are being video-displayed in Fig. 30(D). The semiconductor device according to the disclosed invention can be applied to the display panel 342. By applying the semiconductor device according to the disclosed invention to the display panel 342, a high-quality image can be displayed. Note that the mobile phone has a booster circuit for boosting the voltage output from the solar cell 349 to the voltages required for each circuit. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, etc.

[0383] The display direction of the display panel 342 changes appropriately according to the usage form. Also, since a camera lens 347 is provided on the same plane as the display panel 342, a video phone is possible. The speaker 343 and the microphone 344 are not limited to voice calls, and video phone, recording, playback, etc. are possible. Further, the housings 340 and 341 can be slid and changed from the state of being unfolded as shown in Fig. 30(D) to a state of overlapping each other, enabling miniaturization suitable for carrying.

[0384] The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, a recording medium can be inserted into the external memory slot 350. ​​Insert it to enable storage and transfer of a larger amount of data. In addition to the above functions, it may also be equipped with an infrared communication function, a television receiving function, etc. By applying the semiconductor device according to the disclosed invention to a mobile phone, a mobile phone with excellent performance can be provided.

[0385] FIG. 30(E) is a digital camera including the semiconductor device according to the previous embodiment. The digital camera includes a main body 361, a display unit (A) 367, an eyepiece 363, an operation switch 364 , a display unit (B) 365, a battery 366, etc. The semiconductor device according to the disclosed invention can be applied to the display unit (A) 367 and the display unit (B) 365. By applying the semiconductor device according to the disclosed invention to the display unit (A) 367 and the display unit (B) 365, a high-quality image can be displayed. Thus, by applying the semiconductor device according to the disclosed invention to a digital camera, a digital camera with excellent performance can be provided.

[0386] FIG. 30(F) is a television device including the semiconductor device according to the previous embodiment. In the television device 370, a display unit 373 is incorporated in a housing 371. The display unit 373 can display an image. Here, a configuration in which the housing 371 is supported by a stand 375 is shown. By applying the semiconductor device according to the disclosed invention to the display unit 373, the high-speed operation of the switching element becomes possible, and a larger area of the display unit 373 can be realized.

[0387] The operation of the television device 370 is performed by an operation switch provided in the housing 371 or a separate remote control. ​​​​​It can be performed by the operation machine 380. By the operation keys 379 provided in the remote control operation machine 380 , operations such as channel and volume can be performed, and the video displayed on the display unit 373 can be operated . Further, the remote control operation machine 380 may be configured to be provided with a display unit 377 that displays the information output from the remote control operation machine 380 .

[0388] Note that the television device 370 is preferably configured to include a receiver, a modem, and the like . The receiver can receive general television broadcasts. Further, by connecting to a wired or wireless communication network via a modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication can be performed . Thus, by applying the semiconductor device according to the disclosed invention to a television device , a television device with excellent performance can be provided .

[0389] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments .

Description of Reference Numerals

[0390] 100 Substrate 101 Conductive layer 101a Gate electrode layer 102 Insulating layer 104 Oxide semiconductor layer 104a Oxide semiconductor layer 104aa Amorphous region 104ab Crystal region 105 Oxide semiconductor layer 106 Oxide semiconductor layer 106a Oxide semiconductor layer 107a Conductive layer 107b Conductive layer 108 Conductive layer 108a Source electrode layer or drain electrode layer 108b Source electrode layer or drain electrode layer 109a Insulating layer 109b Insulating layer 110 High-purity crystal region 112 Gate insulating layer 114 Gate electrode layer 116 Interlayer insulating layer 118 Interlayer insulating layer 150 Transistor 200 Substrate 206 Element isolation insulating layer 208a Gate insulating layer 210a Gate electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High-concentration impurity region 224 Metal compound region 226 Interlayer insulating layer 228 Interlayer insulating layer 230a Source electrode layer or drain electrode layer 230b Source electrode layer or drain electrode layer 230c Electrode 230c Electrode 234 Insulating layer 236a Electrode 236b Electrode 236c Electrode 250 Transistor 254a Electrode 254b Electrode 254c Electrode 254d Electrode 254e Electrode 256 Insulating layer 258a Electrode 258b Electrode 258c Electrode 258d Electrode 301 Body 302 Housing 303 Display unit 304 Keyboard 311 Main body 312 Stylus 313 Display unit 314 Operation button 315 External interface 320 E-book 321 Housing 323 Housing 325 Display unit 327 Display unit 331 Power supply 333 Operation key 335 Speaker 337 Shaft part 340 Housing 341 Housing 342 Display panel 343 Speaker 344 Microphone 345 Operation key 346 Pointing device 347 Camera lens 348 External connection terminal 349 Solar cell 350 External memory slot 361 Main body 363 Eyepiece 364 Operation switch 365 Display unit (B) 366 Battery 367 Display unit (A) 370 Television device 371 Housing 373 Display unit 375 Stand 377 Display unit 379 Operation key 380 Remote control operation unit 500 Base member 501 Oxide crystal layer 502 Oxide semiconductor layer 503a Oxide crystal layer 503b Oxide crystal layer

Claims

1. A semiconductor device having a transistor, comprising: a first conductive layer having a function as a gate electrode layer; a first insulating layer on the first conductive layer; a first oxide semiconductor layer having a crystalline region on the first insulating layer; a second oxide semiconductor layer having a crystalline region on the first oxide semiconductor layer; a second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a source electrode layer; a third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a drain electrode layer; a second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer; and each of the first insulating layer and the second insulating layer contains silicon oxide; the first oxide semiconductor layer contains In, Sn, Ga, and Zn; the second oxide semiconductor layer contains In, Ga, and Zn; in a cross-sectional view in the channel length direction of the transistor, each of the second conductive layer and the third conductive layer has a first portion overlapping the first oxide semiconductor layer and the second oxide semiconductor layer, and a second portion not overlapping the first oxide semiconductor layer and the second oxide semiconductor layer; each of the second conductive layer and the third conductive layer has a laminated structure having a layer containing titanium; the layer containing titanium has a region in contact with the upper surface of the second oxide semiconductor layer. A semiconductor device.

2. A semiconductor device having a transistor, comprising: a first conductive layer having a function as a gate electrode layer; a first insulating layer on the first conductive layer; a first oxide semiconductor layer having a crystalline region on the first insulating layer; a second oxide semiconductor layer having a crystalline region on the first oxide semiconductor layer; a second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a source electrode layer; a third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a drain electrode layer; a second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer; and each of the first insulating layer and the second insulating layer contains silicon oxide; the first oxide semiconductor layer contains In, Sn, Ga, and Zn; The second oxide semiconductor layer contains In, Ga, and Zn, the thickness of the second oxide semiconductor layer is greater than the thickness of the first oxide semiconductor layer, in a cross-sectional view in the channel length direction of the transistor, each of the second conductive layer and the third conductive layer has a first portion overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer, and a second portion not overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer, each of the second conductive layer and the third conductive layer has a stacked structure having a layer containing titanium, the layer containing titanium has a region in contact with the upper surface of the second oxide semiconductor layer, a semiconductor device.

3. A semiconductor device having a transistor, a first conductive layer having a function as a gate electrode layer, a first insulating layer on the first conductive layer, a first oxide semiconductor layer having a crystalline region on the first insulating layer, a second oxide semiconductor layer having a crystalline region on the first oxide semiconductor layer, a second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a source electrode layer, a third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a drain electrode layer, a second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer, each of the first insulating layer and the second insulating layer contains silicon oxide, the first oxide semiconductor layer contains In, Sn, Ga, and Zn, the second oxide semiconductor layer contains In, Ga, and Zn, in a cross-sectional view in the channel length direction of the transistor, each of the first oxide semiconductor layer and the second oxide semiconductor layer has a first portion overlapping with the first conductive layer, a second portion not overlapping with the first conductive layer and overlapping with the second conductive layer, and a third portion not overlapping with the first conductive layer and overlapping with the third conductive layer, a semiconductor device.

4. A semiconductor device having a transistor, a first conductive layer having a function as a gate electrode layer, a first insulating layer on the first conductive layer, a first oxide semiconductor layer having a crystalline region on the first insulating layer, a second oxide semiconductor layer having a crystalline region on the first oxide semiconductor layer, A second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and functioning as a source electrode layer, A third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and functioning as a drain electrode layer, A second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer, Each of the first insulating layer and the second insulating layer contains silicon oxide, The first oxide semiconductor layer contains In, Sn, Ga, and Zn, The second oxide semiconductor layer contains In, Ga, and Zn, The thickness of the second oxide semiconductor layer is greater than the thickness of the first oxide semiconductor layer, In a cross-sectional view in the channel length direction of the transistor, each of the first oxide semiconductor layer and the second oxide semiconductor layer has a first portion overlapping the first conductive layer, a second portion not overlapping the first conductive layer and overlapping the second conductive layer, and a third portion not overlapping the first conductive layer and overlapping the third conductive layer. A semiconductor device. **Claim 5**: A semiconductor device having a transistor, A first conductive layer functioning as a gate electrode layer, A first insulating layer on the first conductive layer, A first oxide semiconductor layer having a crystalline region on the first insulating layer, A second oxide semiconductor layer having a crystalline region on the first oxide semiconductor layer, A second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and functioning as a source electrode layer, A third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and functioning as a drain electrode layer, A second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer, Each of the first insulating layer and the second insulating layer contains silicon oxide, The first oxide semiconductor layer contains In, Sn, Ga, and Zn, The second oxide semiconductor layer contains In, Ga, and Zn, In a cross-sectional view in the channel length direction of the transistor, each of the first oxide semiconductor layer and the second oxide semiconductor layer has a first portion overlapping with the first conductive layer, a second portion not overlapping with the first conductive layer and overlapping with the second conductive layer, and a third portion not overlapping with the first conductive layer and overlapping with the third conductive layer. In a cross-sectional view in the channel length direction of the transistor, each of the second conductive layer and the third conductive layer has a fourth portion not overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer. Each of the second conductive layer and the third conductive layer has a stacked structure having a layer containing titanium. The layer containing titanium has a region in contact with the upper surface of the second oxide semiconductor layer, a semiconductor device.

6. A semiconductor device having a transistor, A first conductive layer having a function as a gate electrode layer, A first insulating layer on the first conductive layer, A first oxide semiconductor layer having a crystal region on the first insulating layer, A second oxide semiconductor layer having a crystal region on the first oxide semiconductor layer, A second conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a source electrode layer, A third conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer and having a function as a drain electrode layer, A second insulating layer provided on the second conductive layer and the third conductive layer and having a region in contact with a part of the upper surface of the second oxide semiconductor layer. Each of the first insulating layer and the second insulating layer has silicon oxide. The first oxide semiconductor layer has In, Sn, Ga, and Zn. The second oxide semiconductor layer has In, Ga, and Zn. The thickness of the second oxide semiconductor layer is larger than the thickness of the first oxide semiconductor layer. In a cross-sectional view in the channel length direction of the transistor, each of the first oxide semiconductor layer and the second oxide semiconductor layer has a first portion overlapping with the first conductive layer, a second portion not overlapping with the first conductive layer and overlapping with the second conductive layer, and a third portion not overlapping with the first conductive layer and overlapping with the third conductive layer. In a cross-sectional view in the channel length direction of the transistor, each of the second conductive layer and the third conductive layer has a fourth portion that does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer. Each of the second conductive layer and the third conductive layer has a stacked structure having a layer containing titanium. The semiconductor device, wherein the layer containing titanium has a region in contact with the upper surface of the second oxide semiconductor layer.

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