EL display device

Abstract

To provide a semiconductor device with high productivity at low cost by reducing the manufacturing steps, and a semiconductor device with high reliability and lower power consumption.SOLUTION: A photolithography process for forming an island-shaped semiconductor layer is simplified. A semiconductor device is manufactured by at least four photolithography steps including forming a gate electrode (including a wire and the like formed in the same layer), forming a source electrode and a drain electrode (including a wire and the like formed in the same layer), forming a contact hole, and forming a pixel electrode. In the step of forming a contact hole, formation of parasitic channel is prevented by forming a groove part. The groove part and the wire overlap through an insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, including transistors, semiconductor circuits, memory devices, imaging devices, display devices, electro-optical devices, and electronic devices, etc., all of which can be said to be semiconductor devices.

Background Art

[0003] In recent years, transistors composed of semiconductor thin films with a thickness of several nm to several hundred nm formed on a substrate having an insulating surface such as a glass substrate have attracted attention. Transistors are widely applied to electronic devices such as IC (Integrated Circuit) and electro-optical devices. Transistors are being developed rapidly as switching elements for image display devices, typified by display devices such as active matrix liquid crystal display devices and EL (Electro Luminescence) display devices. In an active matrix liquid crystal display device, when a voltage is applied between a pixel electrode connected to a selected switching element and a counter electrode corresponding to the pixel electrode, optical modulation of a liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by an observer as a display pattern. Here, an active matrix display device refers to a display device that adopts a method in which a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix by switching elements. represented by display devices such as EL (Electro Luminescence) display devices, and development is being rushed as a switching element for image display devices. In an active matrix type liquid crystal display device, a voltage is applied between a pixel electrode connected to a selected switching element and a counter electrode corresponding to the pixel electrode, and optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by an observer as a display pattern. Here, an active matrix display device refers to a display device that adopts a method in which a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix by switching elements. and this optical modulation is recognized by an observer as a display pattern. Here, an active matrix display device refers to a display device that adopts a method in which a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix by switching elements. Here, an active matrix display device refers to a display device that adopts a method in which a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix by switching elements. When the pixel electrodes arranged in a matrix are driven by switching elements, a display pattern is formed on the screen. This is the adopted display device.

[0004] The applications of the active matrix type display device as described above are expanding, and there are increasing demands for larger screen sizes, higher resolutions, and higher aperture ratios. In addition, high reliability is required for active matrix type display devices, and high productivity and reduced production costs are required for their production methods. One way to increase productivity and reduce production costs is to simplify the process. In active matrix type display devices, transistors are mainly used as switching elements. Reducing or simplifying the photolithography process in the fabrication of transistors is important for simplifying the entire process. For example, when the number of masks used in the photolithography process increases by one, processes such as resist coating, pre-baking, exposure, development, post-baking, etc., and film formation and etching processes before and after these processes, as well as resist stripping, cleaning, and drying processes, etc. are required. Therefore, just an increase of one mask used in the photolithography process in the fabrication process significantly increases the number of processes. For this reason, numerous technologies have been developed to reduce or simplify the photolithography process in the fabrication process. Transistors are roughly classified into top-gate types in which the channel formation region is provided in a layer below the gate electrode and bottom-gate types in which the channel formation region is provided in a layer above the gate electrode. In active matrix type liquid crystal display devices using these transistors, it is common to be fabricated by at least five photolithography processes using at least five photomasks.

[0005] In active matrix type display devices, transistors are mainly used as switching elements. In the fabrication of transistors, reducing or simplifying the photolithography process is important for simplifying the entire process. For example, when one more mask is used in the photolithography process, processes such as resist coating, pre-baking, exposure, development, post-baking, etc., and film formation and etching processes before and after these processes, as well as resist stripping, cleaning, and drying processes, etc. are required. Therefore, just an increase of one mask used in the photolithography process in the fabrication process significantly increases the number of processes. Therefore, in order to reduce or simplify the photolithography process in the fabrication process, numerous technologies have been developed.

[0006] Transistors are roughly classified into top-gate types in which the channel formation region is provided in a layer below the gate electrode and bottom-gate types in which the channel formation region is provided in a layer above the gate electrode. In active matrix type liquid crystal display devices using these transistors, it is common to be fabricated by at least five photolithography processes using at least five photomasks.

[0007] ​​​​​​​​In an active matrix type EL display device, since it is necessary to form a partition wall layer for separating the EL layer for each pixel, it is generally manufactured by at least a total of six photolithography processes using another photomask. As a conventional technique for simplifying the photolithography process, many use complex techniques such as backside exposure (for example, Patent Document 1), resist reflow, or lift-off method, and many require special devices. By using such complex techniques, various problems caused by this occur, contributing to a decrease in yield. Also, the electrical characteristics of the transistors often deteriorate.

[0008] As a conventional technique for simplifying the photolithography process, many use complex techniques such as backside exposure (for example, Patent Document 1), resist reflow, or lift-off method, and many require special devices. By using such complex techniques, various problems caused by this occur, contributing to a decrease in yield. Also, the electrical characteristics of the transistors often deteriorate.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] However, when reducing or simplifying the photolithography process, channels may be formed in places where they are not originally necessary, and unintended parts may function as transistors. For example, when there is a semiconductor layer that overlaps with the pixel electrode via an insulating layer, depending on the potential supplied to the pixel electrode, a channel may be formed in the semiconductor layer that overlaps with the pixel electrode. Note that such a channel formed in a place where it is not originally necessary is called a parasitic channel.

[0011] For example, when there is a semiconductor layer that overlaps with the pixel electrode via an insulating layer, depending on the potential supplied to the pixel electrode, a channel may be formed in the semiconductor layer that overlaps with the pixel electrode. Note that such a channel formed in a place where it is not originally necessary is called a parasitic channel.

[0012] ​​​​​​Further, for example, when a common wiring A (e.g., , a gate wiring) is used for a first pixel and a second pixel adjacent to the first pixel, a parasitic channel is formed in a semiconductor layer that overlaps with the wiring A via an insulating layer. Then, wiring B owned by the first pixel (e.g., an image signal wiring owned by the first pixel) formed in contact with the semiconductor layer and wiring C owned by the second pixel (e.g., an image signal wiring owned by the second pixel) may be electrically connected by the parasitic channel. That is, there is a case where the wiring A functions as a gate electrode, the wiring B functions as one of a source electrode or a drain electrode, and the wiring C functions as the other of the source electrode or the drain electrode, and a transistor is formed. In this way, an unintentionally formed transistor is called a parasitic transistor.

[0013] Further, when the distance between adjacent wirings is short, even if there is no layer that functions as a gate electrode, a parasitic channel is formed in the semiconductor layer due to the electric field generated between the adjacent wirings, and the adjacent wirings may be electrically connected to each other.

[0014] When a parasitic channel or a parasitic transistor is formed, signals between the wirings interfere with each other, making it difficult to transmit accurate signals. This contributes to a decrease in display quality and a decrease in reliability.

[0015] In addition, a semiconductor device is composed of a plurality of thin films with a complex structure and is manufactured by various materials, methods, and processes. Therefore, depending on the manufacturing process used, there is a risk of poor shape of the obtained semiconductor device and a decrease in electrical characteristics.

[0016] In view of such problems, one of the challenges is to provide a highly reliable semiconductor device.

[0017] One aspect of the present invention aims to reduce the number of photolithography steps used in manufacturing a semiconductor device as compared with the conventional method.

[0018] One aspect of the present invention aims to reduce the number of photomasks used in manufacturing a semiconductor device as compared with the conventional method.

[0019] One aspect of the present invention aims to provide a highly productive semiconductor device.

[0020] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption.

Means for Solving the Problems

[0021] Omit the photolithography step for forming the island-shaped semiconductor layer, and perform the steps of forming a gate electrode (including wirings formed in the same layer), a source electrode and a drain electrode (including wirings formed in the same layer), forming contact holes and grooves, and forming a pixel electrode (including wirings and the like formed in the same layer). A semiconductor device for use in a liquid crystal display device is manufactured through these four photolithography steps.

[0022] In addition, the semiconductor device for use in a liquid crystal display device manufactured by the above method is provided with grooves along a second wiring that is electrically connected to the source electrode of the transistor in order to prevent the generation of parasitic channels or parasitic transistors. For example, as a first groove, the groove is formed across at least a part of the first wiring beyond both ends in the line width direction of the first wiring that is electrically connected to the gate electrode of the transistor. Also, as a second groove, the groove is formed across at least a part of the capacitive wiring beyond both ends in the line width direction of the capacitive wiring. Further, as a third groove, the groove ​​​​​​​​​​​ between the second wiring and the pixel electrode, the end of the pixel electrode is formed beyond along the direction in which the second wiring extends. Note that the third groove portion may overlap with the pixel electrode and be formed beyond the end of the pixel electrode along the direction in which the second wiring extends.

[0023] The first groove portion, the second groove portion, and the third groove portion may be formed independently of each other, or may be configured as a single groove portion that also serves as a plurality or all of the first groove portion to the third groove portion.

[0024] Further, the first groove portion has a region that overlaps with the first wiring and a region that does not overlap. When the first wiring is exposed on the bottom surface of the groove portion, there is a risk of leakage current occurring between the semiconductor layer exposed on the side surface of the groove portion and the first wiring exposed on the bottom surface of the groove portion. For this reason, the first wiring is prevented from being exposed on the bottom surface of the groove portion to prevent the occurrence of leakage current in the groove portion. For this reason, the groove portion formed in the region that overlaps with the first wiring is formed on the first wiring via an insulating layer.

[0025] Also, the second groove portion has a region that overlaps with the capacitance wiring and a region that does not overlap. When the capacitance wiring is exposed on the bottom surface of the groove portion, there is a risk of leakage current occurring between the semiconductor layer exposed on the side surface of the groove portion and the capacitance wiring exposed on the bottom surface of the groove portion. For this reason, the capacitance wiring is prevented from being exposed on the bottom surface of the groove portion to prevent the occurrence of leakage current in the groove portion. For this reason, the groove portion formed in the region that overlaps with the capacitance wiring is formed on the capacitance wiring via an insulating layer.

[0026] One aspect of the present invention includes a transistor having a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, a first wiring electrically connected to the gate electrode, and a source electrode electrically A second wiring to be connected, a pixel electrode electrically connected to the drain electrode, a capacitive wiring, and a groove The semiconductor layer has the first wiring, the second wiring, the pixel electrode, and the capacitive wiring overlapping therewith, and the groove The portion is formed on the first wiring and crosses the first wiring. Also, the groove portion is formed on the capacitive wiring and crosses the capacitive wiring. Further, the groove portion is formed along the direction in which the second wiring extends and extends beyond the end of the pixel electrode and the groove portion has the semiconductor layer removed at the bottom surface and overlaps the first wiring and the capacitive wiring via an insulating layer. and the capacitive wiring via an insulating layer. characterized in that

[0027] One aspect of the present invention forms a gate electrode by a first photolithography process, forms a gate insulating layer on the gate electrode, forms a semiconductor layer on the gate insulating layer, and forms a source electrode and a drain electrode on the semiconductor layer by a second photolithography process, forms a protective layer on the source electrode and the drain electrode, selectively removes a part of the protective layer overlapping with one of the source electrode or the drain electrode by a third photolithography process to form a first contact hole, selectively removes a part of the protective layer, the semiconductor layer, and the gate insulating layer to form a second contact hole, selectively removes a part of the protective layer and the semiconductor layer to form a groove portion, and forms a pixel electrode on the protective layer by a fourth photolithography process characterized in that. By forming a resist mask in the third photolithography process using a multi-tone mask, the formation of the first contact hole, the second contact hole, and the groove portion can be performed in one photolithography process. characterized in that characterized in that characterized in that

[0028] By performing the formation of the resist mask in the third photolithography process using a multi-tone mask, the formation of the first contact hole, the second contact hole, and the groove portion can be performed in one photolithography process. characterized in that characterized in that

[0029] One aspect of the present invention is to form a first electrode, form a first layer on the first electrode, and on the first layer form a semiconductor layer, form a second electrode and a third electrode on the semiconductor layer, and cover the second electrode and the third electrode to form a second layer, remove a part of the second layer that overlaps with the second electrode or the third electrode to form a contact hole, and remove a part of the first layer, a part of the semiconductor layer, and a part of the second layer to form a contact hole, and remove a part of the second layer and a part of the semiconductor layer to form a groove, and perform these operations in the same photolithography process. This is the feature.

[0030] The first layer functions as a gate insulating layer, and the second layer functions as a protective layer. Also, the first electrode functions as a gate electrode, the second electrode functions as one of a source electrode or a drain electrode, and the third electrode functions as the other of the source electrode or the drain electrode.

[0031] Omit the photolithography process for forming the island-shaped semiconductor layer, and perform the process of forming the gate electrode (including the wiring formed in the same layer), the process of forming the source electrode and the drain electrode (including the wiring formed in the same layer), the process of forming the contact hole and the groove, the process of forming the pixel electrode (including the wiring etc. formed in the same layer), and the process of forming the partition layer, and fabricate a semiconductor device used in an EL display device in five photolithography processes. Also, in order to prevent the generation of parasitic channels or parasitic transistors, the semiconductor device used in the EL display device fabricated by the above method is provided with a groove along the second wiring that is electrically connected to the source electrode of the first transistor. For example, as the first groove, the groove is formed in the first transistor

[0032] The first wiring extends beyond both ends in the line width direction of the first wiring that is electrically connected to the gate electrode of the first wiring. The second groove is formed so as to cross at least a part of the pixel. Between the electrodes, the second wiring is formed in the direction in which it extends, beyond the end of the pixel electrode. The second groove portion overlaps with the pixel electrode and is disposed at the edge of the pixel electrode along the direction in which the second wiring extends. The third groove may be formed between adjacent pixels, so that the second groove is formed beyond the second alignment portion. A groove is formed along the direction in which the wire extends.

[0033] The first groove, the second groove, and the third groove may be formed independently of each other, or may be formed as a single groove. The groove may serve as a plurality of or all of the first to third grooves.

[0034] In addition, when the first wiring is exposed at the bottom surface of the first trench, the semiconductor exposed on the side surface of the trench A leakage current (hereinafter also referred to as "leak current") flows between the layer and the first wiring exposed at the bottom of the trench. For this reason, the first wiring is not exposed at the bottom of the groove, and To prevent leakage current from occurring in the first wiring, the first groove is provided with an insulating layer on the first wiring. and form.

[0035] One aspect of the present invention is a liquid crystal display device comprising: a first wiring, a second wiring, a semiconductor layer, a pixel electrode, and a first groove portion. and a second groove portion, the semiconductor layer overlapping the first wiring and the pixel electrode, the first groove portion being The second groove is formed on the first wiring so as to cross the first wiring, and the second groove is a groove through which the second wiring extends. A first wiring is formed between the second wiring and the pixel electrode and beyond the edge of the pixel electrode along the first direction. The semiconductor layer is removed from the bottom surfaces of the groove and the second groove, and the first groove is provided with a first wiring. The stacking is characterized by being performed via an insulating layer.

[0036] One aspect of the present invention has a first pixel and a second pixel adjacent to the first pixel. The first pixel has a first wiring, a second wiring, a semiconductor layer, a pixel electrode, a first groove portion, and a second groove portion. The semiconductor layer overlaps with the first wiring and the pixel electrode. The first groove portion is formed on the first wiring and crosses the first wiring. The second groove portion is formed along the direction in which the second wiring extends, between the second wiring and the pixel electrode and beyond the end portion of the pixel electrode. The semiconductor layer is removed at the bottom surfaces of the first groove portion and the second groove portion. The first groove portion overlaps with the first wiring via an insulating layer, and there is a third groove portion having the semiconductor layer removed at the bottom surface between the first pixel and the second pixel. The third groove portion is formed beyond the end portion of the first pixel, which is characterized.

[0037] One aspect of the present invention has a first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a pixel electrode, a first groove portion, and a second groove portion. The first transistor and the second transistor have a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. The gate electrode of the first transistor is electrically connected to the first wiring. One of the source electrode or the drain electrode of the first transistor is electrically connected to the second wiring, and the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor. One of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, and the other of the source electrode or the drain electrode of the second transistor is electrically connected to the pixel electrode. The semiconductor layer is between the first wiring and the second wiring. One of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, and the other of the source electrode or the drain electrode of the second transistor is electrically connected to the pixel electrode. The semiconductor layer is between the first wiring and the second wiring. and a third wiring, which overlaps the pixel electrode, wherein the first groove is formed across the first wiring on the first wiring between the second wiring and the third wiring, and the second groove is formed between the second wiring and the third wiring along the direction in which the second wiring extends, beyond the end of the pixel electrode. The semiconductor layer is removed at the bottom surfaces of the first groove and the second groove, and the first groove overlaps the first wiring via an insulating layer. In one aspect of the present invention, a gate electrode is formed by a first photolithography process, a gate insulating layer is formed on the gate electrode, a semiconductor layer is formed on the gate insulating layer, a source electrode and a drain electrode are formed on the semiconductor layer by a second photolithography process, an insulating layer is formed on the source electrode and the drain electrode, and a first contact hole is formed by selectively removing a part of the insulating layer that overlaps one of the source electrode or the drain electrode by a third photolithography process, a second contact hole is formed by selectively removing a part of the insulating layer, the semiconductor layer, and the gate insulating layer, a groove is formed by selectively removing a part of the insulating layer and the semiconductor layer, a pixel electrode is formed on the insulating layer by a fourth photolithography process, and a partition layer is formed by a fifth photolithography process. By forming a resist mask in the third photolithography process using a multi-tone mask, the formation of the first contact hole, the second contact hole, and the groove can be performed in a single photolithography process. In one aspect of the present invention, a first electrode is formed, a first layer is formed on the first electrode,

[0038]

[0039]

[0040] ​​​​​​​​​​​​​​A semiconductor layer is formed, a second electrode and a third electrode are formed on the semiconductor layer, and a second layer covering the second electrode and the third electrode is formed. A part of the second layer overlapping with the second electrode or the third electrode is removed to form a contact hole, and a contact hole is formed by removing a part of the second layer, a part of the semiconductor layer, and a part of the first layer. The formation of a groove by removing a part of the second layer and a part of the semiconductor layer is performed in the same photolithography process, and a third layer is formed on the second layer. A part of the second layer covering the third electrode is removed to form a contact hole, and a contact hole is formed by removing a part of the second layer, a part of the semiconductor layer, and a part of the first layer. The formation of a groove by removing a part of the second layer and a part of the semiconductor layer is performed in the same photolithography process, and a third layer is formed on the second layer. A part of the second layer covering the third electrode is removed to form a contact hole, and a contact hole is formed by removing a part of the second layer, a part of the semiconductor layer, and a part of the first layer. The formation of a groove by removing a part of the second layer and a part of the semiconductor layer is performed in the same photolithography process, and a third layer is formed on the second layer. A part of the second layer covering the third electrode is removed to form a contact hole, and a contact hole is formed by removing a part of the second layer, a part of the semiconductor layer, and a part of the first layer. The formation of a groove by removing a part of the second layer and a part of the semiconductor layer is performed in the same photolithography process, and a third layer is formed on the second layer. A part of the second layer covering the third electrode is removed to form a contact hole, and a contact hole is formed by removing a part of the second layer, a part of the semiconductor layer, and a part of the first layer. The formation of a groove by removing a part of the second layer and a part of the semiconductor layer is performed in the same photolithography process, and a third layer is formed on the second layer. Characterized in that a third layer is formed on the second layer.

[0041] The first layer functions as a gate insulating layer, the second layer functions as a protective layer, and the third layer functions as a partition wall layer. Also, the first electrode functions as a gate electrode, the second electrode functions as one of a source electrode or a drain electrode, and the third electrode functions as the other of the source electrode or the drain electrode. The first layer functions as a gate insulating layer, the second layer functions as a protective layer, and the third layer functions as a partition wall layer. Also, the first electrode functions as a gate electrode, the second electrode functions as one of a source electrode or a drain electrode, and the third electrode functions as the other of the source electrode or the drain electrode. The first layer functions as a gate insulating layer, the second layer functions as a protective layer, and the third layer functions as a partition wall layer. Also, the first electrode functions as a gate electrode, the second electrode functions as one of a source electrode or a drain electrode, and the third electrode functions as the other of the source electrode or the drain electrode. The first layer functions as a gate insulating layer, the second layer functions as a protective layer, and the third layer functions as a partition wall layer. Also, the first electrode functions as a gate electrode, the second electrode functions as one of a source electrode or a drain electrode, and the third electrode functions as the other of the source electrode or the drain electrode.

[0042] The removal of a part of the first layer, the semiconductor layer, and the second layer can be performed by a dry etching method, a wet etching method, or a combination of a dry etching method and a wet etching method. The removal of a part of the first layer, the semiconductor layer, and the second layer can be performed by a dry etching method, a wet etching method, or a combination of a dry etching method and a wet etching method. The removal of a part of the first layer, the semiconductor layer, and the second layer can be performed by a dry etching method, a wet etching method, or a combination of a dry etching method and a wet etching method.

[0043] By forming a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes with a material containing copper or aluminum, the wiring resistance can be reduced and the signal delay can be prevented. By forming a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes with a material containing copper or aluminum, the wiring resistance can be reduced and the signal delay can be prevented. By forming a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes with a material containing copper or aluminum, the wiring resistance can be reduced and the signal delay can be prevented.

[0044] Also, after forming the source electrode and the drain electrode, it is preferable to perform a cleaning process to remove impurities adhering to the surface and side surfaces of the exposed semiconductor layer. Also, after forming the source electrode and the drain electrode, it is preferable to perform a cleaning process to remove impurities adhering to the surface and side surfaces of the exposed semiconductor layer.

[0045] For the semiconductor layer, single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, etc. can be used. It is possible. Examples of semiconductor materials include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and the like.

[0046] In addition, by using an oxide semiconductor for the semiconductor layer, an EL display device with low power consumption and high reliability can be realized. can be realized.

Advantages of the Invention

[0047] According to one aspect of the present invention, the photolithography process used for manufacturing transistors can be reduced compared to the conventional process. Therefore, the number of photomasks used for manufacturing a display device having transistors can be reduced compared to the conventional process, and a semiconductor device with low cost and high productivity can be provided. Furthermore, by using an oxide semiconductor for the semiconductor layer in which a channel is formed, a semiconductor device with low power consumption and high reliability can be provided.

[0048]

Brief Description of the Drawings

[0049]

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Embodiments for Carrying Out the Invention

[0050] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments shown below. without departing from the spirit and scope of the present invention. and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments shown below. It should not be construed as being limited to the described state. In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted. For the same part or parts having the same function, the same reference numerals are commonly used between different drawings, and the repeated description thereof will be omitted.

[0051] In addition, ordinal numbers such as "first", "second", "third", etc. in this specification are attached to avoid confusion of components and are not numerically limiting.

[0052] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. for the sake of easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0053] A transistor is a type of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non - conduction. The transistors in this specification include IGFET (Insulated Gate Field Effect Transistor) and thin - film transistors (TFT: Thin Film Transistor). IGFET(Insulated Gate Field Effect Transi stor) and thin - film transistors (TFT: Thin Film Transistor) are included.

[0054] In addition, the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are adopted or when the direction of current changes in a circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

[0055] In addition, in this specification, etc., the terms "electrode" and "wiring" functionally limit these components. It is not defined. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0056] (Embodiment 1) In this embodiment, as an example of a semiconductor device with reduced number of photomasks and photolithography processes, a semiconductor device that can be used in an active matrix type liquid crystal display device and an example of its manufacturing method will be described with reference to FIGS. 1 to 13.

[0057] Using FIG. 6(A), a configuration example of a semiconductor device 100 that can be used in a liquid crystal display device will be described. The semiconductor device 100 has a pixel region 102 on a substrate 101, a terminal portion 103 having m (m is an integer of 1 or more) terminals 105_1 to 105_m and a terminal 107, and a terminal portion 104 having n (n is an integer of 1 or more) terminals 106_1 to 106_n. Further, the semiconductor device 100 has m wirings 212_1 to 212_m and a wiring 203 that are electrically connected to the terminal portion 103, and n wirings 216_1 to 216_n that are electrically connected to the terminal portion 104. Also, the pixel region 102 has a plurality of pixels 110 arranged in a matrix of m (rows) × n (columns). The pixel 110(i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) in the i-th row and j-th column is electrically connected to the wiring 212_i and the wiring 216_j, respectively. Each pixel is also connected to a wiring 203 that functions as a capacitive electrode or capacitive wiring, and the wiring 203 is electrically connected to the terminal 107 and the counter electrode connection portion 225. Also, the wiring 212_i is electrically connected to the terminal 105_i, and the wiring 2 is electrically connected to the terminal 107. Also, the wiring 212_i is electrically connected to the terminal 105_i, and the wiring 2​​​​​​​ 16_j is electrically connected to terminal 106_j.

[0058] When the liquid crystal display device formed using the semiconductor device 100 is used as a liquid crystal display device that operates with an electric field in a direction perpendicular to the surface of the substrate 101, a substrate (hereinafter also referred to as the "opposing substrate") provided facing the substrate 101 needs to be provided with an electrode (hereinafter also referred to as the "opposing electrode"). In addition, the opposing electrode is connected to the wiring 203 via the opposing electrode connection portion 225 formed on the substrate 101, and the same potential as that of the wiring 203 is supplied. The opposing electrode and the opposing electrode connection portion 225 can be connected via a conductive paste or conductive particles.

[0059] Note that when the liquid crystal display device formed using the semiconductor device 100 is used as a liquid crystal display device that operates with an electric field in a direction parallel to the surface of the substrate 101, since no opposing electrode is formed on the opposing substrate, the formation of the opposing electrode connection portion 225 can also be omitted.

[0060] The terminal portions 103 and 104 are external input terminals and are connected to a control circuit provided externally using an FPC (Flexible Printed Circuit) or the like. The signal supplied from the control circuit provided externally is input to the semiconductor device 100 via the terminal portions 103 and 104. In FIG. 6(A), a configuration is shown in which the terminal portion 103 is formed on the left and right outer sides of the pixel region 102 and signals are input from two locations. Also, a configuration is shown in which the terminal portion 104 is formed on the upper and lower outer sides of the pixel region 102 and signals are input from two locations. By inputting signals from two locations, the signal supply capacity is increased, so that the semiconductor device 100 can operate at high speed. The operation becomes easy. In addition, it is possible to reduce the influence of signal delay due to the increase in wiring resistance accompanying the increase in size and high definition of the semiconductor device 100. Further, since the semiconductor device 100 can have redundancy, the reliability of the semiconductor device 100 can be improved. Note that, in FIG. 6(A), the terminal portions 103 and 104 are each provided in two locations, but they may be provided in one location each. FIG. 6(B) shows the circuit configuration of the pixel 110. The pixel 110 has a transistor 111, a liquid crystal element 112, and a capacitor element 113. The gate electrode of the transistor 111

[0061] is electrically connected to the wiring 212_i, and one of the source electrode or drain electrode of the transistor 111 is electrically connected to the wiring 216_j. Further, the other of the source electrode or drain electrode of the transistor 111 is electrically connected to one electrode of the liquid crystal element 112 and one electrode of the capacitor element 113. The other electrode of the liquid crystal element 112 is electrically connected to the electrode 114. The potential of the electrode 114 is preferably GND, a common potential, or an arbitrary fixed potential. However, it is also possible to change the potential of the electrode 114 as necessary. The other electrode of the capacitor element 113 is electrically connected to the wiring 203. Also, the potential of the wiring 203 and the potential of the electrode 114 are preferably the same potential.

[0062]

[0062] The transistor 111 has a function of selecting whether to input an image signal supplied from the wiring 216_j to the liquid crystal element 112. When a signal for turning on the transistor 111 is supplied to the wiring 212_i, the image signal of the wiring 216_j passes through the transistor 111 and is supplied to the liquid crystal element. It is supplied to the liquid crystal element 112. The liquid crystal element 112 controls the light transmittance according to the supplied image signal (potential). The capacitance element 113 functions as a holding capacitor (also referred to as a Cs capacitor) for holding the potential supplied to the liquid crystal element 112. The capacitance element 113 is not necessarily provided, but by providing the capacitance element 113, the potential fluctuation applied to the liquid crystal element 112 due to the current (off-current) flowing between the source electrode and the drain electrode when the transistor 11 1 is in the off state can be suppressed. The semiconductor layer in which the channel of the transistor 111 is formed can use single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, amorphous semiconductor, etc. As the semiconductor material, for example,

[0063] silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be mentioned. Since the display device described in this embodiment has a structure in which a semiconductor layer remains in the pixel region, when using a display device using the above semiconductor as a transmissive display device it is preferable to increase the transmittance of visible light by making the semiconductor layer as thin as possible. Also, it is preferable to use an oxide semiconductor for the semiconductor layer in which the channel of the transistor 111 is formed. The oxide semiconductor has a large energy gap of 3.0 eV or more and a large transmittance for visible light. In addition, in a transistor obtained by processing the oxide semiconductor under appropriate conditions, at the temperature conditions during use of the off-current (for example, 25 °C), it is 100 z

[0064] A (1×10 A) or less, or 10 zA (1×10 A) or less, and further 1 zA (1×10 A) -19 A) or less, or 10 zA (1×10 -20 A) or less, and further 1 zA (1×10 -21 ​A) or less. Therefore, it is possible to reduce the power consumption of semiconductors In addition, the liquid crystal element 112 can be printed without providing the capacitor element 113. Since the applied potential can be maintained, the aperture ratio of the pixel can be increased, resulting in improved display quality. In addition, by increasing the aperture ratio of the pixels, it is possible to provide a liquid crystal display device with low backlight. This allows efficient use of light from light sources such as LEDs, thereby reducing the power consumption of liquid crystal displays. It is possible.

[0065] The oxide semiconductor used in the semiconductor layer has reduced impurities such as moisture and hydrogen, and By reducing oxygen vacancies in the body, i-type (intrinsic) or substantially i-type oxide semiconductors can be obtained. Preferably, the body is used.

[0066] Highly purified acid with reduced impurities such as water or hydrogen, which act as electron donors. The oxide semiconductor (purified OS) then supplies oxygen to the oxide semiconductor. By reducing oxygen vacancies in the oxide semiconductor, it is possible to obtain an i-type (intrinsic) oxide semiconductor or an i-type The oxide semiconductor can be substantially i-type. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer to be The off-state current is extremely low. Specifically, a highly purified oxide semiconductor is , Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration measured by hydrogen trometry was 5×10 19 / cm 3 Hereinafter, preferably 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following applies.

[0067] In addition, the carrier density of the i-type or substantially i-type oxide semiconductor that can be measured by Hall effect measurement is less than 1×10 14 / cm 3 , preferably less than 1×10 12 / cm 3 , more preferably less than 1×10 / cm 11 / cm 3 . Further, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an i-type or substantially i-type oxide semiconductor for the semiconductor layer in which the channel is formed, the off-current of the transistor can be reduced.

[0068] Here, the SIMS analysis of the hydrogen concentration in the oxide semiconductor will be described. In principle, it is known that it is difficult to accurately obtain data near the sample surface or near the laminated interface with a film of different material in SIMS analysis. Therefore, when analyzing the thickness direction distribution of the hydrogen concentration in a film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme fluctuation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Further, when the thickness of the film to be measured is small, it may not be possible to find a region where a substantially constant value is obtained due to the influence of the hydrogen concentration in the adjacent film. In this case, the maximum value or the minimum value of the hydrogen concentration in the region where the film exists is adopted as the hydrogen concentration in the film. Furthermore, when there is no peak of a mountain type having a maximum value or a peak of a valley type having a minimum value in the region where the film exists, the value of the inflection point is adopted as the hydrogen concentration.

[0069] In addition, in this embodiment, the transistor 111 is described as an n-channel transistor but it may be a p-channel transistor.

[0070] Next, a configuration example of the pixel 110 shown in FIG. 6 will be described with reference to FIGS. 1 and 2. FIG. 1 is a top view showing the planar configuration of the pixel 110, and FIG. 2 is a cross-sectional view showing the stacked configuration of the pixel 110. The dashed lines A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. 1 are corresponding to the cross-sections A1-A2, B1-B2, C1-C2, and D1-D2 in FIGS. 2(A) to 2(D). Note that, for clarity of the drawing, some configuration elements are omitted in FIG. 1.

[0071] The transistor 111 shown in this embodiment has a shape in which the drain electrode 206b is surrounded by a U-shaped (C-shaped, U-shaped, or horseshoe-shaped) source electrode 206a. By adopting such a shape even if the area of the transistor is small, it is possible to secure a sufficient channel width, and it is possible to increase the amount of current (also referred to as on-current) flowing when the transistor is conducting. When the on-current of the transistor 111 increases, it becomes possible to input a signal more quickly.

[0072] In addition, if the parasitic capacitance generated between the drain electrode 206b electrically connected to the pixel electrode 210 and the gate electrode 202 is large, it is likely to be affected by feed-through, so that the potential supplied to the liquid crystal element 112 cannot be accurately held, which becomes a factor in deteriorating the display quality. As shown in this embodiment, by forming the source electrode 206a in a U-shape to surround the drain electrode 206b, while securing a sufficient channel width, between the drain electrode 206b and the gate electrode 20 ​ Since the parasitic capacitance generated between them can be reduced, the display quality of the liquid crystal display device can be improved.

[0073] The wiring 203 functions as a capacitive electrode or a capacitive wiring. In the present embodiment, the capacitive element 113 is formed by overlapping the wiring 203 and the drain electrode 206b.

[0074] In addition, since the semiconductor device described in the present embodiment does not perform a photolithography process for forming an island-shaped semiconductor layer for simplifying the process, the semiconductor layer 205 remains in all of the pixel regions. As a result, a first parasitic transistor may occur in which the wiring 212_i functions as a gate electrode, the wiring 216_j functions as one of a source electrode or a drain electrode, and the wiring 216_j + 1 of an adjacent pixel functions as the other of the source electrode or the drain electrode.

[0075] In addition, a second parasitic transistor may occur in which the wiring 203 functions as a gate electrode, the wiring 216_j functions as one of a source electrode or a drain electrode, and the wiring 216_j + 1 of an adjacent pixel functions as the other of the source electrode or the drain electrode.

[0076] In addition, a third parasitic transistor may occur in which the pixel electrode 210 functions as a gate electrode, the insulating layer 207 functions as a gate insulating layer, the wiring 216_j functions as one of a source electrode or a drain electrode, and the wiring 216_j + 1 of an adjacent pixel functions as the other of the source electrode or the drain electrode.

[0077] When a potential for turning on the transistor 111 is supplied to the wiring 212_i, the first parasitic ​​​​​​​​​​​The transistor also turns on, and the wiring 216_j of the pixel adjacent to the wiring 216_j +1 will be electrically connected. Due to the first parasitic transistor, the wiring 216_j and the wiring 216_j+1 are electrically connected, and the two image signals interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112.

[0078] Also, when the second parasitic transistor functions as an n-type transistor, the potential of the wiring 216_j or the wiring 216_j+1 of the adjacent pixel is lower than the potential supplied to the wiring 203. When the absolute value of the potential difference is greater than the threshold value of the second parasitic transistor a parasitic channel is formed in the semiconductor layer 205 overlapping the wiring 203, and the second parasitic transistor turns on. When the second parasitic transistor turns on, the wiring 216_j+1 of the pixel adjacent to the wiring 216_j will be electrically connected. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the second parasitic transistor, the two image signals interfere with each other, making it difficult to supply an accurate image signal

[0079] to the liquid crystal element 112.

[0080] Also, when the third parasitic transistor functions as an n-type transistor, the potential of the wiring 216_j or the wiring 216_j+1 of the adjacent pixel is lower than the potential supplied to or held by the pixel electrode 210. When the absolute value of the potential difference is greater than the threshold value of the third parasitic transistor a parasitic channel is formed in the semiconductor layer 205 overlapping the pixel electrode 210, and the third parasitic transistor turns on.

[0081]

[0081] When the third parasitic transistor is turned on, the wiring 216_j+1 of the pixel adjacent to the wiring 216_j is electrically connected. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger. When the wiring 216_j and the wiring 216_j+1 are electrically connected by the third parasitic transistor, the image signals of both interfere with each other, making it difficult to supply an accurate image signal to the liquid crystal element 112. Also, due to reasons such as increasing the aperture ratio of the pixel, when the pixel electrode 210 approaches the wiring 216_j or the wiring 216_j+1, the influence of the third parasitic transistor becomes stronger.

[0082] Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203. Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203. Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203. Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203. Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203. Therefore, in the present embodiment, the pixel 110 is provided with a groove portion 230 from which the semiconductor layer 205 is removed, so as to prevent the above-described parasitic transistor from occurring. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212_i, generation of the first parasitic transistor can be prevented. Also, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of the second parasitic transistor can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212_i or the wiring 203.

[0083] In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. In addition, the groove portion 230 is formed along the extending direction of the wiring 216_j or the wiring 216_j+1 at least on one side between the pixel electrode 210 and the wiring 216_j or between the pixel electrode 210 and the wiring 216_j+1 of the adjacent pixel, beyond the end portion 231 and the end portion 232 of the pixel electrode 210. Thereby, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the extending direction of the wiring 216_j or the wiring 216_j+1 is parallel to the extending direction of the wiring 216_j or the wiring 216_j+1. The guide wire need not necessarily be provided with a bent or curved portion, but may have a bent or curved portion.

[0084] In FIG. 1, the groove 230 is interrupted in the region between the wiring 212_i and the wiring 203. However, the groove 230 provided beyond the end of the wiring 212_i in the line width direction is extended, and the wiring 2 Alternatively, the groove 230 may be connected to the end of the line width direction of the insulating film 03.

[0085] In addition, the groove 230 is not provided on the wiring 203, and the potential of the wiring 203 is set to the wiring 216_j or The potential supplied to the wiring 216_j+1 is set to a potential lower than the potential supplied to the wiring 216_j+2. In this case, however, the above potential is supplied to the wiring 203. A separate power source must be provided to supply the power.

[0086] In addition, there is no particular limit to the size of the groove 230 where the semiconductor layer 205 is removed. In order to reliably prevent the generation of a transistor, the direction in which the wiring 216_j or the wiring 216_j+1 extends is The width of the portion of the groove 230 where the semiconductor layer is removed in the direction perpendicular to the direction of the groove 230 is 1 μm or more. It is preferable that the thickness is 2 μm or more, and more preferable that the thickness is 2 μm or more.

[0087] The cross section A1-A2 shows a stacked structure of the transistor 111 and the capacitor element 113. The transistor 111 is a bottom-gate transistor called a channel-etched type. The cross section B1-B2 is a cross section of the wiring 216_j including the pixel electrode 210 and the groove portion 230. The cross section C1-C2 shows the laminated structure from the wiring 216_j+1 to the wiring 216_j+2. 16_j and the laminated structure at the intersection of the wiring 212_i. D2 shows the laminated structure of wiring 216_j+1, the intersection of wiring 212_i, and groove portion 230. is shown.

[0088] In cross-section A1-A2 shown in FIG. 2(A), an underlayer 201 is formed on substrate 200, and a gate electrode 202 and wiring 203 are formed on underlayer 201. Also, a gate insulating layer 204 and a semiconductor layer 205 are formed on gate electrode 202 and wiring 203. Also, a source electrode 206a and a drain electrode 206b are formed on semiconductor layer 205 and are in contact with a part of semiconductor layer 205. An insulating layer 207 is formed on source electrode 206a and drain electrode 20 6b. A pixel electrode 210 is formed on insulating layer 207 and is electrically connected to drain electrode 206b through contact hole 208 formed in insulating layer 207.

[0089] The overlapping portion where wiring 203 and drain electrode 206b sandwich gate insulating layer 204 and semiconductor layer 205 functions as capacitor element 113. Gate insulating layer 204 and semiconductor layer 2 05 function as a dielectric layer. By forming the dielectric layer formed between wiring 203 and drain electrode 206b into a multilayer structure, even if a pinhole occurs in one dielectric layer, the pinhole is covered by another dielectric layer, so that capacitor element 113 can function normally. Also , since the relative permittivity of the oxide semiconductor is as large as 14 to 16, when an oxide semiconductor is used for semiconductor layer 205 , it becomes possible to increase the capacitance value of capacitor element 113.

[0090] In cross-section B1-B2 shown in FIG. 2(B), an underlayer 201 is formed on substrate 200, and a gate insulating layer 204 is formed on underlayer 201, and a semiconductor layer 205 is formed on gate insulating layer 204 is formed. Wiring 216_j and wiring 216_j+1 are formed on the semiconductor layer 205 and an insulating layer 207 is formed on the semiconductor layer 205, wiring 216_j, and wiring 216_j+1 is formed. Further, a pixel electrode 210 is formed on the insulating layer 207.

[0091] A groove portion 230 is formed between the wiring 216_j+1 and the pixel electrode 210, in which a part of the semiconductor layer 205 and a part of the insulating layer 20 7 are removed. The groove portion 230 is configured such that it does not have a semiconductor layer at least at its bottom surface portion.

[0092] In the cross-section C1-C2 shown in FIG. 2(C), an underlayer 201 is formed on the substrate 200, and a wiring 212_i is formed on the underlayer 201. Further, a gate insulating layer 204 and a semiconductor layer 205 are formed on the wiring 212_i. Also, a wiring 216_ j is formed on the semiconductor layer 205, and an insulating layer 207 is formed on the wiring 216_j. is formed, and an insulating layer 207 is formed on the wiring 216_j. j is formed on the semiconductor layer 205, and an insulating layer 207 is formed on the wiring 216_j.

[0093] In the cross-section D1-D2 shown in FIG. 2(D), an underlayer 201 is formed on the substrate 200, and a wiring 212_i is formed on the underlayer 201. Further, a gate insulating layer 204 and a semiconductor layer 205 are formed on the wiring 212_i. Also, a wiring 216_ j+1 is formed on the semiconductor layer 205, and an insulating layer 207 is formed on the wiring 216_j+1. Also, a groove portion 230 is formed in which a part of the semiconductor layer 205 and a part of the insulating layer 207 are removed is formed. Further, at the bottom surface of the groove portion 230, the gate insulating layer 204 is exposed, and the wiring 2 12_i located in a layer below it is not exposed. is formed. Also, at the bottom surface of the groove portion 230, the gate insulating layer 204 is exposed, and the wiring 2 12_i located in a layer below it is not exposed. 12_i is not exposed.

[0094] Next, a pixel configuration example different from the configuration shown in FIG. 1 will be described with reference to FIGS. 3 and 4. This is the case. FIG. 3 is a top view showing the planar configuration of pixel 120. As shown in FIGS. 4(A) to 4(C), the cross-sections A1 - A2, E1 - E2, and F1 - F2 shown correspond to the cross-sections of the portions indicated by the dashed lines of A1 - A2, E1 - E2, and F1 - F2 in FIG. 3. For ease of viewing the drawings, in FIG. 3, the description of some components is omitted.

[0095] The pixel 120 shown in FIG. 3 has a different planar shape of the groove portion 230 from the pixel 110 shown in FIG. 1. Also, the configuration of the portion indicated by the dashed line of A1 - A2 in FIG. 3 has the same configuration as the cross-section A 1 - A2 described in FIG. 2(A). Also, the configuration of the cross-section E1 - E2 is the same as the configuration in which a groove portion 230 is provided between the pixel electrode 210 and the wiring 216_j in the cross-section B1 - B2. Also, the cross- section F1 - F2 has the same configuration as the configuration with the left and right of the cross-section D1 - D2 swapped. The pixel 120 is configured such that the groove portion 230 is provided between the pixel electrode 210 and the wiring 216_j, and between the pixel electrode 2

[0096] 10 and the wiring 216_j + 1 of the adjacent pixel. Also, the groove portion 230 is provided not only to cross over the widthwise ends of the wiring 212_i and the wiring 203, but also in the region between the wiring 212_i and the wiring 203. In this way, by arranging the groove portion 230 widely, the generation of parasitic channels and parasitic transistors can be more reliably prevented. Next, a pixel configuration example different from the configuration shown in FIGS. 1 to 4 will be described with reference to FIG. 5.

[0097] FIG. 5(A) is a top view showing the planar configuration of pixel 130. The cross-section G1 shown in FIG. 5(B) corresponds to the cross-section of the portion indicated by the dashed line of G1 - G2 in FIG. 5(A). As shown in FIG. 5, the cross-section G1 - G2 shown corresponds to the cross-section of the portion indicated by the dashed line of G1 - G2 in FIG. 5(A). As shown in FIG. 5, The pixel 130 uses a conductive layer with high light reflectance for the pixel electrode 211, so that the pixel 1 shows an example of a pixel configuration that can be applied to a display device.

[0098] In the pixel 130, the grooves 251 and 252 where the semiconductor layer 205 has been removed are connected to the wiring 212. The wiring 212_i is provided so as to cross over both ends of the wiring 212_i in the line width direction. By providing a plurality of grooves that cross over both ends of the wiring 212_i, the wiring 212_i is formed to overlap with the wiring 212_i. The influence of the parasitic channel can be suppressed more reliably.

[0099] In addition, in the pixel 130, the grooves 253 and 254 where the semiconductor layer 205 has been removed are used as wiring. The wiring 203 is provided so as to cross over both ends in the line width direction. By providing a plurality of grooves that cross over both ends, parasitic circuits formed by overlapping with the wiring 203 can be eliminated. This makes it possible to more reliably suppress the effects of the channel.

[0100] In addition, in the pixel 130, the grooves 255 and 256 where the semiconductor layer 205 has been removed are used as wiring. The pixel 216_j or the adjacent pixel 216_j+1 is connected to the pixel 216_j along the extending direction of the line 216_j+1. The wiring 216_j is provided beyond the end 233 and the end 234 of the element electrode 211. or along the direction in which the wiring 216_j+1 extends, By providing a plurality of grooves beyond the portion 234, a parasitic ch formed by overlapping with the pixel electrode 211 can be prevented. The influence of the channel can be more reliably suppressed. The grooves 255 and 256 provided along the direction in which the wiring 216_j+1 extends are Alternatively, the wiring 216_j+1 does not need to be provided in parallel with the extending direction, and may extend up to the bent portion. or may have a curved portion.

[0101] The groove portions 255 and 256 of the pixel 130 have curved portions, and a part thereof is formed to overlap with the pixel electrode 21 1. Further, the pixel 130 has groove portions 257 and 258 formed to overlap with the pixel electrode 211 . Thus, by providing the groove portions 255 to 258 overlapping with the pixel electrode 211, unevenness can be provided on the surface of the pixel electrode 211 . When unevenness is provided on the surface of the pixel electrode 211, the incident external light can be diffusely reflected, enabling better display. Therefore, the visibility in the display is improved.

[0102] In addition, when the side surfaces of the groove portions 255 to 258 formed to overlap with the pixel electrode 211 are in a tapered shape, it is preferable because the coverage of the pixel electrode 211 is improved.

[0103] Next, a configuration example of the terminals 105_1 to 105_m and the terminals 106_1 to 106_n will be described with reference to FIG. 7. FIGS. 7(A1) and 7(A2) respectively show a top view and a cross-sectional view of the terminals 105_1 to 105_m . The dashed line J1 - J2 in FIG. 7(A1) corresponds to the cross-section J1 - J2 in FIG. 7(A2). Also, FIGS. 7(B1) and 7( B2) respectively show a top view and a cross-sectional view of the terminals 106_1 to 106_n. The dashed line K1 - K2 in FIG. 7(B1) corresponds to the cross-section K1 - K2 in FIG. 7(B2). In the cross-sections J1 - J2 and K1 - K2, J2 and K2 correspond to the substrate ends . Note that, for ease of viewing the drawings, some components are not described in FIG. 7 .

[0104] In cross-section J1-J2, an underlying layer 201 is formed on the substrate 200, and wiring 212_i is formed on the underlying layer 201. Further, a gate insulating layer 204, a semiconductor layer 205, and an insulating layer 207 are formed on the wiring 212_i. An electrode 221 is formed on the insulating layer 207, and the electrode 221 is electrically connected to the wiring 212_i through a contact hole 219 formed in the gate insulating layer 204, the semiconductor layer 205,

[0105] and the insulating layer 207. In cross-section K1-K2, on the substrate 200, the underlying layer 201, the gate insulating layer 204, and the semiconductor layer 205 are formed. Wiring 216_j is formed on the semiconductor layer 205, and an insulating layer 207 is formed on the wiring 216_j. An electrode 222 is formed on the insulating layer 207, and the electrode 222 is electrically connected to the wiring 216

[0106] _j through a contact hole 220 formed in the insulating layer 207. Note that the configuration of the terminal 107 can be the same as that of the terminals 105_1 to 105_m

[0107] or the terminals 106_1 to 106 _n. Also, the pixel region 102 and the terminal portion 104 are connected by n wirings 216_1 to 216_n. However, in the routing of the wirings 216_1 to 216_n from the pixel region 102 to the terminals 106_1 to 106_n of the terminal portion 104, if adjacent wirings 216_1 to 216 _n are close to each other, a parasitic channel may be formed in the semiconductor layer 205 existing between the adjacent wirings 216_1 to 216_n due to the potential difference between the

[0108] Such a phenomenon can be prevented by providing a conductive layer on the semiconductor layer 205 through an insulating layer over the entire region from the pixel region 102 to the terminal portion 104, or between adjacent wirings 216_1 to 216_n, and setting the potential of the conductive layer to a potential at which parasitic channels are not formed in the semiconductor layer 205. For example, when an oxide semiconductor is used for the semiconductor layer 205, since many oxide semiconductors tend to be n-type semiconductors, the potential of the conductive layer may be set to a potential lower than the potential supplied to the wirings 216_1 to 216_n. Also, in the contact hole formation process described later, by removing the semiconductor layer 205 between adjacent wirings 216_1 to 216_n,

[0109] unintended electrical connection between adjacent wirings 216_1 to 216_n can be prevented. FIG. 8 shows a configuration in which a groove portion 240 is formed between adjacent wirings 216_j, 216_j+1, and 216_j+2 to remove the semiconductor layer 205. FIG. 8(A) is a top view showing a planar configuration of the wirings 216_j, 216_j+1, and 216_j+2 connected to the terminals 106_j, 106_j+1, and 106_j+2. The cross section L1-L2 shown in FIG. 8(B) corresponds to the cross section of the portion indicated by the dashed line L1-L2 in FIG. 8(A). In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted.

[0110] In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted.

[0111] In FIG. 8, a configuration is shown in which a groove portion 240 is formed between adjacent wirings 216_j, 216_j+1, and 216_j+2 to remove the semiconductor layer 205. FIG. 8(A) is a top view showing a planar configuration of the wirings 216_j, 216_j+1, and 216_j+2 connected to the terminals 106_j, 106_j+1, and 106_j+2. The cross section L1-L2 shown in FIG. 8(B) corresponds to the cross section of the portion indicated by the dashed line L1-L2 in FIG. 8(A). In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. In FIG. 8(A), the wiring 216_j is connected to the terminal 106_j, the wiring 216_j+1 is connected to the terminal 106_j+1, and the wiring 216_j+2 is connected to the terminal 106_j+2. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted. For ease of viewing the drawing, in FIG. 8(A), the description of the substrate 200, the underlayer 201, the gate insulating layer 204, and the insulating layer 207 is omitted.

[0112] In the cross-section L1-L2 shown in FIG. 8(B), an underlayer 201, a gate insulating layer 204, and a semiconductor layer 205 are formed on a substrate 200. Further, wirings 21 6_j, wiring 216_j+1, and wiring 216_j+2 are formed on the semiconductor layer 205. Further, an insulating layer 207 is formed on the wirings 216_j, wiring 216_j+1, and wiring 216_j+2.

[0113] Further, a groove portion 240 from which the semiconductor layer 205 is removed is formed between adjacent wirings 216_j and 216_j+1. Further, a groove portion 240 from which the semiconductor layer 205 is removed is formed between adjacent wirings 216_j+1 and 216_j+ 2 (see FIGS. 8(A) and 8(B)). In this way, by providing the groove portion 240 from which the semiconductor layer 205 is removed between adjacent wirings 216_1 to 216_n, an unintentional electrical connection between adjacent wirings 216_1 to 216_n can be prevented. The groove portion 240 can be formed in the same process as the groove portion 230. Although there is no particular limitation on the size of the groove portion 240 from which the semiconductor layer 205 is removed, in order to surely prevent the generation of parasitic channels, the width of the portion from which the semiconductor layer in the groove portion 240 is removed in the direction orthogonal to the direction in which the wiring 216_j or the wiring 216_j+1 extends is preferably 1 μm or more, and more preferably 2 μm or more.

[0114]

[0115] Subsequently, the manufacturing method of the pixel portion of the liquid crystal display device described with reference to FIGS. 1 and 2 and the terminals 105 and 106 described with reference to FIG. 7 will be described with reference to FIGS. 9 to 12. 9 and 10 is taken along the dashed line A1-A2 in FIG. 11 and 12. Also, cross sections D1-D2 and cross sections in FIG. J1-J2 and the cross section K1-K2 correspond to D1-D2 and J1-J2 in FIG. 1 and FIG. 1 and K1-K2 are cross-sectional views of the areas indicated by the dashed dotted lines.

[0116] First, an insulating layer to be the underlayer 201 is formed on the substrate 200, preferably to a thickness of 50 nm to 300 nm. In most cases, the thickness is 100 nm or more and 200 nm or less (see FIG. 9(A) and FIG. 11(A)). The substrate 200 may be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of the present manufacturing process. A plastic substrate having a high degree of heat resistance can be used. If this is not the case, a metal substrate such as a stainless steel alloy with an insulating layer on its surface may be used. The glass substrate may be, for example, barium borosilicate glass or aluminoborosilicate glass. It is recommended to use a non-alkali glass substrate such as glass or aluminosilicate glass. The substrate 200 may be a silicon substrate, a sapphire substrate, or the like. (550mm x 650mm), 3.5th generation (600mm x 720mm, or 620m m×750mm), 4th generation (680mm×880mm, or 730mm×920mm ), 5th generation (1100mm x 1300mm), 6th generation (1500mm x 1850mm ), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400mm ), 9th generation (2400mm x 2800mm, 2450mm x 3050mm), 10th generation A glass substrate of a size of 2950 mm×3400 mm or the like can be used. In this example, aluminoborosilicate glass is used for the substrate 200 .

[0117] The underlayer 201 can be formed by a laminated structure of one or more insulating layers selected from aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide, and has a function of preventing the diffusion of impurity elements from the substrate 200. In the present specification, silicon nitride oxide means that the nitrogen content is higher than the oxygen content in its composition, and preferably, when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering Spectrometry (HFS), the composition range includes oxygen at 5 atomic% or more and 30 atomic% or less, nitrogen at 20 atomic% or more and 55 atomic% or less, silicon at 25 atomic% or more and 35 atomic% or less, and hydrogen at 10 atomic% or more and 30 atomic% or less. The underlayer 201 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. a plurality of insulating layers, and has a function of preventing the diffusion of impurity elements from the substrate 200. In the present specification, silicon nitride oxide means that the nitrogen content is higher than the oxygen content in its composition, and preferably, when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering Spectrometry (HFS), the composition range includes oxygen at 5 atomic% or more and 30 atomic% or less, nitrogen at 20 atomic% or more and 55 atomic% or less, silicon at 25 atomic% or more and 35 atomic% or less, and hydrogen at 10 atomic% or more and 30 atomic% or less. The underlayer 201 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. a plurality of insulating layers, and has a function of preventing the diffusion of impurity elements from the substrate 200. In the present specification, silicon nitride oxide means that the nitrogen content is higher than the oxygen content in its composition, and preferably, when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering Spectrometry (HFS), the composition range includes oxygen at 5 atomic% or more and 30 atomic% or less, nitrogen at 20 atomic% or more and 55 atomic% or less, silicon at 25 atomic% or more and 35 atomic% or less, and hydrogen at 10 atomic% or more and 30 atomic% or less. The underlayer 201 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. a plurality of insulating layers, and has a function of preventing the diffusion of impurity elements from the substrate 200. In the present specification, silicon nitride oxide means that the nitrogen content is higher than the oxygen content in its composition, and preferably, when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering Spectrometry (HFS), the composition range includes oxygen at 5 atomic% or more and 30 atomic% or less, nitrogen at 20 atomic% or more and 55 atomic% or less, silicon at 25 atomic% or more and 35 atomic% or less, and hydrogen at 10 atomic% or more and 30 atomic% or less. The underlayer 201 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. a plurality of insulating layers, and has a function of preventing the diffusion of impurity elements from the substrate 200. In the present specification, silicon nitride oxide means that the nitrogen content is higher than the oxygen content in its composition, and preferably, when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering Spectrometry (HFS), the composition range includes oxygen at 5 atomic% or more and 30 atomic% or less, nitrogen at 20 atomic% or more and 55 atomic% or less, silicon at 25 atomic% or more and 35 atomic% or less, and hydrogen at 10 atomic% or more and 30 atomic% or less. The underlayer 201 can be appropriately formed using a sputtering method, a CVD method, a coating method, a printing method, or the like. tering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa tering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa rdscattering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa rdscattering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa rdscattering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa rdscattering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa rdscattering spectrometry) and hydrogen forward scattering spectrometry (HFS:Hydrogen Forwa

[0118]

[0119] 15 3 / cm 20 3 20 / cm 3 3

[0119] In this embodiment, on the substrate 200, as the underlayer 201, the film thickness is formed by using the plasma CVD method Form silicon oxynitride of 200 nm. Also, the temperature during the formation of the underlayer 201 is preferably higher but below the temperature that the substrate 2 00 can withstand. For example, while heating the substrate 200 to a temperature of 350 °C or higher and 450 °C or lower, form the underlayer 201. Note that the temperature during the formation of the underlayer 201 is preferably constant. For example, perform the formation of the underlayer 201 by heating the substrate to 350 °C .

[0120] Also, after the formation of the underlayer 201, heat treatment may be performed under reduced pressure, in a nitrogen atmosphere, in a noble gas atmosphere, or in an ultra-dry air atmosphere. By the heat treatment, the concentrations of hydrogen, moisture, hydrides, or hydroxides contained in the underlayer 201 can be reduced. The temperature of the heat treatment is preferably higher but below the temperature that the substrate 200 can withstand. Specifically , it is preferably performed at a temperature equal to or higher than the film formation temperature of the underlayer 201 and below the strain point of the substrate 200.

[0121] Note that the hydrogen concentration in the underlayer 201 is 5×10 18 atoms / cm 3 less than, preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less, and it is desirable to set it as such.

[0122] Also, after the formation of the underlayer 201, introduce oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) into the underlayer 201 to make the underlayer 201 have a region with more oxygen than the stoichiometric composition (have an oxygen-rich region). The introduction of oxygen can be performed by ion ... ... ​​It can be carried out using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. Further, it can also be carried out by heat treatment in an oxygen atmosphere or plasma treatment carried out in an oxygen atmosphere. Moreover, by introducing oxygen, the bond between the element constituting the underlying layer 201 and hydrogen, or the bond between the element and the hydroxyl group is broken, and these hydrogens or hydroxyl groups react with oxygen to

[0123] generate water. Therefore, when heat treatment is performed after introducing oxygen, hydrogen or hydroxyl groups, which are impurities, are likely to be desorbed as water. For this reason, heat treatment may be performed after introducing oxygen into the underlying layer 201. Then, oxygen may be further introduced into the underlying layer 201 to make the underlying layer 201 in an oxygen-excessive state. Also, the introduction of oxygen and the heat treatment into the underlying layer 201 may be repeatedly performed a plurality of times alternately with each other. Further, the introduction of oxygen and the heat treatment may be performed simultaneously. Next, a conductive layer is formed on the underlying layer 201 with a thickness of 100 nm or more and 500 nm or less, preferably 200 nm or more and 300 nm or less, using a sputtering method, a vacuum evaporation method, or a plating method. A resist mask is formed by the first photolithography process, and a part of the conductive layer is selectively etched away to form the gate electrode 202, the wiring 203, and the wiring 212_i (see FIGS. 9(A) and 11(A)). The conductive layer for forming the gate electrode 202, the wiring 203, and the wiring 212_i is made of metals such as molybdenum

[0124] (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (A l), copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc), etc. (See FIGS. 9(A) and 11(A).)

[0125] (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (A l), copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc), etc. It can be formed by using a material or an alloy material mainly composed of these materials, either in a single layer or in a laminated structure. It can be formed by using a material or an alloy material mainly composed of these materials, either in a single layer or in a laminated structure.

[0126] For example, there are a single-layer structure using aluminum containing silicon, a two-layer structure with titanium laminated on aluminum, a two-layer structure with titanium laminated on titanium nitride, a two-layer structure with tungsten laminated on titanium nitride, a two-layer structure with tungsten laminated on tantalum nitride, a two-layer structure with copper laminated on a Cu-Mg-Al alloy, a two-layer structure with copper laminated on titanium nitride and then tungsten laminated thereon, etc. There are also a three-layer structure with copper laminated on titanium nitride and then tungsten laminated thereon, etc.

[0127] In addition, the above conductive layer can also be applied with a conductive material having light transmittance such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. It is also possible to form a laminated structure of the above conductive material having light transmittance and the material containing the above metal element. It is also possible to form a laminated structure of the above conductive material having light transmittance and the material containing the above metal element.

[0128] In addition, as the above conductive layer, a metal oxide containing nitrogen, specifically, an In-Ga-Zn-based oxide containing nitrogen, an In-Sn-based oxide containing nitrogen, an In-Ga-based oxide containing nitrogen, an In-Zn-based oxide containing nitrogen, a Sn-based oxide containing nitrogen, an In-based oxide containing nitrogen, or a metal nitride (such as InN, SnN, etc.) can be used. These materials have a work function of 5 eV (electron volt) or more, and when used as a gate electrode,

[0129] it can make the threshold voltage of the electrical characteristics of the transistor positive, that is, the so-called normally It can make the threshold voltage of the electrical characteristics of the transistor positive, that is, the so-called normally An off n-type transistor can be realized.

[0130] Since the conductive layer serves as wiring, it is preferable to use Al or Cu, which are low-resistance materials. By using Al or Cu, signal delay can be reduced and high image quality can be achieved. Note that Al has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. To prevent Al migration, it is preferable to laminate a metal material with a higher melting point than Al, such as Mo, Ti, or W, on Al. u, signal delay can be reduced and high image quality can be achieved. Note that Al has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. To prevent Al migration, it is preferable to laminate a metal material with a higher melting point than Al, such as Mo, Ti, or W, on Al. easily. To prevent Al migration, it is preferable to laminate a metal material with a higher melting point than Al, such as Mo, Ti, or W, on Al. To prevent Al migration, it is preferable to laminate a metal material with a higher melting point than Al, such as Mo, Ti, or W, on Al. To prevent Al migration, it is preferable to laminate a metal material with a higher melting point than Al, such as Mo, Ti, or W, on Al.

[0131] Etching of the conductive layer can be performed by a dry etching method or a wet etching method. Also, etching of the conductive layer may be performed by combining both the dry etching method and the wet etching method. The resist mask formed on the conductive layer can be appropriately formed using a photolithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Etching of the conductive layer can be performed by a dry etching method or a wet etching method. Also, etching of the conductive layer may be performed by combining both the dry etching method and the wet etching method. The resist mask formed on the conductive layer can be appropriately formed using a photolithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Etching of the conductive layer can be performed by a dry etching method or a wet etching method. Also, etching of the conductive layer may be performed by combining both the dry etching method and the wet etching method. The resist mask formed on the conductive layer can be appropriately formed using a photolithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Etching of the conductive layer can be performed by a dry etching method or a wet etching method. Also, etching of the conductive layer may be performed by combining both the dry etching method and the wet etching method. The resist mask formed on the conductive layer can be appropriately formed using a photolithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Etching of the conductive layer can be performed by a dry etching method or a wet etching method. Also, etching of the conductive layer may be performed by combining both the dry etching method and the wet etching method. The resist mask formed on the conductive layer can be appropriately formed using a photolithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0132] When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat When etching the conductive layer by the dry etching method, a gas containing a halogen element can be used as the etching gas. As an example of a gas containing a halogen element, chlorine-based gases represented by chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4), fluorine-based gases represented by carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3), hydrogen bromide (HBr), or oxygen can be appropriately used. An inert gas may also be added to the etching gas used. Also, as the dry etching method, a flat A line-plate type RIE (Reactive Ion Etching) method or an ICP (Indu ctively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are adjusted

[0133] appropriately so that etching can be performed into a desired processed shape. In the present embodiment, tungsten with a thickness of 100 nm is formed on the underlying layer 201 as a conductive layer by sputtering. Thereafter, the conductive layer is selectively removed by a first photolithography process to form the gate electrode 202, the wiring 203,

[0134] and the wiring 212_i (see Fig. 9(A)). Further, if the ends of the formed gate electrode 202, wiring 203, and wiring 212_i are in a taper shape, it is preferable because the covering property of the insulating layer and the conductive layer to be laminated later is improved. Specifically, the ends of the gate electrode 202, wiring 203, and wiring 212_i are tapered so that the cross-sectional shapes of the gate electrode 202, wiring 203, and wiring 212_i are trapezoidal or triangular. Here, the taper angle θ of the ends of the gate electrode 202, It is possible to prevent the phenomenon of breakage (step discontinuity) and improve the coverage property.

[0135] In addition, the gate electrode 202, the wiring 203, and the wiring 212_i are formed into a stacked structure composed of multiple layers so that the ends of the gate electrode 202, the wiring 203, and the wiring 212_i can be formed into a stepped shape to prevent step discontinuity of the layer formed thereon and improve the coverage property.

[0136] Note that, unless otherwise specified, the photolithography process referred to in this specification includes a resist mask formation process, a conductive layer or insulating layer etching process, and a resist mask peeling process shall be included.

[0137] Next, a gate insulating layer 204 is formed on the gate electrode 202, the wiring 203, and the wiring 212_i (see FIGS. 9(B) and 11(B)). For the gate insulating layer 204, silicon oxide, nitride silicon, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride aluminum oxynitride, aluminum nitride oxide, tantalum oxide, gallium oxide, yttrium oxide yttrium, lanthanum oxide, hafnium oxide, hafnium silicate, hafnium silicate into which nitrogen is introduced hafnium aluminate into which nitrogen is introduced, etc. can be used and can be formed by a plasma CVD method, a sputtering method, or the like. Also, the gate insulating layer 204 is not limited to a single layer and may be a stack of different layers. For example, silicon nitride is formed as the gate insulating layer A by a plasma CVD method, and silicon oxide is formed as the gate insulating layer B on the gate insulating layer A to form the gate insulating layer 204.

[0138] Generally, a capacitive element has a configuration in which a dielectric is sandwiched between two opposing electrodes, and the thickness of the dielectric is The thinner (the shorter the distance between the two opposing electrodes), and the larger the dielectric constant of the dielectric, the larger the capacitance value. However, if the dielectric is made thinner to increase the capacitance value of the capacitive element, two the leakage current flowing between the two electrodes tends to increase, and the breakdown voltage of the capacitive element also tends to decrease.

[0139] The portion where the gate electrode, gate insulating layer, and semiconductor layer of the transistor overlap functions as the above-described capacitive element (hereinafter, also referred to as "gate capacitance"). Note that a channel is formed in the region of the semiconductor layer that overlaps with the gate electrode via the gate insulating layer. That is, the gate electrode and the channel formation region function as the two electrodes of the capacitive element, and the gate insulating layer functions as the dielectric of the capacitive element. It is preferable that the capacitance value of the gate capacitance is large. However, if the gate insulating layer is made thinner to increase the capacitance value, problems such as the increase in the leakage current and the decrease in the breakdown voltage described above tend to occur.

[0140] On the other hand, as the gate insulating layer 204, hafnium silicate (HfSi x O y (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSi x O y N z (x > 0, y > 0, z > 0)), hafnium aluminate with nitrogen added (HfAl x O y N z (x > 0, y > 0, z > 0)), high-k materials such as hafnium oxide and yttrium oxide are used, it is possible to sufficiently secure the capacitance value between the gate electrode 202 and the semiconductor layer 205 even if the gate insulating layer 204 is thickened.

[0141] ​​​​​​For example, if a high-k material with a large dielectric constant is used as the gate insulating layer 204, even if the gate insulating layer 204 is thickened, a capacitance value equivalent to that when silicon oxide is used for the gate insulating layer 204 can be achieved, so that the leakage current generated between the gate electrode 202 and the semiconductor layer 205 can be reduced. In addition, the leakage current generated between the wiring formed using the same layer as the gate electrode 202 and another wiring superimposed on the wiring can be reduced. Note that the high-k material may have a stacked structure with any one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, and gallium oxide. The thickness of the gate insulating layer 204 is preferably 10 nm or more and 300 nm or less, more preferably 50 nm or more and 200 nm or less. For example, the gate insulating layer 204 may have a stacked structure of silicon nitride with a thickness of 10 nm or more and 50 nm or less and silicon oxynitride with a thickness of 100 nm or more and 300 nm or less.

[0142] In addition, the temperature during the formation of the gate insulating layer 204 is preferably not higher than the temperature that the substrate 200 and the gate electrode 202 (including the wiring formed in the same layer) can withstand, and the higher the better. For example, while heating the substrate 200 to 350 °C or more and 450 °C or less as the gate insulating layer 204, silicon oxynitride with a thickness of 100 nm is formed by the high-density plasma CVD method. Note that the temperature during the formation of the gate insulating layer 204 is preferably constant. For example, the formation of the gate insulating layer 204 is performed while heating the substrate 200 to 350 °C.

[0143] In addition, after the formation of the gate insulating layer 204, heat treatment may be performed under reduced pressure, in a nitrogen atmosphere, in a noble gas atmosphere, or in an ultra-dry air atmosphere. By the heat treatment, the gate insulating layer 20 ​​ The concentration of hydrogen, moisture, hydride, or hydroxide contained in 4 can be reduced . The heat treatment temperature should be below the temperature that the substrate 200 can withstand, and it is preferably carried out at a higher temperature . Specifically, it is preferably carried out at a temperature equal to or higher than the film formation temperature of the gate insulating layer 204 and below the distortion point of the substrate 200 .

[0144] Note that the hydrogen concentration in the gate insulating layer 204 is 5×10 18 atoms / cm 3 less than, preferably or 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less, which is desirable .

[0145] Also, when an oxide semiconductor is used for the semiconductor layer 205, the gate insulating layer 204 preferably contains oxygen at the portion in contact with the semiconductor layer 2 05. In particular, it is preferable that at least a stoichiometric ratio excess amount of oxygen exists in the layer (in the bulk). For example, when silicon oxide is used as the gate insulating layer 204, it is SiO (where α>0). 2+α (provided that α>0).

[0146] The gate insulating layer 204 can be formed by appropriately using a sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc. Also, a high-density plasma CVD method using microwaves (for example, a frequency of 2.45 GH z) can be applied. Also, for the gate insulating layer 204, a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface Alternatively, the film may be formed using a sputtering apparatus that performs film formation in a heated state.

[0147] After the gate insulating layer 204 is formed, the gate insulating layer 204 is The gate insulating layer 204 is chemically treated by introducing oxygen atoms or oxygen ions. It is also possible to have a region in which there is more oxygen than in the stoichiometric composition (an oxygen excess region). The introduction of elements is performed by ion implantation, ion doping, plasma immersion ion implantation, etc. It can be performed by heat treatment in an oxygen atmosphere or by using an oxygen atmosphere. It can also be performed by a plasma treatment in a nitrogen atmosphere.

[0148] In addition, the introduction of oxygen may cause a bond between the elements constituting the gate insulating layer 204 and hydrogen, or The bond between the element and the hydroxyl group is broken, and the hydrogen or hydroxyl group reacts with oxygen. Therefore, if the heat treatment is performed after the introduction of oxygen, the impurities hydrogen or Therefore, when oxygen is introduced into the gate insulating layer 204, the hydroxyl group is easily desorbed as water. After that, oxygen may be further introduced into the gate insulating layer 204 to form a gate insulating film. The gate insulating layer 204 may be in an oxygen-excess state. The introduction and the heat treatment may be alternately repeated several times. Heat treatment may be carried out simultaneously.

[0149] When an oxide semiconductor is used for the semiconductor layer 205, oxygen serving as an oxygen supply source is added in large amounts (excessively). The gate insulating layer 204 is provided in contact with the semiconductor layer 205. Oxygen can be supplied from the gate insulator 04 to the semiconductor layer 205. The semiconductor layer 205 may be heat-treated with at least a part of the edge layer 204 in contact therewith. Oxygen may be supplied to the semiconductor layer 205. By supplying oxygen to the semiconductor layer 205, oxygen vacancies in the semiconductor layer 205 can be filled.

[0150] In this embodiment, silicon oxynitride is used as the gate insulating layer 204. Specifically, silicon oxynitride is formed on the gate electrode 202 to a thickness of 100 nm.

[0151] Next, a semiconductor that will become the semiconductor layer 205 is formed on the gate insulating layer 204 (see FIGS. 9(B) and 11(B)). In this embodiment, an oxide semiconductor is used as the semiconductor layer 205. Also, prior to the formation of the oxide semiconductor, a planarization process may be performed on the region where the semiconductor layer 205 of the gate insulating layer 204 is formed in contact. The planarization process is not particularly limited, but polishing (for example, Chemical Mechanical Polishing: CMP), dry etching, or plasma treatment can be used. For plasma treatment, for example, reverse sputtering can be performed by introducing argon gas to generate plasma. Reverse sputtering is a method of applying a voltage using an RF power supply to the substrate side in an argon atmosphere to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) adhering to the surface of the gate insulating layer 204 can be removed.

[0152]

[0153] ​​​​​​​Further, polishing treatment, dry etching treatment, and plasma treatment as planarization treatments may be performed multiple times, or they may be combined. When combined, the order of the processes is not particularly limited and may be appropriately set according to the uneven state of the surface of the gate insulating layer 204. The oxide semiconductor can be formed by using a sputtering method, a vapor deposition method, a PCVD method, a PLD method, an ALD method, or an MBE method. Note that the oxide semiconductor is preferably formed under conditions where a large amount of oxygen is contained during film formation (for example, film formation is performed by a sputtering method in an atmosphere of 100% oxygen), and the film is made to contain a large amount of oxygen (preferably, a region where the oxygen content is excessive with respect to the stoichiometric composition in the crystalline state of the oxide semiconductor is included). For the target for producing the oxide semiconductor by a sputtering method, for example, a metal oxide containing In, Ga, and Zn can be used, and a target having a composition of In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio] can be used. Also, a target having a composition of In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio], a target having a composition of In2O3:Ga2O3:ZnO = 1:1:4 [molar ratio], or a target having a composition of In2O3:Ga2O3:ZnO = 2:1:8 [molar ratio] can be used.

[0154] Further, the relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor can be made into a dense film.

[0155]

[0156] ​​​​​​​​​​​​​​​

[0157] For forming the oxide semiconductor film, a substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 10 0 °C or higher and 600 °C or lower, preferably 300 °C or higher and 500 °C or lower.

[0158] By forming the film while heating the substrate, the concentrations of impurities such as hydrogen, moisture, hydrides, or hydroxides contained in the formed oxide semiconductor can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor is formed using the above target.

[0159] As an example of the film-forming conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa , the DC (direct current) power supply power is 0.5 kW, and the conditions in an oxygen (oxygen flow ratio 100%) atmosphere are applicable. Note that when using a pulsed DC power supply, it is preferable because the powdery substances (also referred to as particles , dust) generated during film formation can be reduced and the film thickness distribution becomes uniform.

[0160] Note that even when using the above sputtering apparatus, the oxide semiconductor may be formed containing a certain amount of nitrogen. For example, nitrogen may be contained in the oxide semiconductor at a concentration of less than 5×10 18 atoms / cm 3 .

[0161] Here, the sputtering apparatus for forming the oxide semiconductor will be described in detail below.

[0162] The processing chamber for forming the oxide semiconductor preferably has a leak rate of 1×10 -10 Pa·m 3 / second or less, so that when forming a film by the sputtering method, impurities in the film ​ Mixing can be reduced.

[0163] To lower the leak rate, it is necessary to reduce not only external leaks but also internal leaks. External leakage refers to the inflow of gas from outside the vacuum system through minute holes, seal defects, etc. Internal leakage is caused by leakage from partitions such as valves within the vacuum system and outgassing from internal components. To set the leak rate to 1×10 Pa·m -10 / second or less, it is necessary to take measures against both external and internal leaks. 3

[0164] To reduce external leakage, the opening and closing parts of the processing chamber may be sealed with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external leakage. Also, by using a metal material coated with a passivation such as iron fluoride, aluminum oxide, or chromium oxide, the outgassing containing hydrogen generated from the metal gasket can be suppressed, and internal leakage can also be reduced.

[0165] As a member constituting the inner wall of the processing chamber, use aluminum, chromium, titanium, zirconium, nickel, or vanadium with little outgassing containing hydrogen. Alternatively, the aforementioned materials may be coated with an alloy material containing iron, chromium, and nickel, etc., and used. Alloy materials containing iron, chromium, and nickel, etc., are rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing, etc., to reduce the surface area, outgassing can be reduced. Or, the members of the aforementioned film-forming apparatus may be coated with iron fluoride, aluminum oxide, chromium oxide, etc. ​ It may be coated with a passivation such as a ROM.

[0166] Furthermore, it is preferable to provide a purifier for the sputtering gas immediately before introducing the sputtering gas into the processing chamber. At this time, the length of the pipe from the purifier to the processing chamber is set to 5 m or less, preferably 1 m or less. By setting the length of the pipe to 5 m or less or 1 m or less, the influence of the exhaust gas from the pipe can be reduced according to the length.

[0167] Exhaust of the processing chamber may be appropriately combined with a roughing pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbo molecular pump, and a cryopump. In addition, in order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. While a turbo molecular pump is excellent in exhausting large-sized molecules, its exhaust capacity for hydrogen and water is low. Furthermore, it is effective to combine a cryopump with a high water exhaust capacity or a sputter ion pump with a high hydrogen exhaust capacity. In addition, a turbo molecular pump with a cold trap added thereto may be used. The processing chamber exhausted using an adsorption type vacuum pump such as a cryopump exhausts compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), etc., so that the concentration of impurities contained in the oxide semiconductor formed in the processing chamber can be reduced. The adsorbates present inside the processing chamber do not affect the pressure of the processing chamber because they are adsorbed on the inner wall, but they cause gas release when the processing chamber is exhausted. Therefore, the leak rate and the exhaust speed

[0168] ​Although there is no correlation, it is important to use a pump with high exhaust capacity to desorb as much adsorbed material as possible present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbed material, the processing chamber may be baked. By baking, the desorption rate of the adsorbed material can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed material is removed while adding an inert gas, the desorption rate of water, etc., which is difficult to desorb by simply evacuating, can be further increased. In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used. Note that when using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The thickness of the semiconductor layer 205 is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. In this embodiment, as the semiconductor layer 205, indium-gallium-zinc oxide (IGZO) with a film thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device (see Fig. 9(B)). Also, as the target, an indium-gallium-zinc oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3) is used. The film formation conditions are an oxygen and argon atmosphere (oxygen flow ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C. The film formation rate under these film formation conditions is 16 nm / min. In addition, alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor Although there is no correlation, it is important to use a pump with high exhaust capacity to desorb as much adsorbed material as possible present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbed material, the processing chamber may be baked. By baking, the desorption rate of the adsorbed material can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed material is removed while adding an inert gas, the desorption rate of water, etc., which is difficult to desorb by simply evacuating, can be further increased. In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used. Note that when using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable.

[0169] Although there is no correlation, it is important to use a pump with high exhaust capacity to desorb as much adsorbed material as possible present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbed material, the processing chamber may be baked. By baking, the desorption rate of the adsorbed material can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed material is removed while adding an inert gas, the desorption rate of water, etc., which is difficult to desorb by simply evacuating, can be further increased. In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used. Note that when using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The thickness of the semiconductor layer 205 is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. In this embodiment, as the semiconductor layer 205, indium-gallium-zinc oxide (IGZO) with a film thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device (see Fig. 9(B)). Also, as the target, an indium-gallium-zinc oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3) is used. The film formation conditions are an oxygen and argon atmosphere (oxygen flow ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C. The film formation rate under these film formation conditions is 16 nm / min. In addition, alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor

[0170] Although there is no correlation, it is important to use a pump with high exhaust capacity to desorb as much adsorbed material as possible present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbed material, the processing chamber may be baked. By baking, the desorption rate of the adsorbed material can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed material is removed while adding an inert gas, the desorption rate of water, etc., which is difficult to desorb by simply evacuating, can be further increased. In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used. Note that when using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The thickness of the semiconductor layer 205 is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. In this embodiment, as the semiconductor layer 205, indium-gallium-zinc oxide (IGZO) with a film thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device (see Fig. 9(B)). Also, as the target, an indium-gallium-zinc oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3) is used. The film formation conditions are an oxygen and argon atmosphere (oxygen flow ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C. The film formation rate under these film formation conditions is 16 nm / min. In addition, alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor Although there is no correlation, it is important to use a pump with high exhaust capacity to desorb as much adsorbed material as possible present in the processing chamber and evacuate it in advance. In addition, in order to promote the desorption of the adsorbed material, the processing chamber may be baked. By baking, the desorption rate of the adsorbed material can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed material is removed while adding an inert gas, the desorption rate of water, etc., which is difficult to desorb by simply evacuating, can be further increased. In the sputtering method, as a power supply device for generating plasma, an RF power supply device, an AC power supply device, a DC power supply device, etc. can be appropriately used. Note that when using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The thickness of the semiconductor layer 205 is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. In this embodiment, as the semiconductor layer 205, indium-gallium-zinc oxide (IGZO) with a film thickness of 35 nm is formed by a sputtering method using a sputtering device having an AC power supply device (see Fig. 9(B)). Also, as the target, an indium-gallium-zinc oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3) is used. The film formation conditions are an oxygen and argon atmosphere (oxygen flow ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C. The film formation rate under these film formation conditions is 16 nm / min. In addition, alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor

[0171] In addition, alkali metals such as sodium (Na), lithium (Li), and potassium (K) in the oxide semiconductor The concentration of the alkali metal is 5×10 16 cm -3 or less, preferably 1×10 16 cm -3 or less, more preferably 1×10 15 cm -3 or less. For Li, it is 5×10 15 cm -3 or less, preferably 1×10 15 cm -3 or less. For K, it is 5×10 15 cm -3 or less, preferably 1×10 15 cm -3 or less, which is preferable.

[0172] The oxide semiconductor is insensitive to impurities. Even if a considerable amount of metal impurities are contained in the oxide semiconductor, there is no problem. It has been pointed out that inexpensive soda lime glass containing a large amount of alkali metals such as sodium can also be used (Kamiya, Nomura, Hosono, "Physical Properties of Amorphous Oxide Semiconductors and Current Status of Device Development", Solid State Physics, September 2009 issue, Vol. 44, p. 6 21-633). However, such a statement is inappropriate. Since alkali metals are not elements that constitute the oxide semiconductor, they are impurities. Alkaline earth metals also become impurities when they are not elements that constitute the oxide semiconductor. In particular, among alkali metals, when the insulating layer in contact with the oxide semiconductor layer is an oxide, Na diffuses into the insulating layer and becomes Na . Also , Na breaks or interrupts the bond between the metal and oxygen that constitutes the oxide semiconductor within the oxide semiconductor layer. As a result, for example, characteristics of the transistor deteriorate, such as non-ionization due to the threshold voltage shifting in the negative direction, and a decrease in mobility . + In addition, the characteristics of the transistors are also affected by impurities. The deterioration and variation in characteristics occur when the concentration of hydrogen in the oxide semiconductor layer is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor is 5×10 19 cm -3 Below Below, especially 5×10 18 cm -3 If the concentration of the alkali metal in the oxide semiconductor is It is strongly recommended that the above values be set.

[0173] The oxide semiconductor used for the semiconductor layer 205 is at least indium (In) or It is preferable that the alloy contains zinc (Zn). It is particularly preferable that the alloy contains both In and Zn. A stabilizer for reducing variations in electrical characteristics of a transistor using the oxide semiconductor In addition to these, it is preferable to have gallium (Ga) as a stabilizer. It is preferable to have tin (Sn) as the catalyst and hafnium as the stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable that the stabilizer contains zirconium (Zr). is preferred.

[0174] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0175] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide , In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO ), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn -based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based acid oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxidation product, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide , In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based acid oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn -Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based acid oxide can be used.

[0176] Also, as the oxide semiconductor, a material represented by the chemical formula InMO3(ZnO) m (m > 0) can be used. Note that the element M represents one metal element or a plurality of metal elements selected from Zn, Ga, Al, Fe, Mn, and C o. Also, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n > 0) can be used. n

[0177] For example, In:Ga:Zn = 1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n = 2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn = 3:1:2 (=1 / 2:1 / 6:1 / 3) atomic ratio of In-Ga-Zn-based oxide and in the vicinity of its composition Oxides can be used. Alternatively, In:Sn:Zn = 1:1:1 (= 1 / 3: 1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) In-Sn-Zn-based oxides with an atomic ratio of and oxides in the vicinity of its composition may be used.

[0178] However, oxide semiconductors containing indium are not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics ( mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal elements and oxygen appropriate in terms of atomic distance, density, etc.

[0179] For example, relatively high mobility can be obtained easily with In-Sn-Zn-based oxides. However, even with In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

[0180] Note that, for example, the composition of an oxide with an atomic ratio of In:Ga:Zn = a:b:c (a + b + c = 1) is in the vicinity of the composition of an oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 + (b - B) 2 + (c - C) 2 ≤ r 2 where r may be, for example, 0.05. The same applies to other oxides.

[0181] The oxide semiconductor used for the semiconductor layer 205 takes a state such as single crystal, polycrystal (also referred to as polycrystal), or amorphous.

[0182] The oxide semiconductor used for the semiconductor layer 205 is preferably CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) .

[0183] CAAC-OS is neither a perfect single crystal nor a perfect amorphous material. CAAC-OS is an oxide semiconductor having a crystal-amorphous mixed-phase structure with crystal parts in an amorphous phase. Note that the crystal parts are often sized to fit within a cube with sides less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM: Transmission Electron Microsco pe), the boundary between the amorphous part and the crystal part included in CAAC-OS is not clear . Also, no grain boundaries (also referred to as grain boundaries) can be confirmed in CAAC-OS by TEM . Therefore, in CAAC-OS, a decrease in electron mobility due to grain boundaries is suppressed.

[0184] The crystal parts included in CAAC-OS have their c-axes aligned in a direction perpendicular to the formation surface or the surface of CAAC-OS, and have a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab plane , and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers . Note that the directions of the a-axis and b-axis may be different between different crystal parts . In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included .

[0185] Note that in CAAC-OS, the distribution of the crystal parts may not be uniform. For example, CAAC ​When crystal growth is performed from the surface side of the oxide semiconductor film in the formation process of the -OS, the formation surface may have a higher proportion of crystal parts in the vicinity of the surface compared to the vicinity of the formation surface. Also, when impurities are added to the CAAC -OS, the crystal parts may be amorphous in the impurity addition region .

[0186] The c-axes of the crystal parts included in the CAAC-OS are aligned in a direction perpendicular to the formation surface or the surface of the CAAC-OS , so depending on the shape of the CAAC-OS (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal parts is the direction perpendicular to the formation surface or the surface when the CAAC -OS is formed. The crystal parts are formed by film formation , or by performing a crystallization treatment such as a heat treatment after film formation .

[0187] A transistor using CAAC-OS has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light . Therefore, the transistor has high reliability

[0188] Note that part of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen

[0189] Also, in an oxide semiconductor having crystal parts like CAAC-OS, more bulk defects can be reduced, and if the surface flatness is increased, a mobility higher than that of an amorphous oxide semiconductor can be obtained . To increase the surface flatness, it is preferable to form the oxide semiconductor on a flat surface , specifically, on a surface with an average surface roughness (Ra) of 1 nm or less, preferably 0 .3 nm or less, more preferably 0.1 nm or less. Ra can be evaluated with an atomic force microscope (AFM: Atomic Force Microscope) . and Yes.

[0190] However, since the transistor 111 described in this embodiment is a bottom gate type, a gate electrode 202 exists below the gate insulating layer 204. Therefore, after forming the gate insulating layer 204 on the gate electrode 202 to obtain the above flat surface, a planarization process such as CMP processing may be performed on the surface of the gate insulating layer 204 that overlaps at least the gate electrode 202.

[0191] Also, when forming an In-Ga-Zn-based oxide material as the semiconductor layer 205 by sputtering, preferably, an In-Ga-Zn-based oxide target represented by an atomic ratio of In:Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 can be used. By forming the semiconductor layer 205 using an In-Ga-Zn-based oxide target having the above-described atomic ratio, a polycrystalline oxide semiconductor or CAAC-OS is likely to be formed.

[0192] Also, before forming the oxide semiconductor that becomes the semiconductor layer 205, heat treatment may be performed under reduced pressure, in a nitrogen atmosphere, in a rare gas atmosphere, or in an ultra-dry air atmosphere. For example, heat treatment may be performed at a temperature of 350°C or higher and 450°C or lower in a nitrogen atmosphere. For example, heat treatment may be performed at 350°C for 1 hour. By this heat treatment, impurities such as hydrogen, moisture, and hydrocarbon attached to the surface of the gate insulating layer 204 can be reduced. Note that it is preferable to continuously form the oxide semiconductor layer without exposing the substrate 101 to the atmosphere after the heat treatment.

[0193] Also, the steps from the formation of the gate insulating layer 204 to the formation of the semiconductor layer 205 are preferably carried out continuously without exposing to the atmosphere in the middle. When the gate insulating layer 204 and the oxide semiconductor layer are continuously formed without exposing to the atmosphere in the middle, it is possible to prevent impurities such as hydrogen, moisture, and high dopant carbon from adsorbing on the surface of the gate insulating layer 204. That is, the interface between the gate insulating layer 204 and the oxide semiconductor layer can be kept clean, so that the reliability of the semiconductor device can be improved.

[0194] In addition, a heat treatment may be performed on the semiconductor layer 205 to remove excessive hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The temperature of the heat treatment is 300 °C or higher and 700 °C or lower , or less than the distortion point of the substrate. The heat treatment can be performed under reduced pressure, in a nitrogen atmosphere, or in a noble gas atmosphere.

[0195] In this embodiment, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and a heat treatment is performed on the semiconductor layer 205 at a temperature of 350 °C or higher and 450 °C or lower for 1 hour in a nitrogen atmosphere , and further a heat treatment is performed at a temperature of 350 °C or higher and 450 °C or lower for 1 hour in a nitrogen and oxygen atmosphere. For example, a heat treatment is performed at 350 °C for 1 hour.

[0196] Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anne al) apparatus such as a GRTA (Gas R apid Thermal Anneal) apparatus or an LRTA (Lamp Rapid T al) The device can be used. The LRTA device is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. As the high-temperature gas, noble gases such as argon or inert gases that do not react with the object to be processed by heat treatment, such as nitrogen, are used. For example, as a heat treatment, the substrate may be placed in an inert gas heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then GRTA may be performed to take the substrate out of the inert gas. In the heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment device is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In addition, there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, may be simultaneously desorbed and reduced by the heat treatment for dehydration or dehydrogenation. In the oxide semiconductor, oxygen deficiency exists at the location where oxygen is desorbed, and a donor level that causes electrical property fluctuations of the transistor is generated due to the oxygen deficiency. Therefore, after heating the semiconductor layer 205 by heat treatment, high-purity oxygen gas and high-purity

[0197]

[0198]

[0199]

[0200] Nitrogen dioxide gas or ultra-dry air (moisture content when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy ) method is 20 ppm or less (dew point equivalent to -55 °C) , preferably 1 ppm or less, more preferably 10 ppb or less of air) may be introduced. It is preferable that oxygen gas or nitrogen dioxide gas does not contain water, hydrogen, etc. Or , the purity of the oxygen gas or nitrogen dioxide gas introduced into the heat treatment apparatus is preferably 6N or more and preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrogen dioxide gas is 1 ppm or less, preferably 0.1 ppm or less). By supplying oxygen, which is the main component material constituting the oxide semiconductor, which is simultaneously reduced by the impurity elimination step by dehydration or dehydrogenation treatment , the semiconductor layer 205 can be purified to high purity and made into an i-type (intrinsic) form.

[0201] Also, oxygen (including at least any one of oxygen radicals , oxygen atoms, oxygen ions) may be introduced into the semiconductor layer 205 that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film.

[0202] For the introduction of oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation lation method, plasma treatment performed in an oxygen atmosphere, etc. can be used.

[0203] Also, by the introduction of oxygen, the bond between the element constituting the oxide semiconductor and hydrogen, or the bond between the element and the hydroxyl group is broken, and these hydrogen or hydroxyl groups react with oxygen to generate water. Therefore, by the heat treatment performed later, hydrogen, which is an impurity, or The hydroxyl group can be made to be easily desorbed as water. Therefore, after introducing an acid into the semiconductor layer 205, a heat treatment is performed, and then oxygen is introduced into the semiconductor layer 205, and the semiconductor layer 2 05 may be in an oxygen-excess state. Further, the introduction of oxygen into the semiconductor layer 205 and the heat treatment may be performed alternately a plurality of times respectively. Also, the heat treatment and the introduction of oxygen may be performed simultaneously .

[0204] By introducing oxygen into the semiconductor layer 205 that has undergone a dehydration or dehydrogenation treatment (heat treatment) to supply oxygen into the layer, the semiconductor layer 205 can be made into an i-type (intrinsic) semiconductor. A transistor having an i-type (intrinsic) semiconductor layer 205 has suppressed fluctuations in electrical characteristics and is electrically stable.

[0205] As described above, the oxide semiconductor used for the semiconductor layer 205 is highly purified by sufficiently removing impurities such as hydrogen, and sufficient oxygen is supplied to make the oxygen in a supersaturated state . Thus, it is preferably an i-type (intrinsic) or substantially i-type (intrinsic) semiconductor . Specifically, the hydrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 5×10 17 atom s / cm 3 or less. Also, in order to supply sufficient oxygen to make the oxygen in a supersaturated state, an insulating layer containing excess oxygen is provided in contact so as to surround the oxide semiconductor.

[0206] Also, since the hydrogen concentration of the insulating layer containing excess oxygen also affects the characteristics of the transistor, it is important . When the hydrogen concentration of the insulating layer containing excess oxygen is 7.2×10​​​20 atoms / cm 3 above In some cases, an increase in the variation of the initial characteristics of the transistor, an increase in the L-length dependence, and further B Since it deteriorates significantly in the BTS stress test, the hydrogen concentration in the insulating layer containing excess oxygen is 7. 2×10 20 atoms / cm 3 less than. That is, the hydrogen concentration in the oxide semiconductor layer is 5×1 0 19 atoms / cm 3 below, and the hydrogen concentration in the insulating layer containing excess oxygen is 7.2×1 0 20 atoms / cm 3 It is preferably less than.

[0207] In an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and purified, and the defect levels in the energy gap caused by oxygen deficiency are reduced by sufficient oxygen supply, the carrier density is 1×1 / cm 0 12 / cm 3 less than, desirably 1×10 11 / cm 3 less than, more desirably 1.45 ×10 10 / cm 3 less than. For example, the off-current at room temperature (25°C) (here, the value per channel width (1 μm)) is 100 zA (1 zA (zeptoampere) is 1×1 0 0 -21 A) or less, desirably 10 zA or less. Also, at 85°C, 100 zA ([[]] 1×10 -19 A) or less, desirably 10 zA (1×10 -20 A) or less. In this way By using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor with extremely excellent off-current characteristics can be obtained.

[0208] Also, a transistor having an i-type (true-type) or substantially i-type oxide semiconductor shows almost no temperature dependence in electrical characteristics such as threshold voltage and on-current. Also the variation in transistor characteristics due to photo-degradation is small.

[0209] Thus, a transistor having an oxide semiconductor that has been purified and i-type (true-type) converted by reducing oxygen deficiency has suppressed variation in electrical characteristics and is electrically stable Therefore, a highly reliable liquid crystal display device having stable electrical characteristics can be provided ).

[0210] Next, a conductive layer serving as a source electrode 206a, a drain electrode 206b, and a wiring 216 (shown as wiring 216_j and wiring 216_j+1 in FIGS. 9 to 12) is formed on the semiconductor layer 205 (see FIGS. 9(C) and 11(C)). The conductive layer used for the source electrode 206a , the drain electrode 206b, and the wiring 216 can be formed by the same materials and methods as those of the gate electrode 202. Also, as the conductive layer used for the source electrode 206a, the drain electrode 2 06b, and the wiring 216, a conductive metal oxide may be used . As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide (abbreviated as ITO), indium zinc oxide, or those obtained by adding silicon oxide to these metal oxide materials can be used . In the present embodiment, a stack of titanium with a film thickness of 100 nm, aluminum with a film thickness of 400 nm, and titanium with a film thickness of 100 nm is formed as the conductive layer by sputtering. Then, by a second

[0211] photolithography process, the source electrode 206a, the drain electrode 206b, and the wiring 400nm of aluminum, and titanium with a film thickness of 100nm are formed. Thereafter, by a second photolithography process, the source electrode 206a, the drain electrode 206b, and the wiring Form the line 216.

[0212] Note that the etching of the conductive layer can be performed in the same manner as the formation of the gate electrode 202. . In the present embodiment, a two-layer of titanium and aluminum is etched under the first etching conditions and then the remaining single-layer titanium film is removed under the second etching conditions. Note that the first etching condition uses an etching gas (BCl3:Cl2 = 750 sccm:150 sccm), sets the bias power to 1500 W, sets the ICP power supply power to 0 W, and sets the pressure to 2.0 Pa. The second etching condition uses an etching gas (BCl3:Cl2 = 700 sccm:1 00 sccm), sets the bias power to 750 W, sets the ICP power supply power to 0 W, and sets the pressure to 2.0 Pa.

[0213] At this time, on the surface of the semiconductor layer 205 exposed by the formation of the source electrode 206a, the drain electrode 206b, and the wiring 216, elements constituting the conductive layer, elements present in the processing chamber, and elements constituting the etching gas or etching solution used for etching may adhere as impurities.

[0214] When impurities adhere, an increase in the off-current of the transistor or deterioration of the electrical characteristics of the transistor are likely to occur. Also, a parasitic channel is likely to occur in the semiconductor layer 205, and electrodes or wirings that should be electrically separated are likely to be electrically connected through the semiconductor layer 205. .

[0215] In addition, depending on the impurities, they may mix in near the surface inside the semiconductor layer 205 (in the bulk), extract oxygen in the semiconductor layer 205, and cause oxygen deficiency on the surface and in the vicinity of the surface of the semiconductor layer 205. It may be formed. For example, chlorine, boron contained in the above-described etching gas, and aluminum, which is a constituent material of the etching chamber, may be one of the factors for reducing the resistance (n-type conversion) of the semiconductor layer 205.

[0216] Therefore, in one aspect of the present invention, after the etching for forming the source electrode 206a, the drain electrode 206b, and the wiring 216 is completed, a cleaning process (impurity removal process) for removing impurities adhering to the surface of the semiconductor layer 205 is performed.

[0217] The impurity removal process can be performed by plasma treatment or treatment with a solution. As the plasma treatment, oxygen plasma treatment, nitrous oxide plasma treatment, or the like can be used. Also, a rare gas (typically argon) may be used as the plasma treatment.

[0218] Also, as the cleaning process with a solution, an alkaline solution such as a TMAH solution, an acidic solution such as dilute hydrofluoric acid, water, or the like can be used. For example, when using dilute hydrofluoric acid, 50 wt% hydrofluoric acid is diluted with water to about 1 / 10 to 1 / 10, preferably 1 / 10 to 1 / 10. That is, dilute hydrofluoric acid diluted to a concentration of 0.5 wt% to 5 × 10 wt%, preferably 5 × 10 wt% to 5 × 10 wt% is desirably used for the cleaning process. By the cleaning process, the above impurities adhering to the surface of the semiconductor layer 205 can be removed. 2 to 1 / 10 5 3 to 1 / 10 5 -4 -2 -4

[0219] In addition, when impurity removal treatment is performed using a dilute hydrofluoric acid solution, the surface of the semiconductor layer 205 can be etched. That is, impurities attached to the surface of the semiconductor layer 205 and impurities mixed in the vicinity of the surface within the semiconductor layer 205 can be removed together with a part of the semiconductor layer 205. As a result, the film thickness of the region of the semiconductor layer 205 that overlaps with the source electrode 206a, the drain electrode 206b, and the wiring 216_j may become larger than the film thickness of the non-overlapping region. For example, when treating an IGZO film with diluted hydrofluoric acid (0.05 wt% hydrofluoric acid), the film thickness decreases by 1 to 3 nm per second, and when treating an IGZO film with diluted hydrofluoric acid (0.0025 wt% hydrofluoric acid), the film thickness decreases by about 0.1 nm per second. By performing impurity removal treatment, at the peak value of the concentration obtained by analysis using SIMS, the chlorine concentration on the semiconductor layer surface can be made 1×10 / cm or less (preferably 5×10 / cm or less, more preferably 1×10 / cm or less). Also, the boron concentration on the semiconductor layer surface can be made 1×10 / cm or less (preferably 5×10 / cm or less, more preferably 1×10 / cm or less). Also, the aluminum concentration on the semiconductor layer surface can be made 1×10 / cm or less (preferably 5×10 / cm or less, more preferably 1×10 / cm or less). 3 5

[0220] 19 3 18 3 18 3 19 3 18 3 18 3 19 3 18 3 ​18 / cm 3 (below) can be done.

[0221] By carrying out impurity removal processing, highly reliable transistors with stable electrical characteristics can be realized. It can be realized.

[0222] Next, an insulating layer is formed on the source electrode 206a, the drain electrode 206b, and the wiring 216_j. Insulating layer 207 is formed (see FIG. 9(D) and FIG. 11(D)). The insulating layer 207 functions as a protective layer. The insulating layer 204 and the underlayer 201 can be formed of the same material and by the same method. In addition, when an oxide semiconductor is used for the semiconductor layer 205, the insulating layer 207 is In the case of a gas containing oxygen, the gas is in a state in which there is a region in the gas that contains more oxygen than the stoichiometric composition (having an oxygen excess region). It is preferable to do so.

[0223] After the insulating layer 207 is formed, oxygen (at least any of oxygen radicals, oxygen atoms, oxygen ions, etc.) is By introducing oxygen into the film, the insulating layer 207 can be kept in an oxygen-excess state. Oxygen may be introduced directly into the insulating layer 207 or through another layer. When oxygen is introduced through other layers, ion implantation, ion doping, and proton implantation are used. Alternatively, a laser ion implantation method or the like may be used. When oxygen is directly introduced into the 07, in addition to the above method, plasma treatment in an oxygen atmosphere is performed. Also, the following can be used.

[0224] By introducing oxygen, the bond between the element constituting the insulating layer 207 and hydrogen or the bond between the element and hydrogen The bonds between the hydroxyl groups are broken and these hydrogen or hydroxyl groups react with oxygen. To generate water, after introducing oxygen, a heat treatment is performed to make it easier to desorb impurities such as hydrogen and hydroxyl groups as water. That is, the impurity concentration in the insulating layer 207 can be further reduced. Therefore, after introducing oxygen into the insulating layer 207 a heat treatment may be performed. Thereafter, oxygen may be further introduced into the insulating layer 207 to make the insulating layer 207 in an oxygen-excess state. Also, the introduction of oxygen into the insulating layer 207 and the heat treatment may be performed alternately a plurality of times. Further, the introduction of oxygen and the heat treatment may be performed simultaneously.

[0225] Before forming the insulating layer 207, it is preferable to perform an oxygen plasma treatment or a nitrous oxide plasma treatment etc. to remove moisture and organic substances adhering to the surface. The insulating layer 207 is preferably formed continuously without being exposed to the atmosphere after performing an oxygen plasma treatment or a nitrous oxide plasma treatment etc.

[0226] In this embodiment, silicon oxide with a film thickness of 200 nm is used as the insulating layer 207 and is formed by sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C. The film formation of the silicon oxide layer by sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. Also, silicon oxide or silicon can be used as the target. For example, when silicon is used as the target and sputtering is performed in an atmosphere containing oxygen, silicon oxide can be formed.

[0227] After forming the insulating layer 207, in a nitrogen atmosphere, a rare gas atmosphere, an oxygen atmosphere, nitrogen and oxygen, or ​​​Alternatively, heat treatment may be performed in an atmosphere of a mixed gas of a noble gas and oxygen. In the present embodiment, heat treatment is performed at 300 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen.

[0228] Next, a resist mask is formed by a third photolithography process, and a part of the insulating layer 207 on the drain electrode 206b is selectively removed to form a contact hole 208. Further, in the cross section D1-D2, a part of the insulating layer 207 and a part of the semiconductor layer 205 are selectively removed to form a groove portion 230. Further, in the cross section J1-J2, a part of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 on the wiring 212_i are selectively removed to form a contact hole 219. Further, in the cross section K1-K2, a part of the insulating layer 207 on the wiring 216_j is selectively removed to form a contact hole 220. Although not shown in the figure, the groove portion 240 is also formed in the same manner as the groove portion 230.

[0229] In the third photolithography process, first, a resist mask 261 is formed on the insulating layer 207 using a multi-tone mask (see FIGS. 9(E) and 11(E)).

[0230] Here, the multi-tone mask will be described with reference to FIG. 13. A multi-tone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposure portion, and an unexposed portion, and is an exposure mask in which the transmitted light has a plurality of intensities. By performing one exposure and development process, it is possible to form a resist mask having regions of a plurality (typically two types) of thicknesses. Therefore, by using a multi-tone mask, it is possible to reduce the number of exposure masks (photomasks).

[0231] As a representative example of a multi-tone mask, there is a grayscale mask 304 as shown in Fig. 13(A1). , and a halftone mask 314 as shown in Fig. 13(B1).

[0232] As shown in Fig. 13(A1), the grayscale mask 304 is composed of a light-transmissive substrate 301, a light-shielding portion 302 formed thereon, and a diffraction grating 303. In the light-shielding portion 302 , the light transmittance is 0%. On the other hand, the diffraction grating 303 controls the light transmittance by setting the interval between light-transmissive portions such as slits, dots, and meshes to be less than or equal to the resolution limit of the light used for exposure. Note that the diffraction grating 303 can be either a periodic slit, dot, mesh, or an aperiodic slit, dot, or mesh. As the light-transmissive substrate 301, a light-transmissive substrate such as quartz can be used. The light-shielding portion 302 and the diffraction grating 303 can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide.

[0233] When the grayscale mask 304 is irradiated with exposure light, as shown in Fig. 13(A2), in the light-shielding portion 302, the light transmittance is 0%, and in the region where neither the light-shielding portion 302 nor the diffraction grating 303 is provided, the light transmittance is 100%. Also, the light transmittance can be adjusted in the range of 10 to 70% by the diffraction grating 303. The adjustment of the light transmittance in the diffraction grating 303 is possible by adjusting the interval and pitch of the slits, dots, or meshes of the diffraction grating.

[0234] As shown in Fig. 13(B1), the halftone mask 314 is composed of a light-transmissive substrate 311 and its

[0235] As shown in Fig. 13(B1), the halftone mask 314 is composed of a light-transmissive substrate 311 and its ​​​​​​​It is composed of a semi-transmissive portion 312 and a light-shielding portion 313 formed thereon. The semi-transmissive portion 312 is M oSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 313 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be done.

[0236] When the exposure light is irradiated on the halftone mask 314, as shown in Fig. 13(B2), in the light-shielding portion 313, the light transmittance is 0%, and in the region where neither the light-shielding portion 313 nor the semi-transmissive portion 312 is provided, the light transmittance is 100%. Also, the light transmittance can be adjusted in the range of 10 to 70% by the semi-transmissive portion 312. The light transmittance in the semi-transmissive portion 312 can be adjusted by the material used for the semi-transmissive portion 3 12. It can be adjusted.

[0237] The resist mask 261 formed using a multi-tone mask is a resist mask composed of a plurality of regions with different thicknesses. Here, it has two regions (a thick region and a thin region). In the resist mask 261, the thick region is sometimes called the convex portion of the resist mask 261, and the thin region is sometimes called the concave portion of the resist mask 261. In the resist mask 261, the concave portion is located at a position overlapping with the region where the contact hole 208, the contact hole 220, and the groove portion 230 are formed. Also, the resist mask 261 is not provided on the region where the contact hole 219

[0238] is formed. Next, the first etching process is performed. By the first etching process, using the resist mask 26 1 as a mask, a part of the insulating layer 207 on the wiring 212_i in the cross section J1-J2,

[0239] Etch a part of the semiconductor layer 205 and a part of the gate insulating layer 204 to form a contact hole 219. On the side surface of the contact hole 219, the side surfaces of the insulating layer 207, the semiconductor layer 2 05, and the gate insulating layer 204 are exposed, and the wiring 212_i is exposed on the bottom surface ( see Fig. 12(A)).

[0240] The etching of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 may be dry etching , wet etching, or both. As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) can be used.

[0241] As dry etching, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Note that since the cross-sections A1-A2, D1- D2, and K1-K2 are covered with the resist mask 261, they are not etched (see Fig. 10(A) and Fig. 12(A)).

[0242] Next, reduce the resist mask 261 by ashing with oxygen plasma, etc. to form a resist mask 26 2. At this time, the resist in the thin region (concave portion ) of the resist mask 261 is removed, and the insulating layer 207 is exposed (see Fig. 10(B) and Fig. 12(B)).

[0243] Next, perform a second etching process. By the second etching process, the resist mask 26 Using 2 as a mask, a part of the insulating layer 20 that overlaps with the drain electrode 206b in the cross-section A1 - A2 is etched. A part of 7 is etched to form the contact hole 208. Also, in the cross-section D1 - D2, a part of the insulating layer 207 and a part of the semiconductor layer 205 are etched to form the groove portion 230. Also, a part of the insulating layer 207 that overlaps with the wiring 216_j in the cross-section K1 - K2 is etched to form the contact hole 220. At this time, in the cross-section J1 - J2, a part of the insulating layer 207 not covered by the resist mask 262 and a part of the semiconductor layer 205 are also etched (see Fig. 12(C)). On the side surface of the contact hole 208, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the drain electrode 206b is exposed. On the side surface of the groove portion 230, the side surfaces of the insulating layer 207 and the semiconductor layer 205 are exposed, and the gate insulating layer 204 is exposed on the bottom surface. On the side surface of the contact hole 220, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the wiring 216_j is exposed.

[0244] The second etching process may be either dry etching or wet etching, or both may be used. At this time, it is important to ensure that the wiring 212_i is not exposed on the bottom surface of the groove portion 230. If the wiring 212_i is exposed on the bottom surface of the groove portion 230, a leakage current is likely to occur between the semiconductor layer 205 exposed on the side surface of the groove portion 230 and the wiring 212_i, which may cause a decrease in display quality and a reduction in reliability. Especially in the groove portion 230 within the display area, the decrease in display quality due to the leakage current becomes significant. By overlapping the groove portion 230 and the wiring 212_i with the gate insulating layer 204 in between, the generation of parasitic channels can be prevented, and at the same time, between the semiconductor layer 205 and the wiring 21 On the side surface of the contact hole 208, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the drain electrode 206b is exposed. On the side surface of the groove portion 230, the side surfaces of the insulating layer 207 and the semiconductor layer 205 are exposed, and the gate insulating layer 204 is exposed on the bottom surface. On the side surface of the contact hole 220, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the wiring 216_j is exposed.

[0245] The second etching process may be either dry etching or wet etching, or both may be used. At this time, it is important to ensure that the wiring 212_i is not exposed on the bottom surface of the groove portion 230. If the wiring 212_i is exposed on the bottom surface of the groove portion 230, a leakage current is likely to occur between the semiconductor layer 205 exposed on the side surface of the groove portion 230 and the wiring 212_i, which may cause a decrease in display quality and a reduction in reliability. Especially in the groove portion 230 within the display area, the decrease in display quality due to the leakage current becomes significant. By overlapping the groove portion 230 and the wiring 212_i with the gate insulating layer 204 in between, the generation of parasitic channels can be prevented, and at the same time, between the semiconductor layer 205 and the wiring 21 On the side surface of the contact hole 208, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the drain electrode 206b is exposed. On the side surface of the groove portion 230, the side surfaces of the insulating layer 207 and the semiconductor layer 205 are exposed, and the gate insulating layer 204 is exposed on the bottom surface. On the side surface of the contact hole 220, the side surface of the insulating layer 207 is exposed, and on the bottom surface, the wiring 216_j is exposed. and a reduction in reliability. Especially in the groove portion 230 within the display area, the decrease in display quality due to the leakage current becomes significant. By overlapping the groove portion 230 and the wiring 212_i with the gate insulating layer 204 in between, the generation of parasitic channels can be prevented, and at the same time, between the semiconductor layer 205 and the wiring 21 2_i can be prevented. It is possible to prevent the generation of leakage current between 2_i and improve the display quality of the display device. It can be achieved.

[0246] Generally, when forming openings with different depths in parts having the same laminated structure, such as the contact hole 219 and the groove 230, for example, the formation of the openings is carried out in multiple photolithography processes. However, according to the manufacturing process shown in this embodiment, it is possible to form openings with different depths in parts having the same laminated structure by a single photolithography process. That is, with fewer photolithography processes, a display device can be manufactured at low cost and with high productivity. Moreover, according to the manufacturing process shown in this embodiment, no photoresist is directly formed in the channel formation region of the semiconductor layer 205. In particular, when an oxide semiconductor is used as the semiconductor layer 205, since the channel formation region of the semiconductor layer 205 is protected by the insulating layer 207, moisture does not adhere to the channel formation region of the semiconductor layer 205 even in the subsequent photoresist stripping and cleaning process. Therefore, the variation in the characteristics of the transistor 111 is reduced and the reliability is improved.

[0247] Next, on the insulating layer 207, a conductive layer having translucency (also referred to as a transparent conductive layer) that becomes the pixel electrode 210, the electrode 221, and the electrode 222 is formed by using a sputtering method, a vacuum evaporation method, or the like to have a thickness of 30 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. As the conductive layer having translucency, indium oxide containing tungsten oxide, tungsten oxide is improved.

[0248] Next, on the insulating layer 207, a conductive layer having translucency (also referred to as a transparent conductive layer) that becomes the pixel electrode 210, the electrode 221, and the electrode 222 is formed by using a sputtering method, a vacuum evaporation method, or the like to have a thickness of 30 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. 0, the electrode 221, and the electrode 222 is formed by using a sputtering method, a vacuum evaporation method, or the like to have a thickness of 30 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. is formed.

[0249] Indium zinc oxide containing Si, indium oxide containing titanium oxide, titanium oxide Containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc Oxide, conductive materials having translucency such as indium tin oxide added with silicon oxide can be used. Also, a material composed of one to ten graphene sheets may be used.

[0250] In addition, in this embodiment, an example of a method for manufacturing a pixel portion of a transmissive liquid crystal display device has been illustrated. However, the present invention is not limited to transmissive types, and can also be applied to pixel portions of reflective and transflective liquid crystal display devices. When obtaining a pixel portion of a reflective liquid crystal display device, a conductive layer having a high light reflectance (also referred to as a reflective conductive layer), for example, a metal having a high reflectance of visible light such as aluminum, titanium, silver, rhodium, nickel, or an alloy containing at least one of these metals, or a laminate thereof may be used. When obtaining a pixel portion of a transflective liquid crystal display device, one pixel electrode is formed of a transparent conductive layer and a reflective conductive layer, and a transmissive portion and a reflective portion are provided.

[0251] In this embodiment, an ITO layer having a thickness of 80 nm is formed as a conductive layer having translucency, and a resist mask is formed by a fourth photolithography process, and the conductive layer having translucency is selectively etched to form a pixel electrode 210, an electrode 221, and an electrode 222 (see FIGS. 10(D) and 12(D)).

[0252] The pixel electrode 210 is electrically connected to the drain electrode 206b through the contact hole 208. Also, the electrode 221 is electrically connected to the wiring 212_i through the contact hole 219. ​​​​​​​​​​​is connected thereto. Further, the electrode 222 is electrically connected to the wiring 216_j through the contact hole 220. is electrically connected.

[0253] Further, in the contact holes 219 and 220 formed in the terminal portions 103 and 104, it is important not to expose the wirings 212_i and 216_j together and to cover them with an oxide conductive material such as ITO. Since the wirings 212_i and 216_j are metal layers, if the exposed surfaces of the wirings 212_i and 216_j are left as they are, the exposed surfaces will be oxidized and the contact resistance with an FPC or the like will increase. The increase in the contact resistance causes a delay in the signal input from the outside and a rounding of the waveform, and the signal from the outside is not accurately transmitted, resulting in a decrease in the reliability of the semiconductor device. By covering the exposed surfaces of the wirings 212_i and 216_j with a conductive oxide material such as ITO, an increase in the contact resistance can be prevented and the reliability of the semiconductor device can be improved. without exposing the wirings 212_i and 216_j, but it is important to cover them with an oxide conductive material such as ITO. Since the wirings 212_i and 216_j are metal layers, if the exposed surfaces of the wirings 212_i and 216_j are left as they are, the exposed surfaces will be oxidized and the contact resistance with an FPC or the like will increase. The increase in the contact resistance causes a delay in the signal input from the outside and a rounding of the waveform, and the signal from the outside is not accurately transmitted, resulting in a decrease in the reliability of the semiconductor device. By covering the exposed surfaces of the wirings 212_i and 216_j with a conductive oxide material such as ITO, an increase in the contact resistance can be prevented and the reliability of the semiconductor device can be improved.

[0254] According to the present embodiment, a semiconductor device can be manufactured with fewer photolithography processes than in the prior art. Therefore, a liquid crystal display device with low cost and high productivity can be manufactured. Thus, a liquid crystal display device with low cost and high productivity can be manufactured.

[0255] In the present embodiment, a transistor having a bottom gate structure has been described as an example, but it can also be applied to a transistor having a top gate structure.

[0256] The present embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0257] (Embodiment 2) ​​​One form of the liquid crystal display device using the semiconductor device exemplified in the above Embodiment 1 is shown in FIG. 14.

[0258] FIG. 14(A) is a plan view of a panel in which the transistor 4010 and the liquid crystal element 4013 are sealed with a sealing material 4005 between the first substrate 400 1 and the second substrate 4006, and FIG. 14(B) corresponds to a cross-sectional view taken along M1-M2 in FIG. 14(A). Further, a groove portion 4040 is provided on the first substrate 4001. A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and the second substrate 4006 is provided on the pixel portion 4002. Therefore, the pixel portion 4

[0259] 002 is sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, an input terminal 4020 is provided in a region outside the region surrounded by the sealing material 4005 on the first substrate 4001, and FPC (Flexible printed circ uit) 4018a and FPC4018b are connected. FPC4018a is electrically connected to a signal line driving circuit 4003 formed on a separate substrate, and FPC4018b is electrically connected to a scanning line driving circuit 4004 formed on a separate substrate. Various signals and potentials applied to the pixel

[0260] portion 4002 are supplied from the signal line driving circuit 4003 and the scanning line driving circuit 4004 via FPC4018a and FPC4018 b. It should be noted that the connection method of the driving circuit formed on a separate substrate is not particularly limited. The FPC4018a is electrically connected to a signal line driving circuit 4003 formed on a different substrate, and the FPC4018b is electrically connected to a scanning line driving circuit 4004 formed on a different substrate. The various signals and potentials applied to the pixel portion 4002 are supplied from the signal line driving circuit 4003 and the scanning line driving circuit 4004 via the FPC4018a and FPC4018 b.

[0261] The connection method of the driving circuit formed on a different substrate is not particularly limited. , methods such as COG (Chip On Glass), wire bonding, and TCP (Tape Carrier Package) can be used.

[0262] Also, although not shown, the signal line drive circuit 4003 or the scan line drive circuit 4004 may be formed on the first substrate 4001 using the transistors disclosed in this specification.

[0263] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) can be used. In addition, display media such as electronic ink, whose contrast changes due to an electrical action, can also be applied.

[0264] The display device shown in FIG. 14 has electrodes 4016 and wiring 4015, and the electrodes 4016 and the wiring 4015 are electrically connected via an anisotropic conductive layer 4019 to the terminals of the FPC 4018a.

[0265] The electrode 4016 is formed from the same conductive layer as the first electrode 4030, and the wiring 4015 is formed from the same conductive layer as the source electrode and the drain electrode of the transistor 4010.

[0266] In this embodiment, as the transistor 4010, the transistor shown in Embodiment 1 can be applied. The transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element and constitutes a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

[0267] FIG. 14 shows an example of a display device using a liquid crystal element as the display element. In FIG. 14 ​The liquid crystal element 4013, which is a display element, includes a first electrode 4030, a second electrode 4031, and and a liquid crystal layer 4008. Note that the liquid crystal layer 4008 is sandwiched between two layers functioning as alignment films. An insulating layer 4032 and an insulating layer 4033 are provided. The second electrode 4032 is also provided on the groove portion 4040. The second electrode 4031 is 4006 side, and the first electrode 4030 and the second electrode 4031 are connected via a liquid crystal layer 4008. The structure is such that the electrodes are laminated.

[0268] The spacer 4035 is a columnar spacer formed of an insulating layer on the second substrate 4006. It is a sensor provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may also be used.

[0269] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0270] In addition, liquid crystals exhibiting a blue phase, which does not require an alignment film, may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the chirality, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Since the film is short and optically isotropic, no alignment treatment is required, and the viewing angle dependency is small. Since it is not necessary to provide a film, rubbing treatment is also unnecessary, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0271] In addition, the resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 1 1 Ω·cm or more, more preferably 1×10 12 Ω·cm or more. Note that the resistivity value in this specification is the value measured at 20°C.

[0272] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. When a transistor using an oxide semiconductor that is i-type (intrinsic) or substantially i-type is used for the semiconductor layer in which a channel is formed, which is disclosed in the above embodiment, the size (capacitance value) of the holding capacitance can be made 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel. The transistor using the oxide semiconductor disclosed in the above embodiment for the semiconductor layer in which a channel is formed can lower the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the input interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption is achieved. Also, when the semiconductor layer in which a channel is formed is i-type (intrinsic) or

[0273] The transistor using the oxide semiconductor disclosed in the above embodiment for the semiconductor layer in which a channel is formed can lower the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the input interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption is achieved. Also, when the semiconductor layer in which a channel is formed is i-type (intrinsic) or substantially i-type, the transistor can reduce the leakage current, and the holding time of the electrical signal can be extended. A transistor using a substantially i-type oxide semiconductor can hold the potential applied to the liquid crystal element without providing a holding capacitance. It enables the retention of the potential applied to the liquid crystal element.

[0274] In addition, a transistor using an oxide semiconductor for the semiconductor layer in which a channel is formed can obtain a relatively high field-effect mobility, enabling high-speed driving of the liquid crystal display device. Therefore, by using the above transistor in the pixel portion of the liquid crystal display device, the vertical synchronization frequency can be increased to 1.5 times the normal value preferably 2 times or more, which facilitates the application of a driving technique called double-speed driving that reduces problems such as afterimage phenomena and video blurring during video display. Thus, a liquid crystal display device with good display quality can be provided. Moreover, since the above transistor can also be fabricated separately for the driving circuit portion or the pixel portion on the same substrate, the number of components of the liquid crystal display device can be reduced. Therefore, the productivity of the liquid crystal display device can be improved.

[0275]

[0276] The liquid crystal display device can use TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc.

[0277] ​​​​​​​​​​​In addition, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. As the vertical alignment mode, several can be mentioned. For example, the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, the ASV (Advanced Super-View) mode, etc. can be used. In addition, a method called multi-domainization or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. In addition, in the liquid crystal display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, as the light source, a backlight, a side light, etc. may be used. In addition, it is also possible to use a plurality of light emitting diodes (LEDs) as the backlight and perform a time division display method (field sequential drive method). By applying the field sequential drive method, color display can be performed without using a color filter. In addition, as the display method in the pixel portion, a progressive method, an interlace method, etc. can be used.

[0278]

[0279]

[0280] ​ It is possible. Also, as the color elements controlled by pixels when performing color display, it is not limited to the three colors of RGB (where R represents red, G represents green, and B represents blue). For example, RGBW (where W represents white) , or there are those in which one or more of yellow, cyan, magenta, etc. are added to RGB. Note that the size of the display area may be different for each dot of the color element. However, the present invention is not limited to a color -display liquid crystal display device, and can also be applied to a monochrome display liquid crystal display device.

[0281] In FIG. 14, as the first substrate 4001 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmittance such as FRP (Fiberglass-Reinforced Plastics) plate, PVF (polyvinyl fluoride) film, a polyester film or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0282] A transmissive liquid crystal display device performs display by transmitting light from a light source or a display element. Therefore, all thin films such as the substrate, insulating layer, and conductive layer provided in the pixel portion through which light passes should preferably be transparent to light in the wavelength range of visible light.

[0283] In the first electrode and the second electrode (also referred to as a pixel electrode, a common electrode, a counter electrode, etc.) to which a voltage is applied to the display element, the light transmittance and reflectivity can be selected according to the direction of the light to be extracted, the location where the electrode is provided, and the pattern structure of the electrode. ​​​​​​

[0284] The first electrode 4030 and the second electrode 4031 can be made of a conductive material with light transmittance, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Also, a material composed of one to ten graphene sheets may be used. Moreover, either one of the first electrode 4030 and the second electrode 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V),

[0285] niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (N i), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) or their alloys, or their nitrides. It can also be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or

[0286] its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives can be mentioned.

[0287] In addition, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit. Preferably, the protection circuit is configured using a non-linear element.

[0288] By applying the transistor exemplified in the above embodiment as described above, a highly reliable liquid crystal display device can be provided. Note that the transistor exemplified in the above embodiment is not limited to a semiconductor device having a display function, but can also be applied to semiconductor integrated circuits such as power devices and LSIs mounted on a power supply circuit, and semiconductor devices having an image sensor function for reading information of an object. It can be applied to semiconductor devices having various functions such as a semiconductor integrated circuit such as a power device and an LSI mounted on a power supply circuit, and a semiconductor device having an image sensor function for reading information of an object. It is possible to apply it to semiconductor devices having various functions.

[0289] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0290] (Embodiment 3) In this embodiment, as an example of a semiconductor device with reduced number of photomasks and number of photolithography processes, a semiconductor device that can be used for an active matrix type EL display device and an example of a manufacturing method thereof will be described with reference to FIGS. 15 to 23. First, with reference to FIG. 20(A), an example of the configuration of a semiconductor device 150 that can be used for an EL display device will be described. The semiconductor device 150 has a pixel region 102 on a substrate 101, a terminal portion 103 having m (m is an integer of 1 or more) terminals 105_1 to 105_m and a terminal 107, and a terminal portion 104 having n (n is an integer of 1 or more) terminals 106_1 to 106_n and a terminal 108. Further, the semiconductor device 150 has m

[0291] wires 212_1 to 212_m electrically connected to the terminal portion 103, a wire 224, and n wires electrically connected to the terminal portion 104. wires 212_1 to 212_m and wires 224, and n wires electrically connected to the terminal portion 104. wires electrically connected to the terminal portion 103, and n wires 212_1 to 212_m and a wire 224, and n It has wirings 216_1 to 216_n and a wiring 217. Also, the pixel region 102 has a plurality of pixels 160 arranged in a matrix of m (rows) × n (columns) . The pixel 160 at the i-th row and j-th column (i is an integer from 1 to m, j is an integer from 1 to n ) is electrically connected to the wiring 212_i (the i-th wiring 212) and the wiring 216_j (the j-th wiring 216) respectively. Also, each pixel is electrically connected to a wiring 224 that functions as a wiring to which one of the anode or cathode potentials is supplied, and a wiring 217 that functions as a wiring to which the other of the anode or cathode potentials is supplied. The wiring 224 is electrically connected to the terminal 107, and the wiring 217 is electrically connected to the terminal 108. Also, the wiring 212_i is electrically connected to the terminal 105_i, and the wiring 216_j is electrically connected to the terminal 106_j . The terminal portion 103 and the terminal portion 104 are external input terminals, and are connected to an external control circuit and a PC or the like using an F . Signals supplied from an external control circuit are input to the semiconductor device 150 via the terminal portion 103 and the terminal portion 104. In FIG. 20(A), the terminal portion 103 is formed on the left and right outer sides of the pixel region 102, showing a configuration in which signals are input from two locations

[0292] . Also, the terminal portion 104 is formed on the upper and lower outer sides of the pixel region 102, showing a configuration in which signals are input from two locations . By inputting signals from two locations, the signal supply capacity is increased, so that the high-speed operation of the semiconductor device 150 becomes easy. Also, the influence of signal delay due to an increase in wiring resistance accompanying the enlargement and high definition of the semiconductor device 150 can be reduced. Also, since the semiconductor device 150 can be made redundant, the reliability of the semiconductor device 150 is improved. In FIG. 20(B), the terminal portion 103 is formed on the left and right outer sides of the pixel region 102, showing a configuration in which signals are input from two locations . Also, the terminal portion 104 is formed on the upper and lower outer sides of the pixel region 102, showing a configuration in which signals are input from two locations . By inputting signals from two locations, the signal supply capacity is increased, so that the high-speed operation of the semiconductor device 150 becomes easy. Also, the influence of signal delay due to an increase in wiring resistance accompanying the enlargement and high definition of the semiconductor device 150 can be reduced. Also, since the semiconductor device 150 can be made redundant, the reliability of the semiconductor device 150 is improved. It can be raised. In FIG. 20(A), the terminal portions 103 and 104 are each provided in two locations, but they may each be provided in one location. Although it is configured to provide two locations each, it may be configured to provide one location each.

[0293] FIG. 20(B) shows the circuit configuration of the pixel 160. The pixel 160 has a transistor 11 1, a transistor 121, an EL element 116, and a capacitor element 113. The gate electrode of the transistor 111 is electrically connected to the wiring 212_i, and one of the source electrode or drain electrode of the transistor 111 is electrically connected to the wiring 216_j. Also One of the source electrode or drain electrode of the transistor 111 is electrically connected to the node 115 where the gate electrode of the transistor 121 and one electrode of the capacitor element 113 are electrically connected. Also One of the source electrode or drain electrode of the transistor 121 is electrically connected to one electrode of the EL element 116, and the other of the source electrode or drain electrode is electrically connected to the other electrode of the capacitor element 113 and the wiring 217. Also, the other electrode of the EL element 1 16 is electrically connected to the wiring 224. The potential difference between the wiring 217 and the wiring 224 is set to be larger than the sum of the threshold voltage of the transistor 121 and the threshold voltage of the EL element 116. The transistor 111 has a function of selecting whether to input the image signal supplied from the wiring 216_j to the gate electrode of the transistor 121. When a signal that turns on the transistor 111 is supplied to the wiring 212_i, the image signal of the wiring 216 _j is supplied to the node 115 via the transistor 111. The transistor 111 has a function of selecting whether to input the image signal supplied from the wiring 216_j to the gate electrode of the transistor 121. When a signal that turns on the transistor 111 is supplied to the wiring 212_i, the image signal of the wiring 216 _j is supplied to the node 115 via the transistor 111. The potential difference between the wiring 217 and the wiring 224 is set to be larger than the sum of the threshold voltage of the transistor 121 and the threshold voltage of the EL element 116. The potential difference between the wiring 217 and the wiring 224 is set to be larger than the sum of the threshold voltage of the transistor 121 and the threshold voltage of the EL element 116.

[0294] The transistor 111 has a function of selecting whether to input the image signal supplied from the wiring 216_j to the gate electrode of the transistor 121. When a signal that turns on the transistor 111 is supplied to the wiring 212_i, the image signal of the wiring 216 _j is supplied to the node 115 via the transistor 111. When a signal that turns on the transistor 111 is supplied to the wiring 212_i, the image signal of the wiring 216 _j is supplied to the node 115 via the transistor 111.

[0295] The transistor 121 supplies a current corresponding to the potential (image signal) supplied to the node 115 as E The capacitor 113 has a function of supplying a current to the L element 116. The transistor 121 supplies a current corresponding to an image signal to the EL element. It functions as a current source for supplying current to 116.

[0296] The semiconductor layer in which the channels of the transistors 111 and 121 are formed is A crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used. Examples of the material include silicon, germanium, silicon germanium, and silicon carbide. Examples of the display device described in this embodiment include gallium arsenide and gallium arsenide. Since the device has a structure in which the semiconductor layer remains in the pixel region, the display device using the semiconductor is When used in an emission type display device, the semiconductor layer should be made as thin as possible to reduce visible light It is preferable to increase the transmittance of the

[0297] In addition, in the semiconductor layer in which the channels of the transistors 111 and 121 are formed, It is preferable to use the oxide semiconductor described in the above embodiment. The energy gap is large at 3.0 eV or more, and the transmittance of visible light is high. In transistors obtained by processing semiconductors under appropriate conditions, the off-state current Under temperature conditions (e.g., 25°C), 100zA (1×10 -19 A) The following or is 10zA(1×10 -20 A) or less, even 1zA (1×10 -21 A) The following: Therefore, the gate voltage of the transistor 121 can be reduced without providing the capacitor 113. The potential applied to the pole can be held. Further, the power consumption of the semiconductor device can be reduced.

[0298] Also, in the present embodiment, the transistor 111 and the transistor 121 are both described as n-channel type transistors, but either one or both of them may be p-channel type transistors.

[0299] The capacitor element 113 has a function of holding the image signal supplied to the gate electrode of the transistor 121. The capacitor element 113 does not necessarily have to be provided, but it can suppress the fluctuation of the potential applied to the gate electrode of the transistor 121 due to the current (off-current) flowing between the source and the drain when the transistor 111 is in the off state.

[0300] The EL element 116 has a structure in which an EL layer is sandwiched between one electrode serving as an anode and the other electrode serving as a cathode, and the luminance is controlled according to the amount of current flowing through the EL layer. That is, the luminance of the EL element 116 is controlled according to the amount of current flowing between the source and the drain of the transistor 121.

[0301] Next, a configuration example of the pixel 160 shown in FIG. 20 will be described with reference to FIGS. 15 to 18. FIGS. 15 and 16 are top views showing the planar configuration of the pixel 160. FIG. 15 is a top view of a state in which the pixel electrode 210 is formed on the uppermost layer, and FIG. 16 is a top view of a state in which the partition layer 218 and the EL layer 271 are further formed. For ease of viewing the drawings, some components are omitted in FIGS. 15 and 16. For example, in FIG. 16, the description of the counter electrode 226 formed on the EL layer 271 is omitted.

[0302] FIGS. 17 and 18 are cross-sectional views showing the stacked structure of pixel 160. FIG. 17(A) corresponds to the cross-section along the dashed line P1-P2 in FIGS. 15 and 16, and FIG. 17(B) corresponds to the cross-section along the dashed line Q1-Q2 in FIGS. 15 and 16. FIG. 18 corresponds to the cross-section along the dashed line R1-R2 in FIGS. 15 and 16.

[0303] In addition, when the parasitic capacitance generated between the drain electrode 206b electrically connected to the node 115 (see FIG. 20(B)) and the gate electrode 202 is large, the node 115 is likely to be affected by the potential fluctuation of the wiring 212_i. As a result, when the transistor 111 changes from the on state to the off state, the potential supplied to the node 115 cannot be accurately held, which becomes a factor for degrading the display quality. As described in the above embodiment, by forming the source electrode 206a in a U shape to surround the drain electrode 206b, it is possible to reduce the parasitic capacitance generated between the drain electrode 206b and the gate electrode 202 while ensuring a sufficient channel width. Therefore, the display quality of the EL display device can be improved.

[0304] Also, in the semiconductor device described in this embodiment, since the photolithography process for forming the island-shaped semiconductor layer is not performed for process simplification, the semiconductor layer 205 remains in all of the pixel regions. As a result, similar to the above embodiment, there is a possibility of generating parasitic transistors in the semiconductor device described in this embodiment.

[0305] In the semiconductor device described in this embodiment, the wiring 212_i functions as a gate electrode, and the wiring ​​​​​The line 216_j functions as one of the source electrode or the drain electrode, and there is a risk that a first parasitic transistor may occur in which the wiring 217 functions as the other of the source electrode or the drain electrode.

[0306] Note that since the semiconductor device described in this embodiment does not have the wiring 203, the second parasitic transistor described in the above embodiment does not occur. However, the pixel electrode 210 functions as a gate electrode, the insulating layer 207 functions as a gate insulating layer, the wiring 216_j functions as one of the source electrode or the drain electrode, and there is a risk that a third parasitic transistor may occur in which the wiring 217 functions as the other of the source electrode or the drain electrode. In particular, if the pixel electrode 210 is brought closer to the wiring 216_j or the wiring 217 for reasons such as increasing the aperture ratio of the pixel, the influence of the third parasitic transistor becomes stronger. Also, when the potential difference between the wiring 217 and the wiring 216_j+1 of the adjacent pixel increases, a parasitic channel may be generated in the semiconductor layer 205 between the two wirings due to the electric field generated between the two wirings.

[0307] When a potential for turning on the transistor 111 is supplied to the wiring 212_i, the first parasitic transistor also becomes in an on state, and the wiring 216_j and the wiring 217 are electrically connected. When the wiring 216_j and the wiring 217 are electrically connected by the first parasitic transistor, it becomes difficult to supply an accurate

[0308] image signal to the node 115. When the wiring 216_j and the wiring 217 are electrically connected by the first parasitic transistor, it becomes difficult to supply an accurate image signal to the node 115.

[0309] Also, when the third parasitic transistor functions as an n-type transistor, the potential of the wiring 216_j becomes lower than the potential supplied to or held by the pixel electrode 21 0, and ​​​​When the absolute value of the potential difference becomes greater than the threshold value of the third parasitic transistor, a channel is formed in the semiconductor layer 205 located below the pixel electrode 21 and the third parasitic transistor turns on .

[0310] When the third parasitic transistor turns on, the wiring 216_j and the wiring 217 are electrically connected . When the wiring 216_j and the wiring 217 are electrically connected by the third parasitic transistor , it becomes difficult to supply an accurate image signal to the node 115. Also, due to reasons such as increasing the aperture ratio of the pixel , when the pixel electrode 210 is brought closer to the wiring 216_j or the wiring 217 , the influence of the third parasitic transistor becomes stronger

[0311] . Also, when a parasitic channel is generated between the wiring 217 and the wiring 216_j+1 of an adjacent pixel , the wiring 217 and the wiring 216_j+1 are electrically connected, and it becomes difficult to supply an accurate image signal to the node 115 of each of the pixels .

[0312] . Therefore, a groove portion 230 from which the semiconductor layer 205 is removed is provided in the pixel 160, and a configuration is adopted in which the above-described parasitic transistor does not occur . By providing the groove portion 230 so as to cross both end portions in the line width direction of the wiring 212_i located between the wiring 216_j and the wiring 217 , generation of the first parasitic transistor and the parasitic channel can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212 _i .

[0313] . Also, the groove portion 230 is provided in at least one of the space between the wiring 216_j and the pixel electrode 210 or the space between the wiring 217 and the pixel electrode 210 , and the wiring 216_j or the wiring 217 extends It is formed along the direction beyond the end portions 231 and 232 of the pixel electrode 210. By this way, generation of the third parasitic transistor can be prevented. Note that the groove portion 230 provided along the direction in which the wiring 216_j or the wiring 217 extends does not need to be provided exactly parallel to the wiring 216_j or the wiring 217, and may have a bent portion or a curved portion. Also, by providing the groove portion 230 beyond the end portion of the pixel between the wiring 217 and the wiring 216_j + 1 of the adjacent pixel, generation of a parasitic channel between the wiring 217 and the wiring 216_j + 1 can be prevented. Moreover, although there is no particular limitation on the size of the groove portion 230 from which the semiconductor layer 205 is removed, in order to surely prevent generation of parasitic transistors and parasitic channels, the width of the portion from which the semiconductor layer in the groove portion 230 is removed in the direction orthogonal to the direction in which the wiring 216_j or the wiring 217 extends is preferably 1 μm or more, and more preferably 2 μm or more.

[0314] The cross-section P1 - P2 shown in FIG. 17(A) shows the stacked structure of the transistor 111, the transistor 121, and the capacitor element 113. The transistor 111 and the transistor 121 are transistors having a bottom gate structure called a channel etching type. The cross-section Q1 - Q2 shown in FIG. 17(B) shows the stacked structure from the wiring 216_j to the wiring 216_j + 1 including the pixel electrode 210 and the groove portion 230. Also, the cross-section R1 - R2 shown in FIG. 18 shows the stacked structure at the intersection of the wiring 212_i, the wiring 217, and the wiring 216_j + 1.

[0315]

[0316] ​​​​​​​​​​​​​​

[0317] In the cross-section P1-P2 shown in FIG. 17(A), an underlayer 201 is formed on a substrate 200, and a gate electrode 202, a gate electrode 243, and a capacitor electrode 215 are formed on the underlayer 201. Also, a gate insulating layer 204 and a semiconductor layer 205 are formed on the gate electrode 202. Also, a source electrode 206a and a drain electrode 206b are formed on the semiconductor layer 205. Also, an insulating layer 207 is formed in contact with the semiconductor layer 205 and on the source electrode 206a, the drain electrode 206b, the source electrode 236a, and the drain electrode 236b. A pixel electrode 210 is formed on the insulating layer 207 and is electrically connected to the source electrode 236a of the transistor 121 through a contact hole 2 08 formed in the insulating layer 207.

[0318] Also, a contact hole 209 is formed by removing a part of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204, and a wiring 213 is formed to overlap with the contact hole 209. The drain electrode 206b of the transistor 111 and the gate electrode 243 of the transistor 121 are electrically connected by the wiring 213. Although not shown in FIG. 17(A), a contact hole 214 is formed by removing another part of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204, and a wiring 22 3 formed to overlap with the contact hole 214 electrically connects the capacitor electrode 215 and a wiring 217. The wiring 213 and the wiring 223 are formed of the same layer as the pixel electrode 210. The contact hole 208, the contact hole 209, the contact hole 214, and the groove 230 are formed in the same process.

[0319] ​Also, although not shown in FIG. 17(A), the drain electrode 236b of the transistor 121 is electrically connected to the wiring 217. In this embodiment, an example is shown where a part of the wiring 217 functions as the drain electrode 236b (see FIG. 15).

[0320] Also, a partition layer 218 for separating the EL layer 271 for each pixel is formed on the insulating layer 207. Further, the EL layer 271 is formed on the pixel electrode 210 and the partition layer 218, and the counter electrode 226 is formed on the partition layer 218 and the EL layer 271. The portion where the pixel electrode 210, the EL layer 271, and the counter electrode 226 are superimposed functions as the

[0321] EL element 116. The portion where the capacitive electrode 215 and the drain electrode 206b overlap with the gate insulating layer 204 and the semiconductor layer 205 interposed there between functions as the capacitive element 113. The gate insulating layer 204 and the semiconductor layer 205 function as a dielectric layer. By forming the dielectric layer formed between the capacitive electrode 215 and the drain electrode 206b as a multilayer structure, even if a pinhole occurs in one dielectric layer, the

[0322] pinhole is covered by another dielectric layer, so that the capacitive element 113 can function normally. Also, since the relative permittivity of the oxide semiconductor is as large as 14 to 16, when an oxide semiconductor is used for the semiconductor The wiring 217 is formed, and the semiconductor layer 205, the wiring 216_j, the wiring 216_j+1, and an insulating layer 207 is formed on the wiring 217. Further, a pixel electrode 210 is formed on the insulating layer 207.

[0323] A groove portion 230 is formed between the wiring 216_j and the pixel electrode 210, where a part of the semiconductor layer 205 and the insulating layer 207 is removed. Further, a groove portion 230 is formed between the wiring 217 and the wiring 216_j+1, where a part of the semiconductor layer 205 and the insulating layer 207 is removed. The groove portion 230 is configured such that it does not have a semiconductor layer at least at its bottom surface.

[0324] In the cross-section R1-R2 shown in FIG. 18, an underlayer 201 is formed on the substrate 200, and a wiring 212_i is formed on the underlayer 201. Further, a gate insulating layer 204 and a semiconductor layer 205 are formed on the wiring 212_i. Also, a wiring 217 and a wiring 216_j+1 of an adjacent pixel are formed on the semiconductor layer 205, and an insulating layer 207 is formed on the semiconductor layer 205, the wiring 217, and the wiring 216_j+1. Further, a partition layer 218 is formed on the insulating layer 207, and a counter electrode 226 is formed on the partition layer 218. Also, a groove portion 230 is formed where a part of the semiconductor layer 205 and the insulating layer 207 is removed. The groove portion 230 is configured such that it does not have a semiconductor layer at least at its bottom surface. Also, the wiring 212_i is not exposed at the bottom surface of the groove portion 230.

[0325] Next, an example of a pixel having a planar configuration different from that in FIG. 15 will be described with reference to FIG. 19. FIG. 19 is a top view showing the planar configuration of the pixel 120. For ease of viewing the drawing, In FIG. 19, the description of the base layer 201, the gate insulating layer 204, the semiconductor layer 205, the insulating layer 207, the partition wall layer 218, the EL layer 271, and the counter electrode 226 is omitted. The pixel 120 shown in FIG. 19 has a different planar configuration of the groove portion 230 from the pixel 160 shown in FIGS. 15 and 16. Note that the laminated structure of the portion indicated by the dashed-dotted line P1 - P2 in FIG. 19 is the same as the structure described in FIG. 17(A).

[0326] The pixel 120 is configured such that the groove portion 230 is provided between the wiring 217 and the pixel electrode 210, and between the wiring 216_j and the pixel electrode 210. Also, the groove portion 230 is provided not only to simply cross over the widthwise end of the wiring 212_i, but also to be formed wider than the pixel 160. Also, the contact hole 209 and the contact hole 214 are formed integrally with the groove portion 230, and the groove portion 230 is formed as much as possible around the capacitor electrode 215 and the gate electrode 243. By arranging the groove portion 230 over a wide range in this way, the generation of parasitic transistors can be more reliably prevented. Next, a method for manufacturing a semiconductor device that can be used in the EL display device described with reference to FIGS. 15 to 18 will be described with reference to FIGS. 21 to 23. Note that the cross-section P1 - P2 in FIGS. 21 to 23

[0327] is a cross-sectional view of the portion indicated by the dashed-dotted line P1 - P2 in FIGS. 15 and 16. The semiconductor device described in this embodiment can be formed by the same processes as the semiconductor device shown in Embodiment 1 up to the step of forming the pixel electrode 210. Also, at least the portions indicated by the same reference numerals as those used in the above embodiment are the same as those in the embodiment. up to the step of forming the pixel electrode 210, it can be formed by the same processes as the semiconductor device shown in Embodiment 1. Also, at least the portions indicated by the same reference numerals as those used in the above embodiment are the same as those in the It can be formed using the same materials and methods as those shown in Form 1. Therefore, , detailed description in this embodiment is omitted.

[0328] First, an insulating layer serving as an underlayer 201 is formed on a substrate 200, and a conductive layer is formed on the underlayer 201 (see Fig. 21(A)). Subsequently, by a first photolithography process, a resist mask is formed on the conductive layer, and a part of the conductive layer is selectively removed to form a gate electrode 202, a gate electrode 243, a capacitor electrode 215, and a wiring 212_i (not shown in Fig. 21) (see Fig. 21(A)). In this embodiment, aluminoborosilicate glass is used for the substrate 200, silicon oxynitride is used for the underlayer 201, and tungsten is used as the conductive layer. Subsequently, a gate insulating layer 204 is formed on the gate electrode 202, the gate electrode 243, the capacitor electrode 215, and the wiring 212_i, and a semiconductor layer 205 is formed on the gate insulating layer 204 (see Fig. 21(B)). In this embodiment, silicon oxynitride is used as the gate insulating layer 204, and an oxide semiconductor is used as the semiconductor layer 205. Next, a conductive layer serving as a source electrode 206a, a drain electrode 206b, a source electrode 236a, a drain electrode 236b, and a wiring 216_j (not shown in Fig. 21) is formed on the semiconductor layer 205. In this embodiment, a stacked layer of titanium, aluminum, and titanium is formed as the conductive layer. Thereafter, by a second photolithography process, a part of the conductive layer is selectively removed to form the source electrode 206a, the drain electrode 206b, the source electrode 236a, the drain electrode 236b, and the wiring 216_j (see Fig. 21(C)). In this embodiment,

[0329]

[0330]

[0331] ​​​​​​​​​​​​ Next, an insulating layer 207 is formed on the source electrode 206a, the drain electrode 206b, the source electrode 236a, the drain electrode 236b, and the wiring 216_j (see Fig. 21(D)). In this embodiment, silicon oxide is formed as the insulating layer 207.

[0332] Next, a resist mask is formed by a third photolithography process, and a part of the insulating layer 207 on the source electrode 236a is selectively removed to form a contact hole 208.

[0333] In the third photolithography process, first, a resist mask 261 is formed on the insulating layer 207 using a multi-tone mask (see Fig. 22(A) and Fig. 13(A)).

[0334] The resist mask 261 has a recess at a position overlapping with the region for forming the contact hole 208 and the groove portion 230 (not shown in Fig. 22). Also, no resist mask 261 is provided on the region for forming the contact hole 209.

[0335] Next, a first etching process is performed. By performing the first etching process using the resist mask 261 as a mask, a part of the insulating layer 207, a part of the semiconductor layer 205, and a part of the gate insulating layer 204 are etched to form a contact hole 209 (see Fig. 22(B)). On the side surface of the contact hole 209, the side surfaces of the insulating layer 207, the semiconductor layer 205, and the gate insulating layer 204 are exposed. Also, on the bottom surface of the contact hole 209, a part of the drain electrode 206b and a part of the gate electrode 243 are exposed.

[0336] Next, the resist mask 261 is reduced by ashing with oxygen plasma or the like, and the re ​​​​​​​​​​A resist mask 262 is formed. At this time, the resist in the thin region (concave portion ) of the resist mask 261 is removed, and the insulating layer 207 is exposed (see FIG. 22(C)).

[0337] Next, a second etching process is performed. By the second etching process, using the resist mask 26 2 as a mask, a part of the insulating layer 207 that overlaps with the source electrode 236a in the cross section P1 - P2 is etched to form a contact hole 208. At this time, also in the contact hole 209, a part of the insulating layer 207 not covered by the resist mask 262 and a part of the semiconductor layer 205 are etched (see FIG. 23(A)). Although not shown in FIG. 23(A), the groove portion 230 is also formed in the same manner as the contact hole 208 by the second etching process. At the side surface of the contact hole 208, the side surface of the insulating layer 207 is exposed, and at the bottom surface, the source electrode 236a is exposed. At the side surface of the groove portion 230, the side surfaces of the insulating layer 207 and the semiconductor layer 205 are exposed, and the gate insulating layer 204 is exposed at the bottom surface.

[0338] Next, a transparent conductive layer that becomes the pixel electrode 21 0 is formed on the insulating layer 207 using a sputtering method, a vacuum evaporation method, etc. In this embodiment, ITO is formed as the transparent conductive layer .

[0339] Subsequently, by a fourth photolithography process, a resist mask is formed, and the conductive layer is selectively etched to form the pixel electrode 210, the wiring 213, and the wiring 223 (not shown in FIG. 23).) (see FIG. 23(B)). .

[0340]

[0341] ​​​The pixel electrode 210 is electrically connected to the source electrode 236a of the transistor 121 at the contact hole 208. Also, at the contact hole 209, the drain electrode 206b and the gate electrode 243 are electrically connected via the wiring 213. Also, at the contact hole 214, the capacitive electrode 215 and the wiring 217 are electrically connected via the wiring 223. Note that the terminal portions 103 and 104 can be formed in the same manner as in the above-described embodiment.

[0342] Next, a partition layer 218 is provided on the pixel region 102 (see FIG. 23(C)). As materials for forming the partition layer 218, organic insulating materials and inorganic insulating materials can be used. An opening 272 that overlaps with the pixel electrode 210 is formed in the partition layer 218 by a fifth photolithography process (see FIGS. 16 and 17(B)). Note that the sidewall shape of the partition layer 218 is preferably a trapezoidal shape or a shape having a curvature. When a photosensitive material is used for forming the partition layer 218, the partition layer 218 can be formed without using a photoresist, and the sidewall shape of the partition layer 218 can be a shape having a curvature. As materials for forming the partition layer 218, acrylic resin, phenol resin, polystyrene, polyimide, or the like can be applied. In this embodiment, photosensitive polyimide is used as the partition layer 218.

[0343] Also, the partition layer 218 is also formed on the contact hole 208, the contact hole 209, the contact hole 214, and the groove portion 230. The contact hole 208, the contact hole 209, the contact hole 214, and the groove portion 230 are filled with the partition layer 218. Thus, when forming the contact hole and the groove portion, the end portions of the exposed semiconductor layer and the insulating layer can be covered. By adopting such a configuration, it is possible to protect the above-described exposed portions, and thus improve the reliability of the semiconductor device. Note that the partition layer 218 is not formed on the terminal portion 103 and the terminal portion 104.

[0344] Next, an EL layer 271 is formed in a region in contact with the pixel electrode 210 of the opening 272. Then, a counter electrode 226 is formed on the EL layer 271 and the partition layer 218 (see FIG. 23(C)). .

[0345] The pixel electrode 210 functions as one electrode of the EL element 116. The counter electrode 226 functions as the other electrode of the EL element 116. Note that the EL layer 271 may be formed by laminating a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like. When the pixel electrode 2 10 is used as an anode, a material having a work function larger than that of the hole injection layer is used for the pixel electrode 210. When the pixel electrode 210 has a stacked structure of a plurality of layers, a material having a large work function is used for at least the constituent layer of the pixel electrode 210 in contact with the hole injection layer. When the counter electrode 226 is used as a cathode, a metal material having a work function smaller than that of the electron injection layer may be used for the counter electrode 226. Specifically, an alloy of aluminum and lithium can be used

[0346] for the counter electrode 226. Note that in this embodiment, an example in which one aspect of the present invention is applied to a bottom emission structure in which light emitted from the EL element 116 is extracted from the surface on the substrate 200 side of the EL element 116 is shown, but one aspect of the present invention is a top emission structure in which light is extracted from the surface opposite to the substrate 200 of the EL element 116.It can also be applied to a display device having an out (top emission) structure or a display device having a dual emission structure that emits light from both of the above surfaces. When the EL element 116 has a top emission structure, the pixel electrode 210 is used as the cathode and the counter electrode 226 is used as the anode, and the injection layer, transport layer, light emitting layer, etc. constituting the EL layer 271 are laminated in the reverse order to the bottom emission structure. It can also be applied to a display device having a dual emission structure that emits light from both surfaces. When the EL element 116 has a top emission structure, the pixel electrode 210 is used as the cathode and the counter electrode 226 is used as the anode, and the injection layer, transport layer, light emitting layer, etc. constituting the EL layer 271 are laminated in the reverse order to the bottom emission structure. When the EL element 116 has a top emission structure, the pixel electrode 210 is used as the cathode and the counter electrode 226 is used as the anode, and the injection layer, transport layer, light emitting layer, etc. constituting the EL layer 271 are laminated in the reverse order to the bottom emission structure. When the EL element 116 has a top emission structure, the pixel electrode 210 is used as the cathode and the counter electrode 226 is used as the anode, and the injection layer, transport layer, light emitting layer, etc. constituting the EL layer 271 are laminated in the reverse order to the bottom emission structure. It is only necessary to laminate them.

[0347] According to this embodiment, a semiconductor device can be manufactured with fewer photolithography steps than in the prior art. Therefore, an EL display device with low cost and high productivity can be manufactured. Also, according to this embodiment, it is possible to manufacture a semiconductor device with little deterioration in electrical characteristics and excellent reliability. Therefore, an EL display device with excellent reliability can be manufactured. According to this embodiment, a semiconductor device can be manufactured with fewer photolithography steps than in the prior art. Therefore, an EL display device with low cost and high productivity can be manufactured. Also, according to this embodiment, it is possible to manufacture a semiconductor device with little deterioration in electrical characteristics and excellent reliability. Therefore, an EL display device with excellent reliability can be manufactured. According to this embodiment, a semiconductor device can be manufactured with fewer photolithography steps than in the prior art. Therefore, an EL display device with low cost and high productivity can be manufactured. Also, according to this embodiment, it is possible to manufacture a semiconductor device with little deterioration in electrical characteristics and excellent reliability. Therefore, an EL display device with excellent reliability can be manufactured. According to this embodiment, a semiconductor device can be manufactured with fewer photolithography steps than in the prior art. Therefore, an EL display device with low cost and high productivity can be manufactured. Also, according to this embodiment, it is possible to manufacture a semiconductor device with little deterioration in electrical characteristics and excellent reliability. Therefore, an EL display device with excellent reliability can be manufactured. It is only necessary to laminate them.

[0348] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0349] (Embodiment 4) One form of the EL display device using the transistor exemplified in Embodiment 1 is shown in FIG. 24.

[0350] FIG. 24(A) is a plan view of a panel in which the transistor 4010 and the EL element 4113 are sealed with a sealing material 4105 between a first substrate 4001 and a second substrate 4006. FIG. 24(B) corresponds to a cross-sectional view taken along N1-N2 in FIG. 24(A). Also, a groove portion 4040 is provided on the first substrate 4001. FIG. 24(A) is a plan view of a panel in which the transistor 4010 and the EL element 4113 are sealed with a sealing material 4105 between a first substrate 4001 and a second substrate 4006. FIG. 24(B) corresponds to a cross-sectional view taken along N1-N2 in FIG. 24(A). Also, a groove portion 4040 is provided on the first substrate 4001. FIG. 24(A) is a plan view of a panel in which the transistor 4010 and the EL element 4113 are sealed with a sealing material 4105 between a first substrate 4001 and a second substrate 4006. FIG. 24(B) corresponds to a cross-sectional view taken along N1-N2 in FIG. 24(A). Also, a groove portion 4040 is provided on the first substrate 4001. A groove portion 4040 is provided on the first substrate 4001.

[0351] The sealing material 4105 surrounds the pixel portion 4002 provided on the first substrate 4001. It is provided that a second substrate 4006 is provided on the pixel portion 4002. Therefore, the pixel portion 40 02 is sealed by the first substrate 4001, the sealing material 4105, and the second substrate 4006 The sealing material 4105 can be formed using a known sealing material, glass frit, or the like. Specifically it can be made of organic resins such as thermosetting resins or photocuring resins, or materials such as low melting point glass It is also possible for the sealing material to contain a desiccant.

[0352] The space 400 surrounded by the first substrate 4001, the second substrate 4006, and the sealing material 4105 is filled with a gas. In particular, it is preferably filled with a gas that is inert to the EL element 4113. For example as the gas, it is preferable to use a noble gas or nitrogen.

[0353] Also, outside the region surrounded by the sealing material 4105 on the first substrate 4001, there is an input terminal 4020 to which FPC4018a (Flexible printed circuit), FPC4018b are connected. FPC4018a is electrically connected to a signal line driving circuit 4003 fabricated on a different substrate separately and FPC4018b is electrically connected to a scanning line driving circuit 4004 fabricated on a different substrate separately. Various signals and potentials supplied to the pixel portion 4002 are supplied from the signal line driving circuit 4003 and the scanning line driving circuit 4004 via FPC4018a and FPC4018b

[0354] Note that the connection method of the driving circuit fabricated on a different substrate separately is not particularly limited and COG, wire bonding, TCP, etc. can be used.

[0355] Also, although not shown, the signal line driving circuit 4003 or the scanning line driving circuit 4004 may be formed on the first substrate 4001 using the transistors disclosed in this specification.

[0356] The display device shown in FIG. 24(B) has wiring 4015 and electrodes 4016, and the wiring 40 15 and the electrodes 4016 are electrically connected via an anisotropic conductive layer 4019 to the terminals of the FPC 4018a.

[0357] The wiring 4015 is formed from the same conductive layer as the source electrode and the drain electrode of the transistor 4010, and the electrode 4016 is formed from the same conductive layer as the first electrode 4130 that becomes one of the electrodes of the EL element 4113.

[0358] In this embodiment, the transistor 4010 described in the above embodiment can be applied. The transistor 4010 provided in the pixel portion 4002 is electrically connected to the EL element to constitute a display panel.

[0359] Also, the display device shown in FIG. 24(B) shows an example using an EL element as a display element. In FIG. 24(B), the EL element 4113 has a first electrode 4130, a second electrode 4131 , and an EL layer 4108. The partition layer 4009 provided to electrically isolate the EL element 4113 from other EL elements 4113 is also provided on the groove portion 4040.

[0360] By filling the groove portion 4040 with the partition layer 4009, the side surfaces of the semiconductor layer and the insulating layer exposed when the groove portion 4040 is formed can be covered. With this configuration, since the above-described exposed portion can be protected, the reliability of the semiconductor device can be improved. ​

[0361] In addition, by using an oxide semiconductor for the semiconductor layer of the transistor shown in this embodiment, compared with a transistor using amorphous silicon, a high field-effect mobility can be obtained, so that high-speed driving is possible. Therefore, by using the above transistor for the pixel portion of the EL display device, a high-quality image can be provided. Further, since the above transistor can also be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of parts of the EL display device can be reduced.

[0362] By applying the transistor exemplified in the above embodiment as described above, without increasing the number of photomasks used in the manufacturing process of the display device having the transistor, an EL display device with improved reliability of the transistor can be manufactured. Therefore, an EL display device with low cost, high productivity, and excellent reliability can be provided.

[0363] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0364] (Embodiment 5) In this embodiment, a configuration example of the transistor will be described. Note that the same parts or parts having the same functions as those in the above embodiment, and the processes are the same as those in the above embodiment, and repeated descriptions in this embodiment will be omitted. Note that detailed descriptions of the same parts will also be omitted.

[0365] For the transistor 2450 shown in FIG. 25(A), a gate electrode 2401 is formed on a substrate 2400, a gate insulating layer 2402 is formed on the gate electrode 2401, and the gate insulating layer 240 An oxide semiconductor layer 2403 is formed on 2, and a source electrode 2 405a and a drain electrode 2405b are formed on the oxide semiconductor layer 240 3. Also, an insulating layer 2407 is formed on the oxide semiconductor layer 240 3, the source electrode 2405a, and the drain electrode 2405b. Further, a protective insulating layer 2409 may be formed on the insulating layer 2407. Also, an underlayer may be formed between the substrate 2 400 and the gate electrode 2401. The transistor 2450 is one of the transistors with a bottom gate structure and is also one of the reverse stagger type transistors . .

[0366] For the transistor 2460 shown in FIG. 25(B), a gate electrode 2401 is formed on the substrate 2400, a gate insulating layer 2402 is formed on the gate electrode 2401, an oxide semiconductor layer 2403 is formed on the gate insulating layer 240 2, a channel protection layer 2406 is formed on the oxide semiconductor layer 2403, and a source electrode 2405a and a drain electrode 2405b are formed on the channel protection layer 2406 and the oxide semiconductor layer 2403. Also, a protective insulating layer 2409 may be formed on the source electrode 24 05a and the drain electrode 2405b. Further, an underlayer may be formed between the substrate 2400 and the gate electrode 2401. The transistor 246 0 is one of the transistors with a bottom gate structure called a channel protection type (also called a channel stop type), and is also one of the reverse stagger type transistors. The channel protection layer 24 06 can be formed using the same materials and methods as other insulating layers. By making the cross-sectional shape of the end portion of the channel protection layer 2406 tapered or stepped, it occurs near the end portion of the channel protection layer 2406 that overlaps with the source electrode 2405 a or the drain electrode 2405b . . The transistor 246 0 is one of the transistors with a bottom gate structure called a channel protection type (also called a channel stop type), and is also one of the reverse stagger type transistors. The channel protection layer 24 06 can be formed using the same materials and methods as other insulating layers. By making the cross-sectional shape of the end portion of the channel protection layer 2406 tapered or stepped, it occurs near the end portion of the channel protection layer 2406 that overlaps with the source electrode 2405 a, or the drain electrode 2405b . It is possible to alleviate the electric field concentration that may occur and suppress the deterioration of the electrical characteristics of the transistor 2460. It can be done.

[0367] In the transistor 2470 shown in FIG. 25(C), an underlying layer 2436 is formed on a substrate 2400. An oxide semiconductor layer 2403 is formed on the underlying layer 2436. On the oxide semiconductor layer 2403 and the underlying layer 2436, a source electrode 2405a and a drain electrode 2405b are formed. On the oxide semiconductor layer 2403, the source electrode 2405a, and the drain electrode 2405b, a gate insulating layer 2402 is formed, and a gate electrode 2401 is formed on the gate insulating layer 2402. Also, a protective insulating layer 2409 may be formed on the gate electrode 2401. The transistor 2470 is one of the transistors having a top gate structure.

[0368] In the transistor 2480 shown in FIG. 25(D), a first gate electrode 24 11 is formed on a substrate 2400, and a first gate insulating layer 2413 is formed on the first gate electrode 2411. An oxide semiconductor layer 2403 is formed on the first gate insulating layer 2413. On the oxide semiconductor layer 2403 and the first gate insulating layer 2413, a source electrode 2405a and a drain electrode 2405b are formed. Also, a second gate insulating layer 2414 is formed on the oxide semiconductor layer 2403, the source electrode 2405 a, and the drain electrode 2405b, and a second gate electrode 2412 is formed on the second gate insulating layer 2414. The second gate electrode 2412 may be formed using the same layer as the pixel electrode shown in the above embodiment. Also, a protective insulating layer may be formed on the second gate electrode 2412. Also, an underlying layer may be formed between the substrate 2400 and the first gate electrode 2411. It is also possible to form an underlying layer between the substrate 2400 and the first gate electrode 2411.

[0369] Transistor 2480 has a structure combining transistor 2450 and transistor 2470. The first gate electrode 2411 and the second gate electrode 2412 can be electrically connected to function as one gate electrode. Also, different potentials may be supplied to the first gate electrode 2411 and the second gate electrode 2412 respectively. Of the first gate electrode 2411 and the second gate electrode 2412, either one may be simply called the gate electrode, and the other may be called the back gate electrode. The same potential as that of the gate electrode may be applied to the back gate electrode, or a fixed potential such as a ground potential or a common potential may be applied. Also, by controlling the potential applied to the back gate electrode, the threshold voltages of transistor 2480 and transistor 2570 can be controlled.

[0370]

[0371] Also, the back gate electrode is formed of a conductive material having light-shielding properties, and by covering the channel formation region of the oxide semiconductor layer 2403 with the back gate electrode, light incident on the oxide semiconductor layer 2403 from the back gate electrode side can be prevented. Therefore, light degradation of the oxide semiconductor layer 2403 can be prevented, and deterioration of characteristics such as a shift in the threshold voltage of the transistor can be prevented.

[0372] The transistor 2550 shown in Fig. 26(A) has a gate electrode 2401 formed on a substrate 2400, a gate insulating layer 2402 formed on the gate electrode 2401, a source electrode 2405a and a drain electrode 2405b formed on the gate insulating layer 2402, and a gate insulating layer 2 ​​​​​​​​​​​​402, source electrode 2405a, and drain electrode 2405b, an oxide semiconductor layer 240 3 is formed. Also, an insulating layer 2407 is formed on the oxide semiconductor layer 2403, source electrode 2405a, and drain electrode 2405b. Further, a protective insulating layer 2409 may be formed on the insulating layer 2407. Also, an under layer may be formed between the substrate 2400 and the gate electrode 2401. The transistor 2550 is one of the transistors with a bottom gate structure and is also one of the reverse staggered transistors.

[0373] For the transistor 2560 shown in FIG. 26(B), an underlayer 2436 is formed on the substrate 2400, and a source electrode 2405a and a drain electrode 2405b are formed on the underlayer 2436. An oxide semiconductor layer 2403 is formed on the underlayer 2436, source electrode 2405a, and drain electrode 2405b. A gate insulating layer 2402 is formed on the oxide semiconductor layer 2403, source electrode 2405a, and drain electrode 2405b. A gate electrode 2401 is formed on the gate insulating layer 2402. Further, a protective insulating layer 2409 may be formed on the gate electrode 2401. The transistor 2560 is one of the transistors with a top gate structure.

[0374] For the transistor 2570 shown in FIG. 26(C), a first gate electrode 24 11 is formed on the substrate 2400, and a first gate insulating layer 2413 is formed on the first gate electrode 2411. A source electrode 2405a and a drain electrode 2405b are formed on the first gate insulating layer 2413. An oxide semiconductor layer 2403 is formed on the first gate insulating layer 2413, source electrode 2405a, and drain electrode 2 405b. An oxide semiconductor layer 2403, source electrode​​​ A second gate insulating layer 2414 is formed on the 2405a and the drain electrode 2405b, and a second gate electrode 2412 is formed on the second gate insulating layer 2414. The second gate electrode 2412 may be formed using the same layer as the pixel electrode shown in the above embodiment. Also, a protective insulating layer may be formed on the second gate electrode 2412. Further, an underlayer may be formed between the substrate 240 0 and the first gate electrode 2411.

[0375] The transistor 2570 has a combined structure of the transistor 2550 and the transistor 2560. The first gate electrode 2411 and the second gate electrode 2412 can be electrically connected to function as one gate electrode. Also, either one of the first gate electrode 2411 and the second gate electrode 2412 may be simply referred to as a gate electrode, and the other may be referred to as a back gate electrode.

[0376] As described above, by changing the potential of the back gate electrode, the threshold voltage of the transistor can be changed. Also, by covering the channel formation region of the oxide semiconductor layer 2403 with a back gate electrode formed of a conductive material having light-shielding properties, light incident on the oxide semiconductor layer 2403 from the back gate electrode side can be prevented. Therefore, light deterioration of the oxide semiconductor layer 2403 can be prevented, and deterioration of characteristics such as a shift in the threshold voltage of the transistor can be prevented.

[0377] An insulating layer in contact with the oxide semiconductor layer 2403 (in this embodiment, the gate insulating layer 240 2, the insulating layer 2407, the channel protection layer 2406, the underlayer 2436, the first gate insulating layer 2 413 corresponds to the second gate insulating layer 2414. It is preferable to use an insulating material containing group 13 elements and oxygen. Many oxide semiconductor materials contain group 13 elements. An insulating material containing group 13 elements has good compatibility with an oxide semiconductor, and by using it for the insulating layer in contact with the oxide semiconductor, the state of the interface with the oxide semiconductor can be kept good. The insulating material containing group 13 elements refers to an insulating material containing one or more group 13 elements. Examples of the insulating material containing group 13 elements include, for example, gallium oxide, aluminum oxide,

[0378] aluminum gallium oxide, gallium aluminum oxide, and the like. Here, aluminum gallium oxide indicates a material in which the content (atomic %) of aluminum is more than the content (atomic %) of gallium, and gallium aluminum oxide indicates a material in which the content (atomic %) of gallium is equal to or more than the content (atomic %) of aluminum. For example, when forming an insulating layer in contact with a gallium-containing oxide semiconductor layer, by using a material containing gallium oxide for the insulating layer, the interface characteristics between the oxide semiconductor layer and the insulating layer can be kept good. For example, by providing a contact between an oxide semiconductor layer and an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. When an element of the same group as the component element of the oxide semiconductor layer is used for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has the characteristic of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0379] For example, when forming an insulating layer in contact with a gallium-containing oxide semiconductor layer, by using a material containing gallium oxide for the insulating layer, the interface characteristics between the oxide semiconductor layer and the insulating layer can be kept good. For example, by providing a contact between an oxide semiconductor layer and an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. When an element of the same group as the component element of the oxide semiconductor layer is used for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has the characteristic of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer. For example, when forming an insulating layer in contact with a gallium-containing oxide semiconductor layer, by using a material containing gallium oxide for the insulating layer, the interface characteristics between the oxide semiconductor layer and the insulating layer can be kept good. For example, by providing a contact between an oxide semiconductor layer and an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. When an element of the same group as the component element of the oxide semiconductor layer is used for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has the characteristic of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0380] In addition, the insulating layer in contact with the oxide semiconductor layer 2403 introduces oxygen into the bulk so that the insulating material has a region where oxygen is more abundant than the stoichiometric composition (has an oxygen-excess region). This is preferable. The term "bulk" is used to clarify that oxygen is added not only to the layer surface but also to the layer interior. The introduction of oxygen can be carried out using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Also, it can be carried out by heat treatment in an oxygen atmosphere or plasma treatment carried out in an oxygen atmosphere. When the insulating layer having an oxygen-excess region is in contact with the oxide semiconductor layer, the excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, reducing oxygen deficiency in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and the insulating layer, and enabling the oxide semiconductor layer to be made i-type or substantially i-type.

[0381] A transistor having an i-type or substantially i-type oxide semiconductor has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, a highly reliable semiconductor device having stable electrical characteristics can be provided.

[0382]

[0383] Note that the insulating layer having an oxygen-excess region may be used for only one of the insulating layers located in the upper layer or the insulating layer located in the lower layer among the insulating layers in contact with the oxide semiconductor layer 2403, but it is preferable to use it for both insulating layers. The insulating layer having a region where oxygen is more abundant than the stoichiometric composition is used for the insulating layers located in the upper layer and the lower layer of the insulating layer in contact with the oxide semiconductor layer 2403. By adopting a configuration in which the oxide semiconductor layer 2403 is sandwiched, the above effects can be further enhanced. 。

[0384] Also, the insulating layer used for the upper layer or the lower layer of the oxide semiconductor layer 2403 may be an insulating layer having the same constituent elements for the upper layer and the lower layer, or may be an insulating layer having different constituent elements. 。

[0385] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. 。

[0386] (Embodiment 6) The display device described in the above embodiment can be applied to a semiconductor device that displays 3D images. In this embodiment, an example of viewing a 3D image, which is a moving image or a still image, using a display device that switches between a left-eye image and a right-eye image at high speed and using dedicated glasses synchronized with the image of the display device is shown with reference to FIG. 27. 。 。 。

[0387] FIG. 27(A) shows an external view in which a display device 2711 and a dedicated glasses body 2701 are connected by a cable 2703. The display device 2711 can use the display device disclosed in this specification. The dedicated glasses body 2701 has shutters provided on a left-eye panel 2702a and a right-eye panel 2702b that open and close alternately, enabling the user to recognize the image of the display device 2711 in 3D. 。 。 。 。

[0388] Also, a block diagram of the main configurations of the display device 2711 and the dedicated glasses body 2701 is shown in FIG. 27(B). 。

[0389] The display device 2711 shown in FIG. 27(B) includes a display control circuit 2716, a display unit 2717, a timing It has a timing generator 2713, a source line side drive circuit 2718, an external operation means 2722, and a gate line side drive circuit 2719. Note that the signal output is variable according to the operation by the external operation means 2722 such as a keyboard.

[0390] The timing generator 2713 forms a start pulse signal and the like, and also forms a signal for synchronizing the left-eye image with the shutter of the left-eye panel 2702a, a signal for synchronizing the right-eye image with the shutter of the right-eye panel 2702b, and the like.

[0391] The synchronization signal 2731a of the left-eye image is input to the display control circuit 2716 and displayed on the display unit 2717. At the same time, the synchronization signal 2730a for opening the shutter of the left-eye panel 2702a is input to the left-eye panel 2702a. Also, the synchronization signal 2731b of the right-eye image is input to the display control circuit 2716 and displayed on the display unit 2717. At the same time, the synchronization signal 2730b for opening the shutter of the right-eye panel 2702b is input to the right-eye panel 2702b.

[0392] In addition, in order to switch the left-eye image and the right-eye image at high speed, the display device 2711 preferably uses a light-emitting diode (LED) to perform color display by time division using the sequential addition color mixing method (field sequential method).

[0393] Also, in order to use the field sequential method, it is preferable that the timing generator 2713 inputs signals synchronized with the synchronization signals 2730a and 2730b to the backlight unit of the light-emitting diode as well. Note that the backlight unit has LEDs of R, G, and B and is assumed to be such.

[0394] Note that this embodiment can be appropriately combined with other embodiments described in this specification. 。

[0395] (Embodiment 7) In this embodiment, an example of an electronic device including the display device described in the above embodiment will be described. will be described.

[0396] FIG. 28(A) is a notebook personal computer, which is composed of a main body 3001, a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the display device shown in the above embodiment, a highly reliable notebook personal computer can be obtained. can be obtained.

[0397] FIG. 28(B) is a personal digital assistant (PDA). The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. There is also a stylus 3022 as an accessory for operation. By applying the display device shown in the above embodiment, a highly reliable personal digital assistant (PDA) can be obtained. a highly reliable personal digital assistant (PDA) can be obtained.

[0398] FIG. 28(C) shows an example of an electronic book. For example, the electronic book is composed of two housings, a housing 2706 and a housing 2704. The housing 2706 and the housing 2704 are integrated by a shaft portion 2712 and can perform an opening and closing operation about the shaft portion 2712 as an axis. With such a configuration, it becomes possible to perform an operation similar to that of a paper book. be possible.

[0399] A display unit 2705 is incorporated in the housing 2706, and a display unit 2707 is incorporated in the housing 2704. The display unit 2705 and the display unit 2707 are configured to display consecutive images. be configured. It may also be configured to display different images. By adopting a configuration for displaying different images, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 28(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 28(C)). By applying the display device shown in the above embodiment, a highly reliable electronic book can be obtained. Also, in FIG. 28(C), an example is shown in which the housing 2706 is provided with an operation unit or the like. For example, in the housing 2706, there are provided a power supply terminal 2721, operation keys 2723, a speaker 2725, etc. The page can be advanced by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. Further, the electronic book may be configured to have a function as an electronic dictionary. Also, the electronic book may be configured to be able to wirelessly transmit and receive information. It is also possible to configure the electronic book to purchase and download desired book data, etc. from an electronic book server via wireless communication. FIG. 28(D) shows a mobile phone, which is composed of two housings, namely a housing 2800 and a housing 2801. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. Also, the housing 2800 is provided with a solar cell for charging the portable information terminal. .

[0400] In addition, FIG. 28(C) shows an example in which the housing 2706 is provided with an operation unit or the like. For example, in the housing 2706, there are provided a power supply terminal 2721, operation keys 2723, a speaker 2725, etc. The page can be advanced by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. Further, the electronic book may be configured to have a function as an electronic dictionary. Also, the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. Further, the electronic book may be configured to have a function as an electronic dictionary. on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. may be provided. Further, the electronic book may be configured to have a function as an electronic dictionary. It may also be configured to display different images. By adopting a configuration for displaying different images, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 28(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 28(C)). By applying the display device shown in the above embodiment, a highly reliable electronic book can be obtained. It may also be configured to display different images. By adopting a configuration for displaying different images, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 28(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 28(C)). By applying the display device shown in the above embodiment, a highly reliable electronic book can be obtained.

[0401] Also, the electronic book may be configured to be able to wirelessly transmit and receive information. It is also possible to configure the electronic book to purchase and download desired book data, etc. from an electronic book server via wireless communication. It is also possible to configure the electronic book to purchase and download desired book data, etc. from an electronic book server via wireless communication.

[0402] FIG. 28(D) shows a mobile phone, which is composed of two housings, namely a housing 2800 and a housing 2801. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. It is equipped with a battery cell 2810, an external memory slot 2811, etc. Also, the antenna is built inside the housing 2801.

[0403] Also, the display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 shown by dotted lines in which images are being displayed are shown in Fig. 28(D). Note that a boosting circuit for boosting the voltage output by the solar cell 2810 to the voltage required for each circuit is also implemented.

[0404] The display direction of the display panel 2802 changes appropriately according to the usage form. Also, since a camera lens 2807 is provided on the same surface as the display panel 2802, a videophone is possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, and videophone, recording, playback, etc. are possible. Furthermore, the housing 2800 and the housing 2801 can be slid and changed from the unfolded state as shown in Fig. 28(D) to an overlapping state, enabling miniaturization suitable for portability.

[0405] The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication with a personal computer, etc. Also, a recording medium can be inserted into the external memory slot 2811 to support storage and transfer of a larger amount of data.

[0406] Also, in addition to the above functions, it may be equipped with an infrared communication function, a TV reception function, etc. By applying the display device shown in the above embodiment, a highly reliable mobile phone can be achieved.

[0407] Fig. 28(E) shows a digital video camera, including a main body 3051, a display unit (A) 3057,​​​​​​​​​​​​ It is composed of an eyepiece part 3053, an operation switch 3054, a display part (B) 3055, a battery 3056, etc. By applying the display device shown in the above embodiment, a highly reliable digital video camera can be obtained.

[0408] FIG. 28(F) shows an example of a television device. The television device has a display part 9603 incorporated in a housing 9601. The display part 9603 can display an image. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. By applying the display device shown in the above embodiment, a highly reliable television device can be obtained.

[0409] The operation of the television device can be performed by an operation switch provided in the housing 9601 or by a separate remote control operation device. Further, the remote control operation device may be configured to be provided with a display part for displaying information output from the remote control operation device.

[0410] Note that the television device has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, by connecting to a wired or wireless communication network via the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between receivers, etc.) information communication can also be performed.

[0411] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Description of Reference Numerals

[0412] 100 Semiconductor device 101 Substrate 102 Pixel region 103 Terminal part 104 Terminal part 105 Terminal 106 Terminal 107 Terminal 108 Terminal 110 Pixel 111 Transistor 112 Liquid crystal element 113 Capacitor element 114 Electrode 115 Node 116 EL element 120 Pixel 121 Transistor 130 Pixel 150 Semiconductor device 160 Pixel 200 Substrate 201 Underlayer 202 Gate electrode 203 Wiring 204 Gate insulating layer 205 Semiconductor layer 207 Insulating layer 208 Contact hole 209 Contact hole 210 Pixel electrode 211 Pixel electrode 212 Wiring 213 Wiring 214 Contact hole 215 Capacitor electrode 216 Wiring 217 Wiring 218 Partition layer 219 Contact hole 220 Contact hole 221 Electrode 222 Electrode 223 Wiring 224 Wiring 225 Counter electrode connection part 226 Counter electrode 230 Groove part 231 End part 232 End part 233 End 234 End 240 Groove part 243 Gate electrode 251 Groove part 252 Groove part 253 Groove part 254 Groove part 255 Groove part 256 Groove part 257 Groove part 258 Groove part 261 Resist mask 262 Resist mask 271 EL layer 272 Opening 301 Transparent substrate 302 Light-shielding part 303 Diffraction grating 304 Grayscale mask 311 Transparent substrate 312 Semi-transmissive part 313 Light-shielding part 314 Halftone mask 2400 Substrate 2401 Gate electrode 2402 Gate insulating layer 2403 Oxide semiconductor layer 2406 Channel protection layer 2407 Insulating layer 2409 Protective insulating layer 2411 Gate electrode 2412 Gate electrode 2413 Gate insulating layer 2414 Gate insulating layer 2436 Underlayer 2450 Transistor 2460 Transistor 2470 Transistor 2480 Transistor 2550 Transistor 2560 Transistor 2570 Transistor 2701 Eyeglass body 2703 Cable 2704 Housing 2705 Display Unit 2706 Housing 2707 Display Unit 2711 Display Device 2712 Shaft Portion 2713 Timing Generator 2716 Display Control Circuit 2717 Display Unit 2718 Source Line Side Drive Circuit 2719 Gate Line Side Drive Circuit 2721 Power Supply Terminal 2722 External Operation Means 2723 Operation Key 2725 Speaker 2800 Housing 2801 Housing 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera Lens 2808 External Connection Terminal 2810 Solar Cell 2811 External Memory Slot 3001 Main Body 3002 Housing 3003 Display Unit 3004 Keyboard 3021 Main Body 3022 Stylus 3023 Display Unit 3024 Operation Button 3025 External Interface 3051 Main Body 3053 Eyepiece 3054 Operation Switch 3056 Battery 4001 Substrate 4002 Pixel Portion 4003 Signal Line Drive Circuit 4004 Scanning Line Drive Circuit 4005 Sealing Material 4006 Substrate 4007 Space 4008 Liquid crystal layer 4009 Partition layer 4010 Transistor 4013 Liquid crystal element 4015 Wiring 4016 Electrode 4019 Anisotropic conductive layer 4020 Input terminal 4030 Electrode 4031 Electrode 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4040 Groove portion 4105 Sealing material 4108 EL layer 4113 EL element 4130 Electrode 4131 Electrode 9601 Housing 9603 Display unit 9605 Stand 105_i Terminal 106_j Terminal 206a Source electrode 206b Drain electrode 212_i Wiring 216_j Wiring 236a Source electrode 236b Drain electrode 2405a Source electrode 2405b Drain electrode 2702a Left-eye panel 2702b Right-eye panel 2730a Synchronization signal 2730b Synchronization signal 2731a Synchronization signal 2731b Synchronization signal 4018a FPC 4018b FPC

Claims

1. a first pixel, a second pixel arranged in the same column as the first pixel, a third pixel arranged in the same row as the first pixel, a first source line extending in the column direction, a second source line extending in the column direction, a power supply line extending in the column direction, a gate line extending in the row direction, and having the first source line, the second source line, and the power supply line are arranged in the same layer, the power supply line has a region between the first source line and the second source line in a plan view, the first pixel has a first transistor, a second transistor, and a first EL element, the second pixel has a third transistor, a fourth transistor, and a second EL element, the third pixel has a fifth transistor, a sixth transistor, and a third EL element, one of the source or drain of the first transistor is electrically connected to the first source line, one of the source or drain of the third transistor is electrically connected to the first source line, one of the source or drain of the fifth transistor is electrically connected to the second source line, the gate of the first transistor is electrically connected to the gate line, the gate of the fifth transistor is electrically connected to the gate line, one of the source or drain of the second transistor is electrically connected to the power supply line, one of the source or drain of the fourth transistor is electrically connected to the power supply line, the first transistor has a function of supplying a first image signal from the first source line to the gate of the second transistor, the second transistor has a function of flowing a current corresponding to the first image signal supplied to the gate of the second transistor to the first EL element, the third transistor has a function of supplying a second image signal from the first source line to the gate of the fourth transistor, the fourth transistor has a function of flowing a current corresponding to the second image signal supplied to the gate of the fourth transistor to the second EL element, the fifth transistor has a function of supplying a third image signal from the second source line to the gate of the sixth transistor, The sixth transistor has a function of causing a current corresponding to the third image signal supplied to the gate of the sixth transistor to flow through the third EL element. The first semiconductor layer having a region that functions as a channel of the first transistor has a region that functions as a channel of the second transistor, a region that functions as a channel of the third transistor, and a region that functions as a channel of the fourth transistor. The second semiconductor layer having a region that functions as a channel of the fifth transistor has a region that functions as a channel of the sixth transistor. The first semiconductor layer and the second semiconductor layer contain an oxide semiconductor, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide. The first semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The second semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The gate line has a first region that does not overlap with the first semiconductor layer between the first source line and the power supply line in a plan view. The first region includes a part of a first side in the row direction of the gate line and a part of a second side in the row direction of the gate line, and an EL display device.

2. A first pixel, A second pixel arranged in the same column as the first pixel, A third pixel arranged in the same row as the first pixel, A first source line extending in the column direction, A second source line extending in the column direction, A power supply line extending in the column direction, A gate line extending in the row direction, and has The first source line, the second source line, and the power supply line are arranged in the same layer. The power supply line has a region between the first source line and the second source line in a plan view. The first pixel has a first transistor, a second transistor, and a first EL element. The second pixel has a third transistor, a fourth transistor, and a second EL element. The third pixel has a fifth transistor, a sixth transistor, and a third EL element. One of the source or drain of the first transistor is electrically connected to the first source line. One of the source or drain of the third transistor is electrically connected to the first source line. One of the source or drain of the fifth transistor is electrically connected to the second source line. The gate of the first transistor is electrically connected to the gate line. The gate of the fifth transistor is electrically connected to the gate line. The power supply line is electrically connected to the first EL element via the second transistor. The power supply line is electrically connected to the second EL element via the fourth transistor. The first transistor has a function of supplying a first image signal from the first source line to the gate of the second transistor. The second transistor has a function of flowing a current corresponding to the first image signal supplied to the gate of the second transistor to the first EL element. The third transistor has a function of supplying a second image signal from the first source line to the gate of the fourth transistor. The fourth transistor has a function of flowing a current corresponding to the second image signal supplied to the gate of the fourth transistor to the second EL element. The fifth transistor has a function of supplying a third image signal from the second source line to the gate of the sixth transistor. The sixth transistor has a function of flowing a current corresponding to the third image signal supplied to the gate of the sixth transistor to the third EL element. The first semiconductor layer having a region functioning as a channel of the first transistor has a region functioning as a channel of the second transistor, a region functioning as a channel of the third transistor, and a region functioning as a channel of the fourth transistor. The second semiconductor layer having a region functioning as a channel of the fifth transistor has a region functioning as a channel of the sixth transistor. The first semiconductor layer and the second semiconductor layer contain an oxide semiconductor, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide. The first semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The second semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The gate line has a first region that does not overlap with the first semiconductor layer between the first source line and the power supply line in a plan view. The first region includes a part of a first side in the row direction of the gate line and a part of a second side in the row direction of the gate line, in the EL display device.

3. A first pixel, A second pixel arranged in the same column as the first pixel, A third pixel arranged in the same row as the first pixel, A first source line extending in the column direction, A second source line extending in the column direction, A power supply line extending in the column direction, A gate line extending in the row direction, and having The first source line, the second source line, and the power supply line are arranged in the same layer, The power supply line has a region between the first source line and the second source line in a plan view, The first pixel has a first transistor, a second transistor, and a first EL element, The second pixel has a third transistor, a fourth transistor, and a second EL element, The third pixel has a fifth transistor, a sixth transistor, and a third EL element, One of the source or drain of the first transistor is electrically connected to the first source line, One of the source or drain of the third transistor is electrically connected to the first source line, One of the source or drain of the fifth transistor is electrically connected to the second source line, The gate of the first transistor is electrically connected to the gate line, The gate of the fifth transistor is electrically connected to the gate line, One of the source or drain of the second transistor is electrically connected to the power supply line, One of the source or drain of the fourth transistor is electrically connected to the power supply line, The first transistor has a function of supplying a first image signal from the first source line to the gate of the second transistor, The second transistor has a function of flowing a current corresponding to the first image signal supplied to the gate of the second transistor to the first EL element, The third transistor has a function of supplying a second image signal from the first source line to the gate of the fourth transistor, The fourth transistor has a function of flowing a current corresponding to the second image signal supplied to the gate of the fourth transistor to the second EL element, The fifth transistor has a function of supplying a third image signal from the second source line to the gate of the sixth transistor, The sixth transistor has a function of flowing a current corresponding to the third image signal supplied to the gate of the sixth transistor to the third EL element. The first semiconductor layer having a region functioning as a channel of the first transistor has a region functioning as a channel of the second transistor, a region functioning as a channel of the third transistor, and a region functioning as a channel of the fourth transistor. The second semiconductor layer having a region functioning as a channel of the fifth transistor has a region functioning as a channel of the sixth transistor. The first semiconductor layer and the second semiconductor layer contain an oxide semiconductor, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide. The first semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The second semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view. The gate line has a first region that does not overlap with the first semiconductor layer between the first source line and the power supply line in a plan view. The first region includes a part of a first side in the row direction of the gate line and a part of a second side in the row direction of the gate line. The EL display device having indium oxide in the first semiconductor layer and the second semiconductor layer.

4. A first pixel, A second pixel arranged in the same column as the first pixel, A third pixel arranged in the same row as the first pixel, A first source line extending in the column direction, A second source line extending in the column direction, A power supply line extending in the column direction, A gate line extending in the row direction, and The first source line, the second source line, and the power supply line are arranged in the same layer. The power supply line has a region between the first source line and the second source line in a plan view. The first pixel has a first transistor, a second transistor, and a first EL element. The second pixel has a third transistor, a fourth transistor, and a second EL element. The third pixel has a fifth transistor, a sixth transistor, and a third EL element. One of the source or drain of the first transistor is electrically connected to the first source line. One of the source or drain of the third transistor is electrically connected to the first source line, One of the source or drain of the fifth transistor is electrically connected to the second source line, The gate of the first transistor is electrically connected to the gate line, The gate of the fifth transistor is electrically connected to the gate line, The power supply line is electrically connected to the first EL element via the second transistor, The power supply line is electrically connected to the second EL element via the fourth transistor, The first transistor has a function of supplying a first image signal from the first source line to the gate of the second transistor, The second transistor has a function of flowing a current corresponding to the first image signal supplied to the gate of the second transistor to the first EL element, The third transistor has a function of supplying a second image signal from the first source line to the gate of the fourth transistor, The fourth transistor has a function of flowing a current corresponding to the second image signal supplied to the gate of the fourth transistor to the second EL element, The fifth transistor has a function of supplying a third image signal from the second source line to the gate of the sixth transistor, The sixth transistor has a function of flowing a current corresponding to the third image signal supplied to the gate of the sixth transistor to the third EL element, The first semiconductor layer having a region functioning as a channel of the first transistor has a region functioning as a channel of the second transistor, a region functioning as a channel of the third transistor, and a region functioning as a channel of the fourth transistor, The second semiconductor layer having a region functioning as a channel of the fifth transistor has a region functioning as a channel of the sixth transistor, The first semiconductor layer and the second semiconductor layer include an oxide semiconductor, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, The first semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view, The second semiconductor layer has at least a part of an end portion between the power supply line and the second source line in a plan view, The gate line has a first region that does not overlap with the first semiconductor layer between the first source line and the power supply line in a plan view. The first region includes a part of a first side in the row direction of the gate line and a part of a second side in the row direction of the gate line. The first semiconductor layer and the second semiconductor layer are EL display devices having indium oxide.

5. In claim 2 or claim 4, An EL display device having the first to third pixels on a substrate. An EL display device that extracts light emitted from the first EL element and light emitted from the second EL element from a surface opposite to the substrate.

6. In any one of claims 1 to 5, The gate line is provided in a layer different from the power supply line, the first source line, and the second source line. The gate line is provided so as to intersect the power supply line, the first source line, and the second source line in a plan view.

7. In any one of claims 1 to 6, The gate line has one second region protruding in the column direction per pixel in a plan view.

8. In any one of claims 1 to 7, An EL display device in which the film thicknesses of the first semiconductor layer and the second semiconductor layer are 1 nm or more and 100 nm or less.

9. In any one of claims 1 to 8, An EL display device in which the film thicknesses of the first semiconductor layer and the second semiconductor layer are 5 nm or more and 50 nm or less.

Images