Printed Wiring Board and Method of Manufacturing the Same

Abstract

The printed wiring board (100) includes a base film (10) having main surfaces (10a, 10b), wirings (21, 22) disposed on the main surfaces, and insulating coating layers (31, 32). The normal direction of the main surface is along the first direction (DR1). The height (H1) of the wiring is more than 100 μm. The wiring is wound in a spiral shape when viewed along the first direction at the winding portion. The winding portion has a plurality of wiring portions. Each of the plurality of wiring portions extends along the second direction (DR2). In a cross-sectional view perpendicular to the second direction, the plurality of wiring portions are arranged at intervals along the third direction (DR3). The insulating coating layer is disposed on the main surface so as to cover the wiring. The plurality of wiring portions have a first wiring portion, and a first thickness (T1), which is the minimum value of the thickness of the insulating coating layer covering the side surface of the first wiring portion, is 0.5 times or more and 2 μm or more of a second thickness (T2), which is the thickness of the insulating coating layer covering the top surface of the first wiring portion.

Description

Technical Field

[0001] The present disclosure relates to a printed wiring board and a method for manufacturing a printed wiring board.

Background Art

[0002] International Publication No. 2018 / 211733 (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film and wiring. The base film has a main surface. The wiring has an underlayer disposed on the main surface, a first conductive layer disposed on the underlayer, and a second conductive layer covering the side surface of the underlayer, the side surface of the first conductive layer, and the top surface of the first conductive layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The printed wiring board of the present disclosure includes a base film having a main surface, wiring disposed on the main surface, and an insulating coating layer. The normal direction of the main surface is along a first direction. The height of the wiring is more than 100 μm. The wiring has a winding portion. The wiring is wound in a spiral shape when viewed along the first direction at the winding portion. The winding portion has a plurality of wiring portions in a cross-sectional view perpendicular to a second direction perpendicular to the first direction. Each of the plurality of wiring portions extends along the second direction. In a cross-sectional view perpendicular to the second direction, the plurality of wiring portions are arranged at intervals along a third direction perpendicular to the first direction and the second direction. The insulating coating layer is disposed on the main surface so as to cover the wiring. The plurality of wiring portions include a first wiring portion. A first thickness, which is a minimum value of the thickness of the insulating coating layer covering the side surface of the first wiring portion, is 0.5 times or more and 2 μm or more of a second thickness, which is the thickness of the insulating coating layer covering the top surface of the first wiring portion.

Brief Description of the Drawings

[0005]

Figure 1

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Figure 11

Mode for Carrying Out the Invention

[0006] [Problems to be Solved by the Present Disclosure] The second conductive layer is formed by performing electrolytic plating. The growth rate of the second conductive layer becomes faster as the position is farther from the main surface of the base film. Therefore, as the height of the wiring increases, the width of the upper part of the wiring becomes larger compared to the width of the lower part of the wiring. That is, as the height of the wiring increases, the interval between adjacent portions of the wiring becomes smaller at the upper part of the wiring. As a result, when performing a coating that covers the wiring, the thickness of the coating on the side surface of the wiring becomes smaller compared to the thickness of the coating on the top surface of the wiring.

[0007] The present disclosure has been made in view of the prior art as described above. More specifically, the present disclosure provides a printed wiring board capable of enhancing the uniformity of the thickness of an insulating coating layer while ensuring the thickness of the insulating coating layer.

[0008] [Effects of the Present Disclosure] According to the printed wiring board of the present disclosure, it is possible to enhance the uniformity of the thickness of the insulating coating layer while ensuring the thickness of the insulating coating layer.

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) The printed wiring board according to the embodiment includes a base film having a main surface, wirings disposed on the main surface, and an insulating coating layer. The normal direction of the main surface is along a first direction. The height of the wiring is more than 100 μm. The wiring has a winding portion. The wiring is wound in a spiral shape when viewed along the first direction at the winding portion. The winding portion has a plurality of wiring portions in a cross-sectional view perpendicular to a second direction perpendicular to the first direction. Each of the plurality of wiring portions extends along the second direction. In a cross-sectional view perpendicular to the second direction, the plurality of wiring portions are arranged at intervals along a third direction perpendicular to the first direction and the second direction. The insulating coating layer is disposed on the main surface so as to cover the wiring. The plurality of wiring portions include a first wiring portion. A first thickness, which is the minimum value of the thickness of the insulating coating layer covering the side surface of the first wiring portion, is 0.5 times or more and 2 μm or more of a second thickness, which is the thickness of the insulating coating layer covering the top surface of the first wiring portion. According to the printed wiring board of (1) above, it is possible to enhance the uniformity of the thickness of the insulating coating layer while ensuring the thickness of the insulating coating layer.

[0011] (2) In the printed wiring board of (1) above, the plurality of wiring portions have a second wiring portion adjacent to the first wiring portion in the third direction. The minimum value of the interval between the upper half of the first wiring portion and the upper half of the second wiring portion may be 5 μm or more and 1.2 times or more of the second thickness.

[0012] (3) In the printed wiring board of (1) or (2) above, a plurality of wiring portions have a second wiring portion adjacent to the first wiring portion in the third direction. The minimum value of the distance between the upper half of the first wiring portion and the upper half of the second wiring portion may be equal to or less than twice the distance on the bottom surface between the first wiring portion and the second wiring portion.

[0013] (4) In the printed wiring board of (1) to (3) above, the maximum value of the width of the upper half of the first wiring portion may be equal to or less than 1.2 times the width of the first wiring portion on the bottom surface.

[0014] (5) In the printed wiring board of (1) to (4) above, a plurality of wiring portions have a second wiring portion adjacent to the first wiring portion in the third direction. The value obtained by dividing the sum of the maximum value of the width of the upper half of the first wiring portion and the width of the first wiring portion on the bottom surface by 2 may be equal to or greater than 0.75 times the pitch between the first wiring portion and the second wiring portion.

[0015] (6) In the printed wiring board of (1) to (5) above, the angle formed by the center line that bisects the width of the first wiring portion and the main surface may be greater than 85° and equal to or less than 90° in a cross-sectional view perpendicular to the second direction.

[0016] (7) In the printed wiring board of (1) to (6) above, the constituent material of the insulating coating layer may contain parylene.

[0017] (8) The printed wiring board of (1) to (7) above may further include a magnetic layer. The magnetic layer may be disposed on the main surface so as to cover the wiring with the insulating coating layer interposed therebetween.

[0018] (9) In the printed wiring board of (1) to (8) above, each of the plurality of wiring portions may have a base conductive layer on the main surface, a first conductive layer on the base conductive layer, and a second conductive layer covering the side surface of the base conductive layer, the side surface of the first conductive layer, and the top surface of the first conductive layer. The height of the first conductive layer may be 100 μm or more. The first width, which is the width of the lower surface of the first conductive layer in the third direction, may be greater than the second width, which is the width of the top surface of the first conductive layer in the third direction.

[0019] (10) In the printed wiring board of (9) above, the difference between the first width and the second width may be greater than 0.03 times the height of the first conductive layer and less than 0.09 times the height of the first conductive layer. According to the printed wiring board of (10) above, the collapse of the resist pattern can be suppressed.

[0020] (11) The method for manufacturing a printed wiring board according to an embodiment includes a step of preparing a base film having a main surface, a step of forming an underlying conductive layer on the main surface, a step of disposing a resist layer on the underlying conductive layer, a step of forming a resist pattern from the resist layer by performing exposure and development on the resist layer, and a step of performing electrolytic plating on the underlying conductive layer exposed from the resist pattern. The thickness of the resist layer is greater than 100 μm. The resist layer is a plurality of dry film resists laminated.

[0021] [Details of Embodiments of the Present Disclosure] Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and duplicate descriptions will not be repeated. The printed wiring board according to the embodiment is referred to as a printed wiring board 100.

[0022] (Configuration of Printed Wiring Board 100) The configuration of the printed wiring board 100 will be described below.

[0023] FIG. 1 is a plan view of the printed wiring board 100. FIG. 2 is a plan view of the printed wiring board 100 as viewed from the side opposite to FIG. 1. In FIGS. 1 and 2, the illustration of the insulating coating layer 31, the insulating coating layer 32, the magnetic layer 41, and the magnetic layer 42 is omitted. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. As shown in FIGS. 1 to 3, the printed wiring board 100 has a base film 10, wirings 21 and 22, insulating coating layers 31 and 32, and magnetic layers 41 and 42.

[0024] The base film 10 has a main surface 10a and a main surface 10b. The main surface 10b is the opposite surface of the main surface 10a. The main surface 10a and the main surface 10b are end faces in the thickness direction of the base film 10. The normal direction of the main surface 10a (the normal direction of the main surface 10b) is defined as the first direction DR1. Looking at the printed wiring board 100 along the first direction DR1 is referred to as a plan view.

[0025] The base film 10 is made of an electrically insulating and flexible material. The constituent material of the base film 10 is, for example, polyimide. However, the constituent material of the base film 10 is not limited to this.

[0026] The wiring 21 is disposed on the main surface 10a. The wiring 21 also has a winding portion 21a. In a plan view, the wiring 21 is wound in a spiral shape at the winding portion 21a. The wiring 21 further has lands 21b and 21c. The land 21b is connected to the outermost circumference of the winding portion 21a. The land 21c is connected to the innermost circumference of the winding portion 21a. Let the height of the wiring 21 be height H1. The height H1 is the distance between the main surface 10a and the top surface of the wiring 21 in the first direction DR1.

[0027] The wiring 22 is disposed on the main surface 10b. The wiring 22 also has a winding portion 22a. In a plan view, the wiring 22 is wound in a spiral shape at the winding portion 22a. The wiring 22 further has lands 22b and 22c. The land 22b is connected to the innermost circumference of the winding portion 22a. The land 22b overlaps the land 21c in a plan view. The land 22c is connected to the outermost circumference of the winding portion 22a.

[0028] The winding portion 21a has a plurality of wiring portions 21d. Each of the plurality of wiring portions 21d extends along the second direction DR2. The second direction DR2 is a direction perpendicular to the first direction DR1. When the wiring portion 21d extends linearly in plan view, the second direction DR2 is the direction in which the wiring portion 21d extends linearly. When the wiring portion 21d extends in a curved shape in plan view, the tangential direction of the wiring portion 21d extending in a curved shape is regarded as the second direction DR2.

[0029] In a cross-sectional view perpendicular to the second direction DR2, the plurality of wiring portions 21d are arranged at intervals along the third direction DR3. The third direction DR3 is a direction perpendicular to the first direction DR1 and the second direction DR2. The minimum value of the interval between the upper halves (the portion between the central position of the wiring portion 21d and the top surface of the wiring portion 21d in the first direction DR1) of two adjacent wiring portions 21d is defined as the interval SP1. The interval at the bottom surface between two adjacent wiring portions 21d is defined as the interval SP2. Here, the "interval at the bottom surface between two adjacent wiring portions 21d" is the width of the main surface of the base film 10 located between two adjacent wiring portions 21d.

[0030] The maximum value of the width of the upper half of the wiring portion 21d is defined as the width W1. The width of the wiring portion 21d at the bottom surface is defined as the width W2.

[0031] The pitch between two adjacent wiring portions 21d is defined as the pitch P. The pitch P is the distance between the center of one of two adjacent wiring portions 21d in the third direction DR3 and the center of the other of two adjacent wiring portions 21d in the third direction DR3. In a cross-sectional view perpendicular to the second direction DR2, the angle formed by the center line bisecting the width of the wiring portion 21d and the main surface 10a is defined as the angle θ. The smaller of the angles formed by the center line bisecting the width of the wiring portion 21d and the main surface 10a is defined as the angle θ.

[0032] The winding portion 22a has a plurality of wiring portions 22d. Each of the plurality of wiring portions 22d extends along the second direction DR2. When the wiring portion 22d extends linearly in plan view, the second direction DR2 is the direction in which the wiring portion 22d extends linearly. When the wiring portion 22d extends in a curved shape in plan view, the tangential direction of the wiring portion 22d extending in a curved shape is regarded as the second direction DR2. In a cross-sectional view perpendicular to the second direction DR2, the plurality of wiring portions 22d are arranged at intervals along the third direction DR3.

[0033] Each of the wirings 21 and 22 has an underlying conductive layer 23. The underlying conductive layer 23 has a first layer 23a and a second layer 23b. The first layer 23a is disposed on the main surfaces (main surface 10a, main surface 10b) of the base film 10. The second layer 23b is disposed on the first layer 23a. Although not shown, through holes are formed in the base film 10 and the first layer 23a. These through holes overlap the lands 21c and 22b in plan view. The second layer 23b is also disposed on the inner wall surface of this through hole. Thereby, the wiring 21 is electrically connected to the wiring 22.

[0034] Each of the wirings 21 and 22 further has a first conductive layer 24 and a second conductive layer 25. The first conductive layer 24 is disposed on the underlying conductive layer 23. Let the height of the first conductive layer 24 be height H2. The height H2 is the distance between the bottom surface and the top surface of the first conductive layer 24 in the first direction DR1. In the wiring portion 21d, let the width of the bottom surface of the first conductive layer 24 be width W3, and the width of the top surface of the first conductive layer 24 be width W4. The width W3 and the width W4 are measured in the third direction DR3. The second conductive layer 25 covers the side surface of the underlying conductive layer 23, the side surface of the first conductive layer 24, and the top surface of the first conductive layer 24.

[0035] The first layer 23a is formed of, for example, a nickel-chromium alloy. The first layer 23a is a sputtered layer formed by, for example, sputtering. The second layer 23b is formed of, for example, copper or a copper alloy. The second layer 23b is an electroless plating layer formed by, for example, an electroless plating method. The first conductive layer 24 and the second conductive layer 25 are formed of, for example, copper or a copper alloy. The first conductive layer 24 and the second conductive layer 25 are electrolytic plating layers formed by, for example, an electrolytic plating method.

[0036] The insulating coating layer 31 is disposed on the main surface 10a so as to cover the wiring 21. Let the minimum value of the thickness of the insulating coating layer 31 on the side surface of the wiring 21 be the thickness T1. Let the thickness of the insulating coating layer 31 on the top surface of the wiring 21 be the thickness T2. The insulating coating layer 32 is disposed on the main surface 10b so as to cover the wiring 22. The insulating coating layer 31 and the insulating coating layer 32 are formed of, for example, parylene. That is, the insulating coating layer 31 and the insulating coating layer 32 are parylene coatings formed by, for example, depositing parylene.

[0037] The magnetic layer 41 is disposed on the main surface 10a so as to cover the wiring 21 with the insulating coating layer 31 interposed therebetween. The magnetic layer 42 is disposed on the main surface 10b so as to cover the wiring 22 with the insulating coating layer 32 interposed therebetween. The magnetic layer 41 and the magnetic layer 42 have, for example, a resin layer and a magnetic material contained in the resin layer. The magnetic material is, for example, particles formed of a ferromagnetic material such as ferrite.

[0038] The height H1 may be more than 100 μm, may be 110 μm or more, or may be 115 μm or more. The thickness T1 is 0.5 times or more and 2 μm or more of the thickness T2. The thickness T1 is, for example, 1.5 times or less of the thickness T2. The interval SP1 is, for example, 5 μm or more and 1.2 times or more of the thickness T2. The interval SP2 is, for example, 2 times or less of the interval SP1.

[0039] The width W1 is, for example, 1.2 times or less the width W2. The width W1 is, for example, 0.85 times or more, or 0.90 times or more the width W2. The value obtained by dividing the sum of the widths W1 and W2 by 2 is, for example, 0.75 times or more the pitch P. Note that the value obtained by dividing the sum of the widths W1 and W2 by 2 can be regarded as a pseudo-average value of the width of the wiring portion 21d. The angle θ is, for example, greater than 85° and equal to or less than 90°.

[0040] The width W4 is, for example, smaller than the width W3. That is, the wiring portion 21d has a tapered shape in which the width decreases as it approaches the top surface in a cross-sectional view perpendicular to the second direction DR2. The height H2 is, for example, 100 μm or more. The difference between the width W3 and the width W4 is, for example, greater than 0.03 times the height H2 and less than 0.09 times the height H2.

[0041] Note that, regarding the height of the wiring portion 22d, the thickness of the insulating coating layer 32, the distance between two adjacent wiring portions 22d, the width of the wiring portion 22d, the pitch between two adjacent wiring portions 22d, and the angle formed by the center line bisecting the width of the wiring portion 22d and the main surface 10b, for example, the same conditions as those for the wiring portion 21d are satisfied. Also, regarding the height, the width of the top surface, and the width of the bottom surface of the first conductive layer 24 included in the wiring portion 22d, for example, the same conditions as those for the first conductive layer 24 included in the wiring portion 21d are satisfied.

[0042] (Method for manufacturing the printed wiring board 100) The method for manufacturing the printed wiring board 100 will be described below.

[0043] FIG. 4 is a manufacturing process diagram of the printed wiring board 100. As shown in FIG. 4, the method for manufacturing the printed wiring board 100 includes a preparation step S1, an electroless plating step S2, a resist pattern formation step S3, a first electrolytic plating step S4, a resist pattern removal step S5, an etching step S6, a second electrolytic plating step S7, an insulating coating layer formation step S8, and a magnetic layer formation step S9.

[0044] In the preparation step S1, the base film 10 is prepared. On the main surface 10a and the main surface 10b of the base film 10 prepared in the preparation step S1, a first layer 23a is formed. Further, before the electroless plating step S2 is performed, through holes are formed in the base film 10 and the first layer 23a. The formation of the through holes is performed, for example, by laser processing or drilling. After the preparation step S1, the electroless plating step S2 is performed.

[0045] FIG. 5 is a cross-sectional view for explaining the electroless plating step S2. As shown in FIG. 5, in the electroless plating step S2, by performing electroless plating, a second layer 23b is formed on the first layer 23a. At this time, the second layer 23b is also formed on the inner wall surface of the through hole formed in the base film 10. After the electroless plating step S2, the resist pattern forming step S3 is performed.

[0046] FIG. 6 is a cross-sectional view for explaining the resist pattern forming step S3. As shown in FIG. 6, in the resist pattern forming step S3, first, a resist layer is formed on the underlying conductive layer 23 by overlapping and attaching a plurality of dry film resists 51. The number of the dry film resists 51 is not particularly limited, but is, for example, three.

[0047] Second, the above resist layer is exposed and developed. Thereby, the above resist layer is patterned to form a resist pattern 50. The resist pattern 50 has an opening 52. The underlying conductive layer 23 is exposed from the opening 52. The opening width of the opening 52 increases as it approaches the underlying conductive layer 23. Let the height of the resist pattern 50 be height H3. The height H3 is larger than the height H2. The height H3 is, for example, larger than 100 μm. After the resist pattern forming step S3, the first electrolytic plating step S4 is performed.

[0048] FIG. 7 is a cross-sectional view for explaining the first electrolytic plating step S4. As shown in FIG. 7, in the first electrolytic plating step S4, by performing electrolytic plating, a first conductive layer 24 is formed on the underlying conductive layer 23 exposed from the opening 52. After the first electrolytic plating step S4, a resist pattern removing step S5 is performed.

[0049] FIG. 8 is a cross-sectional view for explaining the resist pattern removing step S5. As shown in FIG. 8, in the resist pattern removing step S5, the resist pattern 50 is removed. After the resist pattern removing step S5, an etching step S6 is performed. FIG. 9 is a cross-sectional view for explaining the etching step S6. As shown in FIG. 9, in the etching step S6, the underlying conductive layer 23 under the resist pattern 50 is removed by etching. After the etching step S6, a second electrolytic plating step S7 is performed.

[0050] FIG. 10 is a cross-sectional view for explaining the second electrolytic plating step S7. As shown in FIG. 10, in the second electrolytic plating step S7, by performing electrolytic plating, a second conductive layer 25 is formed on the side surface of the underlying conductive layer 23, on the side surface of the first conductive layer 24, and on the top surface of the first conductive layer 24. The growth rate of the second conductive layer 25 by electroplating in the second electrolytic plating step S7 is faster as the position is farther from the main surface of the base film 10. Considering this point, since the width W4 is smaller than the width W3, it is suppressed that the width W1 becomes excessively larger than the width W2. After the second electrolytic plating step S7, an insulating coating layer forming step S8 is performed.

[0051] FIG. 11 is a cross-sectional view for explaining the insulating coating layer forming step S8. As shown in FIG. 11, in the insulating coating layer forming step S8, for example, by performing vapor deposition, an insulating coating layer 31 is formed on the main surface 10a so as to cover the wiring 21, and an insulating coating layer 32 is formed on the main surface 10b so as to cover the wiring 22. After the insulating coating layer forming step S8, a magnetic layer forming step S9 is performed.

[0052] In the magnetic layer forming step S9, a magnetic layer 41 is formed so as to cover the wiring 21 with the insulating coating layer 31 interposed therebetween, and a magnetic layer 42 is formed so as to cover the wiring 22 with the insulating coating layer 32 interposed therebetween. In the magnetic layer forming step S9, first, a resin material containing particles made of a ferromagnetic material is applied so as to cover the wiring 21 with the insulating coating layer 31 interposed therebetween, and is applied so as to cover the wiring 22 with the insulating coating layer 32 interposed therebetween. Second, the applied resin material is heated and cured to form the magnetic layer 41 and the magnetic layer 42. From the above, the structure of the printed wiring board 100 shown in FIGS. 1 to 3 is formed.

[0053] (Effect of the printed wiring board 100) The effects of the printed wiring board 100 will be described below.

[0054] By increasing the height H1, the cross-sectional area of the wiring portion 21d increases, and the electrical resistance value of the wiring portion 21d decreases. Further, when the height H1 is increased, the width of the wiring portion 21d increases and the interval SP1 decreases at the upper part of the wiring portion 21d where electroplating easily progresses when the second electroplating step S7 is performed. As a result, when the insulating coating layer forming step S8 is performed, it becomes difficult for the deposition species to reach the lower side surface of the wiring portion 21d, so that the thickness T1 becomes smaller than the thickness T2, and the thickness T2 has to be increased to ensure the thickness T1.

[0055] If the thickness T2 becomes too large, it becomes difficult to embed the magnetic layer 41 between two adjacent wiring portions 21d, and the volume of the magnetic layer 41 cannot be ensured.

[0056] In the printed wiring board 100, by making the width W4 smaller than the width W3, even when the height H1 is 100 μm or more, it is possible to suppress the width at the upper part of the wiring portion 21d from becoming excessively larger than the width at the lower part of the wiring portion 21d. More specifically, the width W1 can be set to 1.2 times or less the width W2, the interval SP2 can be set to 2 times or less the interval SP1, and the angle θ can be set to more than 85° and 90° or less.

[0057] As a result, in the case of the printed wiring board 100, when the insulating coating layer forming step S8 is performed, the deposition seeds can easily reach the side surface below the wiring portion 21d, and it is possible to ensure the uniformity of the thickness of the insulating coating layer 31 (more specifically, making the thickness T1 0.5 times or more of the thickness T2). As a result, while ensuring the thickness T1 (more specifically, while making the thickness T1 2 μm or more), it is possible to suppress the excessive increase in the thickness T2 and the difficulty of embedding the magnetic layer 41 between two adjacent wiring portions 21d.

[0058] When the width W4 is made smaller than the width W3, the area of the resist pattern 50 in contact with the underlying conductive layer 23 becomes smaller, and there is a concern about the collapse of the resist pattern 50. In this regard, by making the difference between the width W4 and the width W3 larger than 0.03 times the height H2 and smaller than 0.09 times the height H2, it is possible to suppress the excessive increase in the width at the upper part of the wiring portion 21d compared to the width at the lower part of the wiring portion 21d while suppressing the collapse of the resist pattern 50.

[0059] When attempting to form the resist layer with a single dry film resist 51 in the resist pattern forming step S3, the thickness of the single dry film resist 51 exceeds 100 μm, and the thickness variation becomes large. Therefore, by forming the resist layer with a plurality of laminated dry film resists 51, it is possible to suppress the variation in the height H2 for each wiring portion 21d.

[0060] (Example) As samples of the printed wiring board, samples 1 to 9, samples 10 to 18, and samples 19 to 26 were prepared. Although not shown in Tables 1 to 3, in samples 1 to 26, the height H2 was 100 μm or more, and the value obtained by dividing the sum of the width W1 and the width W2 by 2 was 0.75 times or more of the pitch P.

[0061] In Samples 1 to 7, as shown in Table 1, the interval SP1 was 5 μm or more and 1.2 times or more the thickness T2. On the other hand, in Samples 8 and 9, neither the condition that the interval SP1 was 5 μm or more nor the condition that the interval SP1 was 1.2 times or more the thickness T2 was satisfied.

[0062] In Samples 1 to 7, the thickness T1 was 2 μm or more and 0.5 times or more the thickness T2. On the other hand, in Samples 8 and 9, at least one of the conditions that the thickness T1 was 2 μm or more and that the thickness T1 was 0.5 times or more the thickness T2 was not satisfied. From this, it became clear that by setting the interval SP1 to 5 μm or more and 1.2 times or more the thickness T2, it is possible to ensure the thickness T1 while ensuring the uniformity of the thickness of the insulating coating layer 31.

[0063]

Table 1

[0064] In Samples 10 to 16, as shown in Table 2, the interval SP2 was 2 times or less the interval SP1. Also, in Samples 10 to 16, the width W1 was 1.2 times or less the width W2. On the other hand, in Samples 17 and 18, neither the condition that the interval SP2 was 2 times or less the interval SP1 nor the condition that the width W1 was 1.2 times or less the width W2 was satisfied.

[0065] Also, in Samples 10 to 16, the thickness T1 was 2 μm or more and 0.5 times or more the thickness T2. In Samples 17 and 18, neither the condition that the interval SP1 was 2 μm or more nor the condition that the interval SP1 was 1.2 times or more the thickness T2 was satisfied. From this, it became clear that by setting the interval SP2 to 2 times or less the interval SP1 and setting the width W1 to 1.2 times or less the width W2, it is possible to ensure the thickness T1 while ensuring the uniformity of the thickness of the insulating coating layer 31.

[0066]

Table 2

[0067] From Sample 19 to Sample 25, as shown in Table 3, the difference between the width W3 and the width W4 was 0.03 times or more of the height H2. On the other hand, in Sample 26, the difference between the width W3 and the width W4 did not satisfy the condition of being 0.03 times or more of the height H2.

[0068] Also, from Sample 19 to Sample 25, the thickness T1 was 2 μm or more and 0.5 times or more of the thickness T2. On the other hand, in Sample 26, the interval SP1 being 2 μm or more and the interval SP1 being 1.2 times or more of the thickness T2 were not satisfied. From this, it became clear that by setting the difference between the width W3 and the width W4 to be 0.03 times or more of the height H2, it is possible to secure the thickness T1 while ensuring the uniformity of the thickness of the insulating coating layer 31.

[0069]

Table 3

[0070] All of the embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present invention is shown not by the above embodiments but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Reference Numerals

[0071] 10 Base film, 10a Main surface, 10b Main surface, 21 Wiring, 21a Winding portion, 21b, 21c Lands, 21d Wiring portion, 22 Wiring, 22a Winding portion, 22b, 22c Lands, 22d Wiring portion, 23 Underlying conductive layer, 23a First layer, 23b Second layer, 24 First conductive layer, 25 Second conductive layer, 31, 32 Insulating coating layers, 41, 42 Magnetic layers, 50 Resist pattern, 51 Dry film resist, 52 Opening, 100 Printed wiring board, DR1 First direction, DR2 Second direction, DR3 Third direction, H1, H2, H3 Height, P pitch, S1 preparation process, S2 electroless plating process, S3 resist pattern formation process, S4 first electroplating process, S5 resist pattern removal process, S6 etching process, S7 second electroplating process, S8 insulating coating layer formation process, S9 magnetic layer formation process, SP1, SP2 intervals, T1, T2 thicknesses, W1, W2, W3, W4 widths.

Claims

1. a base film having a main surface, wiring disposed on the main surface, and an insulating coating layer, wherein the normal direction of the main surface is along a first direction, the height of the wiring is more than 100 μm, the wiring has a winding portion, the wiring is wound in a spiral shape when viewed along the first direction at the winding portion, the winding portion has a plurality of wiring portions in a cross-sectional view perpendicular to a second direction perpendicular to the first direction, each of the plurality of wiring portions extends along the second direction, in a cross-sectional view perpendicular to the second direction, the plurality of wiring portions are arranged at intervals along a third direction perpendicular to the first direction and the second direction, the insulating coating layer is disposed on the main surface so as to cover the wiring, the plurality of wiring portions have a first wiring portion, a first thickness, which is the minimum value of the thickness of the insulating coating layer covering the side surface of the first wiring portion, is 0.5 times or more and 2 μm or more of a second thickness, which is the thickness of the insulating coating layer covering the top surface of the first wiring portion, the plurality of wiring portions have a second wiring portion adjacent to the first wiring portion in the third direction, a printed wiring board, wherein a minimum value of a distance between an upper half of the first wiring portion and an upper half of the second wiring portion is 5 μm or more and 1.2 times or more of the second thickness.

2. The printed wiring board according to claim 1, wherein a minimum value of a distance between an upper half of the first wiring portion and an upper half of the second wiring portion is 2 times or less of a distance at a bottom surface between the first wiring portion and the second wiring portion.

3. The printed wiring board according to claim 1, wherein a maximum value of a width of an upper half of the first wiring portion is 1.2 times or less of a width at a bottom surface of the first wiring portion.

4. The printed wiring board according to claim 1, wherein a value obtained by dividing a sum of a maximum value of a width of an upper half of the first wiring portion and a width at a bottom surface of the first wiring portion by 2 is 0.75 times or more of a pitch between the first wiring portion and the second wiring portion.

5. The printed wiring board according to claim 1, wherein an angle formed between a center line that bisects a width of the first wiring portion and the main surface in a cross-sectional view perpendicular to the second direction is greater than 85° and equal to or less than 90°.

6. The printed wiring board according to claim 1, wherein a constituent material of the insulating coating layer contains parylene.

7. further comprising a magnetic layer The printed wiring board according to claim 1, wherein the magnetic layer is disposed on the main surface so as to cover the wiring with the insulating coating layer interposed therebetween.

8. A base film having a main surface, Wiring disposed on the main surface, And an insulating coating layer, The normal direction of the main surface is along a first direction, The height of the wiring is more than 100 μm, The wiring has a winding portion, The wiring is wound in a spiral shape when viewed along the first direction at the winding portion, The winding portion has a plurality of wiring portions in a cross-sectional view perpendicular to a second direction perpendicular to the first direction, Each of the plurality of wiring portions extends along the second direction, In a cross-sectional view perpendicular to the second direction, the plurality of wiring portions are arranged at intervals along a third direction perpendicular to the first direction and the second direction, The insulating coating layer is disposed on the main surface so as to cover the wiring, The plurality of wiring portions have a first wiring portion, A first thickness, which is the minimum value of the thickness of the insulating coating layer covering the side surface of the first wiring portion, is 0.5 times or more and 2 μm or more of a second thickness, which is the thickness of the insulating coating layer covering the top surface of the first wiring portion, Each of the plurality of wiring portions has a base conductive layer on the main surface, a first conductive layer on the base conductive layer, and a second conductive layer covering the side surfaces of the base conductive layer, the side surfaces of the first conductive layer, and the top surface of the first conductive layer, The height of the first conductive layer is 100 μm or more, A first width, which is the width of the lower surface of the first conductive layer in the third direction, is larger than a second width, which is the width of the top surface of the first conductive layer in the third direction, A printed wiring board in which the difference between the first width and the second width is larger than 0.03 times and smaller than 0.09 times the height of the first conductive layer.

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