Semiconductor device and semiconductor component using the same

Abstract

This semiconductor device comprises: a substrate (101); a first nitride semiconductor layer (103) on the substrate; a second nitride semiconductor layer (104) on the first nitride semiconductor layer; finger-shaped source electrodes (105) on the second nitride semiconductor layer; finger-shaped drain electrodes (106) disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes (107) respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring (117), a plurality of second gate integrated wirings (118), and a third gate integrated wiring (119), to gate pads (113) located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device using a nitride semiconductor such as gallium nitride (GaN) as a semiconductor material and a semiconductor component using the same.

Background Art

[0002] In recent years, commercialization of a gallium nitride field-effect transistor (GaN-FET), which is a nitride semiconductor used as a power transistor for switching, has been progressing. As a GaN-FET, a structure is generally used in which a GaN layer is formed as a channel layer and AlGaN is formed as a barrier layer on a semiconductor substrate, and a two-dimensional electron gas generated by spontaneous polarization and piezoelectric polarization at a hetero-junction interface formed by these two layers is used as a channel.

[0003] The GaN-FET has low loss and can perform high-speed switching operation compared to SiC and the like, and miniaturization at the system level is expected. In a GaN-FET having such a structure, a channel current flows in a direction parallel to the substrate. As a result, source pads, drain pads, and gate pads for supplying a voltage or flowing a current from an external power source through a wire or the like to the FET are all formed on the surface side of the substrate. The source electrode, drain electrode, and gate electrode of the transistor in the active region are electrically connected to each pad through respective lead wires or aggregated wires. In order to improve the high-speed switching characteristics of GaN, it is necessary to make the resistance of the gate aggregated wiring sufficiently small in order to increase the gate current supplied to the gate electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the layout of a conventional GaN-FET, the aggregated wiring of the gate electrode was led out to the gate pad using a thin and narrow gate aggregated wiring electrode. Also in Patent Document 1, the gate electrodes are bundled outside the active region via the gate lead-out wiring, and further bypass the outer periphery of the active region and are connected to the gate electrode pad layer via the gate aggregated wiring. As a result, as the number of unit transistors included in the power transistor increases for higher output, the wiring length of the gate electrode from each unit transistor to the gate pad, which usually exists one or two in the nitride semiconductor device, becomes longer, and there is a problem that the gate wiring resistance increases. Therefore, especially for high-power applications, when the chip size is large and the wiring length of the gate aggregated wiring becomes long, the gate aggregated wiring resistance increases, and there is room for improvement in the high-speed switching characteristics.

[0006] In view of the above problems, the main object of the present disclosure is to provide a semiconductor device suitable for high-speed switching operation and a semiconductor component using the same, which can reduce the gate aggregated wiring resistance while reducing the chip size by alternately forming the gate aggregated wiring and the source wire pad in the gate aggregated wiring.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] To solve the above problems, a semiconductor device according to an aspect of the present disclosure includes a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and spaced apart from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, and a third gate aggregation wiring extending in the first direction. The drain electrode is electrically connected to the drain pad via the drain lead wiring. The source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring. The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring. The plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction and and the third gate integrated wiring and the gate pad are thicker than the first and second gate integrated wirings 。

[0009] Also, a semiconductor component according to an aspect of the present disclosure includes the above semiconductor device and a lead frame. The lead frame has a die pad portion to which the semiconductor device is fixed, a source terminal, a gate terminal, and a drain terminal. The source pad and the source terminal, the gate pad and the gate terminal, and the drain pad and the drain terminal are electrically connected to each other via bonding wires.

Effects of the Invention

[0010] According to the present disclosure, it is possible to reduce the gate aggregation wiring resistance while reducing the chip size.

Brief Description of the Drawings

[0011]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7A

Figure 7B

Figure 8A

Figure 8B

Figure 9

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that all of the embodiments described below show comprehensive or specific examples. Numerical values, shapes, materials, components, arrangement positions of components, connection forms, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Also, the implementation forms of the present disclosure are not limited to the current independent claims and can also be expressed by other independent claims.

[0013] (Embodiment 1) FIG. 1A is a plan view of a nitride semiconductor device according to Embodiment 1. FIG. 1B is a cross-sectional view taken along line Ib-Ib in FIG. 1A.

[0014] The semiconductor devices of FIGS. 1A and 1B include a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a source electrode 105, a drain electrode 106, a gate electrode 107, an active region 108, a source lead wiring 109, a drain lead wiring 110, a source pad 112, a drain pad 113, a gate pad 114, a source aggregation wiring 115, a first gate aggregation wiring 117, a second gate aggregation wiring 118, and a third gate aggregation wiring 119.

[0015] As shown in Fig. 1B, on a substrate 101 (which may be a substrate such as Si, Sapphire, SiC, GaN, AlN, etc.), there is a buffer layer 102 (for example, a single layer or multiple layers of group III nitride semiconductors such as GaN, AlGaN, AlN, InGaN, AlInGaN, etc.), and on top of that, there is a first nitride semiconductor layer 103 made of GaN (alternatively, it may also be, for example, InGaN, AlGaN, AlInGaN, etc., which are group III nitride semiconductors). On top of that, a second nitride semiconductor layer 104 made of AlGaN (alternatively, it may also be, for example, GaN, InGaN, AlGaN, AlN, AlInGaN, etc., which are group III nitride semiconductors) is formed. The second nitride semiconductor layer 104 has a larger bandgap than the first nitride semiconductor layer 103. When the second nitride semiconductor layer 104 is AlGaN and the first nitride semiconductor layer 103 is GaN, due to the effects of piezo-polarization and spontaneous polarization generated from the lattice constant difference between AlGaN and GaN, a high-concentration two-dimensional electron gas (2DEG) layer is formed on the GaN layer side near the AlGaN / GaN interface. The region where this two-dimensional electron gas is formed is the active region 108 in Fig. 1A. On the second nitride semiconductor layer 104, a source electrode 105 and a drain electrode 106 are formed separately. The source electrode 105 and the drain electrode 106 are composed of an electrode formed by combining one or more metals such as Ti, Al, Mo, Hf, etc., which have ohmic contact with any of the two-dimensional electron gas layer, the second nitride semiconductor layer 104, and the first nitride semiconductor layer 103, and it is only necessary to be electrically connected to the two-dimensional electron gas layer in the active region 108. For example, it may be formed on the surface of the second nitride semiconductor layer 104, or it may be in contact with a part of the two-dimensional electron gas layer, the second nitride semiconductor layer 104, and the first nitride semiconductor layer 103 using known ohmic resistor technology. A gate electrode 107 is formed on the second nitride semiconductor layer 104 between the source electrode 105 and the drain electrode 106. The gate electrode 107 may be an electrode formed by combining one or more metals such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, Zr, etc.

[0016] A p-type nitride semiconductor layer containing a p-type impurity (such as Mg, Zn, C, etc.) may be formed between at least one of the source electrode 105, the drain electrode 106, and the gate electrode 107 and the second nitride semiconductor layer 104. Further, at least one of the source electrode 105, the drain electrode 106, and the gate electrode 107 may be formed so as to be in direct contact with the p-type nitride semiconductor layer and the second nitride semiconductor layer 104. Source lead wirings 109 and drain lead wirings 110 made of, for example, Au or Al are formed on the source electrode 105 and the drain electrode 106, respectively.

[0017] As shown in FIG. 1A, when viewed in a plan view, finger-shaped source electrodes 105 and drain electrodes 106 are formed separately on the second nitride semiconductor layer, a finger-shaped gate electrode 107 is formed between the source electrode 105 and the drain electrode 106, and the drain electrode 106 is connected to a drain pad 113 via a drain lead wiring 110. The source electrode 105 is electrically connected to a plurality of source pads 112 via a source lead wiring 109 and a source aggregation wiring 115 extending in a direction perpendicular to the finger direction. Here, the finger direction refers to the longitudinal direction of the finger-shaped gate electrode. Hereinafter, the direction perpendicular to the finger direction may be referred to as the first direction.

[0018] The gate electrode 107 is electrically connected to a gate pad 114 located at both ends or one end of the third gate integrated wiring 119 via a first gate integrated wiring 117 extending in a first direction perpendicular to the finger direction, a plurality of second gate integrated wirings 118, and a third gate integrated wiring 119 extending in the first direction. The plurality of source pads 112 and the second gate integrated wirings 118 are alternately formed in the first direction. The wiring width of each second gate integrated wiring 118 in the first direction can preferably be 50 μm to 1000 μm. The gate electrode 107, the first gate integrated wiring 117, the second gate integrated wiring 118, and the third gate integrated wiring 119 may be formed simultaneously with the same metal composition. Also, an ESD protection element 120 using a transistor-type diode for preventing ESD breakdown is formed near the gate pad 114. The anode of the ESD protection element 120 is electrically connected to the source integrated wiring 115, and the cathode is electrically connected to the gate pad 114 (not shown).

[0019] Here, the source extraction wiring 109 and the drain extraction wiring 110 each serve to extract current and / or voltage from the source electrode 105 and the drain electrode 106 of the finger portion of the active region 108. Also, the first to third gate integrated wirings 117, 118, 119 and the source integrated wiring 115 each serve to aggregate the current and / or voltage extracted from the gate electrode 107 and the source extraction wiring 109. Also, the source pad 112, the drain pad 113, and the gate pad 114 are electrically connected to electrical contacts on the leads of the lead frame via bonding wires.

[0020] With the above configuration, compared to the case of supplying a gate current from a gate pad to a gate electrode in an active region through a thin and single gate-integrated wiring extending in a first direction as in Patent Document 1, a gate current can be supplied through a plurality of second gate-integrated wirings 118 and a third gate-integrated wiring 119 having a wide width extending in the first direction. Therefore, the electrical resistance from the gate pad 114 to the gate electrode 107 becomes smaller, and a larger gate current can be supplied. Generally, the switching speed (dV / dt, dI / dt) of turning on a transistor increases as the gate current increases. Therefore, according to the present disclosure, a high-speed switching operation becomes possible, and miniaturization at the system level becomes possible. In addition, since the inductance of the entire gate-integrated wiring also decreases, parasitic oscillation due to the formation of a positive feedback circuit can be suppressed, the parameter margin of an RC circuit composed of a parallel circuit of R and C (speed-up capacitor) in the gate input section can be improved, and the degree of freedom in designing a drive circuit and a layout can be improved. Further, since the gate current can be increased, it becomes possible to flow a large pulse current of several 100 μs or less through the gate in the product inspection process. As a result, a screening test for removing defects caused by crystal defects in the vicinity of the gate electrode 107 becomes possible, and the product quality can be improved. In addition, by reducing the resistance of the gate-integrated wiring, the occurrence of a so-called electromigration phenomenon in which metal atoms move by flowing a current through the integrated wiring can be suppressed, and the product life can be improved.

[0021] Next, Modification 1 of Embodiment 1 will be described.

[0022] FIG. 2 is a plan view of a semiconductor device according to Modification Example 1 of Embodiment 1. As shown in FIG. 2, the third gate-integrated wiring 219 and the gate pad 214 can be formed of a material thicker than the first and second gate-integrated wirings 217 and 218. For example, the third gate-integrated wiring 219 and the gate pad 214 may be formed of the same metal as the source-integrated wiring 215, for example, formed of Au or Cu. The third gate-integrated wiring 219 and the gate pad 214 are each electrically connected to a plurality of second gate-integrated wirings 218. Thereby, while reducing the chip size, the resistance of the gate-integrated wiring can be further reduced.

[0023] Next, Modification Example 2 of Embodiment 1 will be described.

[0024] FIG. 3 is a plan view of a semiconductor device according to Modification Example 2 of Embodiment 1. As shown in FIG. 3, each source pad 312 can be electrically connected via a plurality of source pad connection portions 324. Each source pad connection portion 324 can be formed of the same material as the source pad 312 and the source-integrated wiring 315 via an interlayer film such as SiO2 or SiN on the upper part of each second gate-integrated wiring 318, and is electrically insulated from each second gate-integrated wiring 318. Since a capacitance is formed via the interlayer film in the overlapping portion between the second gate-integrated wiring 318 and the source pad connection portion, the gate-source capacitance (Cgs) increases. Generally, when the ratio Cgs / Cgd of the gate-drain capacitance Cgd and the gate-source capacitance Cgs of the FET is small due to the change dv / dt of the voltage with respect to time during switching, a voltage is generated at the gate, causing a self-turn-on phenomenon, and this malfunction may lead to destruction. According to the configuration of the present disclosure, it is possible to improve the Cgs / Cgd ratio while reducing the resistance of the entire gate-integrated wiring, and prevent self-turn-on.

[0025] Next, Modification Example 3 of Embodiment 1 will be described.

[0026] FIG. 4 is a plan view of the semiconductor device according to Modification Example 3 of Embodiment 1. As shown in FIG. 4, the gate pad 414 can be formed in the finger direction rather than the source pad 412. Thereby, while reducing the gate-integrated wiring resistance, the degree of freedom in the package design of the gate wire on the semiconductor chip side can be improved. Further, by separating the source pad 412 region, wire bonding can be performed with a high yield.

[0027] Also, in the present embodiment, the source pad 412 is connected to the source terminal of the lead frame via a bonding wire, and the source pad 412, the drain pad 413, and the gate pad 414 are substantially at the same height. If the pad heights are different, the pressing load when the bonding tool descends fluctuates, and the bonding pads, the interlayer film thereunder, and the nitride semiconductor layer are damaged due to the impact load on the bonding pads. Therefore, it is necessary to adjust the pressing of the bonding load. However, by making each pad substantially the same height as in the present embodiment, such adjustment of the pressing of the bonding load becomes unnecessary.

[0028] Next, a specific example of the gate-integrated wiring will be described.

[0029] FIG. 5 is an enlarged view of the gate-integrated wiring of the semiconductor device in Embodiment 1. As shown in FIG. 5, a plurality of slits 523 are formed in the first, second, or third gate-integrated wirings 517, 518, 519. Preferably, in the finger direction, the width of the slit is 0.1 μm to 3.0 μm and the interval between the slits is 1 μm to 10 μm, and in the direction perpendicular to the finger, the width of the slit is 3 μm to 40 μm and the interval between the slits is 1.0 μm to 10 μm. By adopting such a slit configuration, while reducing the gate-integrated wiring resistance, stress dispersion to the integrated wiring becomes possible. For example, plastic deformation of the integrated wiring metal when thermal stress is applied can be alleviated, and also, occurrence of cracks due to compressive stress from the PKG resin or generation of a plurality of stress concentration points at the ends of the integrated wiring and their close coupling can be prevented. Each slit may be configured in a lattice shape, a staggered shape, or any other arbitrary shape.

[0030] As described above, the semiconductor device according to Embodiment 1 includes a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and separated from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, and a third gate aggregation wiring extending in the first direction. The drain electrode is electrically connected to the drain pad via the drain lead wiring. The source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring. The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring. The plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction.

[0031] According to this, the gate wiring resistance can be reduced, that is, the resistance components of the first to third gate aggregation wirings can be made small, and a high-speed switching operation can be facilitated. Also, it enables reduction of the chip size as a semiconductor device.

[0032] For example, the gate electrode, the first gate aggregation wiring, the second gate aggregation wiring, and the third gate aggregation wiring may be formed of the same metal configuration.

[0033] According to this, the gate wiring resistance can be further reduced.

[0034] For example, the third gate-integrated wiring and the gate pad may be formed of a material thicker than the first and second gate-integrated wirings.

[0035] According to this, the gate wiring resistance can be further reduced.

[0036] For example, the semiconductor device may further include a source pad connection portion, and adjacent source pads among the plurality of source pads may be electrically connected via the source pad connection portion.

[0037] According to this, while reducing the resistance of the entire gate wiring, the Cgs / Cgd ratio (that is, the ratio of the gate-drain capacitance Cgd to the gate-source capacitance Cgs) can be improved, and self-turn-on can be suppressed.

[0038] For example, the source pad, the drain pad, and the gate pad may be substantially at the same height with respect to the substrate.

[0039] According to this, the degree of freedom in arranging the gate wire can be improved.

[0040] For example, the source pad may be a pad for bonding a bonding wire.

[0041] According to this, since the source-integrated wiring and the source pad are not connected by a via, the manufacturing process can be simplified.

[0042] For example, the source pad, the drain pad, and the gate pad may be substantially at the same height with respect to the substrate.

[0043] According to this, damage due to wire bonding can be suppressed.

[0044] For example, the gate-integrated wiring may have a plurality of slits.

[0045] According to this, the occurrence of cracks can be suppressed.

[0046] For example, in a plan view of the semiconductor device, in the longitudinal direction, the width of the slit may be 0.1 μm to 3.0 μm and the interval between the slits may be 1 μm to 10 μm, and in the first direction, the width of the slit may be 3 μm to 40 μm and the interval between the slits may be 1.0 μm to 10 μm.

[0047] According to this, the occurrence of cracks can be suppressed.

[0048] (Embodiment 2) FIG. 6A is a plan view of the nitride semiconductor device of Embodiment 2. FIG. 6B is a cross-sectional view taken along line VIb-VIb in FIG. 6A.

[0049] As shown in FIG. 6B, on a substrate 601 (which may be a substrate such as Si, Sapphire, SiC, GaN, AlN, etc.), there is a buffer layer 602 (for example, a single layer or multiple layers of GaN, AlGaN, AlN, InGaN, AlInGaN, etc., which are group III nitride semiconductors). On top of that, there is a first nitride semiconductor layer 603 made of GaN (alternatively, it may also be, for example, InGaN, AlGaN, AlInGaN, etc., which are group III nitride semiconductors). On top of that, a second nitride semiconductor layer 604 made of AlGaN is formed (alternatively, it may also be, for example, GaN, InGaN, AlGaN, AlN, AlInGaN, etc., which are group III nitride semiconductors). The second nitride semiconductor layer 604 has a larger bandgap than the first nitride semiconductor layer 603. When the second nitride semiconductor layer 604 is AlGaN and the first nitride semiconductor layer 603 is GaN, due to the effects of piezoelectric polarization and spontaneous polarization generated from the lattice constant difference between AlGaN and GaN, a high-concentration two-dimensional electron gas (2DEG) layer (not shown) is formed on the GaN layer side near the AlGaN / GaN interface. The region where this two-dimensional electron gas is formed is the active region 608 in FIG. 6A. The active region 608 includes a long finger portion with a long finger length of the transistor and a short finger portion with a short finger length of the transistor. On the second nitride semiconductor layer 604, a source electrode 605 and a drain electrode 606 are formed separately. The source electrode 605 and the drain electrode 606 are composed of an electrode formed by combining one or two or more metals such as Ti, Al, Mo, Hf, etc., which have an ohmic contact with any of the two-dimensional electron gas layer, the second nitride semiconductor layer 604, and the first nitride semiconductor layer 603, as long as they are electrically connected to the two-dimensional electron gas layer in the active region 608. For example, it may be formed on the surface of the second nitride semiconductor layer 604, or it may be in contact with a part of the two-dimensional electron gas layer, the second nitride semiconductor layer 604, and the first nitride semiconductor layer 603 using a known ohmic recess technology (not shown). A gate electrode 607 is formed on the second nitride semiconductor layer 604 between the source electrode 605 and the drain electrode 606.The gate electrode 607 may be an electrode formed by combining one or two or more of metals such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, and Zr.

[0050] A p-type nitride semiconductor layer containing p-type impurities (such as Mg, Zn, and C) may be formed between at least one of the source electrode 605, the drain electrode 606, and the gate electrode 607 and the second nitride semiconductor layer 604. Also, at least one of the source electrode 605, the drain electrode 606, and the gate electrode 607 may be formed so as to be in direct contact with the p-type nitride semiconductor layer and the second nitride semiconductor layer 604 (not shown). On the source electrode 605 and the drain electrode 606, source extraction wirings 609 and drain extraction wirings 610 made of, for example, Au or Al are formed, respectively.

[0051] As shown in FIG. 6A, when viewed in a plan view, finger-shaped source electrodes 605 and drain electrodes 606 with long finger lengths in the long finger portions and short finger lengths in the short finger portions are formed separately on the second nitride semiconductor layer. A finger-shaped gate electrode 607 with a long finger length in the long finger portion and a short finger length in the short finger portion is formed between the source electrode 605 and the drain electrode 606. The drain electrode 606 is connected to a drain pad 613 via a drain extraction wiring 610. The source electrode 605 is electrically connected to a plurality of source pads 612 via a source extraction wiring 609 and a source aggregation wiring extending in a first direction. The source aggregation wiring is electrically connected to the source electrodes 605 in both the long finger portion and the short finger portion. At the boundary between the long finger portion and the short finger portion, the source aggregation wiring is formed to extend so as to surround the outer periphery of the active region 608 in the long finger portion.

[0052] The gate electrode 607 is electrically connected to a gate pad 614 located at both ends or one end of a third gate aggregated wiring 619 via a first gate aggregated wiring 617 extending in a first direction, a plurality of second gate aggregated wirings 618, and a third gate aggregated wiring 619 extending in the first direction. The plurality of source pads 612 and the second gate aggregated wirings 618 are alternately formed in the first direction. Similar to the source aggregated wiring, the first gate aggregated wiring 617 is electrically connected to the gate electrodes 607 of both the long finger portion and the short finger portion. At the boundary between the long finger portion and the short finger portion, the first gate aggregated wiring 617 is formed to extend so as to surround the outer periphery of the active region 608 of the long finger portion. The wiring width in the first direction of each second gate aggregated wiring 618 can preferably be 50 μm to 1000 μm. The gate electrode 607, the first gate aggregated wiring 617, the second gate aggregated wiring 618, and the third gate aggregated wiring 619 may be simultaneously formed with the same metal configuration. Also, an ESD protection element 620 using a transistor-type diode for preventing ESD breakdown is formed near the gate pad 614. The source aggregated wiring, the ESD protection element 620, and the gate pad 614 are arranged in this order in a direction opposite to the finger direction from the short finger portion. The anode 621 of the ESD protection element 620 is electrically connected to the source aggregated wiring, and the cathode 622 of the ESD protection element 620 is electrically connected to the gate pad 614.

[0053] Here, the source extraction wiring 609 and the drain extraction wiring 610 each serve to extract current and / or voltage from the source electrode 605 and the drain electrode 606 of the finger portion of the active region 608. Also, the first to third gate aggregated wirings 617, 618, 619 and the source aggregated wiring 615 each serve to aggregate the current and / or voltage extracted from the gate electrode 607 and the source extraction wiring 609. Also, the source pad 612, the drain pad 613, and the gate pad 614 are electrically connected to the electrical contacts on the leads of the lead frame via bonding wires.

[0054] With the above configuration, compared to the case of supplying a gate current from a gate pad to a gate electrode of an active region through a thin and single gate aggregated wiring extending in a first direction as in Patent Document 1, a gate current can be supplied through a plurality of second gate aggregated wirings 618 and a third gate aggregated wiring 619 having a wide width extending in the first direction. Therefore, the electrical resistance from the gate pad 614 to the gate electrode 607 becomes small, and a larger gate current can be supplied. Further, by dividing the active region 608 into a long finger portion and a short finger portion and making the non-active region space-saving, the chip size can be further reduced while further reducing the gate aggregated wiring resistance. Since the configuration example of the subsequent gate aggregated wiring is the same as that of Embodiment 1, the description thereof is omitted.

[0055] As described above, the semiconductor device according to Embodiment 2 includes a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and separated from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead-out wiring, a plurality of source pads, a source lead-out wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, a third gate aggregation wiring extending in the first direction, an active region, and an ESD protection element. The drain electrode is electrically connected to the drain pad via the drain lead-out wiring. The source electrode is electrically connected to the plurality of source pads via the source lead-out wiring and the source aggregation wiring. The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring. The plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction. The active region includes a long finger portion and a short finger portion. The source aggregation wiring, the ESD protection element, and the gate pad are arranged in this order from the short finger portion in the longitudinal direction. The anode of the ESD protection element is electrically connected to the source aggregation wiring, and the cathode of the ESD protection element is electrically connected to the gate pad.

[0056] According to this, the gate wiring resistance can be reduced, and a high-speed switching operation can be facilitated. Further, the source aggregation wiring that supplies power to the ESD protection element can be reduced, enabling reduction of the chip size.

[0057] (Embodiment 3) FIG. 7A is a plan view of the nitride semiconductor device according to Embodiment 3. FIG. 7B is a cross-sectional view of FIG. 7A.

[0058] As shown in FIG. 7B, on a substrate 701 (which may be a substrate such as Si, Sapphire, SiC, GaN, AlN, etc.), there is a buffer layer 702 (for example, a single layer or multiple layers of GaN, AlGaN, AlN, InGaN, AlInGaN, etc., which are group III nitride semiconductors). On top of that, there is a first nitride semiconductor layer 703 made of GaN (alternatively, it may also be, for example, InGaN, AlGaN, AlInGaN, etc., which are group III nitride semiconductors). On top of that, a second nitride semiconductor layer 704 made of AlGaN is formed (alternatively, it may also be, for example, GaN, InGaN, AlGaN, AlN, AlInGaN, etc., which are group III nitride semiconductors). The second nitride semiconductor layer 704 has a larger bandgap than the first nitride semiconductor layer 703. When the second nitride semiconductor layer 704 is AlGaN and the first nitride semiconductor layer 703 is GaN, due to the effects of piezoelectric polarization and spontaneous polarization generated from the lattice constant difference between AlGaN and GaN, a high-concentration two-dimensional electron gas (2DEG) layer (not shown) is formed on the GaN layer side near the AlGaN / GaN interface. The region where this two-dimensional electron gas is formed is the active region 708 in FIG. 7A. On top of the second nitride semiconductor layer 704, a source electrode 705 and a drain electrode 706 are formed separately. The source electrode 705 and the drain electrode 706 are composed of an electrode formed by combining one or more metals such as Ti, Al, Mo, Hf, etc., which make ohmic contact with any of the two-dimensional electron gas layer, the second nitride semiconductor layer 704, and the first nitride semiconductor layer 703, as long as they are electrically connected to the two-dimensional electron gas layer in the active region 708. For example, it may be formed on the surface of the second nitride semiconductor layer 704, or it may be in contact with a part of the two-dimensional electron gas layer, the second nitride semiconductor layer 704, and the first nitride semiconductor layer 703 using a known ohmic recess technology (not shown). A gate electrode 707 is formed on the second nitride semiconductor layer 704 between the source electrode 705 and the drain electrode 706. The gate electrode 707 may be an electrode formed by combining one or more metals such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, Zr, etc.

[0059] A p-type nitride semiconductor layer containing a p-type impurity (such as Mg, Zn, C, etc.) may be formed between at least one of the source electrode 705, the drain electrode 706, and the gate electrode 707 and the second nitride semiconductor layer 704. Also, at least one of the source electrode 705, the drain electrode 706, and the gate electrode 707 may be formed so as to be in direct contact with the p-type nitride semiconductor layer and the second nitride semiconductor layer 704 (not shown). On the source electrode 705 and the drain electrode 706, source lead wirings 709 and drain lead wirings 710 made of, for example, Au or Al are formed, respectively.

[0060] As shown in FIG. 7A, when viewed in a plan view, finger-shaped source electrodes 705 and drain electrodes 706 are formed separately on the second nitride semiconductor layer, a finger-shaped gate electrode 707 is formed between the source electrode 705 and the drain electrode 706, and the drain electrode 706 is connected to a drain pad 713 via a drain lead wiring 710. The source electrode 705 is electrically connected to a plurality of source pads 712 via a source lead wiring 709 and a source aggregation wiring 715 extending in a first direction.

[0061] The gate electrode 707 is electrically connected to a gate pad 714 located at both ends or one end of the third gate integrated wiring 719 via a first gate integrated wiring 717 extending in a first direction, a plurality of second gate integrated wirings 718, and a third gate integrated wiring 719 extending in the first direction. The plurality of source pads 712 and the second gate integrated wirings 718 are alternately formed in the first direction. The wiring width of each second gate integrated wiring 718 in the first direction can preferably be 50 μm to 7000 μm. The gate electrode 707, the first gate integrated wiring 717, the second gate integrated wiring 718, and the third gate integrated wiring 719 may be formed simultaneously with the same metal composition. Also, an ESD protection element 720 using a transistor-type diode for preventing ESD breakdown is formed between each second gate integrated wiring 718 and each source pad 712 and near the gate pad 714. The ESD protection element 720 is electrically connected to an anode 721 source integrated wiring and a cathode 722 gate integrated wiring. In FIG. 7A, the cathode 722 is electrically connected to the third gate integrated wiring 719, but it may be electrically connected to at least one of the first, second, or third gate integrated wirings 717, 718, 719.

[0062] Here, the source extraction wiring 709 and the drain extraction wiring 710 each serve to extract current and / or voltage from the source electrode 705 and the drain electrode 706 of the finger portion of the active region 708. Also, the first to third gate integrated wirings 717, 718, 719 and the source integrated wiring 715 each serve to aggregate the current and / or voltage extracted from the gate electrode 707 and the source extraction wiring 709. Also, the source pad 712, the drain pad 713, and the gate pad 714 are electrically connected to electrical contacts on the leads of the lead frame via bonding wires.

[0063] With the above configuration, compared to the case of supplying a gate current from a gate pad to a gate electrode of an active region through a thin and narrow single gate-integrated wiring extending in the first direction as in Patent Document 1, a gate current can be supplied through a plurality of second gate-integrated wirings 718 and a third gate-integrated wiring 719 having a wide width extending in the first direction. Therefore, the electrical resistance from the gate pad 714 to the gate electrode 707 becomes smaller, and a larger gate current can be supplied. Further, by forming the ESD protection element 720 between each second gate-integrated wiring 718 and each source pad 712, the non-active region can be made space-saving, and the chip size can be further reduced while further reducing the gate-integrated wiring resistance. Since the configuration example of the subsequent gate-integrated wiring is the same as that of Embodiment 1, the description is omitted.

[0064] As described above, the semiconductor device according to Embodiment 3 includes a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a drain electrode disposed on the second nitride semiconductor layer and separated from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, a third gate aggregation wiring extending in the first direction, an active region, and an ESD protection element. The drain electrode is electrically connected to the drain pad via the drain lead wiring. The source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring. The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring. The source pads and the gate aggregation wirings are alternately formed in the first direction. The ESD protection elements are respectively disposed between the plurality of second gate aggregation wirings and the plurality of source pads.

[0065] According to this, the gate wiring resistance can be reduced, and a high-speed switching operation can be facilitated. Further, the source aggregation wiring for supplying power to the ESD protection element can be reduced, enabling reduction of the chip size.

[0066] (Embodiment 4) FIG. 8A is a cross-sectional view of the semiconductor component according to Embodiment 4. FIG. 8B is a bottom view. The semiconductor chip 825 described in Embodiments 1 to 3 is fixed to the die pad portion (the place where the chip is mounted) of the lead frame 827, and the source pad 812, the source terminal 832 of the lead frame 827, the gate pad 814, the gate terminal 834 of the lead frame 827, the drain pad 813, and the drain terminal 833 of the lead frame 827 are electrically connected via bonding wires 826, respectively.

[0067] The semiconductor component is formed by individually separating the semiconductor chip 825 described in Embodiments 1 to 3 through a back grinding process and a dicing process, then fixing it onto the die pad of the lead frame 827 using a conductive paste-like adhesive, bonding wires to the pads and leads of the semiconductor, and sealing with an epoxy resin molding material.

[0068] The die attach material 828 may be a conductive paste-like adhesive such as solder paste or silver paste, or a non-conductive paste-like adhesive using a resin-based material such as epoxy or polyimide. The metal material of the bonding wire 826 may be any one of Au, Cu, Al alloy, pure Al, or others, or a combination thereof. The bonding method may be any one of ball bonding, wedge bonding, or others, or a combination thereof. The form of the bonding member may be any one of fine wire, thick wire, ribbon, clip, or others, or a combination thereof. Although the figure shows the form of a surface mount device (SMD) package, a through hole device (THD) package may also be used. Also, there may be a plurality of source terminals, one gate terminal, and the plurality of source terminals and the one gate terminal may be arranged in the same order.

[0069] With such a configuration, it is possible to provide a semiconductor component with a reduced chip size and a reduced gate-integrated wiring resistance.

[0070] As described above, the semiconductor component according to Embodiment 4 includes the above semiconductor device and a lead frame. The lead frame has a die pad portion to which the semiconductor device is fixed, a source terminal, a gate terminal, and a drain terminal. The source pad and the source terminal, the gate pad and the gate terminal, and the drain pad and the drain terminal are electrically connected via bonding wires, respectively.

[0071] According to this, the gate wiring resistance can be reduced, and a high-speed switching operation can be facilitated. Further, the chip size can be reduced, enabling miniaturization of the semiconductor component.

[0072] For example, the semiconductor component is any one of an SMD (surface mount device) and a THD (Through-Hole Device). There are a plurality of the source terminals and one gate terminal. The semiconductor component in which the plurality of source terminals and the one gate terminal are arranged in the same order may be any one of an SMD (surface mount device) and a THD (Through-Hole Device). There are a plurality of the source terminals and one gate terminal, and the plurality of source terminals and the one gate terminal may be arranged in the same order.

[0073] According to this, miniaturization of the semiconductor component is enabled.

[0074] (Embodiment 5) FIG. 9 is a cross-sectional view of the semiconductor component of Embodiment 5. The semiconductor chip 925 described in Embodiments 1 to 3 is adhered to the die pad portion, and the source pad 912 and the source terminal of the lead frame 927, the gate pad 914 and the gate terminal of the lead frame 927, and the drain pad 913 and the drain terminal of the lead frame 927 are electrically connected via bumps 929, respectively.

[0075] In such a flip-chip configuration, wiring space by wires becomes unnecessary, the package can be made smaller, and power supply noise, inductance of wiring, and losses due to resistance of wiring can be reduced. The material of the bump 929 may be any one of Ni, Cu, SnAg, Au, Al, or others, or a combination thereof. Also, there are a plurality of source terminals, one gate terminal, and the plurality of source terminals and the one gate terminal may be arranged in the same order.

[0076] By adopting such a configuration, it is possible to provide a semiconductor component that reduces the gate-integrated wiring resistance while reducing the chip size.

[0077] As described above, the semiconductor component according to Embodiment 5 includes the above semiconductor device and a lead frame having a source terminal, a gate terminal, and a drain terminal, and the source pad and the source terminal, the gate pad and the gate terminal, and the drain pad and the drain terminal are electrically connected via bumps, respectively.

[0078] According to this, the gate wiring resistance can be reduced, and a high-speed switching operation can be facilitated. Also, it enables reduction of the chip size and miniaturization of the semiconductor component.

[0079] Although the semiconductor device and the semiconductor component according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by those skilled in the art applied to these embodiments, or forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects.

Industrial Applicability

[0080] In the semiconductor device according to the present disclosure, in particular, it can be used as a switching transistor that operates at a high frequency of 1 MHz or more. Among them, in particular, it can be used for GaN power transistors.

Explanation of symbols

[0081] 101, 601, 701 Substrate 102, 602, 702 Buffer layer 103, 603, 703 First nitride semiconductor layer 104, 604, 704 Second nitride semiconductor layer 105, 605, 705 Source electrode 106, 606, 706 Drain electrode 107, 607, 707 Gate electrode 108, 608, 708 Active region 109, 609, 709 Source lead wiring 110, 610, 710 Drain lead wiring 112, 212, 312, 412, 612, 712 Source pad 113, 213, 413, 613, 713 Drain pad 114, 214, 414, 614, 714 Gate pad 115, 215, 315, 615, 715 Source aggregation wiring 117, 217, 517, 617, 717 First gate aggregation wiring 118, 218, 318, 518, 618, 718 Second gate aggregation wiring 119, 219, 519, 619, 719 Third gate aggregation wiring 120, 620, 720 ESD protection element 324 Source pad connection part 621, 721 Anode 622, 722 Cathode 523 Slit 825, 925 Semiconductor chip 826 Bonding wire 827 Lead frame 828 Die attach material 929 bumps 630 long finger part 631 short finger part 832 source terminal 833 drain terminal 834 gate terminal

Claims

1. A substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and spaced apart from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, a third gate aggregation wiring extending in the first direction, and comprising: the drain electrode is electrically connected to the drain pad via the drain lead wiring, the source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring, the gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring, the plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction, the third gate aggregation wiring and the gate pad are thicker than the first and second gate aggregation wirings, a semiconductor device.

2. The gate electrode, the first gate aggregation wiring, the second gate aggregation wiring, and the third gate aggregation wiring are formed of the same metal configuration. The semiconductor device according to claim 1.

3. A substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and spaced apart from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction; a plurality of second gate aggregation wirings; a third gate aggregation wiring extending in the first direction; a source pad connection portion; the drain electrode is electrically connected to the drain pad via the drain lead wiring; the source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring; the gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring; the plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction; adjacent source pads among the plurality of source pads are electrically connected via the source pad connection portion; a semiconductor device.

4. the gate pad is located at a position shifted in the longitudinal direction rather than in the arrangement direction of the plurality of source pads; the semiconductor device according to any one of claims 1 to 3.

5. A substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and separated from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain lead wiring, a plurality of source pads, a source lead wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, a third gate aggregation wiring extending in the first direction; the drain electrode is electrically connected to the drain pad via the drain lead wiring; the source electrode is electrically connected to the plurality of source pads via the source lead wiring and the source aggregation wiring; the gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring; The plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction, wherein the source pad is a pad for bonding a bonding wire, a semiconductor device. **Claim 6** A substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, finger-shaped source electrodes on the second nitride semiconductor layer, finger-shaped drain electrodes disposed on the second nitride semiconductor layer and separated from the source electrodes, finger-shaped gate electrodes disposed between the source electrodes and the drain electrodes, drain pads, drain lead-out wirings, a plurality of source pads, source lead-out wirings, source aggregation wirings extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrodes in a plan view of the substrate, gate pads, first gate aggregation wirings extending in the first direction, a plurality of second gate aggregation wirings, and third gate aggregation wirings extending in the first direction, wherein the drain electrodes are electrically connected to the drain pads via the drain lead-out wirings, wherein the source electrodes are electrically connected to the plurality of source pads via the source lead-out wirings and the source aggregation wirings, wherein the gate electrodes are electrically connected to the gate pads located at both ends or one end of the third gate aggregation wirings via the first gate aggregation wirings, the plurality of second gate aggregation wirings, and the third gate aggregation wirings, wherein the plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction, wherein the source pads, the drain pads, and the gate pads are substantially at the same height with respect to the substrate, a semiconductor device. **Claim 7** The gate aggregation wirings have a plurality of slits, The semiconductor device according to any one of claims 1 to 6. **Claim 8** A semiconductor device, a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, finger-shaped source electrodes on the second nitride semiconductor layer, finger-shaped drain electrodes disposed on the second nitride semiconductor layer and separated from the source electrodes, finger-shaped gate electrodes disposed between the source electrodes and the drain electrodes, drain pads, drain lead-out wirings, a plurality of source pads, A source extraction wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, and a third gate aggregation wiring extending in the first direction, wherein the drain electrode is electrically connected to the drain pad via the drain extraction wiring, the source electrode is electrically connected to the plurality of source pads via the source extraction wiring and the source aggregation wiring, the gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate aggregation wiring via the first gate aggregation wiring, the plurality of second gate aggregation wirings, and the third gate aggregation wiring, the plurality of source pads and the plurality of second gate aggregation wirings are alternately formed in the first direction, the gate aggregation wiring has a plurality of slits, in a plan view of the semiconductor device, in the longitudinal direction, the width of the slit is 0.1 μm to 3.0 μm, the interval between the slits is 1 μm to 10 μm, and in the first direction, the width of the slit is 3 μm to 40 μm, and the interval between the slits is 1.0 μm to 10 μm, a semiconductor device.

9. a substrate, a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, a finger-shaped source electrode on the second nitride semiconductor layer, a finger-shaped drain electrode disposed on the second nitride semiconductor layer and separated from the source electrode, a finger-shaped gate electrode disposed between the source electrode and the drain electrode, a drain pad, a drain extraction wiring, a plurality of source pads, a source extraction wiring, a source aggregation wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, a gate pad, a first gate aggregation wiring extending in the first direction, a plurality of second gate aggregation wirings, a third gate aggregation wiring extending in the first direction, an active region, and an ESD protection element, wherein the drain electrode is electrically connected to the drain pad via the drain extraction wiring, the source electrode is electrically connected to the plurality of source pads via the source extraction wiring and the source aggregation wiring, The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate integrated wiring via the first gate integrated wiring, a plurality of second gate integrated wirings, and the third gate integrated wiring. The plurality of source pads and the plurality of second gate integrated wirings are alternately formed in the first direction. The active region includes a long finger portion and a short finger portion. The source integrated wiring, the ESD protection element, and the gate pad are arranged in this order from the position of the short finger portion in the longitudinal direction. The anode of the ESD protection element is electrically connected to the source integrated wiring. The cathode of the ESD protection element is electrically connected to the gate pad. Semiconductor device.

10. A substrate, A first nitride semiconductor layer on the substrate, A second nitride semiconductor layer on the first nitride semiconductor layer, A finger-shaped source electrode on the second nitride semiconductor layer, A drain electrode arranged separately from the source electrode on the second nitride semiconductor layer, A finger-shaped gate electrode arranged between the source electrode and the drain electrode, A drain pad, A drain lead-out wiring, A plurality of source pads, A source lead-out wiring, A source integrated wiring extending in a first direction perpendicular to the longitudinal direction of the finger-shaped gate electrode in a plan view of the substrate, A gate pad, A first gate integrated wiring extending in the first direction, A plurality of second gate integrated wirings, A third gate integrated wiring extending in the first direction, An active region, An ESD protection element, and The drain electrode is electrically connected to the drain pad via the drain lead-out wiring. The source electrode is electrically connected to the plurality of source pads via the source lead-out wiring and the source integrated wiring. The gate electrode is electrically connected to the gate pad located at both ends or one end of the third gate integrated wiring via the first gate integrated wiring, the plurality of second gate integrated wirings, and the third gate integrated wiring. The source pads and the gate integrated wirings are alternately formed in the first direction. The ESD protection elements are respectively arranged between the plurality of second gate integrated wirings and the plurality of source pads. Semiconductor device.

11. A semiconductor device according to any one of claims 1 to 10, and A lead frame. The lead frame has a die pad portion to which the semiconductor device is fixed, a source terminal, a gate terminal, and a drain terminal. The source pad and the source terminal, the gate pad and the gate terminal, and the drain pad and the drain terminal are electrically connected via bonding wires, respectively. Semiconductor component.

12. The semiconductor component is any one of an SMD (surface mount device) and a THD (Through-Hole Device). There are a plurality of the source terminals and one gate terminal. The plurality of source terminals and the one gate terminal are arranged side by side in the same order. The semiconductor component according to claim 11.

13. A semiconductor device according to any one of claims 1 to 10, comprising a lead frame having a source terminal, a gate terminal, and a drain terminal, wherein the source pad and the source terminal, the gate pad and the gate terminal, and the drain pad and the drain terminal are electrically connected via bumps, respectively. Semiconductor component.

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