Unidirectional transition suppression diode and its manufacturing process

Abstract

The embodiment of the present application provides a unidirectional transient suppression diode and process, the diode includes a substrate of a first conductivity type, a first implantation region of a second conductivity type, and a second implantation region, the first implantation region is disposed on the front surface of the substrate, and the second implantation region is disposed on the rear surface of the substrate, where the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. A blocking layer and an insulating layer are disposed on the front surface of the substrate in order from bottom to top, the first implantation region leads to a first electrode by a first metal, and an insulating layer is disposed between the blocking layer and the first metal layer, the second implantation region on the rear surface and the substrate respectively lead to a second electrode by a second metal, thereby shorting the second implantation region on the rear surface of the substrate and the substrate, the first conductivity type and the second conductivity type are different, and the present application improves the negative surge prevention ability.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically, to a unidirectional transient suppression diode and its manufacturing process.

Background Art

[0002] A surge is an instantaneous overvoltage exceeding the normal operating voltage in electrical equipment. The instantaneous energy of the surge is huge enough to break down the circuit. A TVS (Transient Voltage Suppressor) is a commonly used surge protection device that can effectively protect the circuit.

[0003] With the increasing complexity of the application environment day by day, the requirements for the surge prevention ability of circuits are getting higher and higher. To improve the surge prevention ability, the area of the protection device can be increased, but the cost will increase. As the integration degree is getting higher and higher, the area of the surge protection device is getting smaller and smaller. Therefore, it is particularly important to improve the surge prevention ability without increasing the area.

[0004] At the same time, the reliability of TVS is extremely susceptible to the influence of charge. The instability of the breakdown voltage causes various problems in actual applications. Therefore, it is also very important to improve the reliability of TVS, ensure the stability of the breakdown voltage, and ensure that the device can operate normally for a long time.

Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide an ultra-low capacitance ESD protection device and its manufacturing method, and the embodiments of the present application can improve the unidirectional TVS surge prevention ability and the reliability of TVS.

[0006] According to a first aspect, the embodiments of the present application provide a unidirectional transient suppression diode, and the unidirectional transient suppression diode includes a substrate of a first conductivity type, a first implantation region of a second conductivity type, and a second implantation region. The first injection region is disposed on the surface of the substrate, and the second injection region is disposed on the back surface of the substrate. Here, the junction depth of the pn junction formed between the second injection region and the substrate is smaller than the junction depth of the pn junction formed between the first injection region and the substrate. On the front surface of the substrate, a blocking layer and an insulating layer are sequentially disposed from bottom to top. The first injection region leads out a first electrode by a first metal, and the insulating layer is disposed between the blocking layer and the first metal layer. The second injection region on the back surface and the substrate respectively lead out a second electrode by a second metal, thereby shorting the second injection region on the back surface of the substrate and the substrate. The first conductivity type and the second conductivity type are different.

[0007] Compared with the prior art, the embodiment according to the first aspect disposes an insulating layer between the blocking layer and the first metal layer, and the junction depth of the pn junction formed between the second injection region and the substrate is smaller than the junction depth of the pn junction formed between the first injection region and the substrate. The insulating layer is used to shield charges, thereby ensuring that the breakdown voltage of the diode is not affected, and relatively shallow the junction depth of the second injection region on the back surface of the substrate to improve the negative surge prevention ability.

[0008] According to a second aspect, the embodiment of the present application provides another unidirectional transient suppression diode. The unidirectional transient suppression diode includes a substrate of a first conductivity type, a first injection region of a second conductivity type, a second injection region, and a groove. The first injection region is disposed on the surface of the substrate, and the second injection region is disposed on the back surface of the substrate. Here, the junction depth of the pn junction formed between the second injection region and the substrate is smaller than the junction depth of the pn junction formed between the first injection region and the substrate. The groove covers the first implantation region, an isolation layer is grown on the groove wall of the groove, and the depth of the groove is greater than the junction depth of the pn junction formed between the first implantation region and the substrate. The first implantation region leads out the first electrode with the first metal, and the second implantation region on the back surface and the substrate lead out the second electrode with the second metal respectively, so that the second implantation region on the back surface of the substrate and the substrate are shorted, and the first conductivity type and the second conductivity type are different.

[0009] Compared with the prior art, the embodiment according to the second aspect installs a groove around the first implantation region, grows an isolation layer on the groove wall of the groove, and the depth of the groove is greater than the junction depth of the pn junction formed between the first implantation region and the substrate, and the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. The groove is used to shield charges, thereby ensuring that the breakdown voltage of the diode is not affected, and making the junction depth of the second implantation region on the back surface of the substrate relatively shallow to improve the negative surge prevention ability.

[0010] According to the third aspect, the embodiment of the present application provides a manufacturing process of a unidirectional transient suppression diode. The manufacturing process is used to manufacture the diode described in the first aspect, and the manufacturing process includes forming a blocking layer on a substrate of the first conductivity type; forming a first implantation region on the surface of the substrate in sequence, and forming a second implantation region on the back surface. The first implantation region and the second implantation region have the first conductivity type, and the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different; forming a second implantation region on the back surface of the substrate. The first implantation region and the second implantation region have the second conductivity type, and the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different; Forming an insulating layer on top of the blocking layer on the surface of the substrate; Pulling out a first electrode with a first metal in a first implantation region, the insulating layer being disposed between the blocking layer and the first metal layer, and shorting the second implantation region on the back surface of the substrate and the substrate by pulling out a second electrode with a second metal in the second implantation region and the substrate.

[0011] Compared with the prior art, the beneficial effects of the embodiments according to the third aspect are the same as those of the embodiments of the first aspect of the present application for the unidirectional transient suppression diode.

[0012] According to a fourth aspect, embodiments of the present application provide a manufacturing process for a unidirectional transient suppression diode, the manufacturing process being used to manufacture the diode described in the second aspect, and the manufacturing process includes: Forming a first implantation region on the surface of the substrate; Forming a groove on the surface of the substrate, forming an isolation layer in the groove, the groove covering the first implantation region, and the depth of the groove being greater than the junction depth of the pn junction formed between the first implantation region and the substrate; Forming a second implantation region on the back surface of the substrate, the first implantation region and the second implantation region having a first conductivity type, the junction depth of the pn junction formed between the second implantation region and the substrate being smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type being different; Pulling out a first electrode with a first metal in the first implantation region, and shorting the second implantation region on the back surface of the substrate and the substrate by pulling out a second electrode with a second metal in the second implantation region and the substrate.

[0013] Compared with the prior art, the beneficial effects of the unidirectional transient suppression diode according to the fourth aspect are the same as those of the technical solution according to the second aspect, and will not be described further here.

Brief Description of the Drawings

[0014] A non-limiting and non-exhaustive implementation solution of the present invention will be described in an exemplary manner with reference to the following drawings, where

Figure 1

Figures 2 - 5

Figure 6

Figures 7 - 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0015] To make the above and other features and advantages of the present invention clearer, the present invention will be further described below in conjunction with the drawings. It should be understood that the specific implementation solutions described herein are for the purpose of interpretation by those skilled in the art, and are merely exemplary and not limiting.

[0016] To enable those skilled in the art to better understand the technical solution of the present invention, the following will clearly and completely describe the technical solution in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts should belong to the protection scope of the present invention.

[0017] It should be noted that terms such as "first" and "second" in the specification, claims and drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that data used in this way is interchangeable where appropriate, and the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. Additionally, the terms "comprising", "having" and any variations thereof are intended to cover non-exclusive "comprising", for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, and may include other steps or units not explicitly listed or inherent to these processes, methods, products or devices.

[0018] As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a one-way transient suppression diode in the prior art, and the specific structure shown in FIG. 1 is as follows.

[0019] On the front and back surfaces of the substrate 11, implantation regions 12 and 13 with the same implantation depth are sequentially formed. By connecting the implantation region 13 on the back surface and the substrate 11 with the metal 16, the implantation region 13 on the back surface of the substrate 11 and the substrate 11 are shorted. The implantation region 12 on the front surface of the substrate 11 is connected to the metal 15, and the implantation region 12 on the front surface of the substrate 11 and the substrate 11 are separated by the blocking layer 14. The blocking layer 14 is silica. The implantation region 12 on the front surface of the substrate 11 has the same conductivity type as the implantation region 13 on the back surface. The conductivity types of the implantation region 12 and the implantation region 13 are different from the conductivity type of the substrate 12. Here, the substrate 11 may be P-type, the implantation region 12 and the implantation region 13 are both N-type, and the junction depth of the pn junction between the implantation region 12 on the front surface of the substrate 11 and the substrate 11 is the same as the junction depth of the pn junction between the implantation region 13 on the back surface and the substrate 11. In the prior art, the charge on the blocking layer 14 is extremely likely to affect the breakdown voltage of the device, and the negative surge is protected only by the forward pn junction formed between the substrate 11 and the implantation region 12 on the front surface of the substrate 11. Therefore, its surge prevention ability is relatively weak. In the prior art, there is only one layer of the blocking layer 14 between the implantation region 12 on the surface and the metal layer 15. During the production and manufacturing of the chip, charges are likely to be generated at the interface of the blocking layer 14. The charges form an electric field and change with respect to the depletion region of the pn junction, causing the breakdown voltage to drift. The negative surge is a surge whose current direction is from the back surface of the substrate 11 to the front surface. From the back surface to the front surface of the substrate 11, there are two paths. Path 1 is from the substrate 11 to the implantation region 12 on the front surface, and path 2 is from the implantation region 13 on the back surface through the substrate 11 to the implantation region 12 on the front surface. In the prior art, since the pn junction formed between the implantation region 13 on the back surface and the substrate 11 is a high-voltage reverse bias junction, path 2 is difficult to conduct, and the current can only escape through path 1. Therefore, the current-carrying area is small, the heat generation is large, and the surge prevention ability is weak.

[0020] Therefore, in order to solve the problems of the structure shown in FIG. 1 in the prior art, the applicant considered solving the problems in the prior art by the following specific embodiments.

[0021] <Example 1> As shown in FIG. 2, the embodiment of the present application provides a unidirectional transient suppression diode, including a substrate 21 of a first conductivity type, a first implantation region 22 of a second conductivity type, and a second implantation region 23, The first implantation region 22 is disposed on the surface of the substrate 21, and the second implantation region 23 is disposed on the back surface of the substrate 21. Here, the junction depth of the pn junction formed between the second implantation region 23 and the substrate 21 is smaller than the junction depth of the pn junction formed between the first implantation region 22 and the substrate 21. On the front surface of the substrate 21, a blocking layer 24 and an insulating layer 27 are sequentially disposed from bottom to top. The first implantation region 22 leads out a first electrode by a first metal 25, and the insulating layer 27 is disposed between the blocking layer 24 and the first metal layer 25. The second implantation region 23 on the back surface and the substrate 21 respectively lead out a second electrode by a second metal 26, so that the second implantation region 23 on the back surface of the substrate 21 and the substrate 21 are short-circuited. The first conductivity type and the second conductivity type are different. In the embodiment of the present application, both the first implantation region 22 and the second implantation region 23 are highly doped.

[0022] In the embodiment of the present application, the first conductivity type is P type, the second conductivity type is N type, and an NPN structure is formed. In another embodiment, the first conductivity type may be N type, and the second conductivity type is P type, forming a PNP structure. And the blocking layer 24 is silica, which plays an isolation role and a blocking role. The insulating layer 27 is lindley - doped silica, and the role of the insulating layer 27 is to prevent short - circuit. The breakdown voltage drift of the diode device is affected by charges. There are many unsaturated dangling bonds in lindley - doped silica, and these dangling bonds can play a role in shielding the electric field.

[0023] In the embodiment of the present application, the width of the second implantation region 23 is larger than the width of the first implantation region 22. This is mainly considered in terms of the distribution problem of the positive and negative surge prevention capabilities. The wider the second implantation region 23 on the back surface is, the stronger the positive surge prevention ability is, and the weaker the negative surge prevention ability is. The second implantation region 23 on the back surface is wider than the first implantation region 22 on the surface, and the positive and negative surge prevention capabilities can be effectively distributed.

[0024] <Example 2> In addition to Example 1, as shown in FIG. 3, the diode according to the embodiment of the present application further includes a third implantation region 31 of a second conductivity type. The second implantation region 23 is larger than the width of the third implantation region 31. The reason for setting the second implantation region 23 on the back surface to be wider than the first implantation region 22 on the surface of the substrate is that the second implantation region 23 on the back surface is an electron emission region. The number of electrons emitted is related to the area. The larger the area, the more electrons are emitted, and its current-carrying capacity becomes stronger. In the embodiment of the present application, the junction depth of the pn junction formed between the third implantation region 31 and the substrate 21 is larger than the junction depth of the pn junction formed between the first implantation region 22 and the substrate 21. The second implantation region 23 is highly doped. In the embodiment of the present application, the first conductivity type is P-type, the second conductivity type is N-type. When the substrate 21 is P-type, the third implantation region 31 is N-type. When the substrate 21 is N-type, the third implantation region 31 is P-type. In another embodiment, the first conductivity type may be N-type, and the second conductivity type is P-type. In the embodiment of the present application, the third implantation region 31 shortens the base region length of the first implantation region 22 on the surface - substrate 21 - the second implantation region 23 on the back surface, and improves the maximum current-carrying capacity by improving the current amplification factor.

[0025] In the embodiment of the present application, the width of the second implantation region 23 is larger than the width of the first implantation region 22. This is mainly considering the distribution problem of the positive and negative surge prevention capabilities. The wider the second implantation region 23 on the back surface, the stronger the positive surge prevention ability, and the weaker the negative surge prevention ability. The second implantation region 23 on the back surface is wider than the first implantation region 22 on the surface, and the positive and negative surge prevention capabilities can be effectively distributed.

[0026] <Example 3> In addition to Example 2, as shown in FIG. 4, the one-way transient suppression diode according to the embodiment of the present application further includes a fourth implantation region 42 of the first conductivity type and / or a fifth implantation region 41 of the second conductivity type. The fifth implantation region 41 covers the first implantation region 22, and the fifth implantation region 41 is spaced from the first implantation region 22 by a preset distance. By being spaced by the preset distance, the spread of the boundary of the surface depletion region can be moderated. The fourth implantation region 42 covers the second implantation region 23, and the fourth implantation region 42 is in contact with the second implantation region 23. When the fourth implantation region 42 is in contact with the second implantation region 23 on the back surface of the substrate, a pn junction is formed between the fourth implantation region 42 and the second implantation region 23 on the back surface of the substrate. Otherwise, a pn junction is formed between the substrate 21 and the second implantation region 23 on the back surface of the substrate.

[0027] In the embodiment of the present application, the one-way transient suppression diode according to the embodiment of the present application may include only one of the fourth implantation region 42 of the first conductivity type or the fifth implantation region 41 of the second conductivity type.

[0028] In this embodiment, when the substrate 21 is of P type, the fourth implantation region 42 is of P type, the fifth implantation region 41 is of N type, the fourth implantation region 42 is of P type, the fifth implantation region 41 is of N type, and is highly doped.

[0029] In this embodiment, the fifth implantation region 41 can make the pn junction formed between the first implantation region 22 on the surface of the substrate and the substrate 21 gentler with respect to the depletion region edges of Examples 1 and 2, making it easier for breakdown to occur inside rather than on the surface. When there is charge on the surface and breakdown occurs on the surface, the breakdown voltage is affected.

[0030] The fourth implantation region 42 has a high-concentration doping. Since the doping of both the P region and the N region of the pn junction formed between the fourth implantation region 42 and the fifth implantation region 41 is of high concentration, Zener breakdown is extremely likely to occur, the breakdown voltage is very low, and in the case of a negative surge, the path of the fourth implantation region 42 on the back surface of the substrate - the substrate 21 - the first implantation region 22 on the front surface of the substrate is more likely to conduct and allow current to flow.

[0031] <Example 4> In addition to Example 3, in Example 4, as shown in FIG. 5, the third implantation region is a plurality of divided implantation regions 31-1 that are uniformly spaced apart.

[0032] It should be noted that the third implantation region 31 in Example 2 may also be a plurality of divided implantation regions that are spaced apart. At the same time, the fifth implantation region 41 can make the pn junction formed between the first implantation region 22 on the front surface of the substrate and the substrate 21 gentler with respect to the depletion region edges in Examples 2 and 3.

[0033] In the examples of this application, in the case of a negative surge, the path of the fourth implantation region 42 on the back surface of the substrate - the first implantation region 22 on the front surface of the substrate 21 is more likely to conduct and allow current to flow. The current is not concentrated at both left and right ends but is more uniformly dispersed, and the conduction area becomes larger.

[0034] <Example 5> As shown in FIG. 6, on the substrate 61, injection regions 62 and 63 with the same junction depth are sequentially formed on the front and back surfaces of the substrate 61, respectively. By connecting the injection region 63 on the back surface and the substrate 61 with the metal 66, the injection region 63 on the back surface of the substrate 61 and the substrate 61 are short-circuited. The injection region 62 on the front surface of the substrate 61 is connected to the metal 65. The injection region 62 on the front surface of the substrate 61 has the same conductivity type as the injection region 63 on the back surface. The conductivity types of the injection region 62 and the injection region 63 are different from the conductivity type of the substrate 61. A groove 67 is formed in the substrate 61, and the groove 67 covers the first injection region 62. An isolation layer 64 is grown on the groove wall of the groove 67. The isolation layer 64 is silica. The isolation layer 64 isolates the metal 65 and the substrate 61. Otherwise, a short circuit (i.e., the current direction follows the surface metal 65 - substrate 61 - back surface metal 66) will occur. On the other hand, the side of the pn junction formed between the first injection region 62 on the front surface of the substrate and the substrate 61 can be isolated from the external environment, preventing the pn junction from being affected by the external environment. Here, the substrate 61 may be of P type. The injection regions 62 and 63 are both of N type. The junction depth of the pn junction between the injection region 62 on the front surface of the substrate 61 and the substrate 61 is the same as the junction depth of the pn junction between the injection region 63 on the back surface and the substrate 61. The negative surge is protected only by the forward pn junction formed between the substrate 61 and the injection region 62 on the front surface of the substrate 61, and its surge prevention ability is relatively weak. To solve the problems in the prior art, the technical solution of the embodiment of the present application is proposed.

[0035] As shown in FIG. 7, the difference between Example 5 and Example 1 is that a groove 77 is provided on the substrate 71. The groove 77 covers the first implantation region 72, and an isolation layer 74 is grown on the groove wall of the groove 77. The depth of the groove 77 is greater than the junction depth of the pn junction formed between the first implantation region 72 and the substrate 71. The first implantation region 72 is provided on the surface of the substrate 71, and the second implantation region 73 is provided on the back surface of the substrate 71. Here, the junction depth of the pn junction formed between the second implantation region 72 and the substrate 71 is smaller than the junction depth of the pn junction formed between the first implantation region 72 and the substrate 71. The first implantation region 72 leads out the first electrode with the first metal, and the second implantation region 73 on the back surface and the substrate 71 each lead out the second electrode with the second metal, so that the second implantation region 73 on the back surface of the substrate and the substrate 71 are shorted, and the first conductivity type and the second conductivity type are different.

[0036] In the embodiment of the present application, the width of the second implantation region 73 is larger than the width of the first implantation region 72. This is mainly considering the distribution problem of the positive and negative surge prevention capabilities. The wider the second implantation region 73 on the back surface is, the stronger the positive surge prevention ability becomes, and the weaker the negative surge prevention ability becomes. The second implantation region 73 on the back surface is wider than the first implantation region 72 on the surface, and the positive and negative surge prevention capabilities can be effectively distributed.

[0037] <Example 6> In addition to Embodiment 5, as shown in FIG. 8, the diode according to the embodiment of the present application further includes a third implantation region 81 of a second conductivity type. The second implantation region 73 is larger than the width of the third implantation region 81, and the junction depth of the pn junction formed between the third implantation region 81 and the substrate 71 is larger than the junction depth of the pn junction formed between the first implantation region 72 and the substrate 71. The second implantation region 73 is highly doped. In the embodiment of the present application, when the substrate 71 is of P type, the third implantation region 81 is of N type, and when the substrate 71 is of N type, the third implantation region 81 is of P type. In the embodiment of the present application, the first conductivity type is P type, and the second conductivity type is N type. In another embodiment, the first conductivity type may be N type, and the second conductivity type may be P type. In the embodiment of the present application, the third implantation region 81 shortens the base region length of the first implantation region 72 on the surface - substrate 71 - the second implantation region 73 on the back surface, and improves the maximum current - carrying capacity by improving the current amplification factor.

[0038] In the embodiment of the present application, the width of the second implantation region 73 is larger than the width of the first implantation region 72. This is mainly considering the distribution problem of the positive and negative surge prevention capabilities. The wider the second implantation region 73 on the back surface, the stronger the positive surge prevention ability and the weaker the negative surge prevention ability. The second implantation region 73 on the back surface is wider than the first implantation region 72 on the surface, and the positive and negative surge prevention capabilities can be effectively distributed.

[0039] <Embodiment 7> In addition to Embodiment 6, as shown in FIG. 9, in the embodiment, the diode further includes a fourth implantation region 91 of a second conductivity type. The fourth implantation region 91 covers the second implantation region 73, the fourth implantation region 91 is in contact with the second implantation region 73, and the fourth implantation region 91 forms a pn junction where Zener breakdown is extremely likely to occur. This pn junction is the junction between the fourth implantation region 91 and the second implantation region 73 on the back surface, and it becomes easier to conduct current through this.

[0040] <Embodiment 8> In addition to Example 7, as shown in FIG. 10, the third injection region 81 is a plurality of divided injection regions 81-1 that are uniformly spaced apart.

[0041] It should be noted that the third injection region 81 in Example 6 may also be a plurality of divided injection regions that are spaced apart.

[0042] In the examples of this application, in the case of a negative surge, the path of the second injection region 73 on the back surface of the substrate - the substrate 71 - the first injection region 72 on the front surface of the substrate is more likely to be conductive and allow current to flow, and the current does not concentrate at both left and right ends as shown in FIG. 9.

[0043] As shown in FIG. 11, the examples of this application further provide a manufacturing process for a unidirectional transient suppression diode, and the process is used to manufacture the unidirectional transient suppression diode described in Examples 1 to 4. Specifically, the process includes the following.

[0044] Step S11, forming a blocking layer on a substrate of a first conductivity type.

[0045] Step S12, forming a first injection region on the front surface of the substrate and a second injection region on the back surface in sequence. The first injection region and the second injection region have a first conductivity type. The junction depth of the pn junction formed between the second injection region and the substrate is smaller than the junction depth of the pn junction formed between the first injection region and the substrate, and the first conductivity type and the second conductivity type are different.

[0046] Step S13, forming an insulating layer on top of the blocking layer on the front surface of the substrate.

[0047] Step S14, leading out a first electrode with a first metal in the first injection region. The insulating layer is installed between the blocking layer and the first metal layer, and short - circuiting the second injection region on the back surface of the substrate and the substrate by leading out a second electrode with a second metal in the second injection region and the substrate.

[0048] It should be noted that first, the first oxidation is performed on the substrate to form a blocking layer. On the surface, the pattern of the first implantation region is lithographed, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is carried out to form the first implantation region on the surface of the substrate. Then, lithography of the second implantation region on the back surface of the substrate is performed, impurity implantation or pre-diffusion is carried out, and activation is carried out by high temperature for a short time to form the second implantation region on the back surface of the substrate. Thereafter, an insulating layer is grown on the surface of the substrate. Finally, contact holes corresponding to the size are etched on the front and back surfaces of the substrate, metal is deposited, and the metal is etched to form the final device. Based on steps S11 to S14, the diode structure described in the above Embodiment 1 can be manufactured.

[0049] Before forming the second implantation region in step S12, the process further includes the following steps.

[0050] Step S16, forming a third implantation region of the second conductivity type on the back surface of the substrate, the width of the third implantation region being smaller than the width of the second implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate being larger than the junction depth of the pn junction formed between the first implantation region and the substrate.

[0051] It should be noted that for the first implantation regions on the front and back surfaces of the substrate and the second implantation region, lithography and ion implantation can be performed simultaneously. That is, the front and back surfaces of the substrate are lithographed simultaneously for the first implantation region on the front surface of the substrate and the third implantation region on the back surface, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is carried out to form the first implantation region on the front surface of the substrate and the third implantation region on the back surface of the substrate. Then, lithography of the second implantation region on the back surface of the substrate is performed, impurity implantation or pre-diffusion is carried out, and activation is carried out by high temperature for a short time to form the second implantation region on the back surface, and the diode structure shown in Embodiment 2 can be obtained based on steps S11 to S14 and step S15.

[0052] After creating the first implantation region on the surface of the substrate in this step, the third implantation region may be created, and then the second implantation region may be created. In FIG. 11, only one type of process method for the third implantation region is shown, that is, it is shown that the first implantation region and the third implantation region are created simultaneously.

[0053] When the third implantation region is a plurality of divided implantation regions installed at intervals during lithography, the diode structure shown in Embodiment 4 can be obtained based on steps S11 to S14 and step S15.

[0054] When forming the second implantation region in step S12, the process simultaneously further includes forming a fourth implantation region of the first conductivity type on the back surface of the substrate, where the fourth implantation region covers the second implantation region and the fourth implantation region is in contact with the second implantation region.

[0055] In FIG. 11, only one type of process method for the third implantation region is shown, that is, it is shown that the second implantation region and the fourth implantation region are created simultaneously.

[0056] It should be noted that when lithographing the second implantation region, the fourth implantation region on the back surface of the substrate is simultaneously lithographed, then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region on the back surface of the substrate. In the embodiment of the present application, the fourth implantation region may be created before forming the second implantation region.

[0057] Before forming the second implantation region in step S12, the process further includes forming a fifth implantation region of the first conductivity type on the surface of the substrate, where the fifth implantation region covers the first implantation region and the fifth implantation region is separated from the first implantation region by a preset distance, and the diode structure described in the above Embodiment 3 can be manufactured based on steps S11 to S14 and step S16.

[0058] It should be noted that while forming the first implantation region and lithographing the fifth implantation region on the surface of the substrate, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is carried out to form the fifth implantation region on the surface of the substrate. In this way, the process steps can be saved and the cost can be reduced. The fifth implantation region may be performed before the second implantation region. Performing it before the second implantation region on the back surface is to prevent the high-temperature diffusion of the fifth implantation region from affecting the depth of the implantation region on the back surface. In FIG. 11, only one type of process method for the third implantation region is shown, that is, it is shown that the first implantation region and the fifth implantation region are created simultaneously.

[0059] As shown in FIG. 12, the embodiment of the present application further provides a manufacturing process of a one-way transient suppression diode, and the manufacturing process includes the following steps.

[0060] Step S21: Form a first implantation region on the surface of the substrate in sequence.

[0061] Step S22: Form a groove in the substrate and grow an isolation layer in the groove. The groove covers the first implantation region, and the depth of the groove is greater than the junction depth of the pn junction formed between the first implantation region and the substrate.

[0062] Step S23: Form a second implantation region on the back surface of the substrate. The first implantation region and the second implantation region have the first conductivity type. The junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different.

[0063] Step S24: By leading out the first electrode with the first metal in the first implantation region and leading out the second electrode with the second metal in the second implantation region and the substrate, the second implantation region on the back surface of the substrate and the substrate are short-circuited.

[0064] It should be noted that after lithographing the pattern of the first implantation region on the surface, performing impurity implantation or pre-diffusion into the first implantation region, and then performing high-temperature diffusion to form the first implantation region on the surface of the substrate, after dry etching or wet etching the groove, lithography of the second implantation region on the back surface of the substrate is performed, impurity implantation or pre-diffusion is performed, and activation is carried out by high temperature for a short time to form the second implantation region on the back surface of the substrate. Finally, contact holes corresponding to the size are etched on the front and back surfaces of the substrate, metal is deposited, the metal is etched, and the final device is formed. Based on steps S21 to S24, the diode structure described in the above Embodiment 5 can be manufactured.

[0065] Before forming the second implantation region in step S23, the process further includes the following steps.

[0066] Step S25, forming a third implantation region of a second conductivity type on the back surface of the substrate, the width of the third implantation region being smaller than the width of the second implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate being larger than the junction depth of the pn junction formed between the first implantation region and the substrate.

[0067] It should be noted that for the first implantation regions on the front and back surfaces of the substrate and the second implantation region, lithography and ion implantation can be performed simultaneously. That is, the front and back surfaces of the substrate simultaneously lithograph the first implantation region on the front surface of the substrate and the third implantation region on the back surface, perform impurity implantation or pre-diffusion, and then perform high-temperature diffusion to form the first implantation region on the front surface of the substrate and the third implantation region on the back surface of the substrate. Then, lithography of the second implantation region on the back surface of the substrate is performed, impurity implantation or pre-diffusion is performed, and activation is carried out by high temperature for a short time to form the second implantation region on the back surface. Based on steps S21 to S24 and step S25, the diode structure shown in Embodiment 6 can be manufactured.

[0068] This step may create the third implantation region and then the second implantation region after the first implantation region on the surface of the substrate is completed. In FIG. 12, only one type of process method for the third implantation region is shown, that is, it is shown that the third implantation region is created simultaneously when the first implantation region is completed.

[0069] When the third implantation region is a plurality of divided implantation regions installed at uniform intervals during lithography, the diode structure shown in Embodiment 8 can be obtained based on Steps S21 to S24 and Step S25.

[0070] When forming the second implantation region in Step S23, the process further includes forming a fourth implantation region of the first conductivity type on the back surface of the substrate, where the fourth implantation region covers the second implantation region and the fourth implantation region is in contact with the second implantation region.

[0071] In FIG. 12, only one type of process method for the third implantation region is shown, that is, it is shown that the second implantation region and the fourth implantation region are created simultaneously.

[0072] It should be noted that when lithographing the second implantation region, the fourth implantation region on the back surface of the substrate is simultaneously lithographed, then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region on the back surface of the substrate. In the embodiments of the present application, the fourth implantation region may be created before the second implantation region is formed.

[0073] It should be noted that the fourth implantation region may be created before the second implantation region is formed. First, the fourth implantation region on the back surface of the substrate is lithographed, then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region on the back surface of the substrate. Based on Steps S21 to S24 and Step S26, the diode structure shown in Embodiment 7 can be manufactured.

[0074] Each technical feature of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered within the scope described in this specification.

[0075] The present invention has been described in connection with the embodiments. However, those skilled in the art should understand that the above description and drawings are merely illustrative and not restrictive, and this application is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the present invention.

Claims

1. A unidirectional transient suppression diode, comprising a substrate of a first conductivity type, a first implantation region of a second conductivity type, and a second implantation region, wherein the first implantation region is disposed on the surface of the substrate, and the second implantation region is disposed on the back surface of the substrate. Here, the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. On the front surface of the substrate, a blocking layer and an insulating layer are sequentially disposed from bottom to top. The first implantation region leads out a first electrode by a first metal. The insulating layer is disposed between the blocking layer and the first metal layer. The second implantation region on the back surface and the substrate respectively lead out a second electrode by a second metal, so that the second implantation region on the back surface of the substrate and the substrate are shorted. The first conductivity type and the second conductivity type are different. The unidirectional transient suppression diode further includes a third implantation region of a second conductivity type. The width of the second implantation region is larger than the width of the third implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate is larger than the junction depth of the pn junction formed between the first implantation region and the substrate. A unidirectional transient suppression diode characterized by the above.

2. The third implantation region is a plurality of divided implantation regions disposed at intervals. The unidirectional transient suppression diode according to claim 1, characterized in that.

3. The diode further includes a fourth implantation region of a first conductivity type and / or a fifth implantation region of a second conductivity type. The fourth implantation region covers the second implantation region, the fourth implantation region is in contact with the second implantation region, the fifth implantation region covers the first implantation region, and the fifth implantation region is separated from the first implantation region by a preset distance. The unidirectional transient suppression diode according to any one of claims 1 to 2, characterized in that.

4. The first conductivity type is a P type, and the second conductivity type is an N type. The unidirectional transient suppression diode according to any one of claims 1 to 3, characterized in that.

5. The blocking layer is silica, and the insulating layer is lindoped silica. The unidirectional transient suppression diode according to any one of claims 1 to 2 and 4, characterized in that.

6. A unidirectional transient suppression diode, comprising a substrate of a first conductivity type, a first implantation region of a second conductivity type, a second implantation region, and a groove, wherein the first implantation region is disposed on the surface of the substrate, the second implantation region is disposed on the back surface of the substrate, and the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, the groove covers the first implantation region, and an isolation layer is grown on the groove wall of the groove. The depth of the groove is larger than the junction depth of the pn junction formed between the first implantation region and the substrate. The first implantation region leads out a first electrode by a first metal, and the second implantation region and the substrate on the back surface respectively lead out a second electrode by a second metal, so that the second implantation region on the back surface of the substrate and the substrate are short-circuited. The first conductivity type and the second conductivity type are different. The diode further includes a third implantation region of the second conductivity type. The width of the second implantation region is larger than the width of the third implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate is larger than the junction depth of the pn junction formed between the first implantation region and the substrate. A unidirectional transient suppression diode characterized by the above.

7. The unidirectional transient suppression diode according to claim 6, wherein the third implantation region is a plurality of divided implantation regions arranged at intervals.

8. The diode further includes a fourth implantation region of the first conductivity type. The unidirectional transient suppression diode according to claim 6 or 7, wherein the fourth implantation region covers the second implantation region and the fourth implantation region is in contact with the second implantation region.

9. The unidirectional transient suppression diode according to claim 8, wherein the first conductivity type is a P type and the second conductivity type is an N type.

10. A manufacturing process of a unidirectional transient suppression diode, which is used for manufacturing the diode according to any one of claims 1 to 5. The manufacturing process includes: forming the blocking layer on the substrate of the first conductivity type, Form the first implantation region on the surface of the substrate in sequence, form the second implantation region on the back surface, the first implantation region and the second implantation region have a second conductivity type, and the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different. Form an insulating layer on top of the blocking layer on the surface of the substrate. Pull out a first electrode with a first metal in the first implantation region, the insulating layer is installed between the blocking layer and the first metal layer, and pull out a second electrode with a second metal with the second implantation region and the substrate, thereby shorting the second implantation region on the back surface of the substrate and the substrate. The manufacturing process of a one-way transient suppression diode is characterized by including this.

11. Before forming the second implantation region on the back surface of the substrate, the manufacturing process includes Forming a third implantation region of a second conductivity type on the back surface of the substrate, the width of the second implantation region is larger than the width of the third implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate is larger than the junction depth of the pn junction formed between the first implantation region and the substrate. The manufacturing process of the one-way transient suppression diode according to claim 10 is characterized by this.

12. Before forming the second implantation region on the back surface of the substrate, the manufacturing process includes Further including forming a fourth implantation region of a first conductivity type on the back surface of the substrate, where the fourth implantation region covers the second implantation region and the fourth implantation region is in contact with the second implantation region. The manufacturing process of the one-way transient suppression diode according to claim 10 or 11 is characterized by this.

13. Before forming the second implantation region on the back surface of the substrate, the manufacturing process includes Further including forming a fifth implantation region of a first conductivity type on the surface of the substrate, where the fifth implantation region covers the first implantation region and the fifth implantation region is separated from the first implantation region by a preset distance. The manufacturing process of the one-way transient suppression diode according to claim 10 is characterized by this.

14. A manufacturing process of a one-way transient suppression diode, which is used to manufacture the diode according to any one of claims 6 to 9, and the manufacturing process includes Forming the first implantation region on the surface of the substrate; Forming a groove in the substrate, growing an isolation layer in the groove, the groove covering the first implantation region, and the depth of the groove being greater than the junction depth of the pn junction formed between the first implantation region and the substrate; Forming the second implantation region on the back surface of the substrate, the first implantation region and the second implantation region having a first conductivity type, the junction depth of the pn junction formed between the second implantation region and the substrate being smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type being different; Pulling out a first electrode with a first metal in the first implantation region, and pulling out a second electrode with a second metal in the second implantation region and the substrate, thereby shorting the second implantation region on the back surface of the substrate and the substrate. A manufacturing process of a one-way transient suppression diode, characterized by including the above.

15. Before forming the second implantation region on the back surface of the substrate, the manufacturing process further includes: Forming a third implantation region of a second conductivity type on the back surface of the substrate, the width of the second implantation region being larger than the width of the third implantation region, and the junction depth of the pn junction formed between the third implantation region and the substrate being larger than the junction depth of the pn junction formed between the first implantation region and the substrate. A manufacturing process of a one-way transient suppression diode according to claim 14, characterized by the above.

16. Before forming the second implantation region on the back surface of the substrate, the manufacturing process further includes: Forming a fourth implantation region of a first conductivity type on the back surface of the substrate, wherein the fourth implantation region covers the second implantation region and the fourth implantation region is in contact with the second implantation region. A manufacturing process of a one-way transient suppression diode according to claim 15, characterized by the above.

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