Semiconductor device

Abstract

To provide a semiconductor device suitable for miniaturization.SOLUTION: A semiconductor device comprises a first transistor, a second transistor located above the first transistor, a barrier layer located between the first and second transistors, a first electrode located between the first transistor and the barrier layer, and a second electrode being located between the barrier layer and the second transistor, and superposed on the first electrode while interposing the barrier layer therebetween. The gate electrode, the first electrode of the first transistor, and one of the source electrode and the drain electrode of the second transistor are connected electrically, the first transistor has a channel formed in a first semiconductor layer containing a single crystal semiconductor, and the second transistor has a channel formed in a second semiconductor layer containing an oxide semiconductor.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a method for manufacturing a semiconductor device. One aspect of the present invention relates to a method for driving a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. One aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, lighting devices, methods for driving them, or methods for manufacturing them. Note that in this specification or the like, the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. In addition, computing devices, storage devices, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may have semiconductor devices.

[0003] Note that in this specification or the like, the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. In addition, computing devices, storage devices, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may have semiconductor devices.

Background Art

[0004] Techniques for constructing transistors using semiconductor materials have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating a transistor using this method have been disclosed (see Patent Documents 1 and 2).

[0006] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization.

[0009] Another object is to provide a semiconductor device with good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of our goals is to provide the following.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention includes a first transistor, a second transistor positioned above the first transistor, a barrier layer positioned between the first transistor and the second transistor, a first electrode positioned between the first transistor and the barrier layer, and a second electrode positioned between the barrier layer and the second transistor and overlapping the first electrode with the barrier layer interposed therebetween. The first transistor has a channel formed in a first semiconductor layer including a single crystal semiconductor, and the second transistor has a channel formed in a second semiconductor layer including an oxide semiconductor. This is a semiconductor device.

[0012] Also, another aspect of the present invention includes a first transistor, a second transistor positioned above the first transistor, a barrier layer positioned between the first transistor and the second transistor, a first electrode positioned between the first transistor and the barrier layer, and a second electrode positioned between the barrier layer and the second transistor and overlapping the first electrode with the barrier layer interposed therebetween. One of the gate electrode of the first transistor, the first electrode, and the source electrode or drain electrode of the second transistor is electrically connected to each other. The first transistor has a channel formed in a first semiconductor layer including a single crystal semiconductor, and the second transistor has a channel formed in a second semiconductor layer including an oxide semiconductor. This is a semiconductor device.

[0013] Also, another aspect of the present invention includes a first transistor, a second transistor positioned above the first transistor, a barrier layer positioned between the first transistor and the second transistor, a first electrode positioned between the first transistor and the barrier layer, and a second electrode positioned between the barrier layer and the second transistor and overlapping the first electrode with the barrier layer interposed therebetween. ​​​​​​​​​​​​​​​ A second electrode that is positioned between the first transistor and the second transistor and overlaps the first electrode with a barrier layer interposed therebetween, and, the semiconductor device includes a semiconductor device in which one of the gate electrode of the first transistor, the second electrode, and the source electrode or drain electrode of the second transistor is electrically connected to each other, a channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor, and a channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

[0014] Also, another aspect of the present invention includes a first transistor, a second transistor positioned above the first transistor, a barrier layer positioned between the first transistor and the second transistor, a first electrode positioned between the first transistor and the barrier layer, and a second electrode positioned between the barrier layer and the second transistor and overlapping the first electrode with the barrier layer interposed therebetween. One of the gate electrode of the first transistor, the first electrode, and the source electrode or drain electrode of the second transistor is electrically connected to each other, the second electrode overlaps the channel formation region of the second transistor, a channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor, and a channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

[0015] Preferably, the barrier layer contains at least one of silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

[0016] Also, an insulating layer containing an oxide is provided between the second transistor and the barrier layer, and the insulating layer preferably has a region containing more oxygen than oxygen satisfying a stoichiometric composition. .

[0017] Also, the insulating layer preferably has a hydrogen concentration of less than 5×10 18 cm -3 . Preferably.

[0018] Also, the second semiconductor layer preferably has a hydrogen concentration of less than 5×10 18 cm -3 . Preferably.

[0019] Also, the gate insulating layer of the second transistor preferably has a hydrogen concentration of less than 5×10 1 8 cm -3 .

[0020] Also, the second electrode preferably contains a conductive metal oxide.

[0021] Also, it is preferable to have a third electrode containing the same material as the second electrode on the same plane as the second electrode, and the third electrode preferably overlaps with the channel formation region of the second transistor. Preferably, and the third electrode preferably overlaps with the channel formation region of the second transistor. Preferably.

[0022] Also, the second transistor preferably has an S value of 60 mV / dec. or more and 100 mV / de c. or less.

Advantages of the Invention

[0023] According to one aspect of the present invention, a semiconductor device suitable for miniaturization can be provided.

[0024] Alternatively, good electrical characteristics can be imparted to the semiconductor device. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a novel configuration can be provided. Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the content described in the following embodiments.

[0027] In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted. Also, when referring to the same function, the hatching pattern may be the same and may not be particularly labeled.

[0028] In each drawing described in this specification, the size of each component, the thickness of the layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0029] The ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and are not numerically limiting.

[0030] A transistor is a type of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non-conduction. The transistor in this specification is an IGFET (Insulated Gate Field Effect Trans istor) or a thin film transistor (TFT: Thin Film Transistor​ includes

[0031] (Embodiment 1) [Configuration Example of Stacked Structure] Hereinafter, an example of a stacked structure applicable to a semiconductor device according to an aspect of the present invention will be described. FIG. 1 is a schematic cross-sectional view of a stacked structure 10 shown below.

[0032] The stacked structure 10 has a stacked structure in which a first layer 11 including a first transistor, a first insulating layer 21, a first wiring layer 31, a barrier layer 41, a second wiring layer 32, a second insulating layer 22, and a second layer 12 including a transistor are stacked in this order.

[0033] The first transistor included in the first layer 11 is formed of a first semiconductor material . Further, the second transistor included in the second layer 12 is formed of a second semiconductor material . The first semiconductor material and the second semiconductor material may be the same material, but are preferably different semiconductor materials. The first transistor and the second transistor each have a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode (or in addition to these, a source region and a drain region).

[0034] For example, as the first semiconductor material or the second semiconductor material, semiconductor materials such as silicon and germanium, compound semiconductor materials having silicon, germanium, gallium, arsenic, aluminum, etc., organic semiconductor materials, or oxide semiconductor materials can be used.

[0035] Here, single-crystalline silicon is used as the first semiconductor material, and an oxide is used as the second semiconductor material ​​​​The case of using a semiconductor will be described.

[0036] The barrier layer 41 has a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. Note that the barrier layer 41 may have an opening or a plug for electrically connecting an electrode or wiring provided above it and an electrode or wiring provided below it. For example, it has a plug for electrically connecting a wiring or an electrode included in the first wiring layer 31 and a wiring or an electrode included in the second wiring layer 32. The first wiring layer 31 and the second wiring layer 32 are provided so as to sandwich the barrier layer 41. The first wiring layer 31 has at least a first electrode, and the second wiring layer 32 has at least a second electrode that overlaps the first electrode. Here, a capacitance can be formed by the first electrode, the barrier layer 41, and the second electrode.

[0037] The first wiring layer 31 and the second wiring layer 32 are provided so as to sandwich the barrier layer 41. The first wiring layer 31 has at least a first electrode, and the second wiring layer 32 has at least a second electrode that overlaps the first electrode. Here, a capacitance can be formed by the first electrode, the barrier layer 41, and the second electrode. Here, a capacitance can be formed by the first electrode, the barrier layer 41, and the second electrode. A capacitance can be formed by the first electrode, the barrier layer 41, and the second electrode.

[0038] As materials used for the wirings or electrodes included in the first wiring layer 31 and the second wiring layer 32, in addition to metal or alloy materials, conductive metal oxides can be used. Also, a layer containing such a material may be used as a single layer or laminated in two or more layers. As materials used for the wirings or electrodes included in the first wiring layer 31 and the second wiring layer 32, in addition to metal or alloy materials, conductive metal oxides can be used. Also, a layer containing such a material may be used as a single layer or laminated in two or more layers. A layer containing such a material may be used as a single layer or laminated in two or more layers.

[0039] The first insulating layer 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. Also, the first insulating layer 21 may have an opening or a plug for electrically connecting the first transistor, electrode, or wiring included in the first layer 11 and the electrode or wiring included in the first wiring layer 31. The first insulating layer 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. Also, the first insulating layer 21 may have an opening or a plug for electrically connecting the first transistor, electrode, or wiring included in the first layer 11 and the electrode or wiring included in the first wiring layer 31. The first insulating layer 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. Also, the first insulating layer 21 may have an opening or a plug for electrically connecting the first transistor, electrode, or wiring included in the first layer 11 and the electrode or wiring included in the first wiring layer 31. The first insulating layer 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. Also, the first insulating layer 21 may have an opening or a plug for electrically connecting the first transistor, electrode, or wiring included in the first layer 11 and the electrode or wiring included in the first wiring layer 31.

[0040] The second insulating layer 22 has a function of electrically insulating the second layer 12 and the second wiring layer 32. This is also the case for the second insulating layer 22, which may have openings or plugs for electrically connecting the second transistor, electrodes, or wiring included in the second layer 12 to the electrodes or wiring included in the second wiring layer 32. It may also have openings or plugs for electrically connecting the second transistor, electrodes,

[0041] Also, the second insulating layer 22 preferably contains an oxide. In particular, it preferably contains an oxide material from which some oxygen desorbs upon heating. Preferably, an oxide containing more oxygen than the oxygen satisfying the stoichiometric composition is used. When an oxide semiconductor is used as the second semiconductor material, the oxygen desorbed from the second insulating layer 22 is supplied to the oxide semiconductor, which makes it possible to reduce oxygen vacancies in the oxide semiconductor. As a result, fluctuations in the electrical characteristics of the second transistor can be suppressed, and the reliability can be improved. and the reliability can be enhanced. As a result, fluctuations in the electrical characteristics of the second transistor can be suppressed, and the reliability can be enhanced.

[0042] Here, it is preferable to reduce hydrogen, water, etc. as much as possible in the layer below the barrier layer 41. Hydrogen and water can be factors that cause fluctuations in the electrical characteristics of the oxide semiconductor. Also, hydrogen and water diffusing from the lower layer to the upper layer of the barrier layer 41 can be suppressed by the barrier layer 41, but there are cases where hydrogen and water diffuse into the upper layer through openings, plugs, etc. provided in the barrier layer 41. but there are cases where hydrogen and water diffuse into the upper layer through openings, plugs, etc. provided in the barrier layer 41. but there are cases where hydrogen and water diffuse into the upper layer through openings, plugs, etc. provided in the barrier layer 41. but there are cases where hydrogen and water diffuse into the upper layer through openings, plugs, etc. provided in the barrier layer 41.

[0043] To reduce hydrogen and water contained in each layer located below the barrier layer 41, it is preferable to perform a heat treatment for removing hydrogen and water contained in the layer below the barrier layer 41 before forming the barrier layer 41 or immediately after forming an opening for forming a plug in the barrier layer 41. In the heat treatment, while considering the heat resistance of conductive films, etc. constituting the semiconductor device, while considering the heat resistance of conductive films, etc. constituting the semiconductor device, while considering the heat resistance of conductive films, etc. constituting the semiconductor device, If the electrical characteristics of the transistor do not deteriorate, the higher the heat treatment temperature, the better. . Specifically, for example, a temperature of 450 °C or higher, preferably 490 °C or higher, more preferably 530 °C or higher may be used, but it may also be carried out at 650 °C or higher. In an inert gas atmosphere or under a reduced pressure atmosphere, heat treatment for 1 hour or more, preferably 5 hours or more, more preferably 10 hours or more is preferably carried out. Also, the heat treatment temperature should be determined in consideration of the heat resistance of the wiring or electrodes included in the first layer 11 and the first wiring layer 31, and the material of the plug provided in the first insulating layer 21. For example, when the heat resistance of the material is low, it may be carried out at a temperature of 550 °C or lower, or 600 °C or lower, or 650 or lower, or 800 °C or lower. Also, such heat treatment may be carried out at least once or more, but it is more preferable to carry it out multiple times.

[0044] The insulating film provided in the layer below the barrier layer 41 has a desorption amount of hydrogen molecules at a substrate surface temperature of 400 °C, measured by temperature programmed desorption gas spectrometry (also called TDS analysis), which is 130% or less, preferably 110% or less of the desorption amount of hydrogen molecules at 300 °C. Alternatively, the desorption amount of hydrogen molecules at a substrate surface temperature of 450 °C, measured by TDS analysis, is preferably 130% or less, preferably 110% or less of the desorption amount at 350 °C. .

[0045] Also, it is preferable that the water and hydrogen contained in the barrier layer 41 itself are reduced. For example, as the barrier layer 41, the desorption amount of hydrogen molecules (M / z = 2) in the range of a substrate surface temperature of 20 °C to 600 °C, measured by TDS analysis, is less than 2×10 15 pieces / cm 2 , preferably less than 1×1015 pieces / cm 2 less than, more preferably 5×10 14 pieces / cm 2 less than It is preferable to use the material for the barrier layer 41. Or, the amount of desorption of water molecules (M / z = 18) in the range where the substrate surface temperature is from 20°C to 600°C as measured by TDS analysis is 1×10 less than, preferably 5×10 16 pieces / cm 2 less than, more preferably 15 pieces / cm 2 less than, even more preferably 2×10 12 pieces / cm 2 less than. It is preferable to use the material for the barrier layer 41.

[0046] Also, when single crystal silicon is used for the semiconductor layer of the first transistor included in the first layer 11 the heat treatment can also serve as a treatment for terminating the unpaired bonds of silicon (also called dangling bonds) with hydrogen (also called hydrogenation treatment). By the hydrogenation treatment, a part of the hydrogen contained in the first layer 11 and the insulating layer 21 is desorbed and diffuses into the semiconductor layer of the first transistor, and by terminating the dangling bonds in silicon the reliability of the first transistor can be improved.

[0047] Examples of the material that can be used for the barrier layer 41 include silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. In particular, aluminum oxide is preferable because it has excellent barrier properties against water and hydrogen.

[0048] In addition to the layer of a material that is difficult to permeate water and hydrogen, the barrier layer 41 includes a layer containing other insulating materials stacked​​​​​ It may be used in a layered form. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing a metal oxide, etc. may be laminated and used.

[0049] Also, it is preferable to use a material with low oxygen permeability for the barrier layer 41. The above-described materials are materials that are excellent in barrier properties against hydrogen, water, and also oxygen. By using such a material it is possible to suppress the diffusion of oxygen released when the second insulating layer 22 is heated to a layer below the barrier layer 41. As a result, the amount of oxygen that can be released from the second insulating layer 22 and supplied to the semiconductor layer of the second transistor in the second layer 12 can be increased.

[0050] Also, the barrier layer 41 can function as a capacitive dielectric layer. Therefore, when a material with a high dielectric constant (also referred to as a high-k material) is used as the barrier layer 41, it is preferable because the capacitance value per unit area can be increased. Also, by laminating a plurality of layers, it is preferable because the leakage current of the capacitance can be reduced.

[0051] Thus, in one aspect of the present invention, the concentration of hydrogen and water contained in each layer located below the barrier layer 41 is reduced, or hydrogen and water are removed, and further the barrier layer 41 suppresses the diffusion of hydrogen and water to the second layer 12. Therefore, the hydrogen and water content in the second insulating layer 22 and each layer constituting the second transistor contained in the second layer 12 can be made extremely low. For example, the hydrogen concentration contained in the second insulating layer 22, the semiconductor layer of the second transistor, or the gate insulating layer is less than 5×10 cm and preferably 18 cm -3 less than, preferably​ 1×10 18 cm -3 less than, more preferably 3×10 17 cm -3 reduce to less than can be achieved.

[0052] By applying the above-described stacked structure 10 to the semiconductor device according to one aspect of the present invention, for either the first transistor included in the first layer 11 or the second transistor included in the second layer 12, it becomes possible to achieve both high reliability, and a semiconductor device with extremely high reliability can be realized.

[0053] [Configuration Example 1] FIG. 2(A) is an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. The semiconductor device shown in FIG. 2(A) has a first transistor 110, a second transistor 100, a capacitor 130, a wiring BL, a wiring WL, a wiring CL, and a wiring BG.

[0054]

[0055] ​​​​​​​​​​​​The semiconductor device shown in Fig. 2(A) applies a potential corresponding to the potential of wiring BL to node FN when the second transistor 100 is in a conductive state (on state). Also, it has a function of holding the potential of node FN when the second transistor 100 is in a non-conductive state (off state). That is, the semiconductor device shown in Fig. 2(A) has a function as a memory cell of a memory device. When the second transistor 100 is in a non-conductive state (off state), it has a function of holding the potential of node FN. That is, the semiconductor device shown in Fig. 2(A) has a function as a memory cell of a memory device. That is, the semiconductor device shown in Fig. 2(A) has a function as a memory cell of a memory device. In addition, when it has a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to node FN, the semiconductor device in Fig. 2(A) can also function as a pixel of a display device. In addition, when it has a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to node FN, the semiconductor device in Fig. 2(A) can also function as a pixel of a display device. In addition, when it has a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to node FN, the semiconductor device in Fig. 2(A) can also function as a pixel of a display device.

[0056] The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to wiring WL or wiring BG. By using a transistor with a small off-current as the second transistor 100, the potential of node FN in the non-conductive state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned.

[0057] A fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to wiring CL. At this time, the apparent threshold voltage of the second transistor 100 varies depending on the potential of node FN. Utilizing the change in the conductive state and non-conductive state of the first transistor 110 due to the variation in the apparent threshold voltage, the information of the potential held at node FN A fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to wiring CL. At this time, the apparent threshold voltage of the second transistor 100 varies depending on the potential of node FN. Utilizing the change in the conductive state and non-conductive state of the first transistor 110 due to the variation in the apparent threshold voltage, the information of the potential held at node FN A fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to wiring CL. At this time, the apparent threshold voltage of the second transistor 100 varies depending on the potential of node FN. Utilizing the change in the conductive state and non-conductive state of the first transistor 110 due to the variation in the apparent threshold voltage, the information of the potential held at node FN A fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to wiring CL. At this time, the apparent threshold voltage of the second transistor 100 varies depending on the potential of node FN. Utilizing the change in the conductive state and non-conductive state of the first transistor 110 due to the variation in the apparent threshold voltage, the information of the potential held at node FN can be read as data.

[0058] In addition, in order to hold the potential held in the node FN at 85°C for 10 years (3.15×10 8 seconds) per 1 μF of capacitance, the off-current value per 1 μm of the channel width of the transistor is preferably less than 4.3 yA (yoctoampere: 1 yA is 10 A). At this time, the allowable fluctuation of the potential of the node FN is preferably within 0.5 V. -24 Or, at 95°C, the off-current is preferably less than 1.5 yA. In the semiconductor device according to one aspect of the present invention, since the hydrogen concentration in the layer below the barrier layer is sufficiently reduced, as a result, the transistor using the oxide semiconductor in the upper layer can achieve such an extremely low off-current.

[0059] Also, the S value (subthreshold value) of the transistor using the oxide semiconductor is 66 m V / dec. or more, preferably 60 mV / dec. or more, more preferably 50 mV / de c. or more, and 200 mV / dec. or less, preferably 150 mV / dec. or less, more preferably 100 mV / dec. or less, and even more preferably 80 mV / dec. or less. The smaller the S value, the smaller the off-current at a specific voltage for turning off the transistor can be.

[0060] By arranging the semiconductor devices shown in FIG. 2(A) in a matrix, a memory device (memory cell array) can be configured.

[0061] FIG. 2(B) shows an example of the cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. 2(A). ​

[0062] The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor 13 0. The second transistor 100 is provided above the first transistor 110, and a barrier layer 120 is provided between the first transistor 110 and the second transistor 100.

[0063] 〔First layer〕 The first transistor 110 is provided on a semiconductor substrate 111 and has a semiconductor layer 112 formed of a part of the semiconductor substrate 111, a gate insulating layer 114, a gate electrode 115, and low resistance layers 113a and 113b that function as a source region or a drain region. The first transistor 110 may be either p-channel type or n-channel type, and an appropriate transistor may be used according to the circuit configuration and driving method.

[0064]

[0065] In the region where the channel of the semiconductor layer 112 is formed, the region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon having strain in the crystal lattice may also be used. Alternatively, by using GaAs and AlGaAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). Mobility Transistor).

[0066] ​The low-resistance layers 113a and 113b are made of a semiconductor material applied to the semiconductor layer 112 and contain an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron.

[0067] The gate electrode 115 can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is particularly preferable to use tungsten.

[0068] Here, the configuration including the first transistor 110 corresponds to the first layer 11 in the above-described stacked structure.

[0069] Here, instead of the first transistor 110, a transistor 160 as shown in FIG. 3(A) may be used. A cross-section in the channel length direction of the transistor 160 is shown on the left side of FIG. 3(A), and a cross-section in the channel width direction is shown on the right side. The transistor 160 shown in FIG. 3(A) has a convex-shaped semiconductor layer 112 (a part of the semiconductor substrate) in which a channel is formed, and a gate insulating layer 114 and a gate electrode 115 are provided along its side surface and upper surface. Since such a transistor 160 utilizes the convex portion of the semiconductor substrate, it is also called a FIN-type transistor. Note that an insulating layer that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Also, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but an SOI substrate may be processed to form a semiconductor layer having a convex shape.

[0070] 〔First Insulating Layer〕 An insulating layer 121, an insulating layer 122, and an insulating layer 123 are sequentially stacked and provided so as to cover the first transistor 110. are sequentially stacked and provided.

[0071] The insulating layer 121 functions as a protective film during the heat treatment for activating the elements imparting conductivity added to the low-resistance layer 113a and the low-resistance layer 113 b in the manufacturing process of the semiconductor device. The insulating layer 121 may not be provided if it is unnecessary. If the semiconductor layer 112 uses a silicon-based semiconductor material, the insulating layer 122 preferably contains an insulating material containing hydrogen. By providing the insulating layer 122 containing hydrogen on the first transistor 110 and performing heat treatment, the dangling

[0072] bonds in the semiconductor layer 112 are terminated by the hydrogen in the insulating layer 122, and the reliability of the first transistor 110 can be improved. material containing hydrogen on the first transistor 110 and performing heat treatment, the dangling bonds in the semiconductor layer 112 are terminated by the hydrogen in the insulating layer 122, and the reliability of the first transistor 110 can be improved. bonds in the semiconductor layer 112 are terminated by the hydrogen in the insulating layer 122, and the reliability of the first transistor 110 can be improved.

[0073] The insulating layer 123 functions as a planarization layer for planarizing the step difference generated by the first transistor 110 and the like provided below it. The upper surface of the insulating layer 123 may be planarized by a planarization process using the CMP (Chemical Mechanical Polishing) method or the like in order to improve the flatness of the upper surface. or the like in order to improve the flatness of the upper surface. or the like in order to improve the flatness of the upper surface.

[0074] In addition, plugs 161 electrically connected to the low-resistance layer 113a, the low-resistance layer 113 b, etc., and plugs 162 electrically connected to the gate electrode 11 5 of the first transistor 110 are embedded in the insulating layer 121, the insulating layer 122, and the insulating layer 123.

[0075] The configuration including the insulating layer 121, the insulating layer 122, and the insulating layer 123 corresponds to the first insulating layer 21 in the above-described stacked structure. corresponds to the first insulating layer 21 in the above-described stacked structure.

[0076] 〔First wiring layer〕 On top of the insulating layer 123, wirings such as wiring 131, wiring 132, wiring 133, and wiring 134 are provided. are provided.

[0077] Wiring 131 is electrically connected to plug 161. Also, wiring 133 is electrically connected to plug 162, and a part of it also functions as the first electrode of capacitor 130. connected, and a part of it also functions as the first electrode of capacitor 130.

[0078] In this specification etc., it is also possible that an electrode and a wiring electrically connected to the electrode are an integral body. That is, there are cases where a part of the wiring functions as an electrode, or a part of the electrode functions as a wiring. functions as a wiring. There are also cases.

[0079] Here, the configuration including wiring 131, wiring 132, wiring 133, wiring 134, etc. corresponds to the first wiring layer 31 in the above-mentioned stacked layer structure. corresponds to the first wiring layer 31 in the above-mentioned stacked layer structure.

[0080] As materials for wiring 131, wiring 132, wiring 133, wiring 134, etc., conductive materials such as metal materials, alloy materials, or metal oxide materials can be used. In particular, it is preferable to use high melting point materials such as tungsten and molybdenum that achieve both high heat resistance and high conductivity, and it is particularly preferable to use tungsten. conductivity, and it is particularly preferable to use tungsten. preferably, and it is particularly preferable to use tungsten. preferable.

[0081] Also, wiring 131, wiring 132, wiring 133, wiring 134, etc. are provided so as to be embedded in the insulating layer 124, and it is preferable that the upper surfaces of the insulating layer 124 and each of wiring 131, wiring 132, wiring 133, and wiring 134 are planarized. 134 etc. are provided so as to be embedded in the insulating layer 124, and it is preferable that the upper surfaces of the insulating layer 124 and each of wiring 131, wiring 132, wiring 133, and wiring 134 are planarized. are planarized.

[0082] 〔Barrier layer〕 The barrier layer 120 is the insulating layer 124, wiring 131, wiring 132, wiring 133, and wiring 13 It is provided to cover the upper surface such as 4. The barrier layer 120 corresponds to the barrier layer 41 in the above-described laminated structure. Regarding the material of the barrier layer 120, the description of the barrier layer 41 can be referred to.

[0083] In the region where the wiring 133 and the wiring 142 described later overlap, the barrier layer 120 also functions as the dielectric layer of the capacitor 130.

[0084] Further, the barrier layer 120 has an opening for electrically connecting the wiring 132 and the wiring 141 described later, and an opening for electrically connecting the wiring 134 and the wiring 142 described later.

[0085] 〔Second Wiring Layer〕 On the barrier layer 120, wirings 141, 142, etc. are provided. The configuration including the wirings 141, 142, etc. corresponds to the second wiring layer 32 in the above-described laminated structure.

[0086] The wiring 141 is electrically connected to the wiring 132 through the opening provided in the barrier layer 120. A part of the wiring 141 overlaps with the channel formation region of the second transistor 100 described later and functions as the second gate electrode of the second transistor 100.

[0087] As shown in FIG. 4(B), a configuration using the wiring 132 as the second gate electrode of the second transistor 100 may be adopted.

[0088] The wiring 142 is electrically connected to the wiring 134 through the opening provided in the barrier layer 120. A part of the wiring 142 overlaps with the wiring 133 and functions as the second electrode of the capacitor 130.

[0089] ​​​​​​​​​​​Here, as the material constituting the wiring 141, wiring 142, etc., a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, when heat resistance is required, it is preferable to use a high melting point material such as tungsten or molybdenum. Also, considering conductivity, it is preferable to use a low-resistance metal material or alloy material, such as a metal material like aluminum, chromium, copper, tantalum, titanium, or an alloy material containing such a metal material, which may be used in a single layer or laminated. In addition, as the material constituting the wiring 141, wiring 142, etc., it is preferable to use a metal oxide containing an element other than the main component such as phosphorus, boron, carbon, nitrogen, or a transition metal element. Such metal oxides can achieve high conductivity. For example, materials with enhanced conductivity by including the above-mentioned elements can be used in metal oxides such as In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). Furthermore, since such metal oxides are difficult to permeate oxygen, covering the openings provided in the barrier layer 120 with the wiring 141, wiring 142, etc. containing such a material can suppress the oxygen released when the insulating layer 125 described later is heat-treated from diffusing downward more than the barrier layer 120. As a result, the amount of oxygen that can be supplied from the insulating layer 125 to the semiconductor layer of the second transistor 100 can be increased. Moreover, as shown in FIG. 4(A), wiring 141a and wiring 141b that are formed simultaneously with the wiring 141 and wiring 142 and etched simultaneously may be provided. The wiring 141a, wiring 14 ... can be formed and used in a single layer or laminated.

[0090] Also, as the material constituting the wiring 141, wiring 142, etc., it is preferable to use a metal oxide containing an element other than the main component such as phosphorus, boron, carbon, nitrogen, or a transition metal element. Such metal oxides can achieve high conductivity. For example, materials with enhanced conductivity by including the above-mentioned elements can be used in metal oxides such as In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). Furthermore, since such metal oxides are difficult to permeate oxygen, covering the openings provided in the barrier layer 120 with the wiring 141, wiring 142, etc. containing such a material can suppress the oxygen released when the insulating layer 125 described later is heat-treated from diffusing downward more than the barrier layer 120. As a result, the amount of oxygen that can be supplied from the insulating layer 125 to the semiconductor layer of the second transistor 100 can be increased. Here, as the material constituting the wiring 141, wiring 142, etc., a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, when heat resistance is required, it is preferable to use a high melting point material such as tungsten or molybdenum. Also, considering conductivity, it is preferable to use a low-resistance metal material or alloy material, such as a metal material like aluminum, chromium, copper, tantalum, titanium, or an alloy material containing such a metal material, which may be used in a single layer or laminated. -Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, C e, Nd or Hf), etc., can be used. Furthermore, since such metal oxides are difficult to permeate oxygen, covering the openings provided in the barrier layer 120 with the wiring 141, wiring 142, etc. containing such a material can suppress the oxygen released when the insulating layer 125 described later is heat-treated from diffusing downward more than the barrier layer 120. As a result, the amount of oxygen that can be supplied from the insulating layer 125 to the semiconductor layer of the second transistor 100 can be increased. Moreover, as shown in FIG. 4(A), wiring 141a and wiring 141b that are formed simultaneously with the wiring 141 and wiring 142 and etched simultaneously may be provided. The wiring 141a, wiring 141b can be formed and used in a single layer or laminated. Here, as the material constituting the wiring 141, wiring 142, etc., a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, when heat resistance is required, it is preferable to use a high melting point material such as tungsten or molybdenum. Also, considering conductivity, it is preferable to use a low-resistance metal material or alloy material, such as a metal material like aluminum, chromium, copper, tantalum, titanium, or an alloy material containing such a metal material, which may be used in a single layer or laminated. In addition, as the material constituting the wiring 141, wiring 142, etc., it is preferable to use a metal oxide containing an element other than the main component such as phosphorus, boron, carbon, nitrogen, or a transition metal element. Such metal oxides can achieve high conductivity. For example, materials with enhanced conductivity by including the above-mentioned elements can be used in metal oxides such as In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). Furthermore, since such metal oxides are difficult to permeate oxygen, covering the openings provided in the barrier layer 120 with the wiring 141, wiring 142, etc. containing such a material can suppress the oxygen released when the insulating layer 125 described later is heat-treated from diffusing downward more than the barrier layer 120. As a result, the amount of oxygen that can be supplied from the insulating layer 125 to the semiconductor layer of the second transistor 100 can be increased. ...

[0091] Note that, as shown in FIG. 4(A), wiring 141a and wiring 141b that are formed simultaneously with the wiring 141 and wiring 142 and etched simultaneously may be provided. The wiring 141a, wiring 14 1b is connected to wiring 131, wiring 133, etc.

[0092] Note that wiring 142 is not connected to wiring 134 and may be connected to another wiring. As an example, as shown in FIG. 4(B), wiring 142 may be connected to wiring 103c that is formed and etched simultaneously with electrodes 103a and 103b.

[0093] 〔Second insulating layer〕 An insulating layer 125 is provided to cover the barrier layer 120, wiring 141, wiring 142, etc. Here, the region including the insulating layer 125 corresponds to the second insulating layer 22 in the above-described stacked structure.

[0094] The upper surface of the insulating layer 125 is preferably flattened by the above-described flattening process.

[0095] The insulating layer 125 is preferably made of an oxide material from which a part of oxygen is desorbed by heating.

[0096] As the oxide material from which oxygen is desorbed by heating, it is preferable to use an oxide containing more oxygen than the oxygen satisfying the stoichiometric composition. An oxide film containing more oxygen than the oxygen satisfying the stoichiometric composition desorbs a part of oxygen by heating. An oxide film containing more oxygen than the oxygen satisfying the stoichiometric composition has an oxygen desorption amount, in terms of oxygen atoms, of 1.0 × 10 atoms / cm or more, preferably 3.0 × 10 atoms / cm 18 or more as analyzed by temperature programmed desorption spectroscopy (TDS). Note that the surface temperature of the film during the above TDS analysis 3 20 at oms / cm 3 ​​​​The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0097] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can also be used. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0098] [Second layer] A second transistor 100 is provided on top of the insulating layer 125. The structure including the resistor 100 corresponds to the second layer 12 in the above-mentioned laminated structure.

[0099] The second transistor 100 includes a first oxide layer 101a in contact with the upper surface of the insulating layer 125 and The semiconductor layer 102 is in contact with the upper surface of the first oxide layer 101a, and the semiconductor layer 102 is in contact with the upper surface of the semiconductor layer 102. The electrodes 103a and 103b are spaced apart in the region where they overlap the semiconductor layer 102, and the semiconductor layer A second oxide layer 101b is in contact with the upper surface of the second oxide layer 101b, and a gate insulating layer is formed on the second oxide layer 101b. The semiconductor layer 102 is connected to the insulating layer 104 via the second oxide layer 101b. and a gate electrode 105 overlapping the second transistor 100. A layer 107, an insulating layer 108, and an insulating layer 126 are provided.

[0100] At least a part (or the whole) of the electrode 103a (and / or the electrode 103b) , the surface, side, etc. of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a) The surface is provided on at least a part (or all) of the face, upper face, and / or lower face.

[0101] Alternatively, at least a part (or all) of electrode 103a (and / or electrode 103b) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a). Or at least a part (or all) of electrode 103a (and / or electrode 103b) is a semiconductor in contact with at least a part ( or all) of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a).

[0102] Alternatively, at least a part (or all) of electrode 103a (and / or electrode 103b) is electrically connected to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a). Or at least a part (or all ) of electrode 103a (and / or electrode 103b) is electrically connected to a part ( or all) of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a).

[0103] Alternatively, at least a part (or all) of electrode 103a (and / or electrode 103b) is disposed in proximity to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a). Or at least a part (or all ) of electrode 103a (and / or electrode 103b) is disposed in proximity to a part ( or all) of a semiconductor layer such as semiconductor layer 102 (and / or first oxide layer 101a).

[0104] ​​Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed at least partially (or entirely) laterally to the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a). Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed laterally to a part (or all) of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a).

[0105] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed obliquely above at least partially (or entirely) the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a). Alternatively, at least a part (or all ) of the electrode 103a (and / or the electrode 103b) is disposed obliquely above a part ( or all) of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a).

[0106] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed above at least partially (or entirely) the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a). Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed above a part (or all) of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a).

[0107] The semiconductor layer 102 is a semiconductor such as a silicon-based semiconductor in a region where a channel is formed.​ It may include a body. In particular, the semiconductor layer 102 preferably contains a semiconductor having a larger bandgap than silicon. Preferably, it is configured to include an oxide semiconductor. Using a semiconductor material with a wider bandgap and a lower carrier density than silicon is preferable because it can reduce the current in the off state of the transistor.

[0108] For example, as the above oxide semiconductor, it is preferable to contain at least indium (In) or zinc (Zn). More preferably, it contains an oxide represented by an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf).

[0109] In particular, as the semiconductor layer, an oxide semiconductor film having a plurality of crystal parts, wherein the c-axis of the crystal parts is oriented perpendicular to the surface to be formed of the semiconductor layer or the upper surface of the semiconductor layer, and there is no grain boundary between adjacent crystal parts, is preferably used.

[0110] By using such a material as the semiconductor layer, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor can be realized.

[0111] Note that the preferred form of the oxide semiconductor applicable to the semiconductor layer and its formation method will be described in detail in the following embodiments.

[0112] A semiconductor device according to an aspect of the present invention preferably has an oxide layer containing at least one metal element among the metal elements constituting the oxide semiconductor layer between the oxide semiconductor layer and the insulating layer overlapping the oxide semiconductor layer. Thereby, between the oxide semiconductor layer and the oxide It is possible to suppress the formation of trap levels at the interface between the insulating layer and the semiconductor layer. That is.

[0113] In one aspect of the present invention, it is preferable that the upper surface and the lower surface in at least the channel formation region of the oxide semiconductor layer are in contact with an oxide layer that functions as a barrier film for preventing the formation of interface levels in the oxide semiconductor layer. By adopting such a configuration, it is possible to suppress the generation of oxygen vacancies and the incorporation of impurities, which are factors for generating carriers, in the oxide semiconductor layer and at the interface. Therefore, the oxide semiconductor layer can be made highly pure and intrinsic. Making the oxide semiconductor layer highly pure and intrinsic means making the oxide semiconductor layer intrinsic or substantially intrinsic. Thus, it is possible to suppress fluctuations in the electrical characteristics of the transistor including the oxide semiconductor layer and provide a highly reliable semiconductor device. The upper surface and the lower surface function as a barrier film for preventing the formation of interface levels in the oxide semiconductor layer. By adopting such a configuration, it is possible to suppress the generation of oxygen vacancies and the incorporation of impurities, which are factors for generating carriers, in the oxide semiconductor layer and at the interface. Therefore, the oxide semiconductor layer can be made highly pure and intrinsic. The generation of oxygen vacancies and the incorporation of impurities, which are factors for generating carriers, in the oxide semiconductor layer and at the interface. Therefore, the oxide semiconductor layer can be made highly pure and intrinsic. Making the oxide semiconductor layer highly pure and intrinsic means making the oxide semiconductor layer intrinsic or substantially intrinsic. Thus, it is possible to suppress fluctuations in the electrical characteristics of the transistor including the oxide semiconductor layer and provide a highly reliable semiconductor device. Therefore, it is possible to provide a highly reliable semiconductor device.

[0114] When substantially intrinsic is mentioned in this specification or the like, the carrier density of the oxide semiconductor layer is less than 1×10 / cm 17 / cm 3 less than 1×10 15 / cm 3 less than 1×10 13 / cm 3 By making the oxide semiconductor layer highly pure and intrinsic, stable electrical characteristics can be imparted to the transistor. Stable electrical characteristics can be imparted to the transistor.

[0115] The first oxide layer 101a is provided between the insulating layer 125 and the semiconductor layer 102.

[0116] The second oxide layer 101b is provided between the semiconductor layer 102 and the gate insulating layer 104. More specifically, the upper surface of the second oxide layer 101b is in contact with the lower surface of the gate insulating layer 104. It is provided in contact therewith, and its lower surface is in contact with the upper surfaces of the first electrode 103a and the second electrode 103b. It is provided in this way.

[0117] The first oxide layer 101a and the second oxide layer 101b each contain an oxide containing one or more of the same metal elements as the semiconductor layer 102. It contains an oxide containing one or more of the same metal elements as the semiconductor layer 102.

[0118] Note that the boundaries between the semiconductor layer 102 and the first oxide layer 101a, and between the semiconductor layer 102 and the second oxide layer 101b may be unclear. The boundaries between the semiconductor layer 102 and the first oxide layer 101a, and between the semiconductor layer 102 and the second oxide layer 101b may be unclear.

[0119] For example, the first oxide layer 101a and the second oxide layer 101b contain In or Ga. Typically, they are In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and a material is used in which the energy of the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 102. Typically the difference between the energy of the lower end of the conduction band of the first oxide layer 101a or the second oxide layer 101b and the energy of the lower end of the conduction band of the semiconductor layer 102 is preferably 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0. the energy of the lower end of the conduction band of the first oxide layer 101a or the second oxide layer 101b and the energy of the lower end of the conduction band of the semiconductor layer 102 is preferably 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0. 5 eV or less, or 0.4 eV or less. By using an oxide with a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 for the first oxide layer 101a and the second oxide layer 101b provided so as to sandwich the semiconductor layer 102, the release of oxygen from the semiconductor layer 102 can be suppressed.

[0120] For the first oxide layer 101a and the second oxide layer 101b provided so as to sandwich the semiconductor layer 102, an oxide with a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 is used. By using an oxide with a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 for the first oxide layer 101a and the second oxide layer 101b provided so as to sandwich the semiconductor layer 102, the release of oxygen from the semiconductor layer 102 can be suppressed.

[0121] As the semiconductor layer 102, for example, In:Ga:Zn = 1:1:1 or 3:1:2 in terms of atomic When an In-Ga-Zn oxide having a numerical ratio is used, the first oxide layer 101a or the second oxide layer The compound layer 101b may be, for example, In:Ga:Zn=1:3:2, 1:3:4, or 1:3:6. , 1:6:4, 1:6:8, 1:6:10, or 1:9:6 atomic ratios of In-G The semiconductor layer 102 and the first oxide layer 101 can be made of a-Zn oxide. The atomic ratios of the first oxide layer 101a and the second oxide layer 101b are calculated by subtracting the above atomic ratios from the atomic ratios as errors. The variation of the first oxide layer 101a and the second oxide layer 10 For 1b, materials having the same composition may be used, or materials having different compositions may be used.

[0122] In addition, when an In-M-Zn oxide is used as the semiconductor layer 102, the semiconductor layer 102 and The target used for forming the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3 or less. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, It is preferable to use an oxide having an atomic ratio of 1 to 6. In addition, when z1 / y1 is 6 or less, This makes it easier to form the CAAC-OS film described later. Representative examples of atomic ratios include In:M:Zn=1:1:1 and 3:1:2.

[0123] The first oxide layer 101a and the second oxide layer 101b are made of In-M-Zn oxide. When a material such as a fluorine-containing oxide is used, oxide films that become the first oxide layer 101a and the second oxide layer 101b are formed. The target used for forming the film has an atomic ratio of metal elements contained in the target of In: When M:Zn=x2:y2:z2, x2 / y2 <x1 / y1であり、z2 / y2 It is preferable to use an oxide having an atomic ratio of 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. It is preferable that z2 / y2 is 6 or less. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1: Examples include 3:4, 1:3:6, 1:3:8, etc.

[0124] In addition, the first oxide layer 101a and the second oxide layer 101b have a higher conductivity than the semiconductor layer 102. By using materials whose conduction band bottom energy is close to the vacuum level, the semiconductor layer 10 A channel is mainly formed in the semiconductor layer 102, and the semiconductor layer 102 becomes the main current path. The semiconductor layer 102 in which the channel is formed is covered with a first oxide layer 101a and a second oxide layer 102b containing the same metal element. By sandwiching the first oxide layer 101b and the second oxide layer 101c, the generation of these interface states is suppressed. This improves the reliability of the electrical characteristics of the transistor.

[0125] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of the transistor, the semiconductor layer 102, the first oxide layer 101a, and the second oxide layer 102 are formed. The carrier density, impurity concentration, defect density, number of metal elements and oxygen atoms of the oxide layer 101b of 2 It is preferable to set the ratio, interatomic distance, density, etc. appropriately.

[0126] Here, the first oxide layer 101a is formed between the first oxide layer 101a and the semiconductor layer 102. In some cases, the semiconductor layer 102 may have a mixed region of the second acid and the semiconductor layer 102. A mixed region of the semiconductor layer 102 and the second oxide layer 101b is formed between the first oxide layer 101a and the second oxide layer 101b. It may occur. In the mixed region, the interface state density decreases. Therefore, the first oxide layer 10 1a, the semiconductor layer 102, and the laminate of the second oxide layer 101b each have near their respective interfaces a band structure in which energy changes continuously (also referred to as a continuous junction).

[0127] Here, the band structure will be described. For ease of understanding, the conduction band bottom energy (Ec) of the insulating layer 1 25, the first oxide layer 101a, the semiconductor layer 102, the second oxide layer 101b, and the gate insulating layer 104 is shown.

[0128] As shown in FIGS. 30(A) and 30(B), in the first oxide layer 101a, the semiconductor layer 102 , and the second oxide layer 101b, the energy at the bottom of the conduction band changes continuously. This is also understood from the fact that the elements constituting the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b are common, and oxygen diffuses easily among them. Therefore, the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b are a laminate of layers with different compositions but can also be said to be physically continuous.

[0129] Oxide films laminated with a common main component are not simply laminated layer by layer but are formed into a continuous junction( here, in particular, a U-shaped well structure in which the energy at the bottom of the conduction band changes continuously between layers) is fabricated. That is, a laminate structure is formed such that there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of the respective layers. If impurities are mixed between the laminated multilayers, the continuity of the energy bands is lost, and carriers disappear due to trapping or recombination at the interface.

[0130]

[0130] Note that, in FIG. 30(A), the Ec of the first oxide layer 101a and the second oxide layer 101b is shown for the case where they are the same, but they may be different from each other. For example, when the Ec of the second oxide layer 101b has a higher energy than that of the first oxide layer 101a, a part of the band structure is shown as in FIG. 30(B).

[0131] From FIGS. 30(A) and 30(B), it can be seen that the semiconductor layer 102 becomes a well, and in the transistor 100, a channel is formed in the semiconductor layer 102. Note that since the energy of the lower end of the conduction band of the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b changes continuously, it can also be called a U-shaped well. Further, the channel formed in such a configuration can also be called an embedded channel.

[0132] Note that trap levels due to impurities or defects may be formed near the interfaces between the first oxide layer 101a and the second oxide layer 101b and an insulating film such as a silicon oxide film. Due to the presence of the first oxide layer 101a and the second oxide layer 101b, the semiconductor layer 102 and the trap levels can be separated from each other. However, when the energy difference between the Ec of the first oxide layer 101a or the second oxide layer 101b and the Ec of the semiconductor layer 102 is small, electrons in the semiconductor layer 102 may reach the trap levels across the energy difference. When electrons that become minority charges are trapped in the trap levels, the threshold voltage of the transistor shifts in the positive direction.

[0133] ​Therefore, in order to reduce the variation in the threshold voltage of the transistor, an energy difference is provided between the Ec of the first oxide layer 10 1a and the second oxide layer 101b and the semiconductor layer 102. Each of these energy differences is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0134] Note that the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b preferably contain a crystalline part. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0135] Also, in the band structure as shown in FIG. 30(B), instead of providing the second oxide layer 101b, an In-Ga oxide (for example, with an atomic ratio of In:Ga = 7:93) may be provided between the semiconductor layer 102 and the gate insulating layer 104.

[0136] The semiconductor layer 102 is made of an oxide with a greater electron affinity than the first oxide layer 101a and the second oxide layer 101b. For example, as the semiconductor layer 102, an oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less greater than that of the first oxide layer 101 a and the second oxide layer 101b is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band.

[0137] Here, the thickness of the semiconductor layer 102 is preferably formed to be at least thicker than the first oxide layer 101a. The thicker the semiconductor layer 102, the higher the on-current of the transistor can be increased. Also, the first oxide layer 101a suppresses the generation of interface levels in the semiconductor layer 102. ​ It may have a thickness such that the effect is not lost. For example, the thickness of the semiconductor layer 102 is greater than 1 times, preferably 2 times or more, more preferably 4 times or more, and even more preferably 6 times or more, with respect to the thickness of the first oxide layer 101a. However, this is not the case when it is not necessary to increase the on-current of the transistor. The thickness of the first oxide layer 101a may be equal to or greater than the thickness of the semiconductor layer 102.

[0138] Also, the second oxide layer 101b may have a thickness such that the effect of suppressing the generation of interface levels at the interface with the semiconductor layer 102 is not lost, similar to the first oxide layer 101a. For example, it may have a thickness equal to or less than that of the first oxide layer 101a. If the second oxide layer 101b is thick, there is a possibility that the electric field by the gate electrode 105 may not easily reach the semiconductor layer 102. Therefore, it is preferable to form the second oxide layer 101b thin. For example, it may be thinner than the thickness of the semiconductor layer 102. However, it is not limited to this. The thickness of the second oxide layer 101b may be appropriately set according to the voltage for driving the transistor, taking into account the breakdown voltage of the gate insulating layer 104.

[0139] Here, for example, when the semiconductor layer 102 is in contact with an insulating layer having different constituent elements (for example, an insulating layer containing a silicon oxide film, etc.), interface levels are formed at these interfaces, and these interface levels may form channels. In such a case, a second transistor with a different threshold voltage may appear, and the apparent threshold voltage of the transistor may vary. However, in the transistor of this configuration, since the first oxide layer 101a contains one or more metal elements constituting the semiconductor layer 102, the first oxide layer 101a and the semiconductor layer 102 have the first oxide layer 101a. It becomes difficult to form an interface level at the interface with [it]. Therefore, by providing the first oxide layer 101a Furthermore, variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor can be reduced. It can be done.

[0140] Also, when a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, interface scattering occurs at the interface, and the field-effect mobility of the transistor may decrease. However, in the transistor of this configuration, since the semiconductor layer 102 contains one or more metal elements constituting it and has the second oxide layer 101b, carrier scattering hardly occurs at the interface between the semiconductor layer 102 and the second oxide layer 1 01b, and the field-effect mobility of the transistor can be increased. 01b, and the field-effect mobility of the transistor can be increased. 01b, and the field-effect mobility of the transistor can be increased. It can be increased.

[0141] One of the electrodes 103a and 103b functions as a source electrode, and the other functions as a drain electrode. It functions as an electrode.

[0142] The electrode 103a is electrically connected to the wiring 13 1 through an opening provided in the insulating layer 125 and the barrier layer 120. The electrode 103b is also electrically connected to the wiring 133 through a similar opening. It is connected.

[0143] In FIG. 2(B), a configuration is shown in which the electrode 103a and the wiring 131, and the electrode 103b and the wiring 133 are in contact with each other. However, as shown in FIG. 3(B), a configuration in which they are electrically connected using plugs 165 and 166 embedded in the insulating layer 125 and the barrier layer 12 0 may also be used. 0 may also be used. It may be a configuration.

[0144] The electrodes 103a and 103b are made of aluminum, titanium, chromium, nickel, copper, or indium. A single metal composed of yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component is used as a single-layer structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. are provided. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used. The gate insulating layer 104 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide, silicon nitride, etc., and may be provided in a laminated or single-layer form. Also, as the gate insulating layer 104, hafnium silicate (HfSiO ), hafnium silicate (HfSi to which nitrogen is added

[0145] O ), hafnium aluminate (HfAl to which nitrogen is added

[0146] ), etc. may be used. x ), hafnium silicate (HfSi to which nitrogen is added x O y N z ), hafnium aluminate (HfAl to which nitrogen is added x O y N z) It is also possible to use high-k materials such as yttrium oxide. This is also acceptable.

[0147] In addition, as the gate insulating layer 104, similar to the insulating layer 125, it is preferable to use an oxide insulating film containing more oxygen than the stoichiometric composition. This is also acceptable.

[0148] Note that when a specific material is used for the gate insulating layer, electrons can be trapped in the gate insulating layer under specific conditions, increasing the threshold voltage. For example, in a stacked film of silicon oxide and hafnium oxide, a material with many electron trapping levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for a part of the gate insulating layer, and at a higher temperature (higher than the operating temperature or storage temperature of the semiconductor device, or 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a higher level than the potential of the source electrode or drain electrode for 1 second or more, typically 1 minute or more. As a result, electrons move from the semiconductor layer toward the gate electrode, and some of them are trapped at the electron trapping levels. For example, in a stacked film of silicon oxide and hafnium oxide, a material with many electron trapping levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for a part of the gate insulating layer, and at a higher temperature (higher than the operating temperature or storage temperature of the semiconductor device, or 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a higher level than the potential of the source electrode or drain electrode for 1 second or more, typically 1 minute or more. As a result, electrons move from the semiconductor layer toward the gate electrode, and some of them are trapped at the electron trapping levels. or a temperature higher than the storage temperature, or 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a higher level than the potential of the source electrode or drain electrode for 1 second or more, typically 1 minute or more. As a result, electrons move from the semiconductor layer toward the gate electrode, and some of them are trapped at the electron trapping levels. In this way, the transistor that has trapped the necessary amount of electrons at the electron trapping levels has a threshold voltage that shifts to the positive side. By controlling the amount of electrons trapped by controlling the voltage of the gate electrode,

[0149] the threshold voltage can be controlled accordingly. In addition, the process of trapping electrons can be performed during the manufacturing process of the transistor. For example, after forming the wiring metal connected to the source electrode or drain electrode of the transistor, or after the completion of the previous process (wafer processing), or after the wafer dicing process.

[0150] For example, after forming the wiring metal connected to the source electrode or drain electrode of the transistor, or after the completion of the previous process (wafer processing), or after the wafer dicing process. , it may be performed at any stage before factory shipment, such as after packaging. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter.

[0151] The gate electrode 105 can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metals as components, or an alloy combining the above-described metals. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. Further, the gate electrode 105 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film and a titanium film is further formed thereon, and the like. Further, an alloy film or a nitride film combining one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium with aluminum may be used. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter.

[0152] Further, the gate electrode 105 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium oxide doped with silicon oxide, Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. Preferably, it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. It is also possible to apply a conductive material having translucency such as indium tin oxide. Also , it is also possible to form a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal.

[0153] Further, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (I nN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more , and since it is a value larger than the electron affinity of the oxide semiconductor, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally -off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration of at least higher than that of the semiconductor layer 102, specifically 7 atomic% or more is used.

[0154] Similar to the barrier layer 120, it is preferable to use a material in which water and hydrogen hardly diffuse for the insulating layer 107. Further, in particular, it is preferable to use a material in which oxygen hardly permeates as the insulating layer 107 .

[0155] By covering the semiconductor layer 102 with the insulating layer 107 containing a material in which oxygen hardly permeates, it is possible to suppress oxygen from being released from the semiconductor layer 102 above the insulating layer 107. Further , since the oxygen desorbed from the insulating layer 125 can be confined below the insulating layer 107 , the amount of oxygen that can be supplied to the semiconductor layer 102 can be increased.

[0156] In addition, the insulating layer 107 that hardly permeates water or hydrogen suppresses the entry of water and hydrogen, which are impurities for the oxide semiconductor from the outside, and the electrical characteristics of the second transistor 100 can be suppressed from fluctuating, and a highly reliable transistor can be realized.

[0157] Note that an insulating layer similar to the insulating layer 125, from which oxygen desorbs by heating, is provided below the insulating layer 107, and oxygen is also supplied from above the semiconductor layer 102 through the gate insulating layer 104 It may be configured as.

[0158] Here, another configuration example of the transistor applicable to the second transistor 100 is shown . FIG. 5(A) is a schematic top view of the transistor illustrated below, and FIGS. 5(B) and 5( C) are schematic cross-sectional views when cut along the cutting lines A1-A2 and B1-B2 in FIG. 5(A), respectively . Note that FIG. 5(B) corresponds to a cross-section in the channel length direction of the transistor, and FIG. 5( C) corresponds to a cross-section in the channel width direction of the transistor.

[0159] In FIG. 5, compared with the second transistor 100 shown in FIG. 2(B), an example is shown in which the top surface shapes of the gate insulating layer 1 04 and the second oxide layer 101b are processed using the same photomask so as to substantially match the top surface shape of the gate electrode 105 .

[0160] In the present specification and the like, "substantially matching top surface shape" means that at least a part of the contours overlap between the stacked layers. For example, it includes the case where the upper layer and the lower layer are processed using the same mask pattern , or a part thereof is processed using the same mask pattern. However, strictly speaking, the contours do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer In some cases, it is also said that "the upper surface shapes are substantially the same".

[0161] Also, as shown in FIG. 5(C), in the cross section in the channel width direction of the transistor, the gate electrode 105 is provided facing the upper surface and the side surface of the semiconductor layer 102, so that a channel is formed not only in the vicinity of the upper surface of the semiconductor layer 10 2 but also in the vicinity of the side surface, increasing the effective channel width and enabling an increase in the current in the on state (on-current). In particular, when the width of the semiconductor layer 102 is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), the region where the channel is formed extends to the inside of the semiconductor layer 102, so that the contribution to the on-current increases as the device is miniaturized.

[0162] The transistors shown in FIGS. 6(A) and (B) are mainly different from the transistor exemplified in FIG. 3 in that the second oxide layer 101b is provided in contact with the lower surfaces of the electrodes 103a and 103b.

[0163] With such a configuration, when forming each of the films constituting the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b, it is possible to continuously form the films without exposing them to the atmosphere, so that interface defects can be reduced.

[0164] Also, in the above description, a configuration in which the first oxide layer 101a and the second oxide layer 101b are provided in contact with the semiconductor layer 102 has been described, but it is also possible to adopt a configuration in which one of, or both of, the first oxide layer 101a and the second oxide layer 10 1b are not provided.

[0165] In FIGS. 7(A) and (B), the first oxide layer 101a and the second oxide layer 101b are not provided. Examples of the case are shown. Also, FIGS. 8(A) and 8(B) show examples of the case where the first oxide layer 101a is provided and the second oxide layer 101b is not provided. Also, FIGS. 9(A) and 9(B) show examples of the case where the second oxide layer 101b is provided and the first oxide layer 101a is not provided.

[0166] Note that all the configurations shown in FIGS. 5 to 9 show the case where the upper surface shape of the gate insulating layer 104 is processed to substantially coincide with the gate electrode 105, but the present invention is not limited to this. As long as the gate electrode 1 is located inside the gate insulating layer 104 in at least the region overlapping the semiconductor layer 102 when viewed from the upper surface side, it may be processed. Even when the second oxide layer 101b is provided, the second oxide layer 101b may be processed to have a different upper surface shape from that of the gate electrode 105 and the gate insulating layer 104. Examples of that case are shown in FIGS. 10, 11, and 12.

[0167] Note that the channel length is, for example, in the top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0168] The channel width is, for example, the semiconductor (or when the transistor is in the on state, the inside of the semiconductor)​​​ the region where the part through which current flows) overlaps with the gate electrode, or the region where the channel is formed refers to the length of the portion where the source and the drain face each other in. Note that in one transistor the channel width does not necessarily take the same value in all regions. That is, in one transistor, the channel width may not be determined to be a single value. Therefore, in this specification the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0169] Note that depending on the structure of the transistor, the actual channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width.) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width.) may be different. For example in a transistor having a three-dimensional structure, the effective channel width becomes larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible In some cases. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the upper surface of the semiconductor to the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the upper surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . becomes larger.

[0170] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, the shape of the semiconductor is known. Therefore, the shape of the semiconductor is known. Therefore, the shape of the semiconductor When the state is not precisely known, it is difficult to accurately measure the effective channel width. .

[0171] Therefore, in this specification, in the top view of the transistor, the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap is defined as the apparent channel width, which may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply referred to as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply referred to as the channel width, it may refer to the effective channel width. The apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap in the top view of the transistor, may be called the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply referred to as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply referred to as the channel width, it may refer to the effective channel width. Width)". Also, in this specification, when simply referred to as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply referred to as the channel width, it may refer to the effective channel width. In addition, when simply described as the channel width in this specification, it may refer to the surrounded channel width or the apparent channel width. Or, when simply described as the channel width in this specification, it may refer to the effective channel width. In addition, when simply described as the channel width in this specification, it may refer to the surrounded channel width or the apparent channel width. Or, when simply described as the channel width in this specification, it may refer to the effective channel width. That is, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. That is, the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. and so on.

[0172] Note that when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. Note that when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. That is, it may take a different value from the case of calculating using the effective channel width.

[0173] The above is the description of the second transistor 100.

[0174] The insulating layer 126 covering the second transistor 100 in FIG. 2(B) etc. functions as a planarization layer covering the concave-convex shape of its lower layer. Also, the insulating layer 108 may have a function as a protective film when forming the insulating layer 126. The insulating layer 108 may not be provided if it is not necessary. The insulating layer 126 covering the second transistor 100 in FIG. 2(B) etc. functions as a planarization layer covering the concave-convex shape of its lower layer. Also, the insulating layer 108 may have a function as a protective film when forming the insulating layer 126. The insulating layer 108 may not be provided if it is not necessary. The insulating layer 108 may have a function as a protective film when forming the insulating layer 126. The insulating layer 108 may not be provided if it is not necessary. That is, it may not be provided if it is not necessary.

[0175] In the insulating layer 107, insulating layer 108, and insulating layer 126, plugs 163 that are electrically connected to the electrode 103a, plugs 164 that are electrically connected to the gate electrode 105, etc. are embedded. .

[0176] On the upper part of the insulating layer 126, wiring 151 that is electrically connected to the plug 163, wiring 152 that is electrically connected to the plug 164, etc. are provided.

[0177] Here, in FIG. 2(B), the wiring 151 corresponds to the wiring BL shown in FIG. 2(A). Similarly, the wiring 152 corresponds to the wiring WL, the wiring 134 corresponds to the wiring CL, and the wiring 132 corresponds to the wiring BG. Also, the gate electrode 115 of the first transistor 110, the wiring 133 that functions as the first electrode of the capacitor 130, and the electrode 103b of the second transistor 100 are included in the node that corresponds to the node FN shown in FIG. 2(A).

[0178] The semiconductor device according to one aspect of the present invention has a first transistor 110 and a second transistor 100 located above the first transistor. Therefore, by stacking and providing these, the occupied area of the elements can be reduced. Further, the barrier layer 120 provided between the first transistor 110 and the second transistor 100 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the second transistor 100 side. Furthermore, with the barrier layer 120 interposed therebetween, wiring 133 that partially functions as the first electrode and wiring 142 that partially functions as the second electrode are provided to form the capacitor 130. Therefore, the capacitor 130 can be easily fabricated without separately adding a process for fabricating the capacitor 130. This can be achieved.

[0179] 3C, a layer similar to the barrier layer 120 is formed on the insulating layer 122 containing hydrogen. The insulating layer 140 may be formed by using the above-mentioned material. The upward diffusion of water and hydrogen remaining in the insulating layer 122 containing hydrogen is effectively suppressed. In this case, the insulating layer 140 can be formed before and after the insulating layer 140 is formed. Before forming the barrier layer 120, a heat treatment for removing water and hydrogen was performed twice in total. It is preferable to do the above.

[0180] The above is the explanation of the first configuration example.

[0181] [Configuration example 2] Below, a configuration example that is partially different from the above-mentioned configuration example 1 will be described with reference to the drawings. In the following, explanations of parts that overlap with those above may be omitted.

[0182] FIG. 13 shows an example of a cross-sectional structure of a semiconductor device that can realize the circuit shown in FIG.

[0183] The semiconductor device shown in FIG. 13 includes a first transistor 110, a second transistor 100, and a capacitance 130. The second transistor 100 is located above the first transistor 110. A barrier layer 1 is provided between the first transistor 110 and the second transistor 100. 20 are provided.

[0184] The semiconductor device shown in FIG. 13 has a capacitance of 130 μm compared to the semiconductor device shown in FIG. 2(B). The main difference is that the configuration of the wiring 133 is different. The wiring 134 functions as one of a pair of electrodes of the capacitor 130. The wiring 133 and the wiring 142 are electrically connected to each other through openings provided in the layer 125. The wiring 134 and the wiring 142 have an overlapping area, whereby a capacitance 130 is formed. is.

[0185] That is, in the configuration illustrated in FIG. 2B, the barrier layer of the pair of electrodes of the capacitor 130 The wiring (wiring 133) arranged below 120 (on the first transistor 110 side) 13, the barrier layer 120 is a part of the barrier FN. The wiring (wiring 142) arranged on the upper side (the second transistor 100 side) is connected to one of the nodes FN. The main difference between the two is in the way they are structured.

[0186] As shown in FIG. 14A, the wiring 141 and the wiring 142 are formed at the same time. Alternatively, wiring 141a and wiring 141b may be provided which are etched in the direction perpendicular to the surface of the substrate. 41b is connected to the wiring 131, the wiring 133, and the like.

[0187] As shown in FIG. 14B, the second gate electrode of the second transistor 100 is 14(B), the electrode 103 may be used. Alternatively, b may be connected to the wiring 134 instead of the wiring 142 .

[0188] In FIG. 13, the electrode 103a and the wiring 131, the electrode 103b and the wiring 133, and the electrode 103b and the wiring 142 are in contact with each other. The plugs 165 and 166 embedded in the insulating layer 125 and the barrier layer 120 167 or the like may be used to electrically connect these.

[0189] A semiconductor device according to one aspect of the present invention includes a first transistor 110 and a second transistor 100 located above the first transistor. By stacking and providing these, the occupied area of the elements can be reduced. Furthermore, a barrier layer 120 provided between the first transistor 110 and the second transistor 100 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the second transistor 100 side. Furthermore, a wiring 134 that partly functions as a first electrode and a wiring 142 that partly functions as a second electrode are provided with the barrier layer 120 interposed therebetween to form a capacitor 130. Therefore, the capacitor 130 can be easily fabricated without separately adding a process for fabricating the capacitor 130.

[0190] Also, as shown in FIG. 15(B), an insulating layer 140 containing the same material as the barrier layer 120 may be provided on the insulating layer 122 containing hydrogen. With such a configuration, the diffusion of water and hydrogen remaining in the insulating layer 122 containing hydrogen upward can be effectively suppressed. In this case, it is preferable to perform heat treatment for removing water and hydrogen a total of two or more times before forming the insulating layer 140 and before forming the barrier layer 120 after forming the insulating layer 140.

[0191] FIG. 16 shows a schematic cross-sectional view of a semiconductor device having a configuration partly different from that of FIG. 13. In the semiconductor device shown in FIG. 16, a part of the wiring 142 is electrically connected to the wiring 133 through an opening provided in the barrier layer 120. Also, an electrode 103b of the second transistor 100 is electrically connected to the wiring 142 through an opening of an insulating layer 125 provided in a region overlapping with the wiring 133. That is, in a region overlapping with one opening provided in the insulating layer 125, the electrode 103b, the wire 142, and the wiring 133 are electrically connected to each other. With such a configuration , the number of openings formed in the insulating layer 125 can be reduced, and the occupied area of the semiconductor device can be further reduced.

[0192] The above is the description of Configuration Example 2.

[0193] [Configuration Example 3] Hereinafter, a configuration example of a semiconductor device having a partially different configuration from the above Configuration Examples 1 and 2 will be described with reference to the drawings. Note that hereinafter, the description of the overlapping parts with the above may be omitted .

[0194] FIG. 17(A) is an example of a circuit diagram of a semiconductor device according to an aspect of the present invention. The semiconductor device shown in FIG. 17(A) is different from the semiconductor device shown in FIG. 2(A) in that the second gate of the second transistor 10 0 is electrically connected to the wiring CL instead of the wiring BG.

[0195] FIG. 17(B) shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. 17(A).

[0196] The semiconductor device shown in FIG. 17(B) includes a first transistor 110, a second transistor 1 00, and a capacitor 130. The second transistor 100 is provided above the first transistor 110, and a barrier layer 120 is provided between the first transistor 110 and the second transistor 100.

[0197] The semiconductor device shown in FIG. 17(B) is different from the semiconductor device illustrated in FIG. 2(B) in that the capacitor 130 and its surrounding configurations mainly differ in that they are different. Specifically, the wiring 142 and the like, such as the wiring 134, are not present. Also, the wiring 133 and the wiring 141 have an overlapping region, and the capacitor 130 is formed. The barrier layer 120 functions as a dielectric layer of the capacitor 130 in the region where the wiring 133 and the wiring 141 to be described later overlap.

[0198] That is, the capacitor 130 overlaps with the second transistor 100 and is provided therebelow. Specifically, at least the channel formation region of the semiconductor layer 102 of the second transistor 100 overlaps, and the wiring 133 having a function as the first electrode of the capacitor 130 and the wiring 141 having a function as the second electrode of the capacitor 130 are provided so as to sandwich the barrier layer 120, constituting the capacitor 130. In this way, by providing the capacitor 130 and the second transistor 100 superposed, it is possible to effectively reduce the occupied area of the semiconductor device.

[0199] Here, in FIG. 17(B), the wiring 151 corresponds to the wiring BL shown in FIG. 17(A). Similarly, the wiring 152 corresponds to the wiring WL, and the wiring 132 corresponds to the wiring CL. Also, the gate electrode 115 of the first transistor 110, the wiring 133 functioning as the first electrode of the capacitor 130, and the node including the electrode 103b of the second transistor 100 correspond to the node FN shown in FIG. 17(A).

[0200] The semiconductor device according to one aspect of the present invention has the first transistor 110 and the second transistor 100 located above the first transistor. Therefore, by stacking and providing these, the occupied area of the element can be reduced. Further, the first transistor 110 and the second​​ The barrier layer 120 provided between the transistor 100 and 2 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the second transistor 100 side. Furthermore, wiring 133 that partially functions as the first electrode and wiring 141 that partially functions as the second electrode are provided with the barrier layer 120 interposed therebetween, so that the capacitor 130 can be easily fabricated without separately adding a process for fabricating the capacitor 130.

[0201] As shown in FIG. 18, wiring 141a and wiring 141b that are formed simultaneously with wiring 141 and etched simultaneously may be provided. Wiring 141a and wiring 141b are connected to wiring 131, wiring 133, etc.

[0202] In FIG. 17(B), the configuration where the electrode 103a and the wiring 131, and the electrode 103b and the wiring 133 are in contact with each other is shown. However, as shown in FIG. 19(A), plugs 165, plugs 166, etc. embedded in the insulating layer 125 and the barrier layer 120 may be used so that they are electrically connected.

[0203] Also, as shown in FIG. 19(B), an insulating layer 140 containing the same material as the barrier layer 120 may be provided on the insulating layer 122 containing hydrogen. By adopting such a configuration, the diffusion of water and hydrogen remaining in the insulating layer 122 containing hydrogen upward can be effectively suppressed. In this case, it is preferable to perform a heat treatment for removing water and hydrogen a total of two or more times before forming the insulating layer 140 and before forming the barrier layer 120 after forming the insulating layer 140.

[0204] FIG. 20(A) shows a circuit diagram of a semiconductor device that is partially different in configuration from that of FIG. 17(A).

[0205] The semiconductor device shown in FIG. 20(A) mainly differs in that it newly has a third transistor 180, it has wiring BL1 and wiring BL2 instead of wiring BL, and it has wiring WL1 and wiring WL2 instead of wiring WL.

[0206] For the third transistor 180, its gate is electrically connected to wiring WL2, and one of its source or drain is electrically connected to the other of the source or drain of the first transistor 110, and the other of its source or drain is electrically connected to wiring BL2. For the second transistor 100, its gate is electrically connected to wiring WL1 instead of wiring WL, and the other of its source or drain is electrically connected to wiring BL1 instead of wiring BL.

[0207] FIG. 20(B) shows a schematic cross-sectional view of a semiconductor device applicable to the circuit of FIG. 20(A). In FIG. 20(B), the third transistor 180 can have the same configuration as the first transistor 110. Also, compared with the configuration of FIG. 17(B), it is different in that the electrode 103a of the second transistor 100 is not electrically connected to the wiring 131.

[0208] In the semiconductor device shown in FIG. 20(B), wiring 152 corresponds to wiring WL1, wiring 151 corresponds to wiring BL1, and wiring 131 corresponds to wiring BL2. Also, the gate electrode of the third transistor 180, or a wiring (not shown) electrically connected to the gate electrode, corresponds to wiring WL2.

[0209] By adopting such a configuration, when a part of the wiring 141 is used as the second gate of the second transistor 100 to apply a potential for controlling the threshold voltage of the second transistor 100, it is possible to suppress the influence of the potential applied to the wiring 141 on the potential of the wiring BL2 for reading information.

[0210] The above is the description of Configuration Example 3.

[0211] [Fabrication Method Example 1] Hereinafter, an example of a method for fabricating the semiconductor device shown in the above Configuration Example 1 will be described with reference to FIGS. 21 to 23.

[0212] First, a semiconductor substrate 111 is prepared. As the semiconductor substrate 111, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide, gallium nitride, or the like can be used. Further, an SOI substrate may be used as the semiconductor substrate 111. Hereinafter, the case where a single crystal silicon is used as the semiconductor substrate 111 will be described.

[0213] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer may be formed by using the LOCOS (Local Oxidation of Silicon) method, the STI (Sh allow Trench Isolation) method, or the like.

[0214] When forming a p-type transistor and an n-type transistor on the same substrate, an n-well or a p-well may be formed in a part of the semiconductor substrate 1 11. For example, an impurity element such as boron that imparts p-type conductivity is added to the n-type semiconductor substrate 11 1 to form a p-well, and the same ​​​​An n-type transistor and a p-type transistor may be formed on the substrate.

[0215] Next, an insulating film that will become the gate insulating layer 114 is formed on the semiconductor substrate 111. For example, The surface of the semiconductor substrate 111 is oxidized to form a silicon oxide film. Alternatively, the surface of the semiconductor substrate 111 is oxidized by a thermal oxidation method. After forming the silicon oxide film, a nitriding treatment is performed to nitride the surface of the silicon oxide film. By this, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also known as high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate, zirconium oxide, Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide Objects etc. may also be used.

[0216] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) Alternatively, the film may be formed by a film formation method such as an ion method.

[0217] Subsequently, a conductive film is formed to become the gate electrode 115. The conductive film is made of tantalum, tantalum, or the like. a metal selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. Polycrystalline silicon with impurities added can be used. Also, a stacked structure of a metal nitride film and the above-mentioned metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride den, and titanium nitride can be used. By providing a metal nitride film, the adhesion of the metal film can be improved, and peeling can be prevented.

[0218] The conductive film can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PEC VD method, etc.). Also, to reduce damage by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0219] Subsequently, a resist mask is formed on the conductive film using a photolithography method or the like, and unnecessary parts of the conductive film are removed. Then, by removing the resist mask, the gate electrode 115 can be formed.

[0220] Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and after removing the dummy pattern, the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, for etching the film to be processed, to achieve a high aspect ratio, it is preferable to use anisotropic dry etching. Also, a hard mask made of an inorganic film or a metal film may be used.

[0221] ​​The light used for forming the resist mask can be, for example, i-line (wavelength 365 nm), g-line (wavelength 43 6 nm), h-line (wavelength 405 nm), or a mixture of these lights. . In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Further, exposure may be performed by immersion lithography technology. Also, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also , instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays or an electron beam is preferable because extremely fine processing becomes possible. When performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0222] Also, before forming the resist film that becomes the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed, for example, by spin coating method or the like so as to cover the step of its lower layer and flatten the surface, and the variation in the thickness of the resist mask provided on the upper layer of the organic resin film can be reduced. In particular, when performing extremely fine processing, as the organic resin film, it is preferable to use a material that functions as an anti-reflection film for the light used for exposure. Examples of such an organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed simultaneously with the removal of the resist mask or may be removed after removing the resist mask. After forming the gate electrode 115, a sidewall covering the side surface of the gate electrode 115 is formed.

[0223] This is also acceptable. After forming an insulating film thicker than the thickness of the gate electrode 115, the sidewall can be formed by performing anisotropic etching to leave only the insulating film on the side surface portion of the gate electrode 115.

[0224] When forming the sidewall, the insulating film that will become the gate insulating layer 114 is also etched simultaneously. As a result, the gate insulating layer 114 is formed under the gate electrode 115 and the sidewall. Alternatively, after forming the gate electrode 115, the insulating film can be etched using a resist mask for processing the gate electrode 115 or the gate electrode 11 5 as an etching mask to form the gate insulating layer 114. Alternatively, the insulating film can be used as the gate insulating layer 114 as it is without performing etching processing on the insulating film.

[0225] Subsequently, an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron is added to the region of the semiconductor substrate 111 where the gate electrode 115 (and the sidewall) is not provided. A schematic cross-sectional view at this stage corresponds to FIG. 21(A).

[0226] Subsequently, after forming the insulating layer 121, a first heat treatment is performed to activate the element that imparts the above-described conductivity.

[0227] The insulating layer 121 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc., and may be provided in a laminated or single-layer form. The insulating layer 121 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method ​​​​​​​​​​Alternatively, it can be formed by using a method such as the PLD method. In particular, when the insulating film is formed by the CVD method, preferably by the plasma CVD method, the coating property can be improved, which is preferable. Also, to reduce plasma damage, the thermal CVD method, MOCVD method or ALD method is preferable.

[0228] The first heat treatment can be carried out, for example, at 400 °C or higher and below the strain point of the substrate in an inert gas atmosphere such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere.

[0229] The first transistor 110 is formed at this stage.

[0230] Subsequently, the insulating layer 122 and the insulating layer 123 are formed.

[0231] In addition to the materials that can be used for the insulating layer 121, when silicon oxynitride (SiNOH) containing oxygen and hydrogen is used for the insulating layer 122, the amount of hydrogen desorbed by heating can be increased, which is preferable. Also, in addition to the materials that can be used for the insulating layer 121, for the insulating layer 123, it is preferable to use a silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane or the like with oxygen or nitrous oxide or the like.

[0232] The insulating layer 122 and the insulating layer 123 can be formed, for example, by using a sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PLD method. In particular, when the insulating layer is formed by the CVD method, preferably by the plasma CVD method, the coating property can be improved, which is preferable. Also, to reduce plasma damage, ​​​​To reduce damage, thermal CVD, MOCVD, or ALD is preferred.

[0233] Next, the upper surface of the insulating layer 123 is planarized using a CMP method or the like.

[0234] Then, the dangling bonds in the semiconductor layer 112 are removed by hydrogen released from the insulating layer 122. The second heat treatment is performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0235] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above.

[0236] Subsequently, the low resistance layer 113a and the low resistance layer 113b are formed on the insulating layer 121, the insulating layer 122, and the insulating layer 123. An opening is formed that reaches the layer 113b and the gate electrode 115. A conductive film is formed on the insulating layer 123, and a planarization treatment is performed on the conductive film so that the top surface of the insulating layer 123 is exposed. By this, plugs 161 and 162 are formed. The conductive film is formed by, for example, sputtering. Tarring method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method The film can be formed by using an ALD method, a PLD method, or the like.

[0237] Next, a conductive film is formed on the insulating layer 123. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the quartz, wiring 131, wiring 132, wiring 133, wiring 134, etc. are formed. It is possible.

[0238] Next, an insulating film is formed to cover the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. Then, by performing a planarization process so that the upper surfaces of the respective wirings are exposed, an insulating layer 124 is formed. A schematic cross-sectional view at this stage corresponds to FIG. 21(B).

[0239] The insulating film that becomes the insulating layer 124 can be formed by the same materials and methods as those for the insulating layer 121 and the like. This is possible.

[0240] After forming the insulating layer 124, it is preferable to perform a third heat treatment. By desorbing water and hydrogen contained in each layer through the third heat treatment, the content of water and hydrogen can be reduced. Performing the third heat treatment immediately before forming the barrier layer 120 described later and thoroughly removing hydrogen and water contained in the layer below the barrier layer 120, and then forming the barrier layer 120 can prevent water and hydrogen from diffusing again to the layer below the barrier layer 120 in subsequent processes. This can be suppressed. This can be suppressed. This can be suppressed. This can be suppressed.

[0241] The third heat treatment can be performed under the conditions exemplified in the description of the above laminated structure.

[0242] Subsequently, a barrier layer 120 is formed on the insulating layer 124, wirings 131, 132, 133, 134, etc. (FIG. 21(C)). This can be suppressed.

[0243] The barrier layer 120 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, forming the insulating film by a CVD method, preferably a plasma CVD method, is preferable because the coverage can be improved. Also, to reduce plasma damage, a thermal CVD method, an MOCVD method, or an ALD method is preferable. This can be suppressed. This can be suppressed. This can be suppressed. This can be suppressed.

[0244] After forming the barrier layer 120, heat treatment may be performed to remove water and hydrogen contained in the barrier layer 120.

[0245] Subsequently, a resist mask is formed on the barrier layer 120 by the same method as described above, and unnecessary portions of the barrier layer 120 are removed by etching. Then, the resist mask is removed. Thereby, openings reaching the wiring 132, the wiring 134, etc. are formed.

[0246] Subsequently, after forming a conductive film on the barrier layer 120, a resist mask is formed by the same method as described above, and unnecessary portions of the conductive film are removed by etching. Then, the resist mask is removed. Thereby, the wiring 141, the wiring 142, etc. can be formed (FIG. 21( D)).

[0247] At this stage, the capacitor 130 is formed. The capacitor 130 is composed of a wiring 133 that partially functions as a first electrode, a wiring 142 that partially functions as a second electrode, and the barrier layer 120 sandwiched therebetween.

[0248] Subsequently, the insulating layer 125 is formed.

[0249] The insulating layer 125 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, it is preferable to form the insulating layer by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Also, to reduce damage by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0250] In order to make the insulating layer 125 contain excess oxygen, for example, the insulating layer 125 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating layer 125 after the film formation to make the insulating layer 125 contain excess oxygen. Alternatively, a region having either of these may be formed, or both approaches may be combined.

[0251] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions) may be added to the insulating layer 125 after the film formation. A region containing excess oxygen is formed by introducing oxygen into the film. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0252] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas.

[0253] After the insulating layer 125 is formed, the CMP method or the like is used to improve the flatness of the upper surface. A flattening process may also be performed.

[0254] Next, an oxide film that will become the first oxide layer 101a and a semiconductor film that will become the semiconductor layer 102 are The oxide film and the semiconductor film are formed in succession without being exposed to the air. It is preferable.

[0255] After the oxide film and the semiconductor film are formed, a fourth heat treatment is preferably performed. At a temperature of 250°C to 650°C, preferably 300°C to 500°C, inert gas The treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after forming the semiconductor film, or may be performed after processing the semiconductor film to form the island-shaped semiconductor layer 102. By the heat treatment, oxygen is supplied from the insulating layer 125 or the oxide film to the semiconductor film, and oxygen vacancies in the semiconductor film can be reduced. Subsequently, a resist mask is formed on the semiconductor film in the same manner as described above, and unnecessary portions of the semiconductor film and the oxide film are removed by etching. Then, by removing the resist mask, a stacked structure of the island-shaped first oxide layer 101a and the island-shaped semiconductor layer 102 can be formed (FIG. 22(A)). As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching. Subsequently, openings reaching the wiring 131, the wiring 133, etc. are formed in the insulating layer 125 and the barrier layer 120 in the same manner as described above. Subsequently, a conductive film is formed, a resist mask is formed on the conductive film in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, the electrodes 103a and 103b can be formed (FIG. 22(B)).

[0256] Subsequently, a resist mask is formed on the semiconductor film in the same manner as described above, and unnecessary portions of the semiconductor film and the oxide film are removed by etching. Then, by removing the resist mask, a stacked structure of the island-shaped first oxide layer 101a and the island-shaped semiconductor layer 102 can be formed (FIG. 22(A)). Subsequently, a resist mask is formed on the semiconductor film in the same manner as described above, and unnecessary portions of the semiconductor film and the oxide film are removed by etching. Then, by removing the resist mask, a stacked structure of the island-shaped first oxide layer 101a and the island-shaped semiconductor layer 102 can be formed (FIG. 22(A)). Subsequently, a resist mask is formed on the semiconductor film in the same manner as described above, and unnecessary portions of the semiconductor film and the oxide film are removed by etching. Then, by removing the resist mask, a stacked structure of the island-shaped first oxide layer 101a and the island-shaped semiconductor layer 102 can be formed (FIG. 22(A)). Subsequently, a resist mask is formed on the semiconductor film in the same manner as described above, and unnecessary portions of the semiconductor film and the oxide film are removed by etching. Then, by removing the resist mask, a stacked structure of the island-shaped first oxide layer 101a and the island-shaped semiconductor layer 102 can be formed (FIG. 22(A)).

[0257] As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching. As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching. As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching. As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching. As shown in FIG. 22(A), when etching the oxide film and the semiconductor film, a part of the insulating layer 125 may be etched, and the insulating layer 125 in the region not covered by the first oxide layer 101a and the semiconductor layer 102 may be thinned. Therefore, it is preferable to form the insulating layer 125 thick in advance so that the insulating layer 125 does not disappear due to the etching.

[0258] Subsequently, openings reaching the wiring 131, the wiring 133, etc. are formed in the insulating layer 125 and the barrier layer 120 in the same manner as described above. Subsequently, openings reaching the wiring 131, the wiring 133, etc. are formed in the insulating layer 125 and the barrier layer 120 in the same manner as described above.

[0259] Subsequently, a conductive film is formed, a resist mask is formed on the conductive film in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, the electrodes 103a and 103b can be formed (FIG. 22(B)). Subsequently, a conductive film is formed, a resist mask is formed on the conductive film in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, the electrodes 103a and 103b can be formed (FIG. 22(B)). Subsequently, a conductive film is formed, a resist mask is formed on the conductive film in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, the electrodes 103a and 103b can be formed (FIG. 22(B)).

[0260] The formation of the conductive film can be carried out using, for example, sputtering method, CVD method (including thermal CVD method, MOCVD method, P ECVD method, etc.), MBE method, ALD method or PLD method. In particular, when the conductive film is formed by CVD method, preferably plasma CVD method, it is preferable because the coverage can be improved. Also, to reduce the damage caused by plasma, thermal CVD method, MOCVD method or ALD method is preferable.

[0261] Here, when etching the conductive film, a part of the upper part of the semiconductor layer 102 and the insulating layer 125 may be etched, and the part that does not overlap with the electrodes 103a and 103b may be thinned. Therefore, it is preferable to form the thickness of the semiconductor film or the like that becomes the semiconductor layer 102 thicker in advance in consideration of the etching depth.

[0262] Subsequently, an oxide film, an insulating film, and a conductive film are laminated and formed in sequence. Then, a resist mask is formed on the conductive film by the same method as above, and unnecessary parts of the conductive film are removed. Then, by removing the resist mask, the gate electrode 105 can be formed. Subsequently, a resist mask is similarly formed on the gate electrode 105 and the insulating film, unnecessary parts of the insulating film and the oxide film are removed by etching, and by removing the resist mask, the gate insulating layer 104 and the second oxide layer 101b can be formed simultaneously.

[0263] Here, as shown in FIG. 5 etc., when the upper surface shapes of the gate insulating layer 104 and the second oxide layer 101b are formed to substantially coincide with the upper surface shape of the gate electrode 105, the gate electrode Etch the insulating film and the oxide film using a resist mask for forming the pole 105. ; Alternatively, after forming the gate electrode 105 and removing the resist mask, the insulating film and the oxide film may be etched using the gate electrode 1 05 as a hard mask.

[0264] At this stage, the second transistor 100 is formed.

[0265] Subsequently, an insulating layer 107 is formed (Fig. 22(C)). The insulating layer 107 can be formed, for example, by sputtering ring method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PLD method. In particular, when the insulating film is formed by CVD method, preferably by plasma CVD method, the coating property can be improved which is preferable. Also, to reduce the damage by plasma, thermal CVD method, MOCVD method or ALD method is preferable.

[0266] After forming the insulating layer 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen is supplied from the insulating layer 125 or the like to the semiconductor layer 102, and the oxygen deficiency in the semiconductor layer 102 can be reduced . Also, at this time, the oxygen desorbed from the insulating layer 125 is blocked by the barrier layer 120 and the insulating layer 107, and does not diffuse to the layer below the barrier layer 120 and the layer above the insulating layer 107 so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 102 can be increased, and the oxygen deficiency in the semiconductor layer 102 can be effectively reduced.

[0267] Subsequently, an insulating layer 108 and an insulating layer 126 are formed in sequence (Fig. 23(A)). The insulating layer 10 8 and the insulating layer 126 can be formed, for example, by sputtering, CVD (including thermal CVD, MOCVD , PECVD, etc.), MBE, ALD or PLD. In particular, when forming the insulating layer 107 by CVD, preferably plasma CVD , it is preferable because the coating property can be made good. Also, to reduce plasma damage, thermal CVD, MOCVD or ALD is preferable. When using an organic insulating material such as an organic resin as the insulating layer 126, it may be formed by a coating method such as spin coating. Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. 126, it may be formed by a coating method such as spin coating. Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. processing on its upper surface is preferable.

[0268] Subsequently, in the same manner as described above, plugs 163 reaching the electrode 103a, plugs 164 reaching the gate electrode 105, etc. are formed in the insulating layer 126, the insulating layer 108, and the insulating layer 107. Subsequently, in the same manner as described above, plugs 163 reaching the electrode 103a, plugs 164 reaching the gate electrode 105, etc. are formed in the insulating layer 126, the insulating layer 108, and the insulating layer 107. are formed.

[0269] Subsequently, a conductive film is formed on the insulating layer 126. Then, a resist mask is formed in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, wirings 151, 152, etc. can be formed (Fig. 23( Subsequently, a conductive film is formed on the insulating layer 126. Then, a resist mask is formed in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, wirings 151, 152, etc. can be formed (Fig. 23( B)). B)).

[0270] Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0271] [Fabrication Method Example 2] Hereinafter, an example of the fabrication method of the semiconductor device shown in the above Configuration Example 2 will be described with reference to Figs. 24 to 26. Note that the description may be omitted for parts overlapping with the above Fabrication Method Example 1. There may be cases where the description is omitted.

[0272] First, an element isolation layer is formed on the semiconductor substrate 111. Thereafter, in the same manner as described above a semiconductor layer 112, a gate insulating layer 114, and a gate electrode 115 are formed (FIG. 24(A)).

[0273] Subsequently, after forming the insulating layer 121, a first heat treatment for activation is performed, whereby a low resistance layer 113a and a low resistance layer 113b are formed, and a first transistor 1 10 is formed.

[0274] Subsequently, an insulating layer 122 and an insulating layer 123 are formed, and the upper surface of the insulating layer 123 is planarized using a CMP method or the like. Thereafter, a second heat treatment is performed.

[0275] Subsequently, openings reaching the low resistance layer 113a, the low resistance layer 113b, and the gate electrode 115 are formed in the insulating layer 121, the insulating layer 122, and the insulating layer 123. Thereafter, plugs 161, plugs 162, etc. are formed. Subsequently, after forming wirings 131, 132, 133, and 134, etc., an insulating layer 124 is formed (FIG. 24(B)). After forming the insulating layer 124, it is preferable to perform a third heat treatment.

[0276] Subsequently, a barrier layer 120 is formed on the insulating layer 124, the wirings 131, 132, 133, and 134, etc. (FIG. 24(C)). After forming the barrier layer 120, a heat treatment for removing water and hydrogen contained in the barrier layer 1 20 may be performed.

[0277] Subsequently, an opening reaching the wiring 132, etc. is formed in the barrier layer 120. Thereafter, wirings 141, 142, etc. are formed on the barrier layer 12 0 (FIG. 24(D)).

[0278] At this stage, a capacitor 130 is formed. The capacitor 130 is partially composed of a wiring 134 that functions as a first electrode, a wiring 142 that functions as a second electrode, and a barrier layer 120 sandwiched therebetween. Subsequently, an insulating layer 125 is formed. After forming the insulating layer 125, a planarization process such as CMP may be performed to improve the flatness of its upper surface. Subsequently, a stacked structure of an island-shaped first oxide layer 101a and an island-shaped semiconductor layer 102 is formed (Fig. 25(A)). After forming the oxide film that becomes the first oxide layer 101a and the semiconductor film that becomes the semiconductor layer 102, it is preferable to perform a fourth heat treatment.

[0279] Subsequently, openings reaching the wiring 131, wiring 133, wiring 142, etc. are formed in the insulating layer 125 and the barrier layer 120. Then, electrodes 103a and 103b are formed (Fig. 25(B)). Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed.

[0280] Subsequently, an insulating layer 107 is formed (Fig. 25(C)). After forming the insulating layer 107, it is preferable to perform a fifth heat treatment. Subsequently, an insulating layer 108 and an insulating layer 126 are sequentially formed (Fig. 26(A)). Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. Then, a plug 163 reaching the electrode 103a, a gate electrode 105, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Subsequently, an insulating layer 107 is formed (Fig. 25(C)). After forming the insulating layer 107, it is preferable to perform a fifth heat treatment.

[0281] Subsequently, openings reaching the wiring 131, wiring 133, wiring 142, etc. are formed in the insulating layer 125 and the barrier layer 120. Then, electrodes 103a and 103b are formed (Fig. 25(B)). Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Subsequently, an insulating layer 107 is formed (Fig. 25(C)). After forming the insulating layer 107, it is preferable to perform a fifth heat treatment.

[0282] Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Subsequently, an insulating layer 107 is formed (Fig. 25(C)). After forming the insulating layer 107, it is preferable to perform a fifth heat treatment.

[0283] Subsequently, an insulating layer 107 is formed (Fig. 25(C)). After forming the insulating layer 107, it is preferable to perform a fifth heat treatment. Subsequently, an insulating layer 108 and an insulating layer 126 are sequentially formed (Fig. 26(A)). Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. Then, a plug 163 reaching the electrode 103a, a gate electrode 105, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed.

[0284] Subsequently, an insulating layer 108 and an insulating layer 126 are sequentially formed (Fig. 26(A)). Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. Then, a plug 163 reaching the electrode 103a, a gate electrode 105, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Subsequently, an insulating layer 108 and an insulating layer 126 are sequentially formed (Fig. 26(A)). Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. Then, a plug 163 reaching the electrode 103a, a gate electrode 105, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Subsequently, an insulating layer 108 and an insulating layer 126 are sequentially formed (Fig. 26(A)). Also, after forming the insulating layer 126, it is preferable to perform a planarization process on its upper surface. Then, a plug 163 reaching the electrode 103a, a gate electrode 105, and a second oxide layer 101b are formed respectively. At this stage, the second transistor 100 is formed. Form plugs 164 and the like that reach the auto electrode 105.

[0285] Subsequently, form wirings 151, 152, etc. (Fig. 26(B)).

[0286] Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0287] [Manufacturing method example 3] Hereinafter, an example of the manufacturing method of the semiconductor device shown in the above configuration example 2 will be described with reference to Figs. 27 to 29. Note that descriptions of portions overlapping with the above manufacturing method example 1 and manufacturing method example 2 may be omitted.

[0288] First, form an element isolation layer on the semiconductor substrate 111. Thereafter, in the same manner as above form the semiconductor layer 112, the gate insulating layer 114, and the gate electrode 115 (Fig. 27(A)).

[0289] Subsequently, after forming the insulating layer 121, perform a first heat treatment for activation to form the low-resistance layers 113a and 113b, thereby forming the first transistor 1 10.

[0290] Subsequently, form the insulating layers 122 and 123, and planarize the upper surface of the insulating layer 123 using the CMP method or the like Thereafter, perform a second heat treatment.

[0291] Subsequently, form openings reaching the low-resistance layers 113a and 113b, the low-resistance layer 113b, and the gate electrode 115, etc. in the insulating layers 121, 122, and 123. Thereafter, form plugs 161, plugs 162, etc. Subsequently, after forming the wirings 131, 132, and 133, etc., form the insulating layer 124 (Fig. 27(B)). After forming the insulating layer 124, perform a third heat treatment ​It is preferable to perform the process.

[0292] Subsequently, a barrier layer 120 is formed on the insulating layer 124, wiring 131, wiring 132, wiring 133, etc. (Fig. 27(C)). After forming the barrier layer 120, a heat treatment may be performed to remove water and hydrogen contained in the barrier layer 120. Subsequently, an opening reaching the wiring 132 or the like is formed in the barrier layer 120. Thereafter, wiring 141 or the like is formed on the barrier layer 120. (Fig. 27(D)). At this stage, the capacitor 130 is formed. The capacitor 130 is composed of a part of the wiring 133 that functions as the first electrode, a part of the wiring 141 that functions as the second electrode, and the barrier layer 120 sandwiched therebetween.

[0293] Subsequently, an insulating layer 125 is formed. After forming the insulating layer 125, a planarization process using a CMP method or the like may be performed to improve the flatness of its upper surface. Subsequently, a stacked structure of an island-shaped first oxide layer 101a and an island-shaped semiconductor layer 102 is formed (Fig. 28(A)). After forming the oxide film that becomes the first oxide layer 101a and the semiconductor film that becomes the semiconductor layer 102, it is preferable to perform a fourth heat treatment.

[0294] At this stage, the capacitor 130 is formed. The capacitor 130 is composed of a part of the wiring 133 that functions as the first electrode, a part of the wiring 141 that functions as the second electrode, and the barrier layer 120 sandwiched therebetween. Subsequently, openings reaching the wiring 131 and the wiring 133 or the like are formed in the insulating layer 125 and the barrier layer 120. Thereafter, electrodes 103a and 103b are formed (Fig. 28(B)). Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are respectively formed. At this stage, the second transistor 100 is formed.

[0295] Subsequently, an insulating layer 125 is formed. After forming the insulating layer 125, a planarization process using a CMP method or the like may be performed to improve the flatness of its upper surface. Subsequently, an insulating layer 125 is formed. After forming the insulating layer 125, a planarization process using a CMP method or the like may be performed to improve the flatness of its upper surface.

[0296] Subsequently, a stacked structure of an island-shaped first oxide layer 101a and an island-shaped semiconductor layer 102 is formed (Fig. 28(A)). After forming the oxide film that becomes the first oxide layer 101a and the semiconductor film that becomes the semiconductor layer 102, it is preferable to perform a fourth heat treatment. After forming the oxide film that becomes the first oxide layer 101a and the semiconductor film that becomes the semiconductor layer 102, it is preferable to perform a fourth heat treatment. Subsequently, openings reaching the wiring 131 and the wiring 133 or the like are formed in the insulating layer 125 and the barrier layer 120. Thereafter, electrodes 103a and 103b are formed (Fig. 28(B)).

[0297] Subsequently, openings reaching the wiring 131 and the wiring 133 or the like are formed in the insulating layer 125 and the barrier layer 120. Thereafter, electrodes 103a and 103b are formed (Fig. 28(B)). Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are respectively formed. At this stage, the second transistor 100 is formed.

[0298] Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are respectively formed. At this stage, the second transistor 100 is formed. Subsequently, a gate electrode 105, a gate insulating layer 104, and a second oxide layer 101b are respectively formed. At this stage, the second transistor 100 is formed.

[0299] Subsequently, an insulating layer 107 is formed (FIG. 28(C)). After the formation of the insulating layer 107, it is preferable to perform a fifth heat treatment.

[0300] Subsequently, an insulating layer 108 and an insulating layer 126 are formed in sequence (FIG. 29(A)). Further, after forming the insulating layer 126, it is preferable to perform a planarization treatment on its upper surface. Thereafter, plugs 163 reaching the electrode 103a, plugs 164 reaching the gate electrode 105, etc. are formed in the insulating layer 126, the insulating layer 108, and the insulating layer 107.

[0301] Subsequently, wirings 151, 152, etc. are formed (FIG. 29(B)).

[0302] Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0303] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0304] (Embodiment 2) In this embodiment, an oxide semiconductor suitably used for the semiconductor layer of a semiconductor device according to one aspect of the present invention will be described.

[0305] The oxide semiconductor has a large energy gap of 3.0 eV or more, and in a transistor to which an oxide semiconductor film obtained by appropriately processing the oxide semiconductor and sufficiently reducing its carrier density is applied, the leakage current (off-current) between the source and the drain in the off state can be made extremely low as compared with a conventional transistor using silicon.

[0306] ​​​​​​​​​​As applicable oxide semiconductors, those containing at least indium (In) or zinc (Zn ) are preferably included. Particularly preferably, those containing In and Zn are included. Further, as a stabilizer for reducing the variation in the electrical characteristics of a transistor using the oxide semiconductor , in addition to them , one or more selected from gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanoids (for example , cerium (Ce), neodymium (Nd), gadolinium (Gd)) are preferably included. For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide

[0307] , Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide , In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO ), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn -based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide , In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide , In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide , In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, , In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, I , In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga- -Zn-based oxide, etc. can be mentioned. Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, I n-Hf-Al-Zn oxides can be used.

[0308] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0309] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer ) may be used, where M is selected from Ga, Fe, Mn and Co. It indicates one or more metal elements, or the above-mentioned stabilizer elements. In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0310] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of the above.

[0311] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to purify it to a high purity so as to remove impurities as much as possible.

[0312] Note that, by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may also decrease simultaneously from the oxide semiconductor film. Therefore, in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide semiconductor. In this specification and the like, the case of supplying oxygen to the oxide semiconductor film may be referred to as an oxygen addition treatment, or the case of making the oxygen contained in the oxide semiconductor film more than the stoichiometric composition may be referred to as a peroxygenation treatment.

[0313] Thus, the oxide semiconductor film can be made into an oxide semiconductor film that is i-type (intrinsic) or substantially i-type approaching i-type infinitely by removing hydrogen or moisture by the dehydration treatment (dehydrogenation treatment) and compensating for the oxygen deficiency by the oxygen addition treatment. Note that substantially intrinsic means that carriers derived from donors are extremely few (close to zero) in the oxide semiconductor film, and the carrier density is 1×10 17 / cm 3 or less, 1×10 16 / cm 3 or less , 1×10 15 / cm 3 or less, 1×10 14 / cm 3 or less, 1×10 13 / cm 3 or less and is said to be so.

[0314] Also, in this way, a transistor including an oxide semiconductor film that is i-type or substantially i-type can realize extremely excellent off-current characteristics. For example, a transistor using an oxide semiconductor film ​​The drain current when the transistor is in the off state is 1×10 at room temperature (about 25°C). -18 A or less, preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1×10 at 85 °C, -15 preferably 1×10 -18 A or less, more preferably 1× 10 -21 A or less. Note that when the transistor is in the off state, in the case of an n-channel type transistor, it means a state where the gate voltage is sufficiently smaller than the threshold voltage. Specifically speaking, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage , the transistor is in the off state.

[0315] Hereinafter, the structure of the oxide semiconductor film will be described.

[0316] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0317] First, the CAAC-OS film will be described.

[0318] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction .

[0319] By a transmission electron microscope (TEM: Transmission Electron Micr oscope), a composite analysis image of the bright field image and the diffraction pattern of the CAAC-OS film By observing (also referred to as a high-resolution TEM image), multiple crystal parts can be confirmed. . On the other hand, even with a high-resolution TEM image, it is impossible to confirm the boundaries between distinct crystal parts, namely, grain boundaries (also referred to as grain boundaries). Therefore, it can be said that in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0320] When observing a high-resolution TEM image of the cross-section of a CAAC-OS film from a direction approximately parallel to the sample surface , it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0321] On the other hand, when observing a high-resolution TEM image of the plane of a CAAC-OS film from a direction approximately perpendicular to the sample surface , it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0322] Figure 31(a) is a high-resolution TEM image of the cross-section of a CAAC-OS film. Also, Figure 31( b) is a high-resolution TEM image of the cross-section obtained by further magnifying Figure 31(a), and the atomic arrangement is highlighted for easy understanding.

[0323] Figure 31(c) is a local Fourier transform image of the region (diameter approximately 4 nm) surrounded by a circle between A-O-A' in Figure 31(a). From Figure 31(c), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between A-O and O-A', different It is suggested that it is rain. Also, between A and O, it can be seen that the angle of the c-axis changes continuously little by little, such as 14.3°, 16. 6°, 26.4°. Similarly, between O and A ’, it can be seen that the angle of the c-axis changes continuously little by little to -18.3°, -17.6°, -15.9°.

[0324] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also called nano-beam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the upper surface of the CAAC-OS film, spots are observed (see Fig. 32(A)).

[0325] From the high-resolution TEM image of the cross-section and the high-resolution TEM image of the plane, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0326] Most of the crystal parts included in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film also include cases where they are sized to fit within a cube with a side length of less than 10 nm, less than 5 nm or less than 3 nm. However, when a plurality of crystal parts included in the CAAC-OS film are connected, a single large crystal region may be formed. For example, in the high-resolution TEM image of the plane, crystal regions of 2500 nm or more, 5 μm or more or 1000 μm 2 or more may be observed. 2 2

[0327] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, a CAAC-OS having crystals of InGaZnO4​​​​​ In the analysis by the out-of-plane method of the film, a peak may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface.

[0328] On the other hand, in the analysis by the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear at around 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor film of InGaZnO4, if the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when the φ scan is performed with 2θ fixed at around 56°.

[0329] From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, it can be seen that each layer of the metal atoms arranged in a layered structure confirmed by the high-resolution TEM observation of the cross section described above is a plane parallel to the ab plane of the crystal.

[0330] Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, in the case of the CAAC-OS film ​ When the shape is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. of the CAAC-OS film.

[0331] Also, in the CAAC-OS film, the distribution of the c-axis oriented crystal portions may not be uniform. For example, when the crystal portions of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher ratio of c-axis oriented crystal portions than the region near the formed surface. Also, in the CAAC-OS film to which impurities are added, the region where impurities are added is altered, and regions with different ratios of partially c-axis oriented crystal portions may be formed.

[0332] In addition, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak near 2θ = 31°, a peak may also appear near 2θ = 36°. The peak near 2θ = 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. The CAAC-OS film preferably shows a peak near 2θ = 31° and does not show a peak near 2θ = 36°.

[0333] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, deprive the oxide semiconductor film of oxygen, disrupting the atomic arrangement of the oxide semiconductor film and becoming a factor in reducing the crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., Since the diameter (or molecular radius) is large, if it is contained inside the oxide semiconductor film, it will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing the crystallinity. Note that impurities contained in the oxide semiconductor film may serve as carrier traps or carrier generation sources.

[0334] In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen.

[0335] A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have electrical characteristics (also called normally-off characteristics) in which the threshold voltage becomes negative. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0336] In addition, a transistor using the CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0337] Next, the polycrystalline oxide semiconductor film will be described.

[0338] In a high-resolution TEM image, crystal grains can be confirmed in the polycrystalline oxide semiconductor film. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, in a high-resolution TEM image, 2 nm or more and 300 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in particle size. In many cases. Also, in a high-resolution TEM image, crystal grain boundaries can be confirmed in the polycrystalline oxide semiconductor film. There are cases.

[0339] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientations may be different between the plurality of crystal grains. Also, when performing structural analysis on the polycrystalline oxide semiconductor film using an XRD apparatus, for example, in the out-of-plane method analysis of a polycrystalline oxide semiconductor film having InGaZnO4 crystals, peaks around 2θ = 31°, peaks around 2θ = 36°, or other peaks may appear.

[0340]

[0340] Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the crystal grain boundaries in the polycrystalline oxide semiconductor film. Also, the crystal grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the crystal grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film.

[0341] ​​​​​Next, the microcrystalline oxide semiconductor film will be described.

[0342] In a high-resolution TEM image, the microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc-OS (nanocrystalline Oxide Semiconductor ) film. Also, in an nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed.

[0343] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, in the nc-OS film, no regularity is seen in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film. Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on an nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction (also called limited-field electron diffraction) on an nc-OS film using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part, a diffraction pattern such as a halo pattern is observed. On the other hand, for an nc-OS film, when using a nano-beam electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 50 nm or more) of the electron beam, a diffraction pattern such as a halo pattern is observed. On the other hand, for an nc-OS film, when using an electron beam with a probe diameter close to the size of the crystal part or smaller than the crystal part for nano-beam electron diffraction, ​​​​​​​​​ When folding is performed, spots are observed. Also, when nano-beam electron diffraction is performed on the nc-OS film there may be cases where regions with high luminance are observed in a circular (ring-shaped) pattern. Also, when nano-beam electron diffraction is performed on the nc-OS film, multiple spots may be observed within the ring-shaped region (see Fig. 32(B)).

[0344] The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore the nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher density of defect levels than the CAAC-OS film.

[0345] Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore a transistor using the nc-OS film may have a high field-effect mobility. Also since the nc-OS film has a higher density of defect levels than the CAAC-OS film, there may be more carrier traps . Therefore, a transistor using the nc-OS film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using the CAAC- OS film. However, since the nc-OS film can be formed even when it contains relatively many impurities it is easier to form than the CAAC-OS film and may be suitably used depending on the application . Therefore, a semiconductor device having a transistor using the nc-OS film may be manufactured with high productivity.

[0346] ​Next, the amorphous oxide semiconductor film will be described.

[0347] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0348] In the high-resolution TEM image, the crystal part cannot be confirmed in the amorphous oxide semiconductor film. .

[0349] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. is observed.

[0350] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. Also, the amorphous oxide semiconductor film is an oxide semiconductor film having a high density of defect levels.

[0351] An oxide semiconductor film having a high impurity concentration and a high density of defect levels is an oxide semiconductor film having many carrier traps and carrier generation sources. is an oxide semiconductor film having many carrier traps and carrier generation sources.

[0352] Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. Therefore, a transistor using the amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. The amorphous oxide semiconductor film has a density of defect levels. Therefore, a transistor using the amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. A transistor using the amorphous oxide semiconductor film may be suitably used for a transistor that requires normally-on electrical characteristics. The amorphous oxide semiconductor film has a density of defect levels. Since it is high, there may be many carrier traps. Therefore, when using an amorphous oxide semiconductor film The transistors using it have larger fluctuations in electrical characteristics and lower reliability compared to transistors using CAAC-OS films or nc-OS films. become transistors with large fluctuations in electrical characteristics and low reliability.

[0353] Next, the single-crystalline oxide semiconductor film will be described.

[0354] The single-crystalline oxide semiconductor film is an oxide semiconductor film with a low impurity concentration and a low density of defect levels (few oxygen deficiencies ). Therefore, the carrier density can be lowered. Therefore, transistors using a single crystalline oxide semiconductor film are less likely to have normally-on electrical characteristics. Also, since the single-crystalline oxide semiconductor film has a low impurity concentration and a low density of defect levels, the number of carrier traps may be reduced. Therefore, transistors using a single-crystalline oxide semiconductor film become transistors with small fluctuations in electrical characteristics and high reliability. become transistors with small fluctuations in electrical characteristics and high reliability.

[0355] Note that the density of the oxide semiconductor film increases when there are few defects. Also, the density of the oxide semiconductor film increases when the crystallinity is high. Also, the density of the oxide semiconductor film increases when the concentration of impurities such as hydrogen is low. The density of the single-crystalline oxide semiconductor film is higher than that of the CAAC-OS film. Also the density of the CAAC-OS film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the polycrystalline oxide semiconductor film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the microcrystalline oxide semiconductor film is higher than that of the non-crystalline oxide semiconductor film. the density of the CAAC-OS film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the polycrystalline oxide semiconductor film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the microcrystalline oxide semiconductor film is higher than that of the non-crystalline oxide semiconductor film. the density of the CAAC-OS film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the polycrystalline oxide semiconductor film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the microcrystalline oxide semiconductor film is higher than that of the non-crystalline oxide semiconductor film. the density of the polycrystalline oxide semiconductor film is higher than that of the microcrystalline oxide semiconductor film. Also, the density of the microcrystalline oxide semiconductor film is higher than that of the non-crystalline oxide semiconductor film. the density of the microcrystalline oxide semiconductor film is higher than that of the non-crystalline oxide semiconductor film.

[0356] Note that the oxide semiconductor film may have a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide film. It is called an amorphous-like oxide semiconductor (amorphous-like OS: amorphous-like O xide Semiconductor) film.

[0357] In a high-resolution TEM image, voids (also called voids in some cases) may be observed in the amorphous-like OS film. Also, in a high-resolution TEM image, there are regions where the crystalline part can be clearly confirmed and regions where the crystalline part cannot be confirmed. The amo rphous-like OS film may crystallize and crystal growth may be observed due to a very small amount of electron irradiation during TEM observation. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a very small amount of electron irradiation during TEM observation is hardly seen.

[0358] The measurement of the size of the crystalline part of the amorphous-like OS film and the nc-OS film can be performed using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between the In-O layers. The unit lattice of the crystal of InGaZnO 4 has three In-O layers and six Ga-Zn-O layers, and a total of nine layers are stacked in a layered manner in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also called the d value). From crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, by paying attention to the lattice fringes in the high-resolution TEM image, at locations where the distance between the lattice fringes is between 0.28 nm and 0.30 nm, each of these lattice fringes is regarded as corresponding to the a-b plane of the crystal of InGaZnO4. The maximum length of the region where the lattice fringes are observed is used as the amorphous-like OS film and the nc-OS film Set it to the size of the crystal part. Note that the size of the crystal part is selectively evaluated for those of 0.8 nm or more. Do.

[0359] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0360] When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction. Analysis may be possible.

[0361] Fig. 32(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. 12, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. 12, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. 12, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. 12, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided.

[0362] Further, Fig. 32(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Fig. 32(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. 10 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. 28 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. 28 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. 28 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 are incident on a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured.

[0363] The camera 618 is installed facing the fluorescent plate 632, and the pattern that appears on the fluorescent plate 632 It is possible to take a picture. The angle formed by the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15° or more and 80° or less , 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern taken by the camera 618. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern . Incidentally, the camera 618 may be installed in the film chamber 622. For example , the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with less distortion can be taken from the back surface of the fluorescent plate 632 . . . .

[0364] In the sample chamber 614, a holder for fixing the substance 628 as a sample is installed. The holder has a structure that allows electrons passing through the substance 628 to pass through. The holder may, for example , have a function of moving the substance 628 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have an accuracy of moving, for example, in a range of 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc. These ranges may be set to an optimal range depending on the structure of the substance 628 . .

[0365] Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measuring apparatus will be described.

[0366] For example, as shown in Fig. 32(D), the irradiation position of the electrons 624 which are nano-beams in the substance By changing (scanning) the position, it is possible to confirm how the structure of the substance changes. At this time, if the substance 628 is a CAAC-OS film, a diffraction pattern as shown in Fig. 32(A) is observed. Or, if the substance 628 is an nc-OS film, a diffraction pattern as shown in Fig. 32( B) is observed.

[0367] By the way, even if the substance 628 is a CAAC-OS film, a diffraction pattern similar to that of a partially nc-OS film may be observed. Therefore, the quality of the CAAC-OS film can sometimes be represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also called the CA AC conversion rate). For example, for a high-quality CAAC-OS film the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90 % or more, and even more preferably 95% or more. Note that the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate.

[0368] As an example, for each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered), or after heat treatment at 450 °C in an oxygen-containing atmosphere, a transmission electron diffraction pattern was obtained while scanning the upper surface. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the CAAC conversion rate was derived by converting the observed diffraction pattern into still images every 0.5 seconds. Note that a nano-beam electron beam with a probe diameter of 1n m was used as the electron beam. The same measurement was performed on 6 samples. And for the calculation of the CA AC conversion rate, the average value of the 6 samples was used. m was used as the electron beam. The same measurement was performed on 6 samples. And for the calculation of the CA AC conversion rate, the average value of the 6 samples was used.

[0369] The CAAC conversion rates for each sample are shown in Fig. 33(A). The C AAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (the non-CAAC conversion rate was 14.7%) . It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation . That is, it can be seen that by heat treatment at a high temperature (for example, 400 °C or higher), the non-CAAC conversion rate decreases (the CAAC conversion rate increases). Also, it can be seen that a CAAC-OS film having a high CAAC conversion rate can be obtained even by heat treatment below 500 °C . . .

[0370] Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as those of the nc-OS film . Also, in the measurement region, the amorphous oxide semiconductor film could not be confirmed . Therefore, it is suggested that by heat treatment, regions having the same structure as the nc-OS film are rearranged under the influence of the structure of adjacent regions and are CAACified . .

[0371] Figs. 33(B) and 33(C) are high-resolution TEM images of the plane of the CAAC- OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 33(B) and Fig. 33(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality . That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved . .

[0372] Using such a measurement method, structural analysis of an oxide semiconductor film having a plurality of structures may be possible .

[0373] The CAAC-OS film can be formed, for example, by the following method.

[0374] The CAAC-OS film is formed, for example, by a sputtering method using a target for sputtering an oxide semiconductor that is polycrystalline.

[0375] By increasing the substrate temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the film is formed with the substrate temperature being 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate temperature during film formation, when flat or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate. At this time, since the sputtering particles are positively charged, the sputtering particles adhere to the substrate while repelling each other, so that the sputtering particles do not gather unevenly and a CAAC-OS film with uniform thickness can be formed.

[0376] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0377] Also, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30% by volume or higher, preferably 100% by volume.

[0378] Alternatively, the CAAC-OS film is formed by the following method.

[0379] First, a first oxide semiconductor film is formed to have a thickness of 1 nm or more and less than 10 nm. The first oxide semiconductor film is formed by a sputtering method. Specifically, the substrate temperature is 100°C or more and 500°C or less, preferably 150°C or more and 450°C or less, and the oxygen ratio in the film-forming gas is 30 volume% or more, preferably 100 volume%, for film formation.

[0380] Next, a heat treatment is performed to obtain a highly crystalline first CAAC-OS film from the first oxide semiconductor film. The temperature of the heat treatment is 350°C or more and 740°C or less, preferably 450°C or more and 650 °C or less. Also, the time of the heat treatment is 1 minute or more and 24 hours or less, preferably 6 minutes or more and 4 hours or less. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after performing the heat treatment in an inert atmosphere, the heat treatment is performed in an oxidizing atmosphere. By the heat treatment in an inert atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies may be generated in the first oxide semiconductor film by the heat treatment in an inert atmosphere. In that case, the oxygen vacancies can be reduced by the heat treatment in an oxidizing atmosphere. Note that the heat treatment may be performed under a reduced pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the first oxide semiconductor film can be further reduced in a shorter time.

[0381] Since the first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm, it can be more easily crystallized by heat treatment compared to the case where the thickness is 10 nm or more.

[0382] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed with a thickness of 10 nm or more and 5 0 nm or less. The second oxide semiconductor film is formed by a sputtering method. Specifically, the substrate temperature is set to 100°C or more and 500°C or less, preferably 150°C or more and 450 °C or less, and the oxygen ratio in the film-forming gas is set to 30% by volume or more, preferably 100% by volume, and the film is formed.

[0383] Next, heat treatment is performed to cause solid-phase growth of the second oxide semiconductor film from the first CAAC-OS film, resulting in a second CAAC-OS film with high crystallinity. The temperature of the heat treatment is 350 °C or more and 740°C or less, preferably 450°C or more and 650°C or less. Also, the time of the heat treatment is 1 minute or more and 24 hours or less, preferably 6 minutes or more and 4 hours or less. Also, the heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after heat treatment in an inert atmosphere, heat treatment is performed in an oxidizing atmosphere. By heat treatment in an inert atmosphere, the impurity concentration of the second oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies may be generated in the second oxide semiconductor film by heat treatment in an inert atmosphere. In that case, the oxygen vacancies can be reduced by heat treatment in an oxidizing atmosphere. Note that the heat treatment may be performed under a reduced pressure of 1 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced even more in a short time.

[0384] As described above, a CAAC-OS film having a total thickness of 10 nm or more can be formed.

[0385] ​​​​​​​This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. It can be implemented in combination as appropriate.

[0386] (Embodiment 3) In this embodiment, an example of a circuit using a transistor according to one aspect of the present invention will be described with reference to the drawings. It will be described with reference to the drawings.

[0387] [Example of Circuit Configuration] In the configuration shown in Embodiment 1, by varying the connection configurations of transistors, wirings, and electrodes, various circuits can be configured. Hereinafter, an example of a circuit configuration that can be realized by using a semiconductor device according to one aspect of the present invention will be described. By varying the connection configurations of transistors, wirings, and electrodes, various circuits can be configured. Hereinafter, an example of a circuit configuration that can be realized by using a semiconductor device according to one aspect of the present invention will be described. It will be described.

[0388] [CMOS Circuit] The circuit diagram shown in Fig. 34(A) shows the configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. In the figure, transistors to which the second semiconductor material is applied are indicated with the symbol "OS". The circuit diagram shown in Fig. 34(A) shows the configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. In the figure, transistors to which the second semiconductor material is applied are indicated with the symbol "OS". In the figure, transistors to which the second semiconductor material is applied are indicated with the symbol "OS". are indicated with the symbol "OS".

[0389] [Analog Switch] Also, the circuit diagram shown in Fig. 34(B) shows a configuration in which the sources and drains of transistor 2100 and transistor 2200 are connected. With such a configuration, it can function as a so-called analog switch. The circuit diagram shown in Fig. 34(B) shows a configuration in which the sources and drains of transistor 2100 and transistor 2200 are connected. With such a configuration, it can function as a so-called analog switch. It can function as a so-called analog switch.

[0390] [Example of Memory Device] An example of a semiconductor device (memory device) that uses a transistor according to one aspect of the present invention and can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations is shown in Fig. 34(C). An example of a semiconductor device (memory device) that uses a transistor according to one aspect of the present invention and can hold memory contents even in a situation where no power is supplied and has no limitation on the number of write operations is shown in Fig. 34(C). is shown in Fig. 34(C).

[0391] The semiconductor device shown in Fig. 34(C) includes a transistor 3200 using a first semiconductor material and a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that as the transistor 3300, the transistors exemplified in the above embodiments can be used. This is possible.

[0392] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 3300 has a small off-current, it is possible to hold the stored content for a longer period of time by using this transistor. That is, it is possible to make a semiconductor memory device that does not require a refresh operation or has an extremely low refresh operation frequency, so that the power consumption can be sufficiently reduced.

[0393] In Fig. 34(C), the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. Then, the gate electrode of the transistor 3200 and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other electrode of the capacitor element 3400.

[0394] In the semiconductor device shown in Fig. 34(C), the potential of the gate electrode of the transistor 3200 is held. By taking advantage of the feature of being possible, writing, holding, and reading information can be performed as follows. Yes.

[0395] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, and the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Thereafter, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, and the transistor 3300 is turned off, whereby the charge applied to the gate electrode of the transistor 3200 is held (holding). Since the off-current of the transistor 3300 is extremely small, the charge of the gate electrode of the transistor 3200 is held for a long time.

[0396]

[0397] th_ H Next, the reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes different potentials according to the amount of charge held in the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 th_ th_ HThis is because when a low-level charge is applied to the gate electrode of the transistor 3200, the apparent threshold voltage V becomes lower. Here, the apparent threshold voltage refers to th_L the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to V between V and V th_H to a potential V0, the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, when a high-level charge is applied, th_L if the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 will turn "on". When a low-level charge is applied, even if the potential of the fifth wiring 3005 becomes V0 (< V ), the transistor 3200 will remain in the "off state". Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out. th_H ). When a low-level charge is applied, even if the potential of the fifth wiring 3005 becomes V0 (< V ), the transistor 3200 will remain in the "off state". th_L ). For this reason, by discriminating the potential of the second wiring 3002, the stored information can be read out.

[0398] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. If the information is not read in this way, a potential such that the transistor 3200 turns "off" regardless of the state of the gate electrode, that is, a potential lower than V th_ H th_L

[0399]

[0399]

[0399] ​​​The semiconductor device shown in FIG. 34D is different from the semiconductor device shown in FIG. 3 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible to create

[0400] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The amount of change in the potential of the third wiring 3003 is the potential of one electrode of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0401] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one electrode of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0402] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0403] In this case, the first semiconductor material is applied to a drive circuit for driving a memory cell A transistor is used, and a transistor in which a second semiconductor material is applied as transistor 3300 is stacked and provided on the drive circuit should be configured.

[0404] In the semiconductor device shown in this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long period of time That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced Moreover, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for a long time Also, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of element degradation For example, unlike conventional non-volatile memories, there is no need to inject electrons into the floating gate or extract electrons from the floating gate Therefore, problems such as degradation of the gate insulating layer do not occur at all

[0405] That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional non-volatile memories and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification

[0406] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification should be configured.

[0407] (Embodiment 4) In this embodiment, the RFID tag including the transistor or the memory device exemplified in the above embodiment will be described with reference to FIG. 35.

[0408] The RFID tag in this embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RFID tag can be used in an individual authentication system that identifies an article by reading individual information such as the article. Note that extremely high reliability is required for these applications.

[0409]

[0410] The configuration of the RFID tag will be described with reference to FIG. 35. FIG. 35 is a block diagram showing an example of the configuration of the RFID tag. As shown in FIG. 35, the RFID tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also called an interrogator, a reader / writer, etc.). The RFID tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format is such that a pair of coils are arranged opposite to each other and mutual induction is used. ​​​​​​​​​​​​​​It is roughly classified into three types: an electromagnetic coupling method that performs communication, an electromagnetic induction method that communicates by an induced electromagnetic field, and a radio wave method that communicates using radio waves. The RFID tag 800 shown in this embodiment can be used in any of these methods. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0411] Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain power to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0412] The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of a stable power supply voltage. The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of a stable power supply voltage. The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of a stable power supply voltage. The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of a stable power supply voltage.

[0413] The demodulation circuit 807 is a circuit for demodulating by envelope detection of the input AC signal and generating a demodulated signal. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804. The demodulation circuit 807 is a circuit for demodulating by envelope detection of the input AC signal and generating a demodulated signal. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804. The demodulation circuit 807 is a circuit for demodulating by envelope detection of the input AC signal and generating a demodulated signal. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

[0414] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit for holding the input information, and has a row decoder, a column decoder, a memory area, etc. In addition, the ROM 811 is a circuit for storing unique numbers (IDs), etc., and outputting according to the processing.

[0415] Note that each of the above circuits can be appropriately selected or discarded as necessary.

[0416] Here, the memory circuit described in the previous embodiment can be used as the memory circuit 810. Since the memory circuit according to one aspect of the present invention can hold information even when the power supply is cut off, it can be suitably used for RFID tags. Furthermore, since the memory circuit according to one aspect of the present invention requires significantly less power (voltage) for writing data than conventional non-volatile memories, it is also possible not to cause a difference in the maximum communication distance between data reading and writing. Furthermore, it is possible to suppress malfunction or miswriting due to insufficient power during data writing.

[0417] In addition, since the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, it can also be applied to the ROM 811. In that case, it is preferable to separately prepare a command for the producer to write data into the ROM 811 and prevent the user from freely rewriting it. After the producer writes the unique number before shipment and then ships the product, it is possible to assign unique numbers only to the good products to be shipped, rather than to all the manufactured RFID tags, and customer management corresponding to the products after shipment becomes easy because the unique numbers of the products after shipment do not become discontinuous. ​​​​​​

[0418] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. It can be implemented in combination.

[0419] (Embodiment 5) In this embodiment, at least the transistors described in the embodiments can be used, and a CPU including the memory device described in the previous embodiment will be described.

[0420] FIG. 36 is a block diagram showing a configuration example of a CPU using at least some of the transistors described in the previous embodiment. It is a block diagram showing a configuration example of one example.

[0421] The CPU shown in FIG. 36 includes, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 36 is only an example shown with its configuration simplified, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in FIG. 36 may be used as one core, and a plurality of such cores may be included so that each core operates in parallel. Also, if the CPU has an internal arithmetic The number of bits that can be handled by the arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, 6 4 bits, etc.

[0422] The instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0423] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program based on their priorities and mask states. The register controller 1197 generates the address of the register 1196 and reads from and writes to the register 1196 according to the state of the CPU .

[0424] Also, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 11 92, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and the internal clock signal CLK2 is used to control the above components. ​Supply it to various circuits.

[0425] In the CPU shown in FIG. 36, a memory cell is provided in register 1196. The register The transistors shown in the previous embodiment can be used as the memory cells of register 1196. It is possible.

[0426] In the CPU shown in FIG. 36, register controller 1197 selects the holding operation in register 1196 according to the instruction from ALU1191. That is, in the memory cells of register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When data holding by a flip-flop is selected, the supply of the power voltage to the memory cells in register 1196 is performed. When data holding in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power voltage to the memory cells in register 1196 can be stopped. According to the instruction from In the memory cells of register 1196, whether to hold data by a flip-flop or to hold data by a capacitive element is selected. When data holding by a flip-flop is selected, the supply of the power voltage to the memory cells in register 1196 is performed. When data holding in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power voltage to the memory cells in register 1196 can be stopped. In the memory cells of register 1196, whether to hold data by a flip-flop or to hold data by a capacitive element is selected. When data holding by a flip-flop is selected, the supply of the power voltage to the memory cells in register 1196 is performed. When data holding in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power voltage to the memory cells in register 1196 can be stopped. When data holding by a flip-flop is selected, the supply of the power voltage to the memory cells in register 1196 is performed. When data holding in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power voltage to the memory cells in register 1196 can be stopped. When data holding in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power voltage to the memory cells in register 1196 can be stopped. It is possible.

[0427] FIG. 37 is an example of a circuit diagram of a memory element that can be used as register 1196. Memory element 1200 includes a circuit 1201 in which stored data is volatile when the power is cut off, a circuit 1202 in which stored data is non-volatile when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Note that memory element 1200 may further include other elements such as diodes, resistive elements, and inductors as necessary. Memory element 1200 includes a circuit 1201 in which stored data is volatile when the power is cut off, a circuit 1202 in which stored data is non-volatile when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Memory element 1200 includes a circuit 1201 in which stored data is volatile when the power is cut off, a circuit 1202 in which stored data is non-volatile when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Memory element 1200 includes a circuit 1201 in which stored data is volatile when the power is cut off, a circuit 1202 in which stored data is non-volatile when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Note that memory element 1200 may further include other elements such as diodes, resistive elements, and inductors as necessary.

[0428] Here, the memory device described in the previous embodiment can be used in circuit 1202. . When the supply of the power voltage to the memory element 1200 is stopped, the gate of transistor 12 09 is input with a ground potential (0 V) or a potential at which transistor 1209 turns off and continues to be so. For example, the gate of transistor 1209 is grounded via a load such as a resistor .

[0429] Switch 1203 is configured using a transistor 1213 of one conductivity type (e.g., n-channel type), and switch 1204 is configured using a transistor 1214 of a conductivity type opposite to the one conductivity type (e.g., p-channel type) . Here, the first terminal of switch 1203 corresponds to one of the source and drain of transistor 1213, the second terminal of switch 1203 corresponds to the other of the source and drain of transistor 1213, and switch 1203 is made conductive or non-conductive between the first terminal and the second terminal (i.e., the on state or off state of transistor 1213) by a control signal RD input to the gate of transistor 1213. The first terminal of switch 1204 corresponds to one of the source and drain of transistor 1214, the second terminal of switch 1204 corresponds to the other of the source and drain of transistor 1214, and switch 1204 is made conductive or non-conductive between the first terminal and the second terminal (i.e., the on state or off state of transistor 1214) by a control signal RD input to the gate of transistor 1214.

[0430] One of the source and drain of transistor 1209 is one of the pair of electrodes of capacitor element 1208. One of them is electrically connected to the gate of the transistor 1210. Here, the connection portion is defined as node M2. One of the source and drain of the transistor 1210 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply potential, and the other is electrically connected to the first terminal of the switch 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and drain of the transistor 1214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213), the first terminal of the switch 1204 (one of the source and drain of the transistor 1214), the input terminal of the logic element 1206, and one of the pair of electrodes of the capacitor element 1207 are electrically connected. Here, the connection portion is defined as node M1. The other of the pair of electrodes of the capacitor element 1207 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor element 1207 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply potential. The other of the pair of electrodes of the capacitor element 1208 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor is electrically connected to the D line).

[0431] Note that the capacitor elements 1207 and 1208 can also be omitted by actively using the parasitic capacitance of transistors, wiring, etc.

[0432] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE, and when the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

[0433] A signal corresponding to the data held in the circuit 1201 is input to the other of the source and drain of the transistor 1209. In FIG. 37, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220.

[0434] Note that in FIG. 37, an example in which the signal output from the second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 is input to the circuit 1201 via the logic element 1206 and the circuit 1220 is shown, but the present invention is not limited to this. The signal output from the second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 is not limited thereto. The signal output from the second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 has a logical value ​​​​​​​​​It may be input to circuit 1201 without being inverted. For example, within circuit 1201 , in a case where there is a node that holds a signal whose logic value of the signal input from the input terminal is inverted , the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213 ) can be input to the node.

[0435] In FIG. 37, among the transistors used in memory element 1200, transistors other than transistor 1209 can be transistors in which a channel is formed in a layer or substrate 11 90 made of a semiconductor other than an oxide semiconductor. For example, they can be transistors in which a channel is formed in a silicon layer or a silicon substrate. Also, all of the transistors used in memory element 1200 can be transistors in which a channel is formed in an oxide semiconductor layer . Or, memory element 1200 may also include transistors in which a channel is formed in an oxide semiconductor layer, in addition to transistor 1209, and the remaining transistors can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor .

[0436] For circuit 1201 in FIG. 37, for example, a flip-flop circuit can be used . Also, as logic element 1206, for example, an inverter, a clocked inverter, or the like can be used .

[0437] In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to memory element 1200 , the data stored in circuit 1201 can be held by capacitor 12 08 provided in circuit 1202. ​​

[0438] In addition, in a transistor in which a channel is formed in an oxide semiconductor layer, the off-current is extremely small. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using such a transistor as transistor 1209, the signal held in capacitor element 1208 can be retained for a long time even while no power supply voltage is supplied to memory element 1200. Thus, memory element 1200 can retain the stored content (data) even while the supply of the power supply voltage is stopped. Also, by providing switch 1203 and switch 1204, since it is a memory element characterized by performing a precharge operation, after the resumption of the power supply voltage supply, the time until circuit 1201 retains the original data again can be shortened.

[0439] In addition, in circuit 1202, the signal held by capacitor element 1208 is input to the gate of transistor 1210. Therefore, after the supply of the power supply voltage to memory element 1200 is resumed, the signal held by capacitor element 1208 can be converted into the state (on state or off state) of transistor 1210 and read out from circuit 1202.

[0440] Also, in circuit 1202, the signal held by capacitor element 1208 is input to the gate of the transistor. Therefore, after the supply of the power supply voltage to memory element 1200 is resumed, the signal held by capacitor element 1208 can be converted into the state (on state or off state) of transistor 1210 and read out from circuit 1202. Therefore, even if the potential corresponding to the signal held in capacitor element 1208 fluctuates somewhat, the original signal can be accurately read out. (on state or off state) and read out from circuit 1202. Therefore, even if the potential corresponding to the signal held in capacitor element 1208 fluctuates somewhat, the original signal can be accurately read out.

[0441] By using such a memory element 1200 in a memory device such as a register or a cache memory that a processor has, the loss of data in the memory device due to the stop of the power supply voltage supply can be prevented. This is possible. Also, after resuming the supply of the power voltage, it can return to the state before the power supply stop in a short time. Therefore, in the entire processor or one or more logic circuits constituting the processor, power supply stop can be performed even for a short time, so that power consumption can be suppressed.

[0442] In this embodiment, the memory element 1200 has been described as an example used for the CPU. However, the memory element 1200 can also be applied to LSI such as DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), and RFID (Radio Frequency Identification).

[0443] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0444] (Embodiment 6) In this embodiment, a configuration example of a display panel according to an aspect of the present invention will be described.

[0445] [Configuration Example] FIG. 38(A) is a top view of a display panel according to an aspect of the present invention, and FIG. 38(B) is a circuit diagram for explaining a pixel circuit that can be used when a liquid crystal element is applied to a pixel of the display panel according to an aspect of the present invention. Also, FIG. 38(C) is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel of the display panel according to an aspect of the present invention.

[0446] The transistors arranged in the pixel portion can be formed according to the above embodiment. Also In addition, since it is easy to make the transistor an n-channel type, a part of the driving circuit that can be composed of n-channel type transistors is formed on the same substrate as the transistors in the pixel portion. By using the transistors shown in the above embodiment for the pixel portion and the driving circuit in this way, a highly reliable display device can be provided. A part of the driving circuit that can be composed of n-channel transistors can be formed on the same substrate as the transistors in the pixel portion. In this way, by using the transistors shown in the above embodiment for the pixel portion and the driving circuit, a highly reliable display device can be provided. An example of a block diagram of an active matrix type display device is shown in Fig. 38(A). On the substrate 700 of the display device, there are a pixel portion 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a signal line driving circuit 704. A plurality of signal lines are extended and arranged from the signal line driving circuit 704 in the pixel portion 701, and a plurality of scanning lines are extended and arranged from the first scanning line driving circuit 702 and the second scanning line driving circuit 703. In the intersection region of the scanning line and the signal line, pixels each having a display element are provided in a matrix. Further, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0447] An example of a block diagram of an active matrix type display device is shown in Fig. 38(A). On the substrate 700 of the display device, there are a pixel portion 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a signal line driving circuit 704. A plurality of signal lines are extended and arranged from the signal line driving circuit 704 in the pixel portion 701, and a plurality of scanning lines are extended and arranged from the first scanning line driving circuit 702 and the second scanning line driving circuit 703. In the intersection region of the scanning line and the signal line, pixels each having a display element are provided in a matrix. Further, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit). In Fig. 38(A), the first scanning line driving circuit 702, the second scanning line driving circuit 703, and the signal line driving circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. Also, when a driving circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. When the driving circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced, and the reliability or the yield can be improved. In Fig. 38(A), the first scanning line driving circuit 702, the second scanning line driving circuit 703, and the signal line driving circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. Also, when a driving circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases.

[0448] In Fig. 38(A), the first scanning line driving circuit 702, the second scanning line driving circuit 703, and the signal line driving circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. Also, when a driving circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. When the driving circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced, and the reliability or the yield can be improved. In Fig. 38(A), the first scanning line driving circuit 702, the second scanning line driving circuit 703, and the signal line driving circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced.

[0449] 〔Liquid Crystal Panel〕 Further, an example of the circuit configuration of a pixel is shown in FIG. 38(B). Here, a pixel circuit applicable to the pixels of a VA type liquid crystal display panel is shown.

[0450] This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each of the pixel electrode layers is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the pixels designed with multi-domains can be independently controlled.

[0451] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied thereto. On the other hand, the source electrode layer or the drain electrode layer 714 functioning as a data line is commonly used by the transistor 716 and the transistor 717. The transistor 716 and the transistor 717 can appropriately use the transistors described in the above form. Thereby, a highly reliable liquid crystal display panel can be provided.

[0452] The shape of the first pixel electrode layer electrically connected to the transistor 716 and the shape of the second pixel electrode layer electrically connected to the transistor 717 will be described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a shape that spreads in a V shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0453] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode is connected to the gate wiring 713. Different gate signals are applied to the gate wiring 712 and the gate wiring 71 3 to make the operation timings of the transistor 716 and the transistor 717 different, and the liquid crystal alignment can be controlled.

[0454] Also, a holding capacitor may be formed by the capacitance wiring 710, a gate insulating film functioning as a dielectric, and a capacitance electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

[0455] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween.

[0456] Note that the pixel circuit shown in FIG. 38(B) is not limited thereto. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit may be added to the pixel shown in FIG. 38(B).

[0457] 〔Organic EL panel〕 Another example of the circuit configuration of a pixel is shown in FIG. 38(C). Here, the pixel structure of a panel using an organic EL element is shown.

[0458] In the organic EL element, when a voltage is applied to the light-emitting element, electrons are injected from one of the pair of electrodes and holes are injected from the other into a layer containing a light-emitting organic compound, and a current flows. Then when the electrons and holes recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such light emission ​​​​​The optical element is called a current-excited light-emitting element.

[0459] FIG. 38(C) is a diagram showing an example of an applicable pixel circuit. Here, an example of using two n-channel type transistors in one pixel is shown. Note that the metal oxide film according to one aspect of the present invention can be used for the channel formation region of an n-channel type transistor. Further, the pixel circuit can apply digital time gradation driving.

[0460] The configuration of the applicable pixel circuit and the operation of the pixel when digital time gradation driving is applied will be described.

[0461] The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitive element 723. The switching transistor 721 has a gate electrode layer connected to the scanning line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the other of the source electrode layer and the drain electrode layer) connected to the gate electrode layer of the driving transistor 722. The driving transistor 722 has a gate electrode layer connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724 . The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed on the same substrate.

[0462] The switching transistor 721 and the driving transistor 722 can appropriately use the transistors described in the above embodiment to provide a highly reliable organic EL display panel.

[0463] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GN D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0464] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the gate electrode layer.

[0465] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode layer of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0466] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Furthermore, analog gradation driving can be performed.

[0467] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. The pixel circuit shown in 8(C) does not include a switch, a resistor, a capacitor, a sensor, a transistor or a logic element. A logic circuit or the like may be added.

[0468] When the transistors exemplified in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0469] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0470] (Embodiment 7) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a It is possible. In addition, an electronic device that can use the semiconductor device according to one aspect of the present invention Examples include mobile phones, game machines including portable types, portable data terminals, e-books, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 39 ..

[0471] FIG. 39(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 90 8, etc. Note that the portable game machine shown in FIG. 39(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this ..

[0472] FIG. 39(B) is a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 91 3 is provided on the first housing 911, and the second display unit 914 is provided on the second housing 912 . The first housing 911 and the second housing 912 are connected by a connection unit 915 , and the angle between the first housing 911 and the second housing 912 can be changed by the connection unit 915 . The video on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 at the connection unit 915. Also, the first display unit 913 and ​A display device with a function as a position input device may be added to at least one of the call and the second display unit 914. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0473] FIG. 39(C) is a notebook personal computer and includes a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like.

[0474] FIG. 39(D) is an electric refrigerator-freezer and includes a housing 931, a refrigerator door 932, a freezer door 9 33, and the like.

[0475] FIG. 39(E) is a video camera and includes a first housing 941, a second housing 942, a display unit 943 , operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942 . The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946 . The video on the display unit 943 may be configured to be switched according to the angle between the first housing 941 and the second housing 9 42 at the connection portion 946.

[0476] FIG. 39(F) is an ordinary automobile and includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

[0477] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification.​​​ They can be implemented in combination.

[0478] (Embodiment 8) In this embodiment, an example of the use of an RFID according to one aspect of the present invention will be described with reference to FIG. 40. Although the uses of RFID are extensive, for example, banknotes, coins, securities, bearer bonds, certificates (see FIG. 40(A) such as driver's licenses and residence certificates), packaging containers (see FIG. 40(C) such as wrapping paper and bottles), recording media (see FIG. 40( B) such as DVD software and video tapes), vehicles (see FIG. 40(D) such as bicycles), personal belongings (such as bags and glasses), food items, plants, animals, the human body, clothing, daily necessities, medical supplies including drugs and medicines, or electronic devices (such as liquid crystal display devices, EL display devices, television devices, or mobile phones), etc., or tags (see FIGS. 40(E) and 40(F)) attached to each item, etc. can be provided and used. The RFID 4000 according to one aspect of the present invention is fixed to an item by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each item. The RFID D4000 according to one aspect of the present invention is small, thin, and lightweight, so that the design of the item itself is not impaired even after being fixed to the item. Also, by providing the RFID 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Further, for packaging containers, recording media, personal belongings, food items, clothing, daily necessities, or electronic devices, etc., the present invention

[0479] The RFID 4000 according to one aspect of the present invention is fixed to an item by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each item. The RFID 4000 according to one aspect of the present invention is small, thin, and lightweight, so that the design of the item itself is not impaired even after being fixed to the item. Also, by providing the RFID 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Further, for packaging containers, recording media, personal belongings, food items, clothing, daily necessities, or electronic devices, etc., the present invention The RFID 4000 according to one aspect of the present invention is fixed to an item by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each item. The RFID 4000 according to one aspect of the present invention is small, thin, and lightweight, so that the design of the item itself is not impaired even after being fixed to the item. Also, by providing the RFID 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Further, for packaging containers, recording media, personal belongings, food items, clothing, daily necessities, or electronic devices, etc., the present invention The RFID 4000 according to one aspect of the present invention is fixed to an item by being pasted on or embedded in the surface. ​By attaching the RFID according to one aspect, the efficiency of a system such as an inspection system can be improved. Also, even in vehicles, by attaching the RFID according to one aspect of the present invention, the security against theft and the like can be enhanced.

[0480] As described above, by using the RFID according to one aspect of the present invention for each application exemplified in this embodiment, the operating power including information writing and reading can be reduced, so that the maximum communication distance can be lengthened. Also, even in a state where the power is cut off, information can be held for an extremely long period, so it can be suitably used for applications with low writing and reading frequencies.

[0481] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Example

[0482] In this example, a semiconductor device having a transistor using single crystal silicon and a transistor using an oxide semiconductor laminated on the transistor was fabricated, and the electrical characteristics of each transistor were evaluated.

[0483] [Description of Samples] The method for fabricating the samples is described below.

[0484] First, as a substrate, an SOI substrate having a single crystal silicon film with a thickness of 52 nm was prepared.

[0485] Next, a part of the single crystal silicon film was etched by photolithography to form the single crystal silicon film into an island shape.

[0486] ​​​​​Next, using the microwave CVD method, the single-crystal silicon film was oxidized from the surface to form a silicon oxide film with a thickness of 1 0 nm. Note that the microwave CVD method is also called the high-density plasma CVD method or the like. Next, a heat treatment was performed at 950 °C for 1 hour in a nitrogen atmosphere to form a gate insulating film.

[0487] Next, in order to form a p-channel transistor, phosphorus ions were implanted into a part of the single-crystal silicon film . The implantation of phosphorus ions was carried out using an ion implantation apparatus (having a mass separation function), with an acceleration voltage of 18 kV and a concentration of 6.5×10 11 ions / cm 2 .

[0488] Next, in order to form an n-channel transistor, boron ions were implanted into a part of the single-crystal silicon film . The implantation of boron ions was carried out using an ion implantation apparatus, with an acceleration voltage of 14 kV and a concentration of 3.0×10 12 ions / cm 2 .

[0489] Next, using the sputtering method, a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 170 nm were sequentially formed. Next, a part of the tantalum nitride film and the tungsten film was etched by photolithography to form a gate electrode .

[0490] Next, boron ions were implanted into the region of the single-crystal silicon film that would become a p-channel transistor, using the gate electrode as a mask. The implantation of boron ions was carried out using an ion implantation apparatus, with an acceleration voltage of 9 kV and a concentration of 1.0×10 13 ions / cm 2 .

[0491] Next, for the region of the single-crystalline silicon film that will become the n-channel transistor, a gate electrode was used as a mask to implant phosphorus ions. The implantation of phosphorus ions was carried out using an ion implantation apparatus with an acceleration voltage of 9 kV at a concentration of 1.0×10 13 ions / cm 2 .

[0492] Next, a silicon oxynitride film with a thickness of 300 nm was formed using the plasma CVD method, and by performing anisotropic etching, an insulating film (also referred to as a sidewall insulating film or a spacer wall insulating film) that contacts the side surface of the gate electrode was formed. Note that a part of the gate insulating film is etched simultaneously with the etching of this silicon oxynitride film. As a result, a part of the single-crystalline silicon film is exposed.

[0493] Next, for the region of the single-crystalline silicon film that will become the p-channel transistor, a gate electrode and the sidewall insulating film were used as masks to implant boron ions. The implantation of boron ions was carried out using an ion doping apparatus (without a mass separation function) with an acceleration voltage of 10 kV at a concentration of 1. 5×10 16 ions / cm 2 . The region where boron ions are implanted functions as the source region or drain region of the p-channel transistor. Also, the region of the single-crystalline silicon film directly under the sidewall insulating film has a carrier density intermediate between the channel formation region formed by the above-described process and the source region or drain region, and thus functions as an LDD (Lightly Doped Drain) region.

[0494] Next, for the region of the single-crystalline silicon film that will become the n-channel transistor, a gate electrode Using the sidewall insulating film as a mask, phosphorus ions were implanted. The accelerating voltage was set to 10 kV, and the 15 ions / cm 2 Concentration The phosphorus ion implanted region was located in the source region of the n-channel transistor. The region of the single crystal silicon film directly below the sidewall insulating film functions as a drain region. The channel forming region and the source or drain region formed by the above-mentioned process are Since it has a carrier density intermediate between the LDD region and the LDD region, it functions as an LDD region.

[0495] Next, a silicon oxynitride film was formed to a thickness of 50 nm by using a plasma CVD method.

[0496] Next, heat treatment was performed at 550° C. for 1 hour in a nitrogen atmosphere.

[0497] Next, a silicon oxynitride film with a thickness of 280 nm was formed using the plasma CVD method. The silicon nitride oxide film is also called a SiNOH film because it contains a large amount of hydrogen. .

[0498] Next, a silicon oxynitride film was formed to a thickness of 300 nm by thermal CVD.

[0499] Next, heat treatment was performed at 490° C. for 1 hour in a nitrogen atmosphere. The hydrogen is released from the SiNOH film. The released hydrogen reaches the single crystal silicon film. This terminates the dangling bonds of the single crystal silicon film. This is called hydrotreating.

[0500] Next, a silicon oxynitride film having a thickness of 50 nm and a silicon nitride oxide film having a thickness of 280 nm are By etching a part of the silicon oxide film with a thickness of 300 nm, openings reaching the source region, drain region, gate electrode, etc. were formed.

[0501] Next, a tungsten film with a thickness of 150 nm was formed using the sputtering method.

[0502] Next, a part of the tungsten film was etched by photolithography to form the first wiring layer.

[0503] Next, a silicon oxide film with a thickness of 900 nm was formed using the plasma CVD method.

[0504] Next, from the upper surface of the silicon oxide film, by CMP treatment, the thickness of the silicon oxide film was flattened until it reached about 400 nm to 500 nm.

[0505] Next, heat treatment was performed in a nitrogen atmosphere. Sample 1 was heat-treated at 490 °C for 10 hours and Sample 2 was heat-treated at 450 °C for 5 hours. This heat treatment is called dehydrogenation treatment because it causes the hydrogen remaining in each layer to diffuse outward without being diffused outward by the above hydrogenation treatment or used as the termination of dangling bonds. The dehydrogenation treatment is more effective as the temperature is higher and the time is longer. Therefore, it can be said that Sample 1 has less remaining hydrogen than Sample 2.

[0506] Next, by etching a part of the silicon oxide film with a thickness of about 400 nm to 500 nm, openings reaching the first wiring layer, etc. were formed.

[0507] Next, a tungsten film with a thickness of 150 nm was formed using the sputtering method.

[0508] Next, a part of the tungsten film was etched by photolithography to form a conductive film 220 having the function of a second gate electrode and a conductive film 174 having the function of a second wiring layer.

[0509] Next, a silicon oxide film with a thickness of 500 nm was formed using the plasma CVD method.

[0510] Next, from the upper surface of the silicon oxide film, it was planarized by CMP processing until the thickness of the silicon oxide film became about 0 nm to 50 nm, and the upper surface of the tungsten film was exposed.

[0511] Next, a silicon oxide film with a thickness of 100 nm was formed using the plasma CVD method.

[0512] Next, heat treatment was performed in a nitrogen atmosphere. Sample 1 was heat-treated at 490 °C for 10 hours. Also, sample 2 was heat-treated at 450 °C for 1 hour. By this heat treatment, further dehydrogenation treatment was performed.

[0513] Next, an aluminum oxide film with a thickness of 50 nm was formed using the sputtering method. The aluminum oxide film has the function of blocking oxygen, hydrogen, etc. Therefore, by providing the aluminum oxide film, hydrogen released from transistors using single-crystalline silicon and insulating films, conductive films, etc. provided around them can be prevented from mixing into transistors using oxide semiconductors to be fabricated later.

[0514] Next, a silicon oxynitride film with an excess of oxygen and a thickness of 100 nm was formed using the plasma CVD method. Note that the silicon oxynitride film releases oxygen by subsequent heat treatment, etc. It is a silicon oxynitride film to be formed. The oxygen released is used to reduce the oxygen deficiency of the oxide semiconductor, and can improve the electrical characteristics and reliability of the transistor. On the other hand, when the released oxygen reaches the single crystal silicon, the electrical characteristics and reliability of the transistor may deteriorate. The aluminum oxide film described above has a function of preventing the mixing of oxygen into the single crystal silicon. Therefore, even if a silicon oxynitride film having excess oxygen is provided, a transistor using a single crystal silicon with high electrical characteristics and reliability can be manufactured. For this purpose, it can be utilized to improve the electrical characteristics and reliability of the transistor. On the other hand, when the released oxygen reaches the single crystal silicon, the electrical characteristics and reliability of the transistor may deteriorate. When the released oxygen reaches the single crystal silicon, the electrical characteristics and reliability of the transistor may deteriorate. The above-described aluminum oxide film has a function of preventing the mixing of oxygen into the single crystal silicon. Therefore, even if a silicon oxynitride film having excess oxygen is provided, a transistor using a single crystal silicon with high electrical characteristics and reliability can be manufactured. When using a single crystal silicon with high electrical characteristics and reliability, a transistor can be manufactured.

[0515] Next, for Sample 1, using the sputtering method, a first oxide semiconductor film with a thickness of 20 nm and a second oxide semiconductor film with a thickness of 20 nm were sequentially formed. Also, for Sample 2, using the sputtering method, a first oxide semiconductor film with a thickness of 20 nm and a second oxide semiconductor film with a thickness of 15 nm were sequentially formed. For the formation of the first oxide semiconductor film, a target with In:Ga:Zn = 1:3:2 [atomic ratio] was used. Also, for the formation of the second oxide semiconductor film, a target with In:Ga:Zn = 1:1:1 [atomic ratio] was used. Next, for Sample 1, using the sputtering method, a first oxide semiconductor film with a thickness of 20 nm and a second oxide semiconductor film with a thickness of 20 nm were sequentially formed. Also, for Sample 2, using the sputtering method, a first oxide semiconductor film with a thickness of 20 nm and a second oxide semiconductor film with a thickness of 15 nm were sequentially formed. For the formation of the first oxide semiconductor film, a target with In:Ga:Zn = 1:3:2 [atomic ratio] was used. Also, for the formation of the second oxide semiconductor film, a target with In:Ga:Zn = 1:1:1 [atomic ratio] was used. For the formation of the first oxide semiconductor film, a target with In:Ga:Zn = 1:3:2 [atomic ratio] was used. Also, for the formation of the second oxide semiconductor film, a target with In:Ga:Zn = 1:1:1 [atomic ratio] was used. For the formation of the first oxide semiconductor film, a target with In:Ga:Zn = 1:3:2 [atomic ratio] was used. Also, for the formation of the second oxide semiconductor film, a target with In:Ga:Zn = 1:1:1 [atomic ratio] was used. For the formation of the second oxide semiconductor film, a target with In:Ga:Zn = 1:1:1 [atomic ratio] was used. Note that the first oxide semiconductor film and the second oxide semiconductor film together are called the oxide semiconductor film 206. Note that the first oxide semiconductor film and the second oxide semiconductor film together are called the oxide semiconductor film 206.

[0516] Next, after performing heat treatment at 450 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 450 °C for 1 hour in an oxygen atmosphere. Next, after performing heat treatment at 450 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 450 °C for 1 hour in an oxygen atmosphere.

[0517] Next, a part of the oxide semiconductor film 206 was etched by the photolithography method to form the oxide semiconductor film 206 into an island shape. Next, a part of the oxide semiconductor film 206 was etched by the photolithography method to form the oxide semiconductor film 206 into an island shape.

[0518] Next, by etching a part of the silicon oxynitride film having excess oxygen, a part of the aluminum oxide film, and a part of the silicon oxide film, openings (such as opening 260) reaching the conductive film 220, the conductive film 174, etc. were formed.

[0519] Next, a tungsten film with a thickness of 100 nm was formed using the sputtering method.

[0520] Next, a part of the tungsten film was etched by photolithography to form conductive films 216a and 216b having a function as a source electrode or a drain electrode of a transistor using an oxide semiconductor.

[0521] Next, a third oxide semiconductor film with a thickness of 5 nm was formed using the sputtering method. For the formation of the third oxide semiconductor film, a target with In:Ga:Zn = 1:3:2 [atomic ratio] was used.

[0522] Next, a silicon oxynitride film with a thickness of 20 nm was formed using the plasma CVD method.

[0523] Next, a titanium nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm were sequentially formed using the sputtering method.

[0524] Next, a part of the titanium nitride film and the tungsten film was etched by photolithography to form the gate electrode 204.

[0525] Next, a part of the third oxide semiconductor film and the silicon oxynitride film was etched by photolithography. Since the silicon oxynitride film is disposed between the second oxide semiconductor film, which is the channel formation region, and the gate electrode 204, it has a function as a gate insulating film. ​​​​​​​​​ Do it.

[0526] Next, an aluminum oxide film with a thickness of 150 nm was formed using a sputtering method. The aluminum oxide film has a function of blocking oxygen, hydrogen, etc. Therefore, by providing the aluminum oxide film, hydrogen released from a transistor using single-crystalline silicon, an insulating film provided around it, a conductive film, etc., and hydrogen mixed in from the outside of the semiconductor device can be prevented from mixing into a transistor using an oxide semiconductor. Also, oxygen released from a silicon oxynitride film having excess oxygen can be prevented from diffusing outward, and the oxygen can be efficiently used to reduce the oxygen deficiency of the oxide semiconductor. .

[0527] Next, a heat treatment was performed at 400 °C for 1 hour in an oxygen atmosphere. By this heat treatment, a part of the oxygen contained in the silicon oxynitride film having excess oxygen is released and first supplied to the first oxide semiconductor film. Since the supplied oxygen moves in a ball-bouncing manner in the first oxide semiconductor film, oxygen is apparently also supplied to the second oxide semiconductor film. That is, it can be seen that by this heat treatment, the oxygen deficiency of the second oxide semiconductor film, which is the channel formation region, can be reduced. At this time, an aluminum oxide film is disposed around the second oxide semiconductor film. Therefore, it can be seen that the oxygen released from the silicon oxynitride film having excess oxygen is efficiently used to reduce the oxygen deficiency of the second oxide semiconductor film.

[0528] Next, a silicon oxynitride film with a thickness of 300 nm was formed using a plasma CVD method.

[0529] Next, the silicon oxynitride film and the aluminum oxide film are partially etched. Openings reaching the conductive film 216a, the conductive film 216b, and the like were formed.

[0530] Next, a titanium film with a thickness of 50 nm and an aluminum film with a thickness of 200 nm were deposited by sputtering. An aluminum film and a titanium film having a thickness of 50 nm were formed in this ord...

Claims

1. A semiconductor device having a first transistor, a second transistor, and a capacitive element, a first insulating layer having a region located above the channel formation region of the first transistor, a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitive element, a second insulating layer having a region located above the first conductive layer, a second conductive layer having a region located above the second insulating layer and functioning as the first gate electrode of the second transistor, a third insulating layer having a region located above the first conductive layer, an oxide semiconductor layer having a region located above the third insulating layer and having the channel formation region of the second transistor, a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of the source or drain of the second transistor, a fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source or drain of the second transistor, a fourth insulating layer having a region located above the oxide semiconductor layer and functioning as the gate insulating layer of the second transistor, a fifth conductive layer having a region located above the fourth insulating layer and functioning as the second gate electrode of the second transistor, and the third conductive layer is always in conduction with the gate of the first transistor through a first opening provided in the second insulating layer, the fourth conductive layer is always in conduction with one of the source or drain of the first transistor through a second opening provided in the second insulating layer, the first conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer, the second conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer. A semiconductor device.

2. A semiconductor device having a first transistor, a second transistor, and a capacitive element, a first insulating layer having a region located above the channel formation region of the first transistor, a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitive element, a second insulating layer having a region located above the first conductive layer, A second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor, A third insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source or a drain of the second transistor, A fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of a source or a drain of the second transistor, A fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor, A fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor, and having, The third conductive layer is always in conduction with the gate of the first transistor through a first opening provided in the second insulating layer, The fourth conductive layer is always in conduction with one of a source or a drain of the first transistor through a second opening provided in the second insulating layer, The first conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer, The second conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer, The oxide semiconductor layer has In, Ga, and Zn, The second insulating layer has nitrogen and silicon, a semiconductor device.

3. A semiconductor device having a first transistor, a second transistor, and a capacitive element, comprising: A first insulating layer having a region located above a channel formation region of the first transistor, A first conductive layer having a region located above the first insulating layer and functioning as one of electrodes of the capacitive element, A second insulating layer having a region located above the first conductive layer, A second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor, A third insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source or a drain of the second transistor, A fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of a source or a drain of the second transistor, A fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor, A fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor, The third conductive layer is always in conduction with the gate of the first transistor through a first opening provided in the second insulating layer, The fourth conductive layer is always in conduction with one of a source or a drain of the first transistor through a second opening provided in the second insulating layer, The first conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer, The second conductive layer has a region overlapping the oxide semiconductor layer through the third insulating layer and a region overlapping the third conductive layer through the third insulating layer, The first conductive layer contains molybdenum, The second conductive layer contains molybdenum, a semiconductor device.

4. A semiconductor device having a first transistor, a second transistor, and a capacitive element, A first insulating layer having a region located above the channel formation region of the first transistor, A first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitive element, A second insulating layer having a region located above the first conductive layer, A second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor, A third insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source or a drain of the second transistor, A fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source or drain of the second transistor; A fourth insulating layer having a region located above the oxide semiconductor layer and functioning as the gate insulating layer of the second transistor; A fifth conductive layer having a region located above the fourth insulating layer and functioning as the second gate electrode of the second transistor; and The third conductive layer is always in conduction with the gate of the first transistor through a first opening provided in the second insulating layer; The fourth conductive layer is always in conduction with one of the source or drain of the first transistor through a second opening provided in the second insulating layer; The first conductive layer has a region overlapping with the oxide semiconductor layer through the third insulating layer and a region overlapping with the third conductive layer through the third insulating layer; The second conductive layer has a region overlapping with the oxide semiconductor layer through the third insulating layer and a region overlapping with the third conductive layer through the third insulating layer; The oxide semiconductor layer contains In, Ga, and Zn; The second insulating layer contains nitrogen and silicon; The first conductive layer contains molybdenum; The second conductive layer contains molybdenum. A semiconductor device

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