Control device

Abstract

A control device (103) for memory included in a device for realizing a stochastic computing calculating mechanism is provided with: a write interface (11) into which a spike train is input; a read interface (12) which outputs the spike train; and shift circuits (13-0 to 13-15). The shift circuits (13-0 to 13-15) read and write levels held by each thereof to memory cells (c0-0 to c0-15, c1-0 to c1-15, c2-0 to c2-15).

Description

Technical Field

[0001] The present disclosure relates to a control device for a memory.

Background Art

[0002] A stochastic computing (SC) computing mechanism (hereinafter referred to as an SC computing mechanism) performs information processing based on a spike train (for example, Patent Document 1). More specifically, the SC computing mechanism performs arithmetic processing based on a spike train and storage processing based on a spike train.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a device that implements an SC computing mechanism, when performing storage processing based on a spike train, it is preferable that the spike train be written into the memory as it is and read from the memory as it is.

[0005] One aspect of the present disclosure aims to realize a control device for a memory having a novel configuration that enables a spike train to be written into the memory as it is and read from the memory as it is.

Means for Solving the Problems

[0006] To solve the above problems, a control device according to one aspect of the present disclosure is a control device for a memory included in a device that realizes a stochastic computing mechanism, and includes a writing interface to which a spike train is input, a reading interface from which a spike train is output, and a plurality of shift circuits that hold the levels of signals input to each of them. The plurality of shift circuits are serially connected between the writing interface and the reading interface. Between two adjacent shift circuits, the shift circuit located on the writing interface side moves the level held by the shift circuit to the shift circuit located on the reading interface side. A plurality of memory cells capable of writing and reading the levels held by each shift circuit are connected to each of the shift circuits. (i) When a spike train is input from the writing interface to the control device, each shift circuit moves the level of each digit of the spike train sequentially input from the writing interface between two adjacent shift circuits from the writing interface side toward the reading interface side. After the level of each digit is held by the corresponding shift circuit, the level held by each shift circuit is written to the memory cells connected to each shift circuit. (ii) When the control device outputs a spike train from the reading interface, each shift circuit reads the level of each digit from the memory cells connected to each shift circuit. After the level of each digit is held by the corresponding shift circuit, the level held by each shift circuit is moved between two adjacent shift circuits from the writing interface side toward the reading interface side.

Advantages of the Invention

[0007] According to one aspect of the present disclosure, it is possible to provide a control device for a memory having a novel configuration.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0009] 〔Overview of the Present Disclosure〕 Research on information processing based on spike trains in the SC calculation mechanism has begun. However, most of the current research focuses on arithmetic processing among information processing based on spike trains, and there is no research focusing on memory processing.

[0010] In current research, regarding arithmetic processing based on spike trains, a configuration has already been realized in which the spike train is directly input to the arithmetic unit and the spike train is directly output from the arithmetic unit. In contrast, regarding memory processing based on spike trains, a configuration in which the spike train is directly written to the memory and the spike train is directly read from the memory has not yet been realized. Note that "directly" in this specification means that no processing is performed on the spike train. For example, "the spike train is directly input to the arithmetic unit" means that the spike train is input to the arithmetic unit without performing any processing on the spike train.

[0011] In current research, regarding memory processing based on spike trains, a configuration using a conventional memory has been proposed. In this proposed configuration, the spike train output from the arithmetic unit is input to a bit number counter arranged outside the conventional memory. Then, the count value output from the bit number counter is written to the conventional memory. On the other hand, the data read from the conventional memory is input to a spike generator arranged outside the conventional memory. Then, a spike train is output from the spike generator. The spike train output from the spike generator is input to the arithmetic unit.

[0012] As described above, in current research, regarding memory processing based on spike trains, when writing a spike train to a conventional memory, it is necessary to perform predetermined processing on the spike train using the above-described bit number counter and spike generator. However, it is preferable to eliminate the bit number counter and the spike generator. This is because if the bit number counter and the spike generator are eliminated, the hardware can be reduced and the data processing can be speeded up in the device that realizes the SC computing mechanism.

[0013] In view of the current research results, the present inventors have intensively studied to realize a configuration that enables a spike train to be directly written to a memory and directly read from the memory also for memory processing based on spike trains, and as a result, have invented the present disclosure.

[0014] Note that, in the following, each embodiment will be described by taking, as an example, a control device for a memory included in a device that implements an SC computing mechanism. However, the device including the control device according to each embodiment is not limited to the device that implements the SC computing mechanism.

[0015] [Embodiment 1] Hereinafter, an embodiment of the present disclosure will be described in detail. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals.

[0016] FIG. 1 is a schematic configuration diagram of a device 100 including a control device 103 according to Embodiment 1 of the present disclosure. As shown in FIG. 1, the device 100 includes an arithmetic device 101, a storage device 102, and a control device 103. The device 100 is a device that implements an SC computing mechanism.

[0017] <Configuration of a device that implements an SC computing mechanism> (Arithmetic device) The arithmetic device 101 includes a plurality of arithmetic units (not shown). Spike trains are input to each arithmetic unit as they are. Each arithmetic unit executes various operations based on the spike train input to the arithmetic unit. Each arithmetic unit outputs, as it is, the spike train that is the operation result of the arithmetic unit.

[0018] Here, a spike train is a pattern of spikes generated at a predetermined time interval. The predetermined time interval is the time interval from the timing at which the first spike is generated to the timing at which the next spike is generated with respect to two continuously generated spikes.

[0019] Note that, in the present Embodiment 1, the number of spikes constituting the spike train is two or more. Also, the time intervals between the generation timings of two continuously generated spikes are the same. However, the present disclosure is not limited to the above-described number of spikes and time intervals.

[0020] In addition, in the first embodiment, the presence or absence of spike generation that constitutes a spike train is represented by "1" level and "0" level. More specifically, the presence of spike generation is represented by "1" level, and the absence of spike generation is represented by "0" level. Also, the generation timing of the spike train is the generation timing of the first spike. For example, when the number of spikes is two, the spike train is represented by "1010". In this case, the arithmetic unit 101 sequentially outputs a "1" level signal, a "0" level signal, a "1" level signal, and a "0" level signal in this order at a predetermined time interval. If the generation timing of the spike train is set to be before the generation timing of the first spike, the spike train will be represented by "0101". In the present application, "1" represents a positive logic value corresponding to a high-level voltage, and "0" represents a negative logic value corresponding to a low-level voltage.

[0021] Note that numerical values can be expressed using the presence or absence of spike generation that constitutes a spike train as follows.

[0022] (1) A numerical value is expressed based on which spike it is among the spikes generated counting from a predetermined timing as the starting point. For example, a numerical value of "1" can be expressed based on the generation of the first spike, a numerical value of "2" can be expressed based on the generation of the second spike, and a numerical value of "3" can be expressed based on the generation of the third spike, respectively.

[0023] (2) The clock signal is counted from a predetermined timing as the starting point, and when a spike is generated in accordance with the rising edge of the clock signal, a numerical value is expressed based on the count number at the time of generation of the spike. For example, if the count number at the time when a spike is generated in accordance with the rising edge of the clock signal is two, a numerical value of "2" can be expressed based on the count number.

[0024] (3) Express a numerical value based on the count of the clock signal counted during the period when one spike occurs. For example, if the count during the period when one spike occurs is 2, the numerical value "2" can be expressed based on the count.

[0025] (Memory device) The memory device 102 includes a plurality of memory cells (not shown). Each memory cell is an element that stores either a "1" level or a "0" level. Each memory cell is a semiconductor memory cell that can be written to and read from. Each memory cell is, for example, a known semiconductor memory cell, an SRAM (Static Randum Accsess Memory) memory cell. The memory device 102 has a configuration in which a plurality of memory cells are arranged in a planar and regular array. Hereinafter, this configuration is referred to as a memory cell array.

[0026] A spike train is input to the memory device 102 as it is. Each memory cell of the memory cell array of the memory device 102 stores the presence or absence of the occurrence of a spike in the spike train input to the memory cell. Also, the memory device 102 outputs as it is the spike train that is the read result from each memory cell. The read result is the presence or absence of the occurrence of a spike stored in each memory cell.

[0027] In the first embodiment, each memory cell stores the presence or absence of the occurrence of a spike in the spike train input to the memory device 102 as the "1" level and the "0" level as described later. In the first embodiment, each memory cell stores the presence of a spike as the "1" level and the absence of a spike as the "0" level. However, in the present disclosure, each memory cell may store the presence of a spike as the "0" level and the absence of a spike as the "1" level.

[0028] For example, let the spike train input to the memory device 102 be "0101". In this case, signals of "1" level, "0" level, "1" level, and "0" level are sequentially input to the memory device 102 at predetermined time intervals in this order. The memory device 102 stores the level of each sequentially input signal in the memory cells selected from the memory cell array. The levels of each signal are stored in different memory cells from each other.

[0029] (Control device) The control device 103 outputs the spike train, which is the calculation result of the arithmetic device 101, to the memory device 102 as it is. Also, the control device 103 outputs the spike train read from the memory device 102 to the arithmetic device 101 as it is.

[0030] (Configuration and operation of the control device) Hereinafter, the configuration and operation of the control device 103, which is a characteristic part of the present disclosure, will be described in detail. Note that, regarding the configurations and operations of the arithmetic device 101 and the memory device 102, only the contents necessary for explaining the configuration and operation of the control device 103 will be described, and the others will be omitted.

[0031] (Configuration) FIG. 2 is a diagram showing the circuit configuration of the control device 103. Note that, although various members of the memory device 102 are also shown in FIG. 2, as described above, the description of the members not related to the control device 103 will be omitted.

[0032] As shown in FIG. 2, the control device 103 includes a write interface 11, a read interface 12, and shift circuits 13-0, 13-1, ···, 13-14, 13-15. The shift circuits 13-0, 13-1, ···, 13-14, 13-15 are serially connected between the write interface 11 and the read interface 12. Hereinafter, when collectively referring to the shift circuits 13-15, 13-14, ···, 13-1, 13-0, they are referred to as the shift circuit 13.

[0033] Also, as shown in FIG. 2, the storage device 102 includes the memory cell array 51, the peripheral circuit 52, the address generation circuit 53, and the memory interface 54 described above. Note that the memory interface 54 is not an essential element of the storage device 102. The memory interface 54 is an interface used when writing data to the storage device 102 without going through the control device 103. However, by providing the memory interface 54 in the storage device 102, the functions of the storage device 102 can be verified, and the convenience of the storage device 102 and the compatibility with the conventional system can be improved.

[0034] Here, the point to note is that as shown in FIG. 2, while the clock signal CK is input to the control device 103, the clock signal CK2 is input to the storage device 102. As will be described later, data is input and output to and from the storage device 102 in synchronization with the clock signal CK2. As will be described later, data is input and output to and from the control device 103 in synchronization with the clock signal CK.

[0035] FIG. 9 shows the timing charts of the clock signal CK and the clock signal CK2. As shown in FIG. 9, the interval between the rising edges T of the clock signal CK is smaller than the interval between the rising edges T2 of the clock signal CK2. That is, the period of the clock signal CK is shorter than the period of the clock signal CK2. In other words, it can be said that the clock signal CK is a high-frequency clock signal and the clock signal CK2 is a low-frequency clock signal.

[0036] As described above, writing and reading of known memory cells are required for the storage device 102. Therefore, the storage device 102 executes a low-speed operation based on the clock signal CK2.

[0037] On the other hand, different from the storage device 102, writing and reading of known memory cells are not required for the control device 103. Therefore, the control device 103 executes a high-speed operation based on the clock signal CK.

[0038] The memory cell array 51 includes a plurality of memory cells c0-0 to c2-0, c0-1 to c2-1, ···, c0-14 to c2-14, and c0-15 to c2-15. The peripheral circuit 52 includes read circuits R0 to R15 and write circuits W0 to W15. Hereinafter, when collectively referring to the memory cells c0-0 to c2-0, c0-1 to c2-1, ···, c0-14 to c2-14, and c0-15 to c2-15, they are referred to as memory cells c. Also, when collectively referring to the read circuits R0 to R15 and the write circuits W0 to W15 respectively, they are referred to as read circuit R and write circuit W.

[0039] Each of the memory cells c0-0 to c2-0 is connected to the read circuit R0 and the write circuit W0 via the bit line BL0 and the bit line XBL0. Each of the memory cells c0-1 to c2-1 is connected to the read circuit R1 and the write circuit W1 via the bit line BL1 and the bit line XBL1. Each of the memory cells c0-14 to c2-14 is connected to the read circuit R14 and the write circuit W14 via the bit line BL14 and the bit line XBL14. Each of the memory cells c0-15 to c2-15 is connected to the read circuit R15 and the write circuit W15 via the bit line BL15 and the bit line XBL15. Hereinafter, when collectively referring to the bit lines BL0 to BL15 and the bit lines XBL0 to XBL15 respectively, they are referred to as bit line XBL.

[0040] The address generation circuit 53 has row addresses WL0 to WL2. The address generation circuit 53 selects the memory cells c0-0 to c2-0, c0-1 to c2-1, ···, c0-14 to c2-14, and c0-15 to c2-15 from the memory cell array 51 using the row addresses WL0 to WL2, the bit lines BL0 to BL15, and the bit lines XBL0 to XBL15.

[0041] In the first embodiment, the total number of shift circuits 13 is 16, but the present disclosure is not limited to this number. The reason for setting the total number of shift circuits 13 to 16 in the first embodiment is that it is assumed that the design is based on a 16-bit CPU (Central Processing Unit) as each arithmetic unit of the arithmetic device 101. Along with the total number of shift circuits 13 being 16, the total numbers of the read circuit R, the write circuit W, the bit lines BL, and the bit lines XBL are also 16. Further, in the memory cell array 51, 48 memory cells c are arranged in a 3-row × 16-column array. Along with the total number of shift circuits 13 being 16, the total number of columns is also 16. On the other hand, the total number of rows is 3, but the present disclosure is not limited to this number.

[0042] The write interface 11 is an interface for connecting the arithmetic device 101 and the control device 103 in FIG. 1. The write interface 11 includes an input terminal connected to the output terminal of the arithmetic device 101 in FIG. 1. A spike train is input to the input terminal of the write interface 11. The spike train is the arithmetic result of the arithmetic device 101.

[0043] The write interface 11 includes an output terminal connected to the input terminals of the shift circuits 13 - 15. More specifically, the write interface 11 includes a pair of output terminals. The output signal of one output terminal is the BLi signal. The output signal of the other output terminal is the XBLi signal. The level of the BLi signal and the level of the XBLi signal are complementary. That is, if the level of the BLi signal is at the "1" level, the level of the XBLi signal is at the "0" level. Conversely, if the level of the BLi signal is at the "0" level, the level of the XBLi signal is at the "1" level.

[0044] When a spike train is input to the input terminal of the write interface 11, the write interface 11 outputs the BLi signal from one output terminal of the write interface 11 and outputs the XBLi signal from the other output terminal of the write interface 11.

[0045] For example, assume that the spike train input to the write interface 11 is "1010". In this case, signals of "1" level, "0" level, "1" level, and "0" level are sequentially input to the write interface 11 at a predetermined time interval in this order. When the first "1" level signal is input to the write interface 11, the write interface 11 outputs a BLi signal of "1" level and an XBLi signal of "0" level. When the second "0" level signal is input to the write interface 11, the write interface 11 outputs a BLi signal of "0" level and an XBLi signal of "1" level. When the third "1" level signal is input to the write interface 11, the write interface 11 outputs a BLi signal of "1" level and an XBLi signal of "0" level. When the last "0" level signal is input to the write interface 11, the write interface 11 outputs a BLi signal of "0" level and an XBLi signal of "1" level.

[0046] The read interface 12 is an interface for connecting the arithmetic unit 101 and the control unit 103 in FIG. 1. The read interface 12 includes an output terminal connected to the input terminal of the arithmetic unit 101 in FIG. 1. A spike train is output from the output terminal of the read interface 12. The spike train is the spike train read from the memory cell array 51 of the storage device 102. The read spike train is an object of arithmetic operation by the arithmetic unit 101.

[0047] The read interface 12 includes an input terminal connected to the output terminal of the shift circuit 13-0. More specifically, the read interface 12 includes a pair of input terminals. The input signal of one input terminal is the BLo signal. The input signal of the other input terminal is the XBLo signal. The level of the BLo signal and the level of the XBLo signal are complementary. That is, if the level of the BLo signal is "1" level, the level of the XBLo signal is "0" level. Conversely, if the level of the BLo signal is "0" level, the level of the XBLo signal is "1" level.

[0048] When a BLo signal is input to one input terminal of the read interface 12 and an XBLo signal is input to the other input terminal of the read interface 12, the read interface 12 outputs a spike train from its output terminal.

[0049] For example, let the spike train output from the read interface 12 be “1010”. In this case, from the read interface 12, signals of “1” level, “0” level, “1” level, and “0” level are sequentially output in this order at a predetermined time interval. When a BLo signal of “1” level is input and an XBLo signal of “0” level is input, the read interface 12 outputs the first “1” level signal. When a BLo signal of “0” level is input and an XBLo signal of “1” level is input, the read interface 12 outputs the second “0” level signal. When a BLo signal of “1” level is input and an XBLo signal of “0” level is input, the read interface 12 outputs the third “1” level signal. When a BLo signal of “0” level is input and an XBLo signal of “1” level is input, the read interface 12 outputs the last “0” level signal.

[0050] Each of the shift circuits 13 has the same configuration. Also, the shift circuits 13 are arranged between the write interface 11 and the read interface 12 in the order of shift circuits 13-15, 13-14, ···, 13-1, 13-0. As will be described later, the shift circuit 13 holds the level of the signal input to each shift circuit 13. Between two adjacent shift circuits 13, the shift circuit 13 located on the write interface 11 side moves the level held by the shift circuit 13 to the shift circuit 13 located on the read interface 12 side.

[0051] The shift circuits 13-15 include a pair of input terminals, a pair of output terminals, a gate G15, a latch L15, and a buffer B15. Each of the pair of input terminals is connected to each output terminal of the writing interface 11. Each of the pair of output terminals is connected to each input terminal of the shift circuits 13-14. The shift circuit 13-14 is a shift circuit subsequent to the shift circuit 13-15.

[0052] The gate G15 includes a first switching element g15-1 and a second switching element g15-2. Both the first switching element g15-1 and the second switching element g15-2 are, for example, known semiconductor transistors. The first switching element g15-1 and the second switching element g15-2 each become conductive when the clock signal CK rises and become non-conductive when the clock signal CK falls.

[0053] The latch L15 holds two complementary levels input to the latch L15. For example, if the level input to the latch L15 is the "1" level, the latch L15 holds the "1" level. On the other hand, if the level input to the latch L15 is the "0" level, the latch L15 holds the "0" level.

[0054] The buffer B15 includes a first buffer b15-1 and a second buffer b15-2. The first buffer b15-1 and the second buffer b15-2 are composed of, for example, known semiconductor elements. The first buffer b15-1 outputs one of the two complementary levels held by the latch L15 to one output terminal of the shift circuit 13-15. The second buffer b15-2 outputs the other of the two complementary levels held by the latch L15 to the other output terminal of the shift circuit 13-15. Both the first buffer b15-1 and the second buffer b15-2 move the level only in the direction from the shift circuit 13-15 to the shift circuit 13-14.

[0055] The differences between shift circuits 13-14 to 13-0 and shift circuit 13-15 are as follows. That is, each input terminal of shift circuits 13-14 to 13-0 is connected to each output terminal of the shift circuit in the previous stage of each of shift circuits 13-14 to 13-0. For example, each input terminal of shift circuit 13-14 is connected to each output terminal of shift circuit 13-15, which is the shift circuit in the previous stage of shift circuit 13-14.

[0056] However, regarding shift circuit 13-0, there is a further difference from shift circuit 13-15. That is, as described above, each output terminal of shift circuit 13-0 is connected to each input terminal of read interface 12.

[0057] In addition, although Figure 2 shows the members constituting each of shift circuits 13-0 to 13-14, the description of each of these members is omitted. Also, each member with the description omitted corresponds to the member of shift circuit 13-15 in which the number following the alphabet of the symbol attached to each is read as "15". Further, by such a reading substitution, when understanding the members of shift circuits 13-0 to 13-14, the above description regarding the members of shift circuit 13-15 can be easily referred to. For example, in the case of a member with the symbol B14, by reading "14" following the alphabet "B" as "15", it is understood that the member is a buffer corresponding to buffer B15 of shift circuit 13-15.

[0058] Also, when collectively referring to the members constituting shift circuit 13, the alphabets attached to each member shall be used. For example, when collectively referring to gates G0, G1, G14, and G15 of shift circuit 13, they are collectively referred to as gate G.

[0059] (Operation) Hereinafter, the operation of control device 103 will be described. Control device 103 has a write operation and a read operation. First, the write operation will be described, and then the read operation will be described.

[0060] 1. Write operation While referring to FIG. 2, the writing operation of the control device 103 will be described. Hereinafter, the case where a spike train represented by "0000111101000001" (hereinafter referred to as "spike train A") is input to the writing interface 11 will be described as an example. The spike train A is a 16-bit spike train. Also, the spike train A is the calculation result of the arithmetic unit 101. Further, at a predetermined time interval, the level of the first digit (=1), the level of the second digit (=0), the level of the third digit (=0), ···, the level of the 15th digit (=0), and the level of the 16th digit (=0) of the spike train A are sequentially input to the writing interface 11.

[0061] (1) Input of the level of the first digit (=1) of the spike train A When the level of the first digit (=1) of the spike train A is input to the writing interface 11, the writing interface 11 outputs a BLi signal of "1" level and an XBLi signal of "0" level from each of a set of output terminals.

[0062] Next, when the clock signal CK rises, the first switching element g15-1 and the second switching element g15-2 of the gate G15 of the shift circuits 13-15 become conductive. When the first switching element g15-1 and the second switching element g15-2 become conductive, the "1" level of the BLi signal and the "0" level of the XBLi signal are input to the latch L15. The latch L15 holds the "1" level and the "0" level. The clock signal CK falls again, and the first switching element g15-1 and the second switching element g15-2 become non-conductive again.

[0063] Note that the clock signal CK is usually stable in the falling state. The clock signal CK instantaneously rises in synchronization with the timing at which the level of each digit of the spike train A is input to the write interface 11, and then falls again. Also, the clock signal CK may usually be stable in the rising state and instantaneously fall in synchronization with the timing at which the level of each digit of the spike train A is input to the write interface 11, and then fall again. However, in this case, the first switching element g15-1 and the second switching element g15-2 become conductive when the clock signal CK falls and become non-conductive again when the clock signal CK rises.

[0064] Also, when the clock signal CK rises, in each of the shift circuits 13-0 to 13-14, the first switching elements g0-1 to g14-1 and the second switching elements g0-2 to g14-2 of each gate 0 to 14 also become conductive. Also, when the clock signal CK falls, in each of the shift circuits 13-0 to 13-14, the first switching elements g0-1 to g14-1 and the second switching elements g0-2 to g14-2 of each gate G0 to G14 also become non-conductive.

[0065] The first buffer b15-1 of the buffer B15 outputs the "1" level held in the latch L15 to one output terminal of the shift circuit 13-15. The second buffer b15-2 of the buffer B15 outputs the "0" level held in the latch L15 to the other output terminal of the shift circuit 13-15. Since the first switching element g14-1 and the second switching element g14-2 of the gate G14 of the shift circuit 13-14 are in the non-conductive state, each level output to each of the pair of output terminals of the shift circuit 13-15 is not input to the latch L14 of the shift circuit 13-14.

[0066] Thus, when the level of the first digit (=1) of the spike train A is input to the writing interface 11, the latch L15 of the shift circuits 13 - 15 holds the "1" level and the "0" level. Note that the level held in the latch L15 is originally the "1" level which is the level of the first digit (=1) of the spike train A. The "0" level is the complementary level of the "1" level. Hereinafter, for the sake of simplicity of explanation, when explaining the level held in the latch L15, only the level of each digit of the spike train A will be used for explanation, and the explanation of its complementary level may be omitted in some cases. The same applies to the latches L0 to L14.

[0067] (2) Input of the level of the second digit (=0) of the spike train A Next, when the level of the second digit (=0) of the spike train A is input to the writing interface 11, the writing interface 11 outputs a BLi signal of "0" level and an XBLi signal of "1" level from each of a set of output terminals.

[0068] Next, when the clock signal CK rises, in the shift circuits 13 - 15, the first switching element g15 - 1 and the second switching element g15 - 2 of the gate G15 of the shift circuits 13 - 15 become conductive. When the first switching element g15 - 1 and the second switching element g15 - 2 become conductive, the "0" level of the BLi signal and the "1" level of the XBLi signal are input to the latch L15. The latch L15 holds the "0" level and the "1" level.

[0069] Also, in the shift circuits 13 - 14, the first switching element g14 - 1 and the second switching element g14 - 2 of the gate G14 of the shift circuits 13 - 14 become conductive. When the first switching element g14 - 1 and the second switching element g14 - 2 become conductive, the "1" level and the "0" level output from a pair of output terminals of the shift circuits 13 - 15 are input to the latch L14. The latch L14 holds the "1" level and the "0" level.

[0070] The clock signal CK falls again, and the first switching element g15-1 and the second switching element g15-2 of the gate G15 of the shift circuits 13-15, and the first switching element g14-1 and the second switching element g14-2 of the gate G14 of the shift circuit 13-14 become non-conductive again.

[0071] In this way, when the level of the second digit (=0) of the spike train A is input to the write interface 11, the "0" level, that is, the level of the second digit of the spike train A, is held in the latch L15 of the shift circuit 13-15. Also, the "1" level, that is, the level of the first digit of the spike train A, is held in the latch L14 of the shift circuit 13-14.

[0072] The operation of the control device 103 until the level of the second digit (=0) of the spike train A is input to the write interface 11 has been described above. The operation of the control device 103 when the levels of the third and subsequent digits of the spike train A are input to the write interface 11 is executed in the same manner.

[0073] For example, when the level of the third digit of the spike train A is input to the write interface 11, the level of the third digit of the spike train A is held in the latch L15 of the shift circuit 13-15, the level of the second digit of the spike train A is held in the latch L14 of the shift circuit 13-14, and the level of the first digit of the spike train A is held in the latch L13 of the shift circuit 13-13, respectively.

[0074] Similarly, when the level of the (N)th digit (N: any natural number from 4 to 15) of the spike train A is input to the write interface 11, the level of the (N)th digit of the spike train A is held in the latch L15 of the shift circuit 13-15, the level of the (N-1)th digit of the spike train A is held in the latch L14 of the shift circuit 13-14, the level of the (N-2)th digit of the spike train A is held in the latch L13 of the shift circuit 13-13, ···, the level of the second digit of the spike train A is held in the latch L(N-1) of the shift circuit 13-(N-1), and the level of the first digit of the spike train A is held in the latch L(N) of the shift circuit 13-(N), respectively.

[0075] In this way, when the levels of each digit of the spike train A are sequentially input to the writing interface 11, until all the inputs of the levels of each digit of the spike train A are completed, the level of the 16th digit of the spike train A is stored in the latch L15 of the shift circuits 13 - 15, the level of the 15th digit of the spike train A is stored in the latch L14 of the shift circuits 13 - 14, ···, the level of the 2nd digit of the spike train A is stored in the latch L1 of the shift circuits 13 - 1, and the level of the 1st digit of the spike train A is stored in the latch L0 of the shift circuits 13 - 0, respectively. That is to say, the control device 103 has stored all the levels of each digit of the spike train A.

[0076] When the control device 103 has stored all the levels of each digit of the spike train A, next, the control device 103 stores the levels of each digit of the spike train A in each memory cell selected from the memory cell array 51 of the storage device 102, respectively. Here, the case where the levels of each digit of the spike train A are stored in the memory cells c1 - 0 to c1 - 15 in the memory cell array 51 will be described as an example.

[0077] Here, the frequencies of the clock signal CK and the clock signal CK2 can be determined as follows, for example. Here, the configurations of the control device 103 and the storage device 102 shown in FIG. 2 will be described as an example.

[0078] In the example of FIG. 2, the control device 103 includes 16 shift circuits 13. Therefore, in order to store levels in all the latches of each shift circuit 13, each first switching element g0 - 1 to g15 - 1 and each second switching element g0 - 2 to g15 - 2 of each gate G0 to G15 need to be in the conductive state 16 times. That is to say, the clock signal CK will rise 16 times.

[0079] On the other hand, after levels are stored in all the latches of each shift circuit 13 of the control device 103, the control device 103 executes a reading operation described later. At this time, for the storage device 102, the reading operation will be executed at the rising timing of the clock signal CK2.

[0080] That is, in the example of FIG. 2, the clock signal CK2 rises once every 16 rises of the clock signal CK. Therefore, the frequency of the clock signal CK needs to be 16 times that of the clock signal CK2. Needless to say, the present disclosure is not limited to the ratio of the frequency of the clock signal CK to the frequency of the clock signal CK2 being "16 times". The above ratio is changed according to the number of shift circuits 13 of the control device 103. Also, the above ratio is changed depending on the hardware performance of each of the control device 103 and the storage device 102.

[0081] The address generation circuit 53 of the storage device 102 sets the row address WL1 to the "1" level. On the other hand, the address generation circuit 53 sets the row addresses WL0 and WL2 to the "0" level.

[0082] Here, first, an explanation will be given of storing the "0" level held in the latch L15 of the shift circuits 13-15 of the control device 103, that is, the 16th digit level of the spike train A, in the memory cell c1-15 of the memory cell array 51 of the storage device 102. As described above, the latch L15 holds the "1" level, which is the complementary level of the "0" level, together with the "0" level of the 16th digit of the spike train A.

[0083] The "0" level held in the latch L15 is input to the bit line BL15 via the write circuit W15. Also, the "1" level held in the latch L15 is input to the bit line XBL15 via the write circuit W15. Here, since the row address WL1 is at the "1" level and the row addresses WL0 and WL2 are at the "0" level, the "0" level is input from the bit line BL15 only to the memory cell c1-15 among the memory cells c0-15 to c2-15. Also, the "1" level is input from the bit line XBL15 only to the memory cell c1-15. As a result, the "0" level and the "1" level held in the latch L15, that is, the 16th digit level of the spike train A, are stored in the memory cell c1-15.

[0084] Similarly, the 15th level of the spike train A held by the latch L14 is stored in the memory cell c1-14, ···, the 2nd level of the spike train A held by the latch L1 is stored in the memory cell c1-1, and the 1st level of the spike train A held by the latch L0 is stored in the memory cell c1-0.

[0085] As described above, according to the control device 103, the spike train input to the writing interface 11 can be directly written to the storage device 102.

[0086] 2. Read operation Next, the read operation of the control device 103 will be described. Briefly speaking, the read operation of the control device 103 is to perform the reverse process of the processing performed by the control device 103 in the write operation.

[0087] That is, when the control device 103 performs a write operation, the control device 103 holds the level of each digit of the spike train sequentially input to the writing interface 11 in each shift circuit 13. Then, the control device 103 stores the levels held in each shift circuit 13 in the respective memory cells c selected from the memory cell array 51.

[0088] In contrast, when the control device 103 performs a read operation, the control device 103 reads out the level stored in each memory cell c from each memory cell c selected from the memory cell array 51 and holds it in each shift circuit 13. Then, the control device 103 sequentially outputs the levels held in each shift circuit 13 from the reading interface 12.

[0089] Hereinafter, the description will focus on the differences between the read operation and the write operation.

[0090] The control device 103 reads out the levels stored in each memory cell selected from the memory cell array 51 of the storage device 102. Here, as an example, it is described that the levels stored in the memory cells c2-0 to c2-15 in the memory cell array 51 are read out respectively. Also, it is assumed that the levels stored in the memory cells c2-0 to c2-15 in the memory cell array 51 are the above-mentioned spike train A "0000111101000001". Note that the first digit level of the spike train A is stored in the memory cell c2-0, the second digit level is stored in the memory cell c2-1, ···, the 15th digit level is stored in the memory cell c2-14, and the 16th digit level is stored in the memory cell c2-15.

[0091] First, the address generation circuit 53 of the storage device 102 sets the row address WL2 to the "1" level. On the other hand, the address generation circuit 53 sets the row addresses WL0 and WL1 to the "0" level.

[0092] Here, first, it is explained that the level stored in the memory cell c2-15 of the memory cell array 51 of the storage device 102 is read out, and the read level is held in the latch L15 of the shift circuit 13-15 of the control device 103. Note that in addition to the 16th digit "0" level of the spike train A, the "1" level, which is the complementary level of the "0" level, is also stored in the memory cell c2-15.

[0093] The "0" level stored in memory cell c2-15 is input to latch L15 of shift circuit 15 via read circuit R15. Also, the "1" level stored in memory cell c2-15 is input to latch L15 of shift circuit 15 via read circuit R15. Here, since row address WL2 is at the "1" level and row addresses WL1 and WL1 are at the "0" level, a "0" level is input to read circuit W15 via bit line BL15 only from memory cell c2-15 among memory cells c0-15 to c2-15. Also, a "1" level is input to read circuit W15 via bit line XBL15 only from memory cell c2-15. As a result, the "0" level and the "1" level stored in memory cell c2-15, that is, the 16th digit level of spike train A, are held in latch L15.

[0094] Similarly, the 15th digit level of spike train A stored in memory cell c2-14 is held in latch L14 of shift circuit 13-14, ···, the 2nd digit level of spike train A stored in memory cell c2-1 is held in latch L1 of shift circuit 13-1, and the 1st digit level of spike train A stored in memory cell c2-0 is held in latch L0 of shift circuit 13-0. That is, control device 103 has held all the digit levels of spike train A.

[0095] When control device 103 has held all the digit levels of spike train A, next, control device 103 sequentially moves the levels held in latches L of each shift circuit 13 to the latches L of each shift circuit 13 located on the read interface 12 side, similar to the case of the above-described write operation.

[0096] The latch L0 of the shift circuit 13-0 sequentially holds the levels of the second digit, third digit, ···, 15th digit, and 16th digit of the spike train A. A pair of output terminals of the shift circuit 13-0 are connected to a pair of input terminals of the readout interface 12. The levels of each digit of the spike train A sequentially held in the latch L0 of the shift circuit 13-0 are respectively input to the pair of input terminals of the readout interface 12 as the levels of the BLo signal and the XBLo signal. The readout interface 12 sequentially outputs the levels of each digit of the spike train A sequentially input to the pair of input terminals from the output terminals. That is, the control device 103 outputs the spike train A from the output terminals of the readout interface 12.

[0097] As described above, according to the control device 103, the spike train stored in the storage device 102 can be directly read from the readout interface 12.

[0098] <Effect of Embodiment 1> According to the control device 103, a spike train can be directly written into the storage device and directly read from the storage device. That is, according to the control device 103, a control device with a novel configuration can be realized.

[0099] Further, according to the control device 103, in a device that realizes the SC calculation mechanism, reduction of hardware and acceleration of data processing can be achieved.

[0100] 〔Embodiment 2〕 Embodiment 2 of the present disclosure will be described below. For the sake of convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals, and the description thereof will not be repeated.

[0101] Embodiment 2 is an embodiment related to the writing operation of the control device 103 when a spike train having a number of digits exceeding the total number of shift circuits 13 is input to the writing interface 11. Further, Embodiment 2 is an embodiment related to the reading operation of the control device 103 when a spike train having a number of digits exceeding the total number of shift circuits 13 is output from the reading interface 12.

[0102] First, the writing operation of the control device 103 according to Embodiment 2 will be described with reference to FIG. 1. In Embodiment 2 as well, as shown in FIG. 1, the total number of shift circuits 13 is 16. Also, it is assumed that the number of digits of the spike train input to the writing interface 11 is 18, which exceeds the total number of 16 of the shift circuits 13.

[0103] To the writing interface 11, signals of the levels of each digit are sequentially input in order from the first digit of the spike train at a predetermined time interval. And when the same number of levels as the total number of shift circuits 13 are input to the writing interface 11, that is, when the signal of the level of the 16th digit of the spike train is input, the control device 103 temporarily stops the input of the spike train to the writing interface 11.

[0104] Here, at the time of this stop, the spikes that have not yet been input to the writing interface 11 are the 17th and 18th digits of the spike train. Also, the control device 103 holds the levels of each digit from the first digit to the 16th digit of the spike train.

[0105] Also, the control device 103 may detect the point in time when the same number of levels as the total number of shift circuits 13 are input by counting the number of clock signals CK. If the total number of shift circuits 13 is 16, the number of clocks required until 16 spikes are input is 16.

[0106] After the control device 103 stops the input of the spike train to the writing interface 11, it stores the levels of each digit from the 1st digit to the 16th digit of the spike train in each memory cell c selected from the memory cell array 51 of the storage device 102, respectively. Thereby, the control device 103 is considered to have written the levels of each digit from the 1st digit to the 16th digit of the spike train into the storage device 102.

[0107] After the control device 103 writes the levels of each digit from the 1st digit to the 16th digit of the spike train into the storage device 102, it starts the input of the spike train to the writing interface 11 again. Signals of the levels of each digit of the 17th digit and the 18th digit are sequentially input to the writing interface 11 in order from the 17th digit of the spike train at a predetermined time interval.

[0108] The control device 103 holds the levels of each digit of the 17th digit and the 18th digit of the spike train. Then, the control device 103 stores the levels of each digit of the 17th digit and the 18th digit of the spike train in each memory cell c selected from the memory cell array 51 of the storage device 102, respectively. Thereby, the control device 103 is considered to have written the levels of each digit from the 1st digit to the 18th digit of the spike train into the storage device 102.

[0109] Note that the levels of each digit from the 1st digit to the 16th digit of the spike train are stored in each memory cell c connected to the same row address. Also, the levels of each digit of the 17th digit and the 18th digit of the spike train are stored in each memory cell c connected to the same row address. However, the former row address and the latter row address are different. For example, the levels of each digit from the 1st digit to the 16th digit of the spike train are stored in each of the memory cells c0-0 to c0-15 connected to the row address WL0. Also, the levels of each digit of the 17th digit and the 18th digit of the spike train are stored in each of the memory cells c1-14 to c1-15 connected to the row address WL1. Also, similar to the control device 103, the address generation circuit 53 of the storage device 102 may detect the time when the same number of levels as the total number of shift circuits 13 are input by counting the number of clock signals CK. Thereby, as described above, the address generation circuit 53 can change the row address to be selected from the row address WL0 to the row address WL1.

[0110] Next, the read operation of the control device 103 according to the second embodiment will be described with reference to FIG. 1. Note that also in the second embodiment, as shown in FIG. 1, the total number of shift circuits 13 is 16. Also, it is assumed that the number of digits of the spike train output from the read interface 12 exceeds 16, which is the total number of shift circuits 13, and is 18.

[0111] The control device 103 reads the levels stored in each memory cell c selected from the memory cell array 51 of the storage device 102. The control device 103 holds all the read levels. Each read level becomes the level of each digit from the 1st digit to the 16th digit of the spike train output from the read interface 12.

[0112] The control device 103 sequentially outputs the held levels from the read interface 12. Thereby, the control device 103 has read the levels of each digit from the 1st digit to the 16th digit of the spike train from the storage device 102.

[0113] Subsequently, the control device 103 reads out the levels stored in each memory cell c selected from the memory cell array 51 of the storage device 102. The control device 103 holds all the read levels. Each read level is the level of each digit of the 17th and 18th digits of the spike train output from the read interface 12.

[0114] The control device 103 sequentially outputs the held levels from the read interface 12. As a result, the control device 103 has read out the levels of each digit from the 1st digit to the 18th digit of the spike train from the storage device 102.

[0115] Note that the levels of each digit from the 1st digit to the 16th digit of the spike train are read out from the memory cells c connected to the same row address. Also, the levels of each digit of the 17th and 18th digits of the spike train are read out from the memory cells c connected to the same row address. However, the former row address and the latter row address are different. For example, the levels of each digit from the 1st digit to the 16th digit of the spike train are read out from each of the memory cells c0-0 to c0-15 connected to the row address WL0. Also, the levels of each digit of the 17th and 18th digits of the spike train are read out from each of the memory cells c1-14 to c1-15 connected to the row address WL1.

[0116] As described above, according to the control device 103, even when the number of digits of the spike train written into the storage device 102 exceeds the total number of shift circuits 13, the spike train can be written into the storage device 102 as it is.

[0117] Also, according to the control device 103, even when the number of digits of the spike train read out from the storage device 102 exceeds the total number of shift circuits 13, the spike train can be read out from the storage device 102 as it is.

[0118] In addition, in the second embodiment, regarding both the writing operation and the reading operation of the control device 103, the case where the number of digits of the spike train is 18 has been described as an example. However, the second embodiment is not limited to the case where the number of digits of the spike train is 18.

[0119] 〔Embodiment 3〕 Embodiment 3 of the present disclosure will be described below. For convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and their descriptions will not be repeated.

[0120] FIG. 3 is a diagram showing the circuit configuration of the control device 103A according to Embodiment 3 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 3, descriptions of members not related to the control device 103A are omitted.

[0121] As shown in FIG. 3, the difference between the control device 103A and the control device 103 of the first embodiment is that the control device 103A further includes a counter 14 and selectors 15-15_14 and 15-1_0. Hereinafter, similar to the first embodiment, the case where the spike train A represented by "0000111101000001" is input to the writing interface 11 will be described as an example.

[0122] At the writing interface 11, the levels of the 1st digit (=1), 2nd digit (=0), 3rd digit (=0), ···, 15th digit (=0), and 16th digit (=0) of the spike train A are sequentially input at predetermined time intervals.

[0123] If the level of the BLi signal input from the write interface 11 to the latch L15 of the shift circuits 13-15 is at the "1" level, the counter 14 increments by one the count value held in the counter 14. Note that a clock signal CK is input to the counter 14. The "1" level of the BLi signal is input to the latch L15 at the rising timing of the clock signal CK. After the "1" level of the BLi signal is input to the latch L15, the counter 14 increments by one the count value at the next rising timing of the clock signal CK.

[0124] Also, if the level of the signal input from the shift circuit 13-1 to the latch L0 of the shift circuit 13-0 is at the "1" level, the counter 14 decrements by one the count value held in the counter 14. The "1" level is input to the latch L0 of the shift circuit 13-0 from the shift circuit 13-1 at the rising timing of the clock signal CK. After the "1" level is input to the latch L0, the counter 14 decrements by one the count value at the next rising timing of the clock signal CK.

[0125] Also, when the level of the BLi signal input from the write interface 11 to the latch L15 of the shift circuits 13-15 matches the level of the signal input from the shift circuit 13-1 to the latch L0 of the shift circuit 13-0, the counter 14 maintains the count value held in the counter 14.

[0126] More specifically, when the level of the first digit (=1) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuits 13-15, the counter 14 sets the count value to 1. Next, when the level of the second digit (=0) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuits 13-15, the counter 14 maintains the count value. That is, the count value remains 1.

[0127] Similarly, the levels of the 3rd digit (=0) to the 16th digit (=0) of the spike train A are sequentially input from the write interface 11 to the latch L15 of the shift circuits 13-15. Since the number of digits with the "1" level among the 1st digit to the 16th digit of the spike train A is 6, the count value held by the counter 14 becomes 6.

[0128] Among the selectors 15-15_14 and 15-1_0, when the selector 15-15_14 is on, the counter 14 outputs the count value held by the counter 14 to the selector 15-15_14. The selector 15-15_14 outputs the count value input from the counter 14 to the write circuits W14 and W15. Among the selectors 15-15_14 and 15-1_0, when the selector 15-1_0 is on, the counter 14 outputs the count value held by the counter 14 to the selector 15-1_0. The selector 15-1_0 outputs the count value input from the counter 14 to the write circuits W0 and W1.

[0129] The write circuits W14, W15, W0, and W1 store the count value of the counter 14 in the memory cell c connected to each of them. The address generation circuit 53 selects the memory cell c in which the count value is stored using the row addresses WL0 to WL2.

[0130] When the level of the 16th digit (=0) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuits 13-15, the level of the signal input to the latch L0 of the shift circuits 13-1 to 13-0 is the level of the 1st digit (=1) of the spike train A. For this reason, the counter 14 decreases the counter value by one. That is, the count value becomes 5. Similarly, when the levels of the 3rd digit (=0) to the 16th digit (=0) of the spike train A are sequentially input to the latch L0, the counter value of the counter 14 becomes 0 again. That is, if the levels of the 1st digit (=1) to the 16th digit (=0) of the spike train A are sequentially input to the latch L0, the counter value of the counter 14 will finally return to 0.

[0131] Therefore, even when a spike train different from the spike train A (hereinafter referred to as the spike train B) is continuously input from the writing interface 11 after the spike train A is input, the process of once resetting the counter value of the counter 14 before the input of the spike train B starts, in other words, the process of returning the count value to 0 is unnecessary. This is because when the levels of each digit of the spike train B are sequentially input to the latch L15, at the same time, the levels of each digit of the spike train A are sequentially input to the latch L0. Therefore, the counter 14 can count the number of "1" levels of the spike train B input to the latch L15 while subtracting the number of "1" levels of the spike train A input to the latch L0 from the count value.

[0132] As described above, according to the control device 103A, the number of spikes of the spike train written into the storage device 102 can be counted, and only the count value can be written into the storage device 102. Therefore, according to the control device 103A, the amount of data written into the storage device 102 can be compressed compared to the case where the spike train is directly written into the storage device 102.

[0133] 〔Embodiment 4〕 Embodiment 4 of the present disclosure will be described below. For the sake of convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and their descriptions will not be repeated.

[0134] FIG. 4 is a diagram showing the circuit configuration of the control device 103B according to Embodiment 4 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 4, descriptions of members not related to the control device 103B are omitted.

[0135] As shown in FIG. 4, the difference between the control device 103B and the control device 103 of the above Embodiment 1 is that the control device 103B further includes a counter 14, a register 16-15_14 (first register), a register 16-1_0 (second register), a comparator 17-15_14 (first comparator), a comparator 17-1_0 (second comparator), and an AND circuit 18.

[0136] Embodiment 4 is a modification of the above Embodiment 3. The control device 103A according to the above Embodiment 3 is configured to count the number of spikes in the spike train written to the storage device 102 and write only the count value to the storage device 102.

[0137] On the other hand, the control device 103B counts the number of spikes in the spike train input to the writing interface 11, and compares the count value with each of the minimum value and the maximum value previously written to the storage device 102. The control device 103B determines whether or not the count value falls within a predetermined range defined by the minimum value and the maximum value based on the result of the magnitude comparison. Note that the minimum value and the maximum value may be input from the writing interface 11 as a spike train, or may be input from the memory interface 102.

[0138] As shown in FIG. 4, the counter 14 counts the number of spikes in the spike train input to the writing interface 11. The process of the counter 14 counting the number of spikes in the spike train is the same as the process executed by the counter 14 in the above Embodiment 3, and thus the description thereof will not be repeated here.

[0139] The counter 14 outputs the count value to both the comparators 17-15_14 and 17-1_0.

[0140] In FIG. 4, the maximum value is stored in the memory cell c connected to each of the read circuits R14 and R15. The address generation circuit 53 selects the memory cell c in which the maximum value is stored using the row addresses WL0 to WL2. The read circuits R14 and R15 read the maximum value from the memory cell c connected to each of them. The read circuits R14 and R15 output the maximum value read from the memory cell c to the register 16-15_14. The register 16-15_14 holds the maximum value.

[0141] The minimum value is stored in the memory cell c connected to each of the read circuits R0 and R1. The address generation circuit 53 selects the memory cell c in which the minimum value is stored, using the row addresses WL0 to WL2. The read circuits R0 and R1 read the minimum value from the memory cell c connected to each of them. The read circuits R0 and R1 output the minimum value read from the memory cell c to the register 16-1_0. The register 16-1_0 holds the minimum value.

[0142] The value held in the register 16-15_14 and the value held in the register 16-1_0 are a set of values that define a predetermined range, with the value held in the register 16-15_14 being the maximum value and the value held in the register 16-1_0 being the minimum value.

[0143] When a count value is input from the counter 14, the comparator 17-15_14 obtains the maximum value held in the register 16-15_14 from the register 16-15_14. The comparator 17-15_14 compares the count value with the maximum value. If the count value is less than or equal to the maximum value, the comparator 17-15_14 outputs a signal at the "1" level to the AND circuit 18. If the count value is greater than the maximum value, the comparator 17-15_14 outputs a signal at the "0" level to the AND circuit 18.

[0144] When a count value is input from the counter 14, the comparator 17-1_0 obtains the minimum value held in the register 16-1_0 from the register 16-1_0. The comparator 17-1_0 compares the count value with the minimum value. If the count value is greater than or equal to the minimum value, the comparator 17-1_0 outputs a signal at the "1" level to the AND circuit 18. If the count value is less than the minimum value, the comparator 17-1_0 outputs a signal at the "0" level to the AND circuit 18.

[0145] When a signal at the "1" level is input from the comparator 17-15_14 to the AND circuit 18 and a signal at the "1" level is input from the comparator 17-1_0 to the AND circuit 18, the AND circuit 18 outputs a PASS signal at the "1" level. On the other hand, when a signal at the "0" level is input from at least one of the comparator 17-15_14 or the comparator 17-1_0 to the AND circuit 18, the AND circuit 18 outputs a PASS signal at the "0" level.

[0146] That is, if the count value is within a predetermined range defined by the minimum value and the maximum value, a PASS signal at the "1" level is output from the AND circuit 18. On the other hand, if the count value is not within the predetermined range defined by the minimum value and the maximum value, a PASS signal at the "0" level is output from the AND circuit 18.

[0147] Note that the "1" level and the "0" level output from the AND circuit 18 may be input to the write interface 11 of the other control device 103. In this case, each level output from the AND circuit 18 constitutes a spike train input to the write interface 11 of the other control device 103.

[0148] As described above, according to the control device 103B, the number of spikes in the spike train input to the write interface 11 can be counted, and it can be determined whether the count value is within a predetermined range.

[0149] Therefore, a comparison program that was conventionally realized by software can be realized by hardware. Note that the process of determining whether a predetermined value is within a predetermined range based on the result of magnitude comparison as described above is the essence of the discrimination process in AI (Artificial Intelligence).

[0150] 〔Embodiment 5〕 Embodiment 5 of the present disclosure will be described below. For the sake of convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and the description thereof will not be repeated.

[0151] FIG. 5 is a diagram showing the circuit configuration of the control device 103C according to Embodiment 5 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 5, description of members not related to the control device 103C will be omitted.

[0152] As shown in FIG. 5, the difference between the control device 103C and the control device 103 of the above-described Embodiment 1 is that the control device 103C further includes a counter 19-15_14 (first counter), a counter 19-1_0 (second counter), a register 20-15_14, and a register 20-1_0.

[0153] The control device 103C performs multiplication and division. Hereinafter, as in Embodiment 1, a case where a spike train A represented by "0000111101000001" is input to the writing interface 11 will be described as an example.

[0154] To the writing interface 11, the levels of the first digit (=1), the second digit (=0), the third digit (=0), ···, the 15th digit (=0), and the 16th digit (=0) of the spike train A are sequentially input at predetermined time intervals.

[0155] The initial value of the count value of the counter 19-15_14 (hereinafter referred to as the "first initial value") is held in the register 20-15_14. The initial value of the count value of the counter 19-1_0 (hereinafter referred to as the "second initial value") is held in the register 20-1_0.

[0156] The first initial value is stored in the memory cell c connected to each of the read circuits R14 and R15. The address generation circuit 53 selects the memory cell c in which the first initial value is stored, using the row addresses WL0 to WL2. The read circuits R14 and R15 read the first initial value from the memory cell c connected to each of them. The read circuits R14 and R15 output the first initial value read from the memory cell c to the register 20-15_14. The register 20-15_14 holds the first initial value.

[0157] The second initial value is stored in the memory cell c connected to each of the read circuits R0 and R1. The address generation circuit 53 selects the memory cell c in which the second initial value is stored, using the row addresses WL0 to WL2. The read circuits R0 and R1 read the second initial value from the memory cell c connected to each of them. The read circuits R0 and R1 output the second initial value read from the memory cell c to the register 20-1_0. The register 20-1_0 holds the second initial value.

[0158] Returning again to the description of the counters 19-15_14 and 19-1_0.

[0159] The clock signal CK is input to the counter 19-15_14. Each time the clock signal CK rises, the counter 19-15_14 decrements the count value by one. That is, each time the level of each digit of the spike train A is input to the write interface 11, the counter 19-15_14 decrements the count value by one. When the count value of the counter 19-15_14 reaches 0, the counter 19-15_14 rewrites the level of the signal held in the latch L14 of the shift circuit 13-14 to the "1" level at the time of reaching. Specifically, if the level of the signal held in the latch L14 is the "1" level, the counter 19-15_14 maintains the "1" level. On the other hand, if the level of the signal held in the latch L14 is the "0" level, the counter 19-15_14 rewrites the "0" level to the "1" level. When the count value held in the counter 19-15_14 reaches 0, the counter 19-15_14 sets the count value to the above-described first initial value held in the register 20-15_14 again.

[0160] Each time the count value of the counter 19-15_14 reaches 0, the counter 19-15_14 rewrites the level of the signal held in the latch L14 to the "1" level. Therefore, it means that the multiplication process of multiplying the spike train A corresponding to the multiplicand by the first initial value corresponding to the multiplier has been executed.

[0161] A clock signal CK is input to the counter 19-1_0. Each time the clock signal CK rises, the counter 19-1_0 decrements its count value by one. That is, each time the level of each digit of the spike train A is input to the writing interface 11, the counter 19-1_0 decrements its count value by one. When the count value of the counter 19-1_0 reaches 0, the counter 19-1_0 rewrites the level of the signal held in the latch L0 of the shift circuit 13-0 to the "0" level at the time of reaching. Specifically, if the level of the signal held in the latch L0 is the "0" level, the counter 19-1_0 maintains the "0" level. On the other hand, if the level of the signal held in the latch L14 is the "1" level, the counter 19-1_0 rewrites the "1" level to the "0" level. Note that when the count value held in the counter 19-1_0 reaches 0, the counter 19-1_0 sets the count value to the second initial value again.

[0162] Each time the count value of the counter 19-1_0 reaches 0, the counter 19-1_0 rewrites the level of the signal held in the latch L14 to the "0" level. Therefore, it means that a division process of dividing the second initial value corresponding to the divisor by the spike train A corresponding to the dividend has been executed.

[0163] As described above, according to the control device 103C, multiplication and division can be performed.

[0164] [Embodiment 6] Embodiment 6 of the present disclosure will be described below. For the sake of convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and the description thereof will not be repeated.

[0165] As shown in FIG. 6, the difference between Embodiment 6 of the present disclosure and the above Embodiment 1 is that the control device 103 performs a writing operation and a reading operation on the storage device 102A instead of the storage device 102.

[0166] The memory device 102A has a configuration in which, in the memory device 102, the memory cells c0-0 to c0-15 connected to the row address WL0 are respectively replaced with the memory cells D0-0 to D0-15. Similarly, the memory cells c1-0 to c1-15 connected to the row address WL1 and the memory cells c2-0 to c2-15 connected to the row address WL2 are also replaced with memory cells having the same configuration as the memory cells D0-0 to D0-15.

[0167] The memory cells D0-0 to D0-15 each have the same configuration. Here, the configuration of the memory cell D0-15 will be described. The memory cell D0-15 is composed of a first cell D0-15-1 and a second cell D0-15-2. The first cell D0-15-1 has the same configuration as the memory cell c0-15 of the memory device 102. The second cell D0-15-2 is a known associative memory cell.

[0168] When all the values stored in the first cells D0-0-1 to D0-15-1 of the memory cells D0-0 to D0-15 connected to the match line ML0 match the values input from the write circuit W, the control device 103 holds the match line ML0 precharged to the "1" level at the "1" level. On the other hand, when at least one of the values stored in the first cells D0-0-1 to D0-15-1 of the memory cells D0-0 to D0-15 is different from the value input from the write circuit W, the control device 103 discharges the match line ML0 to the "0" level.

[0169] Note that the "1" level and "0" level output from the match line ML0 may be input to the write interface 11 of another control device 103. In this case, each level output from the match line ML0 constitutes a spike train input to the write interface 11 of another control device 103.

[0170] As described above, according to the sixth embodiment, when the control device 103 performs a write operation, it is possible to compare the value stored in the memory cell array 51A of the memory device 102A with the value input from the write circuit W.

[0171] 〔Embodiment 7〕 Embodiment 7 of the present disclosure will be described below. For convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and the description thereof will not be repeated.

[0172] FIG. 7 is a diagram showing a schematic configuration of an apparatus 200 that realizes the SC calculation mechanism according to Embodiment 7 of the present disclosure. As shown in FIG. 7, the apparatus 200 includes a configuration in which two sets of the control device 103 and the storage device 102 of the above Embodiment 1 are arranged side by side.

[0173] According to the apparatus 200, each control device 103 can simultaneously execute the writing operation and the reading operation of the above Embodiment 1.

[0174] In the apparatus 200, instead of the control device 103 and the storage device 102 of the above Embodiment 1, the control device 103 and the storage device 102 of the above Embodiment 2, the control device 103A and the storage device 102 of the above Embodiment 3, the control device 103B and the storage device 102 of the above Embodiment 4, the control device 103C and the storage device 102 of the above Embodiment 5, and the control device 103 and the storage device 102A of the above Embodiment 5 may be provided with a configuration in which two sets of any of them are arranged side by side.

[0175] Also, the two sets constituting the apparatus 200 may be different from each other. For example, the first set may be the control device 103 and the storage device 102 of the above Embodiment 1, and the second set may be the control device 103A and the storage device 102 of the above Embodiment 3. Also, the number of sets of control devices constituting the apparatus 200 is not limited to two sets.

[0176] 〔Embodiment 8〕 Embodiment 8 of the present disclosure will be described below. For convenience of explanation, members having the same functions as those described in the above embodiments are denoted by the same reference numerals, and the description thereof will not be repeated.

[0177] FIG. 8 is a diagram for explaining the configuration of the control device according to Embodiment 8 of the present disclosure. As shown in FIG. 8, the control device according to Embodiment 8 has a configuration in which, in the control device 103 of Embodiment 1, the latch L15 of the shift circuits 13-15 is replaced with a latch LR15, and the gate G14 of the shift circuits 13-14 is replaced with a gate GR14.

[0178] The latch LR15 is composed of an inductor LR15-1 and a capacitor LR15-2. The gate GR14 is a delay element.

[0179] Note that, in the control device according to Embodiment 8, the gates G except for the gate G15 are replaced with the gate GR14 or a gate having the same configuration as the gate GR14, and the latch L is replaced with the latch LR15 or a latch having the same configuration as the latch LR15.

[0180] The control device of Embodiment 8 can also perform the writing operation and the reading operation of the control device 103 of Embodiment 1.

[0181] 〔Others〕 The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure.

Explanation of Reference Numerals

[0182] Device for realizing 100 SC computing mechanism, 101 arithmetic unit, 102 storage device, 103 control device, 11 writing interface, 12 reading interface, 13-0, 13-1, 13-14, 13-15 shift circuits, 14, 19-15_14, 19-1_0 counters, 51, 51A memory cell arrays, 15-1_0, 15-15_14 selectors, 16-15_14, 16-1_0, 20-15_14, 20-1_0 registers, 17-15_14, 17-1_0 comparators, 18 AND circuits, 52 peripheral circuits, 53 address generation circuit, 54 memory interface, G0, G1, G14, G15 gates, L0, L1, L14, L15 latches, B0, B1, B14, B15 buffers

Claims

1. A control device for a memory included in an apparatus that realizes a stochastic computing mechanism, comprising: A write interface to which a spike train is input; A read interface from which a spike train is output; A plurality of shift circuits that hold the level of the signal input to each; And; The plurality of shift circuits are connected in series between the write interface and the read interface; Between two adjacent shift circuits, the shift circuit located on the write interface side moves the level held by the shift circuit to the shift circuit located on the read interface side; A plurality of memory cells capable of writing and reading the level held by each shift circuit are connected to each of the shift circuits; (i) When a spike train is input from the write interface to the control device, Each shift circuit: Moves the level of each digit of the spike train sequentially input from the write interface from the write interface side to the read interface side between two adjacent shift circuits; After the level of each digit is held by the corresponding shift circuit, the level held by each shift circuit is written to the memory cell connected to each shift circuit; (ii) When the control device outputs a spike train from the read interface, Each shift circuit: Reads the level of each digit from the memory cell connected to each shift circuit; After the level of each digit is held by the corresponding shift circuit, the level held by each shift circuit is moved between two adjacent shift circuits from the write interface side to the read interface side. A control device.

2. (i) When a spike train having a number of digits exceeding the total number of the plurality of shift circuits is input from the write interface to the control device, The control device temporarily stops the input of the spike train to the write interface when the same number of levels as the total number of the plurality of shift circuits are input to the write interface; Each of the shift circuits writes the level held by each of the shift circuits to the memory cell connected to each of the shift circuits. The control device starts inputting the levels of the remaining digits of the spike train to the writing interface again. (ii) When the control device outputs a spike train having a number of digits exceeding the total number of the plurality of shift circuits from the reading interface, Each of the shift circuits reads the level of each digit from the memory cell connected to each of the shift circuits. When the control device outputs the same number of levels as the total number of the plurality of shift circuits from the reading interface, the control device temporarily stops outputting the spike train from the reading interface. Each of the shift circuits reads the levels of the remaining digits of the spike train from the memory cell connected to each of the shift circuits again. The control device according to claim 1.

3. Further comprising a counter, The counter, When the level held by the shift circuit connected to the writing interface matches the level held by the shift circuit connected to the reading interface, the counter value held by the counter is maintained. When only the level held by the shift circuit connected to the writing interface is at the "1" level, the counter value is incremented by one. When only the level held by the shift circuit connected to the reading interface is at the "1" level, the counter value is decremented by one. The counter value is written to the memory cell connected to each of the shift circuits. The control device according to claim 1 or 2.

4. A first register that holds the maximum value, A second register that holds the minimum value, A first comparator that compares the count value held by the counter with the maximum value held by the first register, A second comparator that compares the count value held by the counter with the minimum value held by the second register, An AND circuit connected to the first comparator and the second comparator, Comprising, The first comparator outputs a signal at the "1" level to the AND circuit when the count value held by the counter is less than or equal to the maximum value held by the first register. The control device according to claim 3, wherein the second comparator outputs a signal at a "1" level to the AND circuit when the count value held in the counter is greater than or equal to the minimum value held in the second register.

5. A first counter, A second counter, A first register that holds a first initial value which is an initial value of a count value held in the first counter, A second register that holds a second initial value which is an initial value of a count value held in the second counter further comprising: (i) Each time a level of each digit of the spike train is input to the writing interface, the first counter decrements the count value held in the first counter by one. When the count value of the first counter reaches 0, at the time of reaching, the first counter rewrites the level held in the shift circuit connected to the writing interface to the "1" level, again sets the count value to the first initial value, (ii) Each time a level of each digit of the spike train is input to the writing interface, the second counter decrements the count value held in the second counter by one. When the count value of the second counter reaches 0, at the time of reaching, the second counter rewrites the level held in the shift circuit connected to the reading interface to the "0" level, again sets the count value to the second initial value, the control device according to any one of claims 1 to 4.

6. A plurality of associative memory cells are connected to each of the shift circuits, After the level of each digit is held in the corresponding shift circuit, When all of the levels held in each shift circuit match the levels held in the memory cells connected to each shift circuit, the match line connected to each associative memory cell outputs a "1" level. When at least one of the levels held in each shift circuit is different from the level held in the memory cells connected to each shift circuit, the match line outputs a "0" level, the control device according to any one of claims 1 to 5.

7. The control device according to any one of claims 1 to 6, wherein a plurality of the control devices are arranged in parallel.

8. Each of the shift circuits includes a gate, a latch, and a buffer, the control device according to any one of claims 1 to 7.

9. Each of the shift circuits includes a capacitor, an inductor, and a delay element, and the control device according to any one of claims 1 to 7.

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