Structure and method for a bridge chip assembly having a capillary underfill

Abstract

A method for fabricating a bridge chip assembly for interconnecting two or more IC dies is provided. Each of the IC dies has a first region including first connections with a first pitch and a second region including second connections or connection pads with a second pitch, the first pitch being greater than the second pitch. The method includes applying a non-conductive underfill film to an upper surface of at least the second region of each of the IC dies; bonding the second connections / connection pads of a first IC die to corresponding first connection pads / connections of a bridge chip; and bonding the second connections / connection pads of a second IC die to the bridge chip. The bridge chip assembly includes the bridge chip bonded to the first and second IC dies, and the non-conductive underfill film disposed between the bridge chip and the IC dies.

Description

Background Art

[0001] The present invention generally relates to the technologies of electricity, electronics, and computers, and more particularly, to an integrated circuit (IC) packaging structure and a method of manufacturing such a structure.

[0002] Regarding advanced IC packaging such as the introduction of silicon interposers or the shift to modularization through multi-chip module designs, the number of technology options has been continuously increasing. Silicon interposers are expensive and require a large silicon footprint, thus posing cost issues, and multi-chip module designs using conventional packaging on organic substrates are limited by input / output (I / O) bandwidth and power efficiency.

[0003] Solutions that have been attempted to address the problems presented with silicon interposers and chip modularization are the industry's introduction of intermediate silicon dies (so-called silicon bridges) that connect two logic chips (e.g., an accelerator chip and a broadband memory chip). These intermediate silicon dies are used only within a limited range and do not use the same footprint as the entire silicon interposer. One silicon bridge technology available from Intel Corporation is called the Embedded Multi-Die Interconnect Bridge (EMIB), which uses a small silicon piece together with a routing layer embedded in a common substrate that connects one chip to another within an IC package. However, the use of an embedded bridge structure can be costly and increase the length of the connection paths within the IC package.

[0004] In a conventional IC packaging method system, thermocompression bonding (TCB) of copper pillar flip chips using an underfill pre-coated with non-conductive paste (NCP) is one of the solutions for joining thin fine pitch flip chip devices to an organic substrate having a die thickness exceeding about 60 μm. However, this joining process involves spreading and curing the NCP, along with the processes of solder wetting and joint formation. Among several problems, some extremely important failure modes, such as confinement of the NCP filler, NCP voiding problems, cracking, and solder wetting failure, can occur if the process parameters and joining profile are not carefully optimized.

Summary of the Invention

[0005] As will become apparent in one or more of its embodiments, aspects of the present invention provide a bridge chip assembly having a non-conductive film underfill for interconnecting two or more integrated circuit (IC) dies, and a method of manufacturing the bridge chip assembly.

[0006] According to one embodiment of the present invention, there is provided a method of manufacturing a bridge chip assembly having a non-conductive underfill for interconnecting two or more IC dies. Each of the IC dies has a first region including a first connection portion having a first pitch associated therewith, and also has a second region including a second connection portion or connection pad having a second pitch associated therewith, and the first pitch is larger than the second pitch. The method includes attaching a non-conductive underfill film to at least the upper surface of the second region of each of the IC dies; bonding a first IC die among the IC dies to the bridge chip using the second connection portion or connection pad of itself, the bridge chip including at least a first connection pad or connection portion having the second pitch associated therewith, and the first connection pad or connection portion of the bridge chip being aligned with the corresponding second connection portion or connection pad of the first IC die among the IC dies; and bonding a second IC die among the IC dies to the bridge chip using the second connection portion or connection pad of itself, the bridge chip including a second connection pad or connection portion having the second pitch associated therewith, and the second connection pad or connection portion of the bridge chip being aligned with the corresponding second connection portion or connection pad of the second IC die among the IC dies. The bridge chip assembly includes the bridge chip bonded to at least the first and second IC dies, and the non-conductive underfill film disposed between the bridge chip and the first and second IC dies.

[0007] According to another embodiment of the present invention, a bridge chip assembly structure comprises at least first and second IC dies. Each of the IC dies has a first pitch associated therewith, and has a first plurality of connections formed on its upper surface, the first plurality of connections including a material having a first melting point and being adapted to bond the bridge chip assembly structure to an organic substrate. The bridge chip assembly structure further comprises a bridge chip, the bridge chip having a second pitch associated therewith and having a second plurality of connections formed on its upper surface, the first pitch being greater than the second pitch. The second plurality of connections are bonded to corresponding connection pads formed on the upper surfaces of the respective IC dies, the second plurality of connections including a material having a second melting point, the first and second melting points being different.

[0008] According to another embodiment of the present invention, a bridge chip assembly structure comprises at least first and second IC dies. Each of the IC dies has a first pitch associated therewith, and has a first plurality of connections formed on its upper surface, the first plurality of connections being configured to bond the bridge chip assembly structure to an organic substrate. The bridge chip assembly structure further comprises a bridge chip, the bridge chip having a second pitch associated therewith and having a second plurality of connections formed on its upper surface, the first pitch being greater than the second pitch. The second plurality of connections are bonded to corresponding connection pads formed on the upper surfaces of the respective IC dies. The bridge chip is formed through itself and has an opening configured to carry an underfill material disposed in an internal space between the bridge chip and the IC dies.

[0009] According to another embodiment of the present invention, a method of manufacturing a bridge chip assembly having a non-conductive underfill for interconnecting two or more IC dies is provided. Each of the IC dies has a first region including a plurality of connections having a first pitch associated therewith, and a second region including a plurality of connection pads having a second pitch associated therewith, and the first pitch is greater than the second pitch. The method includes providing a bridge chip including at least first and second pluralities of connections, the first and second pluralities of connections having the second pitch associated with the bridge chip; attaching a non-conductive underfill film to an upper surface of the bridge chip to cover the first and second pluralities of connections; bonding a first IC die of the IC dies to the bridge chip using the plurality of connection pads of the first IC die, the first plurality of connections of the bridge chip being aligned with the corresponding plurality of connection pads of the first IC die of the IC dies; and bonding a second IC die of the IC dies to the bridge chip using the plurality of connection pads of the second IC die, the second plurality of connections of the bridge chip being aligned with the corresponding plurality of connection pads of the second IC die of the IC dies. The bridge chip assembly includes the bridge chip bonded to at least the first and second IC dies, and the non-conductive underfill film disposed between the bridge chip and the first and second IC dies.

[0010] The technology disclosed herein can provide substantial beneficial technical effects. By way of example only and without limitation, one or more embodiments can provide one or more of the following advantages. · By using a non-conductive underfill film on the surface of the IC die or on the surface of the bridge chip before bonding the bridge chip to the IC die, the need for capillary underfill or non-conductive paste underfill is virtually eliminated, thereby avoiding encapsulation and / or cracking of the filler during bridge chip bonding. · By using a hierarchical structure of solder within the bridge chip assembly component, large solder bumps are prevented from melting during the bonding of the bridge chip to the IC die, thereby reducing the occurrence of oxidation, movement / misalignment, and / or bridging. · By using a hierarchical structure of solder within the bridge chip assembly component, the melting of the bridge chip interconnects during the subsequent bonding of the bridge chip assembly to the organic substrate is prevented. · By using dams formed on the surface of the bridge chip and / or the IC die, the flow of the underfill material beyond the intended bridge chip interconnects is prevented. · By forming injection holes through the bridge chip, a means is provided to introduce an underfill material between the bridge chip and the IC die after the manufacture of the bridge chip assembly, reducing the possibility of underfill confinement and / or crack formation.

[0011] These features and advantages, and other features and advantages, will become apparent from the following detailed description of their exemplary embodiments. This detailed description is to be read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0012] Non-limiting and non-exclusive embodiments of the present invention will be described with reference to the following drawings. These drawings are presented by way of example only, and like reference numerals, where used, indicate corresponding elements within several of the drawings.

[0013]

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[0020] It should be understood that the elements in the drawings are shown for simplicity and clarity. For the sake of reducing interference with the visibility of the illustrated embodiments, generally understood but not essential elements that may be useful or necessary in commercially viable embodiments may not be shown.

DETAILED DESCRIPTION OF THE INVENTION

[0021] The principles of the present disclosure will be described herein in the context of an exemplary bridge chip assembly having a non-conductive film underfill for interconnecting two or more integrated circuit (IC) dies, and a method of manufacturing the bridge chip assembly. However, it should be understood that the specific structures and / or methods shown in the drawings and described herein are not limiting and should be regarded as examples. Further, it will be apparent to those skilled in the art that numerous modifications can be made to the disclosed embodiments included in the appended claims in view of the teachings herein. That is, the limitations with respect to the embodiments shown and described herein are not intended and should not be presumed.

[0022] The overall methods and structures for the disclosed embodiments are novel, but conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tooling may be utilized for the specific individual processing steps required to implement the structures and / or circuits. In view of the teachings herein, these techniques and tooling will be well known to those skilled in the art. Further, many of the processing steps and tooling used to manufacture semiconductor devices are also described in several readily available publications. For example, those publications include: Silicon VLSI Technology by James D. Plummer et al., Prentice Hall, 2nd Edition (November 11, 2008); and Silicon VLSI Technology: Fundamentals, Practice, and Modeling by James D. Plummer et al., Pearson, 1st Edition (July 24, 2000). The entire contents of both of these publications are hereby incorporated by reference herein. Although some individual processing steps may be described herein, it is emphasized that these steps are merely illustrative and that some equally suitable alternatives that should also be within the scope of the present disclosure may be well known to those skilled in the art.

[0023] It should be understood that the various layers, regions, and / or components illustrated in the accompanying figures may not be drawn to scale. Furthermore, for clarity of illustration, one or more semiconductor layers of a type commonly used in such integrated circuit structures may not be explicitly shown in a given figure. However, this does not imply that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit structure.

[0024] As previously described, conventional thermocompression bonding (TCB) of copper pillar flip chips using a non-conductive paste (NCP) as a pre-applied underfill has traditionally been used to bond thin and thick fine-pitch flip chip devices to organic substrates. However, this bonding process involves spreading and curing the NCP along with the solder wetting and joint formation processes, which can introduce several critical failure modes, including, but not limited to, NCP filler entrapment, NCP voiding issues, cracking, and poor solder wetting, among other issues. To address one or more of these issues, embodiments of the present invention provide a novel method and structure for bridge chip assemblies with capillary underfill.

[0025] 1A through 1G are cross-sectional and top perspective views illustrating intermediate processing stages in an overall semiconductor manufacturing methodology for forming an exemplary bridge chip assembly structure in accordance with one or more embodiments of the present invention. Referring to FIG. 1A, a first IC die 100 is shown comprising a semiconductor substrate 102 having a first plurality of connections formed on a top surface of the substrate in a first region 106 of the substrate, in this illustrative embodiment including solder bumps (e.g., C4 solder bumps) 104, and a second plurality of connections formed on the top surface of the substrate in a second region 110 of the substrate, in this embodiment including solder bumps (e.g., microbumps) 108. The first IC die 100 may be one of multiple dies formed on a semiconductor wafer.

[0026] The first plurality of solder bumps 104 are formed to have a defined first size and pitch, and the second plurality of solder bumps 108 are formed to have a defined second size and pitch, where the first size is larger than the second size, and the second pitch is finer (i.e., closer) than the first pitch. For example, in one or more embodiments, the size of the first plurality of solder bumps 104 is from about 60 to 120 microns (μm), preferably about 85 μm, and the size of the second plurality of solder bumps 108 is from about 10 to 40 μm. Similarly, adjacent solder bumps in the first region 106 of the substrate 102 are preferably separated by a solder pitch of about 100 to 200 μm, more preferably about 150 μm, and adjacent solder bumps in the second region 110 of the substrate are preferably separated by about 20 to 80 μm. However, it should be understood that embodiments of the present invention are not limited to any particular dimensions or spacing of any of the plurality of solder bumps 104, 108 on the first IC die 100. In one or more embodiments, the larger first plurality of solder bumps 104 are used to electrically connect to corresponding pads on an organic packaging laminate or an organic packaging substrate, and the smaller second plurality of solder bumps 108 are used to electrically connect to corresponding pads on a bridge chip for interconnecting two or more IC dies.

[0027] To provide structural support to at least solder bumps 108 with closer pitches, a laminate structure is applied to the top surface of the wafer, thereby covering the solder bumps in at least the second region 110 of the IC die 100. In this embodiment, since the laminate structure is applied to cover the entire wafer, the solder bumps 104 in the first region 106 of the IC die 100 will also benefit from the structural support of the laminate structure. In one or more embodiments, the laminate structure comprises a non-conductive underfill (UF) film 112 or a non-conductive film (NCF), and a polyethylene terephthalate (PET) layer 114 formed on at least a portion of the top surface of the underfill film. In one or more embodiments, the underfill film contains 20 to 80 weight percent (wt%) of an epoxy resin, 10 to 35 wt% of a curing agent, and 5 to 60 wt% of silica. The PET layer 114 preferably functions as a substrate or other support structure to facilitate the handling of the underfill film 112 when attached to the IC die 100, i.e., PET is used for the handling of the underfill film 112 (i.e., the NCF layer) during application. The laminate structure is attached to the top surface of the wafer including the first IC die 100, for example, using a well-known lamination or similar bonding process. For example, a suitable exemplary lamination process may involve a vacuum laminator with a heated rubber roller. For NCF lamination, the stage temperature is about 60 to 90 degrees Celsius (°C), the vacuum pressure is about 60 to 90 Pa, and the roller pressure is about 0.3 to 0.7 MPa.

[0028] The thickness of the underfill film 112 is preferably configured to be substantially the same as or slightly smaller than the height of the solder bumps 104, 108 (e.g., from about 20 μm to 30 μm). For example, assuming the height of the solder bump 108 is about 20 μm, the thickness of the underfill film 112 is also preferably configured to be about 20 μm or smaller. In an exemplary thermocompression bonding (TCB) process, even when the thickness of the underfill film is slightly larger than the height of the solder bump, pressure and heat are applied to the die so that the solder bump penetrates the underfill film, thereby exposing the solder bump and providing an electrical connection thereto, and the thickness of the underfill film may be slightly thinner than the height of the solder bump. It should be understood that the embodiments of the present invention are not limited to any specific dimensions of the underfill film 112 and / or the solder bumps 104, 108.

[0029] Next, as shown in FIG. 1B, the bottom surface of the wafer with the laminate structure (including the underfill film 112 and the PET layer 114) attached to the upper surface of the wafer is adhered and attached to the layer of the dicing tape 116. The dicing tape 116 is preferably configured to extend to or beyond the outer periphery of the wafer, but the embodiments of the present invention are not limited to any specific dicing tape dimensions. Next, the PET layer 114 is removed, such as by using a film peeling process. FIG. 1C shows a top perspective view of the entire wafer including the substrate 102 and the underfill film 112 attached to the dicing tape 116.

[0030] As known to those skilled in the art, dicing tape is an adhesive backing tape used during wafer dicing. The dicing tape holds the die together during the cutting process. Dicing tapes suitable for use with embodiments of the present invention can be made from a variety of backing materials, including polyvinyl chloride (PVC), polyolefins, polyethylene, and the like, along with an adhesive that holds the die in place. As shown in FIG. 1D , the wafer is diced into a plurality of individual dies, including the first IC die 100. The dicing process can include, for example, scribing and breaking, mechanical sawing (e.g., using a dicing saw), or laser cutting, among other wafer dicing methodologies known to those skilled in the art. The laminated non-conductive underfill film is adapted to be strong enough to avoid damage during the wafer dicing process.

[0031] Referring to FIG. 1E, first IC die 100 is shown after dicing and removal from the dicing tape backing. A bridge chip is then bonded to first IC die 100 using a flip-chip process such that, when flipped upside down, connection pads 121 formed on the top surface of bridge chip 120 align with corresponding solder bumps (108 in FIG. 1A) on the opposing surface in second region 110 of the first IC die. In this exemplary embodiment, bridge chip 120 does not include microbumps but rather includes fine-pitch pads 121, as described above. As a result, bridge chip 120 does not require an underfill film to serve as a protective layer. In an alternative embodiment in which the bridge chip includes fine-pitch connections, a non-conductive underfill film is applied to protect the bridge chip connections, as described in more detail herein below in conjunction with FIGS. 3A through 3E.

[0032] The bridge chip 120 is preferably bonded to the first IC die 100 using a TCB process, which involves the simultaneous application of heat and pressure to the mating surfaces with a wear-resistant bonding tool, as previously described. The temperature selected and pressure applied will depend primarily on the diffusivity of the materials forming the joint. By way of example only, the peak temperature of the bonding head may be approximately 320 to 400°C, the stage temperature may be approximately 50 to 150°C, and the applied force may be greater than approximately 30 to 400 Newtons (N) for approximately 2 to 60 seconds.

[0033] 1F illustrates bonding of a second IC die 122 to a bridge chip 120 in accordance with one or more embodiments of the present invention. Like the first IC die 100, the second IC die 122 comprises a semiconductor substrate 102 having a first plurality of connections, in this illustrative embodiment including solder bumps 104, formed on a top surface of the substrate in a first region 106 thereof, and a second plurality of connections, in this embodiment including solder bumps 108, formed on a top surface of the substrate in a second region 110 thereof. The first plurality of solder bumps 104 are formed to have a defined first size and pitch, and the second plurality of solder bumps 108 are formed to have a defined second size and pitch, where the first size is larger than the second size and the second pitch is finer than the first pitch. The size and pitch of the solder bumps 104, 108 formed on the second IC die 122 are not necessarily the same as the size and pitch of the solder bumps 104, 108 formed on the first IC die 100. It should be understood that embodiments of the present invention are not limited to any particular dimensions or spacing of the respective plurality of solder bumps 104, 108 on the second IC die 122.

[0034] To provide structural support to at least the solder bumps 108 with closer pitch, the second IC die 122 includes a laminate structure applied to the upper surface of the wafer, whereby the solder bumps within at least the second region 110 of the second IC die are covered. In this embodiment, since the laminate structure is applied to cover the entire wafer, the solder bumps 104 within the first region 106 of the second IC die 122 will also benefit from the structural support of the laminate structure. In one or more embodiments, the laminate structure comprises a non-conductive underfill film 112, which is attached to the upper surface of the wafer including the second IC die 122 using a well-known lamination process made to match the laminate structure attached to the upper surface of the first IC die 100 as previously described in conjunction with FIGS. 1A through 1D.

[0035] When the connection pads formed on the upper surface of the bridge chip 120 are turned upside down, the bridge chip is joined to the second IC die 122 using, for example, a TCB process that is aligned with the way the bridge chip is joined to the first IC die 100 so that the positions match the corresponding solder bumps on the opposing surface within the second region 110 of the second IC die. More specifically, in one or more embodiments, heat and pressure are applied simultaneously to the mating surface (e.g., by a wear-resistant bonding tool, etc.). As previously described, the parameters of the selected temperature and applied pressure, as well as the duration thereof, will mainly depend on the diffusion rate of the material forming the connection.

[0036] 1G, the resulting bridge chip assembly, including bridge chip 120 bonded to first and second IC dies 100 and 122, respectively, is bonded to an organic substrate 124. In this illustrative embodiment, organic substrate 124 includes a recess formed therein that is adapted to receive bridge chip 120 when the bridge chip assembly is inverted, allowing solder bump connections (104 in FIG. 1F) formed on first and second IC dies 100, 122 to be flush with and make electrical contact with corresponding pads formed on the top surface of organic substrate 124. A TCB process or an oven reflow process can be used to bond the bridge chip assembly (100, 120, 122) to the organic substrate 124. In one or more embodiments, after bonding the bridge chip assembly to the organic substrate 124, a capillary underfill layer 126 may optionally be formed that surrounds the larger solder bumps and substantially fills the gap between the bridge chip assembly and the organic substrate 124, resulting in the multi-die structure 130 as shown.

[0037] As previously described, the IC die in the bridge chip assembly includes at least a first and a second set of connections, with the finer pitch connections being the most fragile and therefore of greatest concern. For the illustrative embodiment described in connection with Figures 1A through 1G, a non-conductive underfill film is disposed over the entire wafer, including both the fine-pitch (i.e., narrow) and coarse-pitch (i.e., wide) connections. In an alternative embodiment, the underfill film is applied only within the fine-pitch connection area of the wafer.

[0038] Figures 2A through 2E are cross-sectional views showing intermediate processing steps in a comprehensive semiconductor manufacturing method system for forming an exemplary bridge chip assembly structure with restricted application of a non-conductive underfill film to a fine pitch connection region of bonded dies according to one or more alternative embodiments of the present invention. Referring to FIG. 2A, a first IC die 200 is shown comprising a semiconductor substrate 202, which in this illustrative embodiment includes solder bumps 204, a first plurality of connections formed on the upper surface of the substrate within a first region 206 of the substrate, and in this embodiment, solder bumps 208 and a second plurality of connections formed on the upper surface of the substrate within a second region 210 of the substrate. The first IC die 200 can be one of a plurality of dies formed on a semiconductor wafer.

[0039] A laminate structure is formed that includes a non-conductive underfill (UF) film 212 attached to a PET layer 214. Consistent with the underfill film described previously, the underfill film 212 can include from about 20 to 80 wt% epoxy resin, from about 10 to 35 wt% curing agent, and from about 5 to 60 wt% silica. Unlike the laminate structure formed in connection with the bridge chip assembly manufacturing process described in connection with FIGS. 1A through 1G, the underfill film 212 is formed as a plurality of patterned separate portions, each portion having a width adapted to cover only the fine pitch connections 208 within the second region 210 of the first IC die 200. As shown in FIG. 2B, the laminate structure comprising the underfill film 212 and the PET layer 214 is attached to the upper surface of the first IC die 200 within the second (fine pitch) region 210 using, for example, a well-known lamination process. As shown in FIG. 2B, the fine pitch connections (within the second region 210 shown in FIG. 2A) on the first die 200 are protected by the laminate structure, and the coarse pitch connections within the first region 206 of the first die remain exposed. These coarse pitch connections within the first region 206 will be protected later using a standard capillary underfill material.

[0040] Similar to the underfill film 112 shown in FIG. 1B, the thickness of the underfill film 212 is preferably configured to be substantially the same as or slightly smaller than the height of the solder bump 208. As described above, in an exemplary TCB process, even when the thickness of the underfill film is slightly larger than the height of the solder bump, pressure and heat are applied to the die such that the solder bump penetrates the underfill film, thereby exposing the solder bump and providing an electrical connection thereto. It should be understood that embodiments of the present invention are not limited to any particular dimensions of the underfill film 212 and / or the solder bump 208.

[0041] Continuing to refer to FIG. 2B, the bottom surface of the wafer with the laminate structure (including the underfill film 212 and the PET layer 214) attached is adhered to the layer of the dicing tape 216. The dicing tape 216 preferably extends to or slightly beyond the outer periphery of the wafer, but embodiments of the present invention are not limited to any particular dicing tape dimensions. The PET layer 214 is then removed, such as by using a film peeling process. FIG. 1C shows a top perspective view of the entire wafer including the substrate 102 and the underfill film 112 attached to the dicing tape 116.

[0042] Referring now to FIG. 2C, there is shown a first die 200 after dicing and removal from the backing of the dicing tape (216 in FIG. 2B). Next, when the connection pad 221 formed on the upper surface of the bridge chip 220 is turned upside down, the bridge chip is flip-chip bonded to the first IC die 200 such that it is aligned with the corresponding solder bump (208 in FIG. 2A) on the opposing surface within the second region 210 of the first IC die. The bridge chip 220 is preferably bonded to the first IC die 200 using a TCB process, which, as described previously, involves simultaneously applying heat and pressure to the mating surfaces with a wear-resistant bonding tool. The factors of the selected temperature and applied pressure will mainly depend on the diffusion rate of the materials forming the connection. By way of example only, the peak temperature of the bonding head can be from about 320 to 400 °C, the stage temperature can be from about 50 to 150 °C, and the applied force can be greater than about 30 to 400 Newtons (N) over a period of about 2 to 60 seconds.

[0043] Figure 2D shows the bonding of the second IC die 222 to the bridge chip 220 according to one or more embodiments of the present invention. Similar to the first IC die 200, the second IC die 222 includes a semiconductor substrate 202, which includes solder bumps 204 in this illustrative embodiment, a first plurality of connections formed on the upper surface of the substrate within a first region 206 of the substrate, and solder bumps 208 in this embodiment, and has a second plurality of connections formed on the upper surface of the substrate within a second region 210 of the substrate. The first plurality of solder bumps 204 are formed to have a defined first size and pitch, the second plurality of solder bumps 208 have a defined second size and pitch, the first size is larger than the second size, and the second pitch is finer than the first pitch. The sizes and pitches of the solder bumps 204, 208 formed on the second IC die 222 are not necessarily the same as the sizes and pitches of the solder bumps 204, 208 formed on the first IC die 200. It should be understood that the embodiments of the present invention are not limited to any particular dimensions or spacing of any of the plurality of solder bumps 204, 208 on the second IC die 222.

[0044] To provide structural support to the solder bumps 208 with closer pitch, the second IC die 222 includes a laminate structure applied to the upper surface of the wafer, whereby the solder bumps within at least the second region 210 of the second IC die are covered. In this illustrative embodiment, as described previously, the solder bumps 204 within the first region 206 of the second IC die 222 are not protected by the laminate structure and remain exposed. In one or more embodiments, the laminate structure includes a non-conductive underfill film 212, which is preferably made using a well-known lamination process that aligns with the laminate structure attached to the upper surface of the first IC die 200 as described previously in conjunction with FIGS. 2A through 2C, and is attached to the upper surface of the wafer including the second IC die 222.

[0045] The bridge chip is bonded to second IC die 222, for example, using a TCB process consistent with how the bridge chip was bonded to first IC die 200, such that when flipped upside down, the connection pads formed on the top surface of bridge chip 220 align with corresponding solder bumps on the opposing surface in second region 210 of the second IC die. More particularly, in one or more embodiments, heat and pressure are applied simultaneously to the mating surfaces (e.g., with a wear-resistant bonding tool, etc.). As previously described, the selected temperature and applied pressure parameters, as well as their duration, will depend primarily on the diffusivity of the materials forming the connections.

[0046] 2E, the resulting bridge chip assembly, including bridge chip 220 bonded to first and second IC dies 200 and 222, respectively, is bonded to an organic substrate 224. In this illustrative embodiment, organic substrate 224 includes a recess formed therein that is adapted to receive bridge chip 220 when the bridge chip assembly is inverted, allowing solder bump connections (204 in FIG. 2D) formed on first and second IC dies 200, 222 to be flush with and in electrical contact with corresponding pads formed on the top surface of organic substrate 224. A TCB process or an oven reflow process can be used to bond the bridge chip assembly (200, 220, 222) to organic substrate 224. In one or more embodiments, after bonding the bridge chip assembly to the organic substrate 224, a capillary underfill layer 226 may optionally be formed that surrounds the larger solder bumps (204 in FIG. 2D) and substantially fills the gap between the bridge chip assembly and the organic substrate 224, resulting in the multi-die structure 230 as shown.

[0047] For the exemplary embodiments shown in FIGS. 1A through 1G and FIGS. 2A through 2E, in order to protect at least fine pitch connections (e.g., microbumps) included on the IC die during the bonding process, an underfill film (112, 212) is disposed on the surface of the IC die before the die is bonded to the bridge chip. In one or more alternative embodiments, the bridge chip itself includes fine pitch connections, and the IC die to which the bridge chip is bonded includes pads corresponding to its own upper surface. As a result, in order to protect the fine pitch connections on the bridge chip during bonding of the bridge chip to a plurality of IC dies, the underfill film is disposed on the fine pitch connections of the bridge chip, rather than on the IC die, prior to the bonding process.

[0048] By way of example and not limitation, FIGS. 3A through 3E are cross-sectional views showing intermediate processing steps in an integrated semiconductor manufacturing method system for forming an exemplary bridge chip 300 having an underfill film disposed on its own fine pitch connections, according to one embodiment of the present invention. Referring to FIG. 3A, a bridge chip 300 is shown comprising a semiconductor substrate 302 and a plurality of fine pitch connections (e.g., solder microbumps) 304 formed on the upper surface of at least a portion of the substrate.

[0049] A laminate structure to be attached to the bridge chip 300 to protect the fine-pitch connections 304 includes a non-conductive underfill (UF) film 306 and a PET layer 308 formed on top of the underfill film. The underfill film 306 of the laminate structure is configured to have a width that at least covers the fine-pitch connections 304 and a cross-sectional thickness approximately equal to the height of the fine-pitch connections 304. Consistent with the compositions of the underfill films 112 and 212 described above in conjunction with FIGS. 1A and 2A, respectively, the underfill film 306 of the laminate structure shown in FIG. 3A includes 20 to 80 wt % epoxy resin, 10 to 35 wt % hardener, and 5 to 60 wt % silica. It should be understood that numerous suitable alternative compositions for the underfill film are contemplated by embodiments of the present invention, as would be apparent to one skilled in the art.

[0050] As shown in FIG. 3B, a laminate structure including an underfill film 306 and a PET layer 308 is attached to the top surface of a bridge chip 300, for example, using a well-known lamination process. The bridge chip 300 is preferably one of multiple such chips formed on a semiconductor wafer. As is apparent from FIG. 3B, the fine-pitch connections on the bridge chip 300 (304 in FIG. 3A) are protected by the laminate structure. The bottom side of the wafer, including the bridge chip 300 with the attached laminate structure (including the underfill film 306 and the PET layer 308), is adhesively attached to a layer of dicing tape 310. The dicing tape 310 preferably extends to or slightly beyond the perimeter of the bridge chip 300, although embodiments of the present invention are not limited to any particular dicing tape dimensions. After the bridge chip 300 with the laminate structure is attached to the dicing tape 310, the PET layer 308 is removed, such as by using a film peeling process.

[0051] 3C conceptually illustrates the bridge chip 300, after dicing (e.g., using a dicing process such as that described in conjunction with FIG. 1D), being inverted and aligned for bonding with the first IC die 312 and the second IC die 314. Each of the first and second IC die 312, 314 includes one or more connection pads 316 formed on the top surface of that IC die's substrate 320. The connection pads 316 are configured to have a pitch that matches the pitch (i.e., spacing) of the fine-pitch connections 304 formed on the bridge chip 300. Each of the first and second IC die 312, 314 further includes a plurality of larger, coarser pitch connections (e.g., solder bumps) 318 formed on the top surface of the substrate 320. These coarser pitch connections 318 are adapted for later use in bonding the first and second IC die 312, 314, respectively, to an organic package or substrate.

[0052] FIG. 3D shows that bridge chip 300 is bonded to first and second IC dies 312 and 314, respectively, to form bridge chip assembly 322. In forming bridge chip assembly 322, when bridge chip 300 is inverted, the bridge chip is attached to first IC die 312 and second IC die 314 using a flip-chip bonding process such that the fine-pitch connection pads (316 in FIG. 3C ) formed on the top surface of each of the first and second IC dies align with corresponding solder microbumps (304 in FIG. 3C ) formed on the opposing top surface of the bridge chip. Unlike the embodiments shown in FIGS. 1F and 2D , bridge chip 300 shown in FIG. 3D includes microbumps protected by underfill film 306, and IC dies 312 and 314 include fine-pitch connection pads, as previously described. As a result, the IC dies do not require an underfill film to act as a protective layer.

[0053] Additionally, aspects according to one or more embodiments of the present invention contemplate a method for maintaining the first and second IC dies 312 and 314, respectively, in a precisely aligned and positioned state and for bonding the bridge chip 300 in that position. This method allows the bridge chip 300 to be bonded to both the first and second IC dies 312 and 314, respectively, simultaneously in a single bonding step. One method is to temporarily bond the first IC die 312 to a handle substrate (not shown here) and then temporarily bond the second IC die 314 to the same substrate. This temporarily attached handle substrate is removed after the bridge chip 300 is bonded. Alternatively, the first and second IC dies 312 and 314 are temporarily fixed in a fixture or the like.

[0054] The bridge chip 300 is preferably simultaneously bonded to the first and second IC dies 312, 314 using the well-known TCB process, which generally involves the simultaneous application of heat and pressure to the mating surfaces with a wear-resistant bonding tool, as previously described. The temperature selected and pressure applied will depend primarily on the diffusivity of the materials forming the connection. By way of example only, the peak temperature of the bonding head may be approximately 320 to 400°C, the stage temperature may be approximately 50 to 150°C, and the applied force may be greater than approximately 30 to 400 Newtons (N) for approximately 2 to 60 seconds.

[0055] In FIG. 3E, a bridge chip assembly 322 resulting from including bridge chips 300 respectively bonded to first and second IC dies 312 and 314 is coupled to an organic substrate 324. In this illustrative embodiment, the organic substrate 324 includes a recess formed therein that, when the bridge chip assembly is inverted, receives the bridge chip 300 such that the coarse pitch solder bump connections (318 in FIG. 3C) formed on the first and second IC dies 312, 314 are flush with and in electrical contact with corresponding pads formed on the top surface of the organic substrate 324. It is possible to use a TCB process or a furnace reflow process to bond the bridge chip assembly 322 to the organic substrate 324. In one or more embodiments, following bonding the bridge chip assembly 322 to the organic substrate 324, optionally, a capillary underfill layer 326 is formed that surrounds the larger solder bumps (318 in FIG. 3C) and substantially fills the gap between the bridge chip assembly 322 and the organic substrate 324, resulting in a multi-die structure 328 as shown.

[0056] Embodiments have been shown in which trenches or other recesses are formed in an organic substrate adapted to receive a bridge chip, but it should be understood that the formation of such trenches or recesses is optional, i.e., the present invention contemplates other embodiments that do not require the formation of recesses in the organic substrate. For example, FIG. 4 is a cross-sectional view showing at least a portion of an exemplary bridge chip assembly 400 configured to have a bridge chip attached to a plurality of IC dies, such that the bridge chip is substantially flush with a plurality of coarse pitch connection portions formed on the upper surface of the IC die. The bridge chip assembly 400 includes a first IC die 402 and a second IC die 404. The first IC die 402 has a substrate 406 configured to include a stepped end portion 408 that is thinner than the remainder of the substrate. Similarly, the second IC die 404 has a substrate 410, and an end portion of this substrate that includes a stepped end portion 412 is thinner than the remainder of the substrate. The stepped end portions 408, 412 of each of the first and second IC dies 402, 404 include one or more fine pitch connection pads formed on their upper surfaces, and those fine pitch connection pads are aligned with corresponding fine pitch solder connection portions (e.g., solder microbumps) formed on the bridge chip 414, and the bridge chip is attached to the first and second IC dies when it is inverted. For each IC die, the depth of the stepped portion with respect to the upper surface of the remainder of the substrate is configured such that when the bridge chip is joined to the IC die, it is substantially flush with the coarse pitch connection portions formed on the upper surface of the substrate. By doing so, the bridge chip 414 does not interfere with the first and second IC dies 402, 404 during bonding to the organic substrate.

[0057] In an alternative embodiment, the height of the coarse pitch connections (e.g., those in region 206 shown in Figures 2A-2D) can be greater than the height of the fine pitch connections (e.g., those in region 210 in Figures 2A and 2C) so that when the bridge chip is bonded to the IC die, the coarse pitch connections will contact corresponding connection pads on the organic substrate / laminate without the need to form openings or stepped portions in the organic substrate.

[0058] In accordance with one or more embodiments of the present invention, a solder hierarchy is preferably used regardless of the underfill methodology (e.g., non-conductive film, non-conductive paste, capillary underfill, etc., or even omitting underfill entirely) used to protect the components of the bridge chip assembly during bonding of the bridge chip assembly to an organic laminate or substrate. One important aspect of the solder hierarchy in accordance with the present invention, as will become apparent in one or more embodiments thereof, is the use of a first solder composition on the bridge chip and a second solder composition on the larger IC die to which the bridge chip is bonded, the first and second solder compositions having different melting points.

[0059] 3C , for example, one or more embodiments of the present invention preferably include using a lower melting point solder composition for the fine pitch connections (e.g., solder microbumps) 304 formed on the top surface of at least a portion of bridge chip 300, and using a higher melting point solder composition for the coarser pitch connections (e.g., C4 solder bumps) 318 formed on the top surface of at least a portion of IC dies 312 and 314. In one or more embodiments, the lower melting point solder composition used for the fine pitch connections on the bridge chip is lead-free tin-bismuth solder Sn, which has a eutectic temperature of 138° C. 42 Bi 58 , or tin-indium solder In with a eutectic temperature of 118°C 52 Sn 48, or Bi with a eutectic temperature of 109°C 67 In 33 , or Sn with a eutectic temperature of 198.5°C 91 Zn9 or any of several compositions including one or more of tin (Sn), bismuth (Bi), indium (In), silver (Ag), copper (Cu), zinc (Zn), etc., that have a melting point below about 217° C. In one or more embodiments, higher melting point solder compositions used for course pitch connections on IC dies include lead-free tin silver (SnAg), tin copper (SnCu), or tin silver copper (SnAgCu), or any of several other compositions that have a melting point above about 217° C.

[0060] One advantage of this novel solder hierarchy approach is that the larger, coarse-pitch solder bumps, which have a higher melting point, do not melt when the bridge chip is assembled with the larger IC die (the order is immaterial, whether one die is bonded to the bridge chip at a time or multiple dies are bonded simultaneously), significantly reducing the likelihood of oxidation, migration, or bridging that continues to pose challenges to conventional multi-chip assembly methodologies. Once the smaller IC die forming the bridge chip assembly is successfully bonded to the bridge chip, it can proceed to bond the larger die to the organic laminate or substrate. One variation of this approach uses a small amount of low-temperature solder (e.g., SnBi) that melts and bonds with the bridge chip but is then at least partially consumed as an intermetallic compound, thereby leaving a smaller volume of solder behind that will melt during subsequent bonding of the bridge chip assembly to the organic laminate / substrate.

[0061] According to one or more alternative embodiments of the solder hierarchical structure invention, it is preferred to use a higher melting point solder composition or copper pillar or copper hybrid (non-solder joint) for fine pitch connections (e.g., microbumps) that bond a bridge chip to an IC die, and a lower melting point solder composition is used for coarse pitch connections (e.g., C4 solder bumps) on the IC die that bond the bridge chip assembly to an organic laminate or substrate. When the bridge chip is coupled to the IC die to form a bridge chip assembly (the order in which one die is joined to the bridge chip at a time or multiple dies are joined simultaneously is not important), the coarse pitch solder bumps will melt. However, because the spacing is wider, there is a lower concern that the flow of the molten solder will cause a short circuit between adjacent connections. During the subsequent bonding of the bridge chip assembly to the organic laminate / substrate, the bridge chip interconnects formed of a higher melting point material do not melt, thereby preventing the occurrence of a short circuit between the fine pitch microbumps.

[0062] As previously explained in connection with the illustrative embodiments of FIGS. 1A through 3E, one advantage of using a non-conductive underfill film in initially coupling a bridge chip to an IC die to form a bridge chip assembly is that the application of the underfill film is not subject to extrusion during the bonding process, making it much easier to control the positioning of the underfill film compared to conventional methods. In contrast, in the case of a non-conductive underfill paste, the paste-type underfill material is extruded when the bridge chip is coupled to the IC die. As a result, it becomes difficult to control the amount and direction of the underfill material extruded when bonding the bridge chip to the IC die. For example, when bonding the bridge chip to a first IC die, if the amount of underfill paste is too much, it will overflow and enter the fine pitch connection region used to bond the bridge chip to a second IC die. Alternatively, if the amount of underfill paste is too little, it will not be sufficient to cover the entire area of the fine pitch connection corresponding to the bonded IC die.

[0063] The way an underfill material (e.g., underfill paste) is extruded during chip bonding will depend on a plurality of factors. Some of the factors that affect the way the underfill material is extruded include, but are not limited to, the temperature of the bonding head / stage, the state of the surface of the chip or substrate, and the pattern and density of the solder bumps. Therefore, since it is thus difficult to control the positioning of the underfill material having fluidity during chip bonding, in one or more embodiments of the present invention, dams or barriers are utilized to restrict the flow of the underfill material to only the desired areas of the IC die and / or bridge chip, thereby preventing the underfill material from flowing onto unintended surfaces of the IC die and / or bridge chip during bonding.

[0064] 5A is a top plan view illustrating at least a portion of an exemplary bridge chip and a coupled IC die, each including a dam or barrier, according to one embodiment of the present invention. More specifically, a first IC die 502 includes a first dam 504 formed on its top surface. The first dam 504 has a width that preferably extends across the width of the first IC die 502 from a first edge thereof to an opposing second edge thereof and serves to separate one or more larger coarse-pitch connections (e.g., C4 solder bumps) 506 formed in a first region 508 of the first IC die from one or more smaller fine-pitch connections (e.g., microbumps) 510 formed in a second region 512 of the first IC die. Similarly, the bridge chip 514 to which the first IC die 502 is to be bonded includes a second dam or barrier 516 formed on its top surface. The bridge chip 514 may include one or more dams as needed. The second dam 516 preferably extends across the width of the bridge chip 514 from its first edge to its opposite second edge and serves to separate a first set of fine-pitch connection pads 518 that align with the fine-pitch connections 510 formed on the first IC die 502 and a second set of fine-pitch connection pads 520 that align with corresponding fine-pitch connections formed on a second IC die (not explicitly shown) to which the bridge chip will subsequently be bonded. The first and second dams 504, 516 are configured to prevent the flow of underfill material (e.g., underfill paste) during bonding of the bridge chip to the IC die.

[0065] In one or more embodiments, the dam structures 504, 516 can be formed on the top surface of the bridge chip and / or the IC die and can include virtually any material coating or structure capable of creating a barrier to prevent the flow of underfill material, including but not limited to Teflon® (a registered trademark of DuPont). In a first exemplary method of forming a dam, an opening is provided in a metal mask that coincides with the alignment mark area to be made hydrophobic. Next, a thin coating of a Teflon® release agent is sprayed on the unmasked area. The mask is removed and the wafer is baked at about 315 °C for about 10 minutes. This causes the Teflon® particles to melt and a thin film coating is formed. The underfill does not adhere to the Teflon® coated surface. As an example, it is possible to use the Miller Stephenson MS 122 AX Teflon spray release agent.

[0066] A second exemplary method of forming a dam preferably includes the step of using photolithography to impart hydrophobicity precisely to the alignment mark area. To achieve this, according to one or more embodiments of the present invention, a photoresist is deposited on the surface of the wafer and then the wafer is exposed (e.g., using an ultraviolet light source) and developed to expose the alignment mark area. Next, a self-assembling hydrophobic molecule or solution, such as octadecyltrichlorosilane in toluene or Teflon AF dissolved in a perfluorinated solvent, is applied using a spin coating or spray process, for example. Alternatively, the wafer can be immersed in a solution of the hydrophobic molecule. Then, for example, baking is performed at about 310 °C to 330 °C for about 10 to 15 minutes to fix the Teflon® AF coating in place.

[0067] Alternatively, the dam may include a region of the substrate to be processed that has an affinity for the underfill material, such as a material with low surface tension or a fluorinated polymer. By way of non-limiting example only, suitable materials with low surface tension include polytetrafluoroethylene, fluorinated ethylene propylene, and perfluoroalkoxy alkane. An exemplary material that can be used to form a transparent low surface tension coating is Miller Stephenson MS 122AX Teflon (polytetrafluoroethylene) spray release agent. In one or more embodiments, it is possible to deposit a hydrophobic material on the surface of the bridge chip or IC die using photolithography or other processes. Hydrophobic materials suitable for use in embodiments of the present invention include, among other compositions, for example, octadecyltrichlorosilane in toluene, or DuPont (registered trademark) Teflon (registered trademark) AF dissolved in a perfluorinated solvent at a concentration of about 3% to 15%. It should be understood that embodiments of the present invention are not limited to any particular material and / or process used to form the dam 504.

[0068] In one or more embodiments, the width W of the dam 504 is from about 20 μm to 250 μm, preferably about 100 μm, depending on the spacing between the coarse pitch connection and the fine pitch connection. The vertical height of the dam above the upper surface of the bridge chip or IC die on which the dam is formed is preferably from about 20 μm to 100 μm, more preferably from about 60 to 70 μm. The maximum height of the dam 504 is preferably lower than the height of the larger coarse pitch connection 506 above the upper surface of the first IC die 502. Further, the cross-sectional thickness of the material with low surface tension is less than about 100 μm. However, it should be understood that embodiments of the present invention are not limited to any particular dimensions or shape of the dam 504.

[0069] Figures 5B through 5F are cross-sectional views showing intermediate processing steps in a comprehensive semiconductor manufacturing method system for forming an exemplary bridge chip assembly structure adapted for use with an underfill paste, according to one or more embodiments of the present invention. Referring to Figure 5B, a bridge chip 514 bonded to a first IC die 502 is shown. At this stage, the bridge chip 514 is turned upside down with respect to the first IC die 502, whereby a first plurality of fine pitch connection pads 518 on the bridge chip are aligned with corresponding fine pitch connections (e.g., solder microbumps) 510 on the first IC die. A non-conductive underfill paste 519 deposited on the upper surfaces of the first IC die 502 and / or the bridge chip 514 is pushed out from the area of the fine pitch connections during the process of bonding the bridge chip to the first IC die, but is restricted by respective dams 504 and 516 formed on the first IC die and the bridge chip. In this way, the underfill material is prevented from flowing into the coarse pitch connection region 508 of the first IC die or onto the fine pitch connection pads 520 at the opposite end of the bridge chip.

[0070] Similarly, Figure 5C shows bridge chip 514 bonded to second IC die 522. Like first IC die 502, second IC die 522 includes a dam or barrier 524 formed on its top surface that separates a plurality of larger coarse pitch connections (e.g., C4 solder bumps) 526 formed in a coarse pitch connection region 528 of the second IC die from a plurality of smaller fine pitch connections (e.g., solder microbumps) 530. At this stage, fine pitch connections 530 on second IC die 522 are aligned with a corresponding second set of fine pitch connection pads (520 in Figure 5B) formed on bridge chip 514. Non-conductive underfill paste 532 deposited on the top surface of second IC die 522 and / or bridge chip 514 is extruded from the area of the fine-pitch connections during the process of bonding the bridge chip to the second IC die, but is restricted by dams 524 and 516 formed on the second IC die and bridge chip, respectively. In this manner, the underfill material is prevented from flowing into the coarse-pitch connection region 528 of the second IC die. At this point in the manufacturing process, dam structure 516 formed on bridge chip 514 is effectively unnecessary because the first set of fine-pitch connections (510 in FIG. 5B ) are already covered with underfill material. It should be understood that in one or more embodiments, the first and second IC die may be bonded to bridge chip 514 sequentially or simultaneously, as shown in FIGS. 5B-5C . After bonding the first and second IC die 502, 522 to the bridge chip 514, if desired, the dams 504, 516, 524 can be removed, such as by a standard etching process, resulting in the overall bridge chip assembly 534.

[0071] 5D shows an organic laminate or substrate 536 to be bonded to the bridge chip assembly (534 in FIG. 5C). Optionally, an adhesive material 538 is provided on at least a portion of the top surface of the organic laminate 536, such as using a standard deposition process. The adhesive material 538 may include virtually any material having adhesive properties and serves to stabilize the bridge chip assembly and temporarily secure it to the organic laminate 536 during the bonding process. In this illustrative embodiment, the organic laminate 536 includes a cavity or other recess 540 formed without penetrating its top surface, which is configured to receive the bridge chip (514 in FIG. 5C). As explained above, this recess 540 allows the solder bump connections (506 in FIG. 5B and 526 in FIG. 5C) formed on the first and second IC dies 502, 522 to be substantially flush with and in electrical contact with corresponding pads (not explicitly shown, but implied) formed on the top surface of the organic laminate 536.

[0072] In FIG. 5E, the bridge chip assembly 534 is positioned for bonding to the organic laminate 536, such that the bridge chip 514 is positioned within the recess (540 in FIG. 5D) and the coarse-pitch connections 506, 526 are aligned with corresponding connection pads (not explicitly shown) formed on the top surface of the organic laminate. In one or more embodiments, a formic acid reflow process is used to bond the bridge chip assembly 534 to the organic laminate 536. The formic acid reflow process is a suitable alternative to flux-free soldering, using lower temperatures to perform solder reflow under formic acid (HCOOH) vapor. This vapor chemically reacts with the metal oxides of the solder connections at lower temperatures (150 to 160°C) to create a format. At elevated temperatures, the format decomposes into hydrogen, water, and carbon dioxide. Formic acid can be sufficiently reducing for most solders and is widely used in fluxless soldering.

[0073] Referring to FIG. 5F, when the bridge chip assembly 534 is bonded to the organic laminate 536, capillary underfill material 542 is injected throughout the assembly to fill the space between the assembly and the organic laminate. The underfill material 542 provides additional support to increase the structural integrity of the resulting bonded device.

[0074] FIG. 6 is a cross-sectional view showing an exemplary structure that facilitates the introduction of non-conductive underfill material between a bridge chip and one or more IC dies to which the bridge chip is bonded after manufacture of the bridge chip assembly according to an alternative embodiment of the present invention. The process shown in FIG. 6 includes forming one or more openings (i.e., holes) 602 and 604 through the bridge chip 514. The holes 602, 604 can be formed, for example, by laser drilling or deep reactive ion etching (RIE) before dicing the bridge chip 514 from the wafer. In one or more embodiments, at least one hole is provided for each set of fine pitch connections on the bridge chip. In the example shown in FIG. 6, a first hole 602 is made in the bridge chip 514 in proximity to the area of the first set of fine pitch connections 510, and a second hole 604 is made in proximity to the area of the second set of fine pitch connections 530. More than one hole may be formed through the bridge chip for each set of fine pitch connections. After bonding the bridge chip 514 to each of the first and second IC dies 502, 522, underfill material is supplied through the holes. Injecting the underfill material in this way reduces the likelihood of entrapping the filler, which would otherwise affect the structural integrity of the bridge chip assembly, and / or the formation of cracks.

[0075] At least a portion of the structures and methods described above may be implemented in an integrated circuit. In forming an integrated circuit, identical dies are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each die includes the elements described herein and may include other structures and / or circuits. Individual dies are cut or diced from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dice wafers and package dies to make integrated circuits.

[0076] Those skilled in the art will understand that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare die, in packaged form, or incorporated as part of an intermediate or final product that benefits from having a multi-die structure formed in accordance with one or more of the exemplary embodiments.

[0077] The figures of the embodiments described in this specification are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and / or features of the apparatuses, methods, and systems that may use the structures and techniques described herein. Given the teachings herein, many other embodiments will be apparent to those of ordinary skill in the art. From these, other embodiments may be utilized and derived, thereby enabling structural and logical substitutions and changes without departing from the scope of the present disclosure. It should also be noted that in some alternative implementations, some of the steps of the exemplary methods described herein may be performed in an order different from that described or shown in the drawings (if there are drawings). For example, two steps described or shown consecutively may actually be performed substantially simultaneously, or a particular step may, in some cases, be performed in the reverse order depending on the relevant functions. Also, the drawings are merely illustrative and not drawn to scale. Accordingly, this specification and the drawings are to be interpreted in an illustrative rather than a limiting sense.

[0078] As used herein, when reference is made to "one embodiment" or "an embodiment", it is intended to mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the claimed subject matter. It should be understood that when the phrase "in one embodiment" or "an embodiment" appears, it does not necessarily refer to the same embodiment. Further, although multiple embodiments may be referred to herein individually and / or collectively by the term "embodiment", this is merely for convenience and is not intended to limit the scope of the present application to any single embodiment or inventive concept if more than one embodiment or inventive concept is actually disclosed. Thus, it should be understood that, although a particular embodiment is illustrated and described herein, a mechanism for achieving the same purpose may be substituted for the particular embodiment shown. That is, the present disclosure is intended to cover any and all adaptations or variations of various embodiments. Considering the teachings herein, combinations of the above-described embodiments, as well as other embodiments not specifically described herein will be apparent to those of ordinary skill in the art.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprise" and / or "comprises", as used herein, specify the presence of the stated features, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, acts, elements, components, and / or groups thereof. When phrases such as "above ~" and "below ~" are used, it is intended to indicate the relative arrangement of elements or structures rather than absolute height.

[0080] If there are means or step plus function elements within the scope of the following claims, the corresponding structures, materials, acts, and equivalents of those elements are intended to include any structure, material, or act for performing a function in combination with other claimed elements that are specifically claimed. The descriptions of the various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the embodiments. The embodiments were chosen and described in order to best explain the principles and practical applications, and to enable others of ordinary skill in the art to understand the embodiments with various modifications as are suited to the particular use contemplated.

[0081] An abstract is provided in accordance with 37 C.F.R. § 1.72(b). That section requires an abstract that enables the reader to quickly grasp the characteristics of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Further, in the foregoing detailed description, it can be seen that for the purposes of simplifying the disclosure, various features are grouped in a single embodiment. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as reflected by the appended claims, the claimed subject matter may sometimes not have all of the features of a single embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separately claimed subject matter.

[0082] Considering the teachings provided herein, those of ordinary skill in the art will be able to contemplate other implementations and applications of such techniques and the disclosed embodiments. Illustrative embodiments have been described herein with reference to the accompanying drawings, but the illustrative embodiments are not limited to the precise embodiments shown, and various other changes and modifications will be made by those of ordinary skill in the art without departing from the scope of the appended claims.

Claims

**Claim 1** A method of manufacturing a bridge chip assembly having a non-conductive underfill for interconnecting two or more integrated circuit (IC) dies, each of the IC dies having a first region including a first plurality of connection portions having a first pitch associated therewith, and also having a second region including a second plurality of connection portions or connection pads having a second pitch associated therewith, the first pitch being greater than the second pitch, attaching a non-conductive underfill film to at least the upper surface of the second region of each of the IC dies; bonding a first IC die among the IC dies to a bridge chip using the second plurality of connection portions or connection pads of itself, the bridge chip including at least a first plurality of connection pads or connection portions having the second pitch associated therewith, the first plurality of connection pads or connection portions of the bridge chip being aligned with the corresponding second plurality of connection portions or connection pads of the first IC die among the IC dies; and bonding a second IC die among the IC dies to the bridge chip using the second plurality of connection portions or connection pads of itself, the bridge chip including a second plurality of connection pads or connection portions having the second pitch associated therewith, the second plurality of connection pads or connection portions of the bridge chip being aligned with the corresponding second plurality of connection portions or connection pads of the second IC die among the IC dies; comprising, wherein the bridge chip assembly includes at least the bridge chip bonded to the first IC die and the second IC die, and the non-conductive underfill film disposed between the bridge chip, the first IC die, and the second IC die. **Claim 2** The method according to claim 1, wherein the step of attaching the non-conductive underfill film to at least the upper surface of the second region of each of the IC dies includes laminating the non-conductive underfill film to the upper surface of each of the IC dies in at least the second region of the IC dies. **Claim 3** The method according to claim 1 or 2, wherein a cross-sectional thickness of the non-conductive underfill film matches a height of the first plurality of connection portions above the upper surface of the IC die or is slightly lower than the height.

4. The method according to any one of claims 1 to 3, further comprising the step of bonding the bridge chip assembly to an organic substrate, wherein the organic substrate is adapted to receive the bridge chip such that each of the first plurality of connection portions of the IC die is flush with a corresponding connection pad formed on the upper surface of the organic substrate.

5. The method according to claim 4, further comprising the step of forming a capillary underfill between the bridge chip assembly and the organic substrate.

6. The method according to claim 4 or 5, wherein each of the first plurality of connection portions of the IC die is formed to have a height exceeding a height of the bridge chip after bonding the bridge chip to the IC die, whereby the bridge chip does not prevent bonding of the bridge chip assembly to the organic substrate.

7. The method according to any one of claims 1 to 6, wherein the non-conductive underfill film is configured to cover each of the upper surfaces of the IC die in each of the first region and the second region of the IC die.

8. The method according to any one of claims 1 to 6, wherein the non-conductive underfill film is configured to cover each of the upper surfaces of the IC die in each of the second regions of the IC die and is omitted from each of the first regions of the IC die.

9. The method according to any one of claims 1 to 8, further comprising the steps of forming each of the first plurality of connection portions of the IC die to include a material having a first melting point and forming each of the second plurality of connection portions of the bridge chip to include a material having a second melting point, wherein the first melting point and the second melting point are different.

10. The method according to claim 9, wherein the first melting point is lower than the second melting point, whereby the second plurality of connection portions that couple the bridge chip to the IC die do not melt during bonding of the bridge chip assembly to the organic substrate.

11. The method according to claim 9, wherein the first melting point is higher than the second melting point, so that during the bonding of the bridge chip to the IC die, the first plurality of connection portions adapted to bond the bridge chip assembly to the organic substrate do not melt.

12. The method according to any one of claims 1 to 11, further comprising the step of forming at least one dam on at least one upper surface of one or more of the IC dies of the bridge chip and the IC die, the dam being configured to restrict the flow of the underfill material to only a defined area of the IC die and / or the bridge chip, thereby preventing the underfill material from flowing onto unintended surfaces of the IC die and / or the bridge chip during the bonding of the bridge chip to the IC die.

13. A bridge chip assembly structure, At least first and second integrated circuit (IC) dies, each of the IC dies having a first pitch associated therewith and having a first region including a first plurality of connection portions formed on an upper surface thereof, the first plurality of connection portions including a material having a first melting point and being adapted to bond the bridge chip assembly structure to an organic substrate; A bridge chip having a second pitch associated therewith and having a second plurality of connection portions formed on an upper surface thereof, the first pitch being larger than the second pitch, the second plurality of connection portions being joined to corresponding connection pads formed in a second region of each of the upper surfaces of the IC dies, the second plurality of connection portions having a material having a second melting point, the first melting point and the second melting point being different; and A non-conductive underfill film disposed between at least the upper surface of the second region of each of the IC dies and the bridge chip; A bridge chip assembly structure comprising.

14. The bridge chip assembly structure according to claim 13, wherein the first melting point is lower than the second melting point.

15. The bridge chip assembly structure according to claim 13, wherein the first melting point is higher than the second melting point.

16. Further comprising at least one dam formed on at least one upper surface of one or more of the bridge chip and the IC dies, wherein the dam is configured to restrict the flow of the underfill material only to a defined area of the IC die and / or the bridge chip, the bridge chip assembly structure according to any one of claims 13 to 15.

17. A bridge chip assembly structure, At least first and second integrated circuit (IC) dies, each of the IC dies having a first pitch associated therewith and having a first plurality of connections formed on its upper surface, the first plurality of connections including a material having a first melting point and adapted to bond the bridge chip assembly structure to an organic substrate; and A bridge chip having a second pitch associated therewith and having a second plurality of connections formed on its upper surface, the first pitch being greater than the second pitch, the second plurality of connections being bonded to corresponding connection pads formed on each of the upper surfaces of the IC dies, the second plurality of connections having a material having a second melting point, the first melting point and the second melting point being different; Comprising Here, the bridge chip has at least one opening formed therethrough, the opening being configured to carry an underfill material introduced into the bridge chip assembly structure to fill a space between the bridge chip and the IC die, the bridge chip assembly structure.

18. A bridge chip assembly structure, At least first and second integrated circuit (IC) dies, each of the IC dies having a first pitch associated therewith and having a first plurality of connections formed on its upper surface, the first plurality of connections being configured to bond the bridge chip assembly structure to an organic substrate; A bridge chip having a second pitch associated therewith and having a second plurality of connections formed on its upper surface, the first pitch being greater than the second pitch, the second plurality of connections being bonded to corresponding connection pads formed on each of the upper surfaces of the IC dies, the bridge chip having an opening formed therethrough and configured to carry an underfill material; and An underfill material disposed in an internal space between the bridge chip and the IC die, the underfill material being carried into the internal space through the at least one opening penetrating the bridge chip. A bridge chip assembly structure comprising the same. **Claim 19** The bridge chip assembly structure according to claim 18, further comprising at least one dam formed on at least one upper surface of one or more of the IC dies among the bridge chip and the IC dies, the dam being configured to regulate the flow of the underfill material only to a defined area of the IC die and / or the bridge chip. **Claim 20** A method of manufacturing a bridge chip assembly having a non-conductive underfill for interconnecting two or more integrated circuit (IC) dies, each of the IC dies having a first region including a plurality of connection portions having a first pitch associated therewith, and a second region including a plurality of connection pads having a second pitch associated therewith, the first pitch being greater than the second pitch. Providing a bridge chip including at least a first and a second plurality of connection portions having the second pitch associated therewith. Attaching a non-conductive underfill film to an upper surface of the bridge chip to cover the first and second plurality of connection portions. Bonding a first IC die among the IC dies to the bridge chip using the plurality of connection pads of the first IC die itself, the first plurality of connection portions of the bridge chip being aligned with the corresponding plurality of connection pads of the first IC die among the IC dies; and Bonding a second IC die among the IC dies to the bridge chip using the plurality of connection pads of the second IC die itself, the second plurality of connection portions of the bridge chip being aligned with the corresponding plurality of connection pads of the second IC die among the IC dies. Comprising wherein the bridge chip assembly includes the bridge chip bonded to at least the first IC die and the second IC die, and the non-conductive underfill film disposed between the bridge chip, the first IC die, and the second IC die.

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