Reduction of Resistance Drift in Non-Volatile Memory Cells

Abstract

A mushroom-type phase change memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a drift mitigation liner surrounding an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on an upper surface of the liner and the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on the exposed portion of the first dielectric layer and the top electrode, the second dielectric layer being disposed on sidewalls of the liner, the PCM element, and the top electrode.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly, to a method of forming a mushroom-type phase change memory (PCM) device having a drift-mitigation liner, wherein the bottom surface of the phase change material is in direct contact with both the drift-mitigation liner and the bottom electrode.

Background Art

[0002] Phase change memory (PCM) is based on a chalcogenide glass material that changes its phase from crystalline to amorphous and back again when an appropriate current is applied. The GST alloy (germanium-antimony-tellurium or Ge2Sb2Te5) is one such chalcogenide glass material. Each phase has a different resistance level that is stable until the phase changes. The maximum and minimum resistance levels in a PCM device are the basis for binary values of 1 or 0.

[0003] During electrical programming of a PCM device, at least a portion (or in some cases, all) of the phase change material undergoes a phase transformation, thereby changing the electrical resistance of the PCM device.

[0004] The phase change material undergoes significant resistance drift in the amorphous phase, and the resistance increases over time according to an exponential law. It is necessary to reduce resistance drift in analog computing applications that require multiple states for calculations.

[0005] Resistance drift over time is a particularly difficult problem for multi-level cell operations such as those used in artificial intelligence training and inference applications. Multi-level cell operations can be compared to conventional (binary) resistive memory cells having two states including a high resistance state and a low resistance state corresponding to 1 or 0. Resistive memory devices are an example of multi-level cell devices having three or more states and are used to represent synaptic weights in artificial neural networks.

[0006] To reduce resistance drift, a liner with adjusted resistivity has been proposed. However, the presence of a resistance liner across the entire bottom electrode can lead to multiple problems such as: (a) an increase in the resistance of the SET state, leading to a decrease in the dynamic range (RESET to SET resistance ratio), and (b) Joule heat may concentrate in the liner film above the bottom electrode, making the cell thermally inefficient and requiring a significant increase in the programming voltage for the phase transition from crystal to amorphous. This can dramatically increase the programming voltage required to achieve the RESET condition where the amorphous volume completely covers the bottom electrode. SUMMARY OF THE INVENTION

[0007] According to one embodiment of the present invention, a mushroom-shaped phase change memory (PCM) device includes a substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed within the first dielectric layer, a drift reduction liner disposed on the first dielectric layer, a PCM element disposed directly on the upper surfaces of the drift reduction liner and the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on the exposed portion of the first dielectric layer and on the top electrode, wherein the second dielectric layer is disposed on the sidewalls of the drift reduction liner, the PCM element, and the top electrode.

[0008] A mushroom-shaped phase change memory (PCM) device includes a substrate, a lower interconnect disposed within the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed within the first dielectric layer and extending above the upper surface of the first dielectric layer, a drift reduction liner surrounding an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the upper surfaces of the liner and the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on the exposed portion of the first dielectric layer and on the top electrode, wherein the second dielectric layer is disposed on the sidewalls of the liner, the PCM element, and the top electrode.

[0009] According to some embodiments, a method of manufacturing a mushroom-shaped phase change memory (PCM) device includes providing an intermediate device including a substrate, a lower interconnect disposed within the substrate, a first dielectric layer disposed on the substrate, a drift reduction liner disposed on the first dielectric layer, and a second dielectric layer formed on the drift reduction liner; sequentially depositing a low temperature oxide (LTO) hard mask layer, a silicon-containing anti-reflective coating (SiARC) layer, and a photoresist (PR) layer on the intermediate device; patterning the PR layer to form a PR mask; forming a bottom electrode via by patterning through the drift reduction liner layer using the PR mask; removing the LTO hard mask layer; performing a bottom electrode metallization process to form a bottom electrode metal; polishing the PCM device to expose the second dielectric layer; removing the remaining portion of the second dielectric layer; depositing a PCM layer and a top electrode metal, wherein the PCM layer is deposited directly on the drift reduction liner and the bottom electrode; patterning the drift reduction liner layer, the PCM layer, and the top electrode metal to form the drift reduction liner, the PCM, and the top electrode; depositing a third dielectric layer on the PCM device; depositing an oxide interlayer dielectric (ILD) on the PCM device; and planarizing the PCM device.

[0010] As used herein, "facilitating" an action includes performing the action, making the action easier, assisting in performing the action, or causing the action to be performed. Thus, by way of example and not limitation, instructions executed by one processor can facilitate an action executed by instructions of a remote processor by sending appropriate data or commands to cause or assist in the action being performed. To avoid misunderstanding, if an actor facilitates an action other than by performing the action, the action is still performed by some entity or combination of entities.

[0011] One or more embodiments of the invention, or elements thereof, can be implemented in the form of a computer program product that includes a computer-readable storage medium having computer-usable program code for performing the illustrated method steps. Further, one or more embodiments of the invention, or elements thereof, can be implemented in the form of a system (or apparatus) that includes a memory and at least one processor coupled to the memory and operative to perform exemplary method steps. Further, in another aspect, one or more embodiments of the invention, or elements thereof, can be implemented in the form of means for performing one or more of the method steps described herein, the means including (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii), any of (i)-(iii) implementing the specific techniques described herein.

[0012] The technology of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments have a structure capable of reducing resistance drift without an increase in programming voltage, and A structure in which the read resistance in the SET state does not increase due to the presence of a liner, and thus a larger dynamic range (SET / RESET resistance ratio) is maintained. can be provided.

[0013] These and other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention, which should be read in conjunction with the accompanying drawings.

[0014] Preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Embodiments of the present invention are directed to a mushroom-shaped PCM device including a drift reduction liner, where a bottom electrode is in direct contact with the PCM and the drift reduction liner is in contact with the side surface of the bottom electrode. This structure achieves reduction of resistance drift without increasing the programming voltage (and current) and without affecting the SET resistance as compared to a memory cell without a liner.

[0017] FIG. 1 shows a cross-section of a mushroom-shaped PCM device 100 according to an embodiment of the present invention. Referring to FIG. 1, the mushroom-shaped PCM device 100 includes a substrate 101 and a lower interconnect 102 (lower wiring level). The mushroom-shaped PCM device 100 is encapsulated within a first dielectric layer 103 (e.g., a silicon nitride (SiN) layer) and an oxide 111. The mushroom-shaped PCM device 100 further includes a bottom electrode 104 including an outer portion 105 formed of tantalum nitride (TaN), an intermediate portion 106 formed of titanium nitride (TiN), and an inner portion 107 formed of TaN. The upper portion of the bottom electrode 104 is surrounded by a liner 108. According to some embodiments of the present invention, the liner 108 does not cover the top of the bottom electrode 104. PCM 109 is formed on the upper surfaces of the bottom electrode 104 and the liner 108, and a top electrode 110 is formed on the PCM 109. According to one or more embodiments, the PCM 109 is in direct contact with both the bottom electrode 104 and the liner 108.

[0018] The liner 108 can be formed of, for example, a carbon material, TiN, TaN, titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), hafnium nitride (HfN), or tungsten carbide (WC).

[0019] The PCM 109 can be formed of, for example, GST (germanium - antimony - tellurium or Ge2Sb2Te5), GeTe, Sb2Te3, Sb, or other binary or ternary alloy compositions having Ge, Te, and Sb. The PCM 109 can include additional dopants including carbon, nitrogen, silicon, silicon dioxide, silicon carbide, or SiN.

[0020] According to some embodiments, as shown in FIG. 1, the liner 108 is a drift - reducing liner in direct contact with the PCM 109, and the bottom electrode 104 is also in direct contact with the PCM 109. According to at least one embodiment, the liner 108 does not cover the top of the bottom electrode 104. According to some embodiments, the liner 108 may partially cover the upper part of the bottom electrode. According to at least one embodiment, the liner 108 extends along the entire width of the PCM 109, and the liner 108 is not in direct contact with the top electrode 110.

[0021] The top electrode 110 and the bottom electrode 104 can be formed of, for example, TiN, TaN, tungsten nitride (WN), HfN, WC, TiC, or TaC. According to some embodiments, the electrodes can be formed of a single layer or multiple layers of the aforementioned films. According to some embodiments, the bottom electrode 104 includes a SiN film as one of the layers.

[0022] FIGS. 2 - 4 show the temperature profiles of different devices when 2.5 volts (V) is applied.

[0023] FIG. 2 shows a prior art device 200 that includes a liner 201 that completely separates the bottom electrode 202 from the PCM 203. When a voltage (e.g., 2.5V) is applied across the device 200, due to a significant voltage drop across the ends of the liner 201 immediately above the bottom electrode 202 and the concentration of Joule heat in the liner 201, the temperature of the PCM 203 does not reach the melting point (i.e., the temperature required for the amorphous phase transition).

[0024] FIG. 3 shows a mushroom-shaped PCM device 100 according to an embodiment of the present invention. In this device, the liner 108 includes an opening through which the bottom electrode 104 extends, and the liner 108 and the bottom electrode are in contact with the PCM 109. That is, the liner 108 does not cover the top of the bottom electrode 104, and the PCM 109 is in direct contact with both the bottom electrode 104 and the liner 108. As shown in FIG. 3, when a voltage of 2.5V is applied, the temperature of the PCM 109 is heated to a minimum temperature of 5.231e+02 Kelvin (K), resulting in a reduction in the SET resistance, an increase in the dynamic range, and a reduction in the switching voltage.

[0025] FIG. 4 shows a prior art device 400 in which the liner is omitted such that the bottom electrode 401 contacts the PCM 402, and the PCM 402 contacts the underlying liner without reducing resistance drift.

[0026] FIG. 5 is a graph 500 showing the effect of voltage on the different devices of FIGS. 2 - 4. FIG. 5 shows the characteristics of the resistance versus the programming voltage for the devices 100, 200, and 400.

[0027] Device 100 according to some embodiments of the present invention, having a liner that does not cover the top of the bottom electrode and with the PCM in direct contact with both the bottom electrode and the liner, shows that the SET state resistance (lowest resistance state) 501 does not change compared to the case of device 400 without a liner. That is, device 100 has a large dynamic range (high resistance to low resistance ratio). It should be noted that the SET state resistance of device 200 with the liner disposed on the bottom electrode is relatively high (see, for example, 503), and as a result, the dynamic range decreases.

[0028] Furthermore, device 100 of the present invention has a programming voltage 502 (the voltage at which the device switches from the low resistance state to the high resistance state) that is smaller than the programming voltage of device 200 with the liner disposed on the bottom electrode (see, for example, the programming voltage of 504), enabling lower voltage operation. By reducing the programming voltage, the area footprint of the unit cell (e.g., the smallest circuit block) required for applications including artificial intelligence can be reduced.

[0029] According to some embodiments, a method 600 for manufacturing a non-volatile memory cell including a drift reduction liner in direct contact with the PCM and with the bottom electrode also in direct contact with the PCM is shown in FIG. 6. In block 601, an intermediate device is provided that includes a substrate, and a lower interconnect, a first dielectric layer, a liner layer, and a second dielectric layer disposed within the substrate (see FIG. 7). The first and second dielectric layers can be formed of, for example, SiN. According to some embodiments, the second dielectric layer is a sacrificial SiN film that encapsulates the liner layer, which prevents oxidation of the liner layer during subsequent process steps (e.g., patterning of the bottom electrode via).

[0030] The liner layer can be deposited, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0031] In block 602, the method includes depositing a stack for patterning the bottom electrode via (see FIG. 8). The stack can include a low temperature oxide (LTO) hard mask layer, a silicon-containing anti-reflective coating (SiARC) layer, and a photoresist (PR) layer. In block 603, the PR layer is patterned to form a PR mask.

[0032] In block 604, the bottom electrode via is patterned through the drift reduction liner layer using the PR mask (see FIG. 9).

[0033] In block 605, the LTO hard mask is removed (e.g., by a wet etching process), and in block 606, a bottom electrode metallization process is performed. The bottom electrode metallization process can include sequentially depositing a first TaN layer, a TiN layer, and a second TaN layer (see FIG. 10). In block 607, the device is polished and stops on or within the second dielectric layer.

[0034] In block 608, a wet etching is performed to remove the remaining portion of the second dielectric layer. According to some embodiments, the wet etching does not affect the liner layer (see FIG. 11).

[0035] In block 609, a PCM layer and a top electrode metal are deposited (see FIG. 12).

[0036] According to some embodiments, the PCM layer and the top electrode metal are deposited by PVD.

[0037] In block 610, the drift reduction liner layer, the PCM layer, and the top electrode metal are patterned to form a drift reduction liner, a PCM, and a top electrode. Further, a third dielectric layer (e.g., of SiN) is deposited over the non-volatile memory cell, an oxide interlayer dielectric (ILD) is deposited and planarized to form the device 100 of FIG. 1.

[0038] In block 611, subsequent wiring levels can be formed on the resulting device 100.

[0039] Referring to FIGS. 7-12, in a method for manufacturing a non-volatile memory cell 100 including a drift reduction liner in direct contact with a PCM as shown in FIG. 1, FIG. 7 shows an intermediate device 700 including a substrate 101 and a lower interconnect 102 disposed within the substrate, a first dielectric layer 701, a drift reduction liner layer 702, and a second dielectric layer 703. The first and second dielectric layers can be formed of, for example, SiN. According to some embodiments, the second dielectric layer is a sacrificial SiN film that encapsulates the liner layer, which prevents oxidation of the liner layer during subsequent process steps (e.g., bottom electrode via patterning). The liner layer 702 can be deposited, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0040] FIG. 8 shows a deposited stack 800 for patterning a bottom electrode via (not shown). The stack 800 can include an LTO hard mask layer 801, a SiARC layer 802, and a PR layer 803. The PR layer is patterned to form a PR mask (not shown) by a photolithography process.

[0041] According to some embodiments, the bottom electrode via 901 is patterned through the drift reduction liner layer 702 using the PR layer as a mask (see FIG. 9). The bottom electrode via 901 extends to the lower interconnect 102. The PR mask (not shown) can be removed, for example, by a solvent.

[0042] As shown in FIG. 10, the LTO hard mask 801 is removed to expose the second dielectric layer 703. A bottom electrode metallization process is performed to form a bottom electrode 104 including an outer portion 105 formed of TaN, an intermediate portion 106 formed of TiN, and an inner portion 107 formed of TaN. For example, the bottom electrode metallization process includes sequentially depositing layers of TaN, TiN, and TaN. The device 1000 of FIG. 10 is polished to expose the second dielectric layer 703. The bottom electrode metallization process can include sequentially depositing a first TaN layer, a TiN layer, and a second TaN layer (see FIG. 10).

[0043] According to some embodiments, wet etching is performed to remove the remaining portion of the second dielectric layer 703 (see FIG. 10) without affecting the drift reduction liner layer 702 (see FIG. 11).

[0044] FIG. 12 shows a PCM layer 1201 and a top electrode metal 1202 deposited on the drift reduction liner layer 702. According to some embodiments, the PCM layer 1201 and the top electrode metal 1202 are deposited by PVD.

[0045] The drift reduction liner layer 702, the PCM layer 1201, and the top electrode metal 1202 are patterned to form a drift reduction liner 108, a PCM 109, and a top electrode 110 as shown in FIG. 1. Further, a third dielectric layer 112 (e.g., SiN) is deposited over the non-volatile memory cell, and an oxide interlayer dielectric (ILD) 111 is deposited and planarized (see FIG. 1).

[0046] Summary:

[0047] According to an embodiment of the present invention, a mushroom-type phase change memory (PCM) device includes a substrate (101), a first dielectric layer (103) disposed on the substrate, a bottom electrode (104) disposed within the first dielectric layer, a drift reduction liner (108) disposed on the first dielectric layer, a PCM element (109) disposed directly on the upper surfaces of the drift reduction liner and the bottom electrode, a top electrode (110) disposed on the PCM element, and a second dielectric layer (112) disposed on the exposed portion of the first dielectric layer and the top electrode, and the second dielectric layer is disposed on the sidewalls of the drift reduction liner, the PCM element, and the top electrode.

[0048] According to some embodiments, a mushroom-type phase change memory (PCM) device includes a substrate (101), a lower interconnect (102) disposed within the substrate, a first dielectric layer (103) disposed on the substrate, a bottom electrode (104) disposed within the first dielectric layer and extending above the upper surface of the first dielectric layer, a drift reduction liner (108) surrounding an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element (109) disposed on the upper surfaces of the liner and the bottom electrode, a top electrode (110) disposed on the PCM element, and a second dielectric layer (112) disposed on the exposed portion of the first dielectric layer and the top electrode, and the second dielectric layer is disposed on the sidewalls of the liner, the PCM element, and the top electrode.

[0049] According to some embodiments, a method of manufacturing a mushroom-type phase change memory (PCM) device includes providing an intermediate device (801) comprising a substrate, a lower interconnect disposed within the substrate, a first dielectric layer disposed on the substrate, a drift reduction liner disposed on the first dielectric layer, and a second dielectric layer formed on the drift reduction liner; sequentially depositing a low temperature oxide (LTO) hard mask layer, a silicon-containing anti-reflective coating (SiARC) layer, and a photoresist (PR) layer on the intermediate device (802); patterning the PR layer to form a PR mask (803); forming bottom electrode vias by patterning through the drift reduction liner layer using the PR mask (804); removing the LTO hard mask layer (805); performing a bottom electrode metallization process to form a bottom electrode metal (806); polishing the PCM device to expose the second dielectric layer (807); removing the remaining portion of the second dielectric layer (808); depositing a PCM layer and a top electrode metal (809); patterning the drift reduction liner layer, the PCM layer, and the top electrode metal to form a drift reduction liner, a PCM, and a top electrode (810); depositing a third dielectric layer on the PCM device (810); depositing an oxide interlayer dielectric (ILD) on the PCM device (810); and planarizing the PCM device (810).

[0050] As used herein, references to "one embodiment" or "an embodiment" of the present principles and other variations thereof mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment of the present principles. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" and any other variations thereof appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0051] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative embodiments, the functions shown in the blocks may be performed in an order different from that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagram or flowchart, or combinations of blocks of the block diagram or flowchart, or both, can be implemented by a dedicated hardware-based system that performs the specified function or act, or a combination of dedicated hardware and computer instructions.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" or "comprising", or both, when used herein, specify the presence of the stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0053] In addition to all means or steps in the following claims, corresponding structures, materials, acts, and equivalents of functional elements are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed. The descriptions of various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or technical improvements to technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A mushroom-type phase change memory (PCM) device, comprising: a substrate; a first dielectric layer disposed on the substrate; a bottom electrode disposed within the first dielectric layer; a drift reduction liner disposed on the first dielectric layer; a PCM element disposed directly on the upper surfaces of the drift reduction liner and the bottom electrode; a top electrode disposed on the PCM element; a second dielectric layer disposed on the exposed portion of the first dielectric layer and on the top electrode, the second dielectric layer being disposed on the sidewalls of the drift reduction liner, the PCM element, and the top electrode; and comprising; further comprising an oxide layer disposed on the PCM device, the PCM device being planarized up to the top of the second dielectric layer, a mushroom-type phase change memory (PCM) device.

2. A mushroom-type phase change memory (PCM) device, comprising: a substrate; a first dielectric layer disposed on the substrate; a bottom electrode disposed within the first dielectric layer; a drift reduction liner disposed on the first dielectric layer; a PCM element disposed directly on the upper surfaces of the drift reduction liner and the bottom electrode; a top electrode disposed on the PCM element; a second dielectric layer disposed on the exposed portion of the first dielectric layer and on the top electrode, the second dielectric layer being disposed on the sidewalls of the drift reduction liner, the PCM element, and the top electrode; and comprising; the bottom electrode includes an outer portion formed of tantalum nitride (TaN), an intermediate portion formed of titanium nitride (TiN), and an inner portion formed of TaN, a mushroom-type phase change memory (PCM) device.

3. The PCM device according to claim 1 or 2, wherein the first dielectric layer and the second dielectric layer are formed of silicon nitride (SiN).

4. The PCM device according to any one of claims 1 to 3, wherein the PCM element is formed of a material formed of a germanium-antimony-tellurium (GST) material.

5. The PCM device according to any one of claims 1 to 3, wherein the PCM element is formed of a binary or ternary alloy composition containing at least one of germanium (Ge), antimony (Sb), and tellurium (Te).

6. The PCM device according to any one of claims 1 to 5, wherein the PCM element contains a dopant.

7. A mushroom-type phase change memory (PCM) device, comprising: a substrate; a lower interconnect disposed within the substrate; a first dielectric layer disposed on the substrate; a bottom electrode disposed within the first dielectric layer and extending above the upper surface of the first dielectric layer; a drift reduction liner surrounding an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer; a PCM element disposed on the drift reduction liner and the upper surface of the bottom electrode; a top electrode disposed on the PCM element; a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, the second dielectric layer being disposed on sidewalls of the drift reduction liner, the PCM element, and the top electrode; A mushroom-type phase change memory (PCM) device comprising the above.

8. The PCM device according to claim 7, wherein the first dielectric layer and the second dielectric layer are formed of silicon nitride (SiN).

9. The PCM device according to claim 7 or 8, further comprising an oxide layer disposed on the PCM device, and the PCM device being planarized up to the top of the second dielectric layer.

10. The PCM device according to any one of claims 7 to 9, wherein the bottom electrode includes an outer portion formed of tantalum nitride (TaN), an intermediate portion formed of titanium nitride (Ti), and an inner portion formed of TaN.

11. The PCM device according to any one of claims 7 to 10, wherein the upper surface of the bottom electrode is in direct contact with the PCM element.

12. The PCM device according to any one of claims 7 to 11, wherein the PCM element is formed of a material formed of a germanium-antimony-tellurium (GST) material.

13. The PCM device according to any one of claims 7 to 11, wherein the PCM element is formed of a binary or ternary alloy composition containing at least one of germanium (Ge), antimony (Sb), and tellurium (Te).

14. The PCM device according to any one of claims 7 to 13, wherein the PCM element contains a dopant.

15. A method of manufacturing a mushroom-type phase change memory (PCM) device, comprising: Prepare an intermediate device comprising a substrate, and a lower interconnect disposed within the substrate, a first dielectric layer disposed on the substrate, a drift reduction liner disposed on the first dielectric layer, and a second dielectric layer formed on the drift reduction liner. Sequentially deposit a low-temperature oxide (LTO) hard mask layer, a silicon-containing antireflective coating (SiARC) layer, and a photoresist (PR) layer on the intermediate device. Pattern the PR layer to form a PR mask. Form a bottom electrode via by patterning through the drift reduction liner using the PR mask. Remove the LTO hard mask layer. Perform a bottom electrode metallization process to form a bottom electrode. Polish the PCM device to expose the second dielectric layer. Remove the remaining portion of the second dielectric layer. Deposit a PCM layer and a top electrode metal, wherein the PCM layer is directly deposited on the drift reduction liner and the bottom electrode. Pattern the drift reduction liner, the PCM layer, and the top electrode metal to form the drift reduction liner, PCM, and top electrode. Deposit a third dielectric layer on the PCM device. Deposit an oxide interlayer dielectric (ILD) on the PCM device. Planarize the PCM device. A method comprising the above steps.

16. The method according to claim 15, wherein the bottom electrode metallization process comprises sequentially depositing a first tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, and a second TaN layer.

17. The method according to claim 15 or 16, wherein the planarization of the PCM device exposes the upper surface of the third dielectric layer.

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