Semiconductor memory device

Abstract

To provide a semiconductor storage device which operates at high speed.SOLUTION: A semiconductor storage device has: a first pad which is capable of transmitting and receiving a first timing signal; a second pad which is capable of transmitting and receiving a data signal in accordance with the first timing signal; a third pad which is capable of receiving a second timing signal; a fourth pad which is capable of receiving control information in accordance with the second timing signal; a memory cell array; a sense amplifier which is connected to this; a first register which is connected to this; a second register which is capable of storing first control information; a third register which is capable of storing second control information; and a control circuit which outputs, from the first pad, the data stored in the first register and which is capable of executing data out. The first control information is stored into the second register based on input into the fourth pad in accordance with the second timing signal corresponding to an i cycle. The second control information is stored into the third register based on input into the fourth pad in accordance with the second timing signal corresponding to a j cycle.SELECTED DRAWING: Figure 24

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] A semiconductor memory device including a memory cell array including a plurality of memory cells and a peripheral circuit connected to the memory cell array and outputting user data in response to an input of a command set including command data and address data is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device that operates at high speed.

Means for Solving the Problems

[0005] A semiconductor memory device according to an embodiment includes a first pad capable of transmitting and receiving a first timing signal, a second pad capable of transmitting and receiving a data signal in response to the first timing signal, a third pad capable of receiving a second timing signal, a fourth pad capable of receiving control information in response to the second timing signal, a memory cell array including a string in which a plurality of memory cell transistors are connected in series, a sense amplifier connected to the memory cell array, a first register connected to the sense amplifier and capable of storing data read from the memory cell array, a second register capable of storing first control information, a third register capable of storing second control information, and a control circuit capable of executing data out for outputting the data stored in the first register from the first pad. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal for i cycles (i is an integer of 2 or more). The second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal for j cycles (j is an integer different from i).

Brief Description of the Drawings

[0006]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention.

[0008] Also, in this specification, the term "semiconductor memory device" may mean a memory die (memory chip), or may mean a memory system including a controller die such as a memory card or an SSD. Further, it may mean a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] In addition, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, for example, this circuit or the like includes a transistor or the like, this transistor or the like is provided in the current path between the two wirings, and this transistor or the like may mean that it is in the ON state.

[0012] [First Embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0013] The memory system 10 performs a read operation, a write operation, an erase operation, etc. in response to a signal transmitted from the host computer 20. The memory system 10 is, for example, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD for storing user data, and a controller die CD connected to these plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, a RAM, etc., and performs processes such as conversion of logical addresses and physical addresses, bit error detection / correction, garbage collection (compaction), wear leveling, etc.

[0014] Figure 2 is a schematic side view showing a configuration example of the memory system 10 according to the present embodiment. Figure 3 is a schematic plan view showing the same configuration example. For convenience of explanation, some configurations are omitted in Figures 2 and 3.

[0015] As shown in Figure 2, the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory die MD. Among the upper surface of the mounting substrate MSB, pad electrodes P are provided in the regions at the ends in the Y direction, and some other regions are adhered to the lower surface of the memory die MD via an adhesive or the like. Among the upper surface of the memory die MD, pad electrodes P are provided in the regions at the ends in the Y direction, and the other regions are adhered to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. Among the upper surface of the controller die CD, pad electrodes P are provided in the regions at the ends in the Y direction.

[0016] As shown in Figure 3, the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0017] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configurations can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, the controller die CD is stacked on the plurality of memory dies MD, and these configurations are connected by bonding wires B. In such a configuration, the plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD may be included in a package separate from the memory die MD. Also, the plurality of memory dies MD and the controller die CD may be connected to each other via through electrodes or the like instead of bonding wires B.

[0018] [Configuration of Memory Die MD] FIG. 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. FIG. 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD. FIG. 6 is a schematic perspective view showing a part of the configuration of the memory die MD. FIGS. 7 to 9 are schematic circuit diagrams showing a part of the configuration of the memory die MD. For convenience of explanation, some configurations are omitted in FIGS. 4 to 9.

[0019] In addition, FIG. 4 shows a plurality of control terminals and the like. These plurality of control terminals may be represented as control terminals corresponding to a high-active signal (positive logic signal), as control terminals corresponding to a low-active signal (negative logic signal), or as control terminals corresponding to both a high-active signal and a low-active signal. In FIG. 4, the reference signs of the control terminals corresponding to the low-active signal include an overline (upper line). In this specification, the reference signs of the control terminals corresponding to the low-active signal include a slash (" / "). Note that the description in FIG. 4 is an example, and specific aspects can be adjusted as appropriate. For example, it is also possible to use some or all of the high-active signals as low-active signals, or some or all of the low-active signals as high-active signals.

[0020] Also, arrows indicating the input / output direction are shown beside the plurality of control terminals shown in FIG. 4. In FIG. 4, the control terminals with arrows from left to right can be used for input of data or other signals from the controller die CD to the memory die MD. In FIG. 4, the control terminals with arrows from right to left can be used for output of data or other signals from the memory die MD to the controller die CD. In FIG. 4, the control terminals with arrows in both left and right directions can be used for both input of data or other signals from the controller die CD to the memory die MD and output of data or other signals from the memory die MD to the controller die CD.

[0021] As shown in FIG. 4, the memory die MD includes a memory cell array MCA0, MCA1 for storing user data and a peripheral circuit PC connected to the memory cell arrays MCA0, MCA1. In the following description, the memory cell arrays MCA0, MCA1 may be referred to as the memory cell array MCA. Also, the memory cell arrays MCA0, MCA1 may be referred to as planes PLN0, PLN1.

[0022] [Configuration of Memory Cell Array MCA] As shown in FIG. 5, the memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string units SU. Each of these plurality of string units SU includes a plurality of memory strings MS. One end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. Also, the other end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0023] The memory string MS includes a drain side selection transistor STD, a plurality of memory cells MC (memory cell transistors), a source side selection transistor STS, and a source side selection transistor STSb connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb may be simply referred to as selection transistors (STD, STS, STSb).

[0024] The memory cell MC is a field-effect transistor including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores one-bit or multiple-bits of user data. Incidentally, word lines WL are respectively connected to the gate electrodes of a plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK, respectively.

[0025] The selection transistors (STD, STS, STSb) are field-effect transistors including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines (SGD, SGS, SGSb) are respectively connected to the gate electrodes of the selection transistors (STD, STS, STSb). The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all the memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all the memory strings MS in the memory block BLK. The source-side selection gate line SGSb is commonly connected to all the memory strings MS in the memory block BLK.

[0026] The memory cell array MCA is provided above the semiconductor substrate 100, as shown in FIG. 6, for example. Incidentally, in the example of FIG. 6, a plurality of transistors Tr constituting the peripheral circuit PC are provided between the semiconductor substrate 100 and the memory cell array MCA.

[0027] The memory cell array MCA includes a plurality of memory blocks BLK arranged in the Y direction. Further, an inter-block insulating layer ST such as silicon oxide (SiO2) is provided between two adjacent memory blocks BLK in the Y direction.

[0028] As shown in FIG. 6 for example, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0029] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Further, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0030] Among the plurality of conductive layers 110, two or more conductive layers 110 located at the lowermost layer function as gate electrodes of the source side selection gate lines SGS, SGSb (FIG. 5) and a plurality of source side selection transistors STS, STSb connected thereto. These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0031] Also, the plurality of conductive layers 110 located above this function as gate electrodes of the word line WL (FIG. 5) and a plurality of memory cells MC (FIG. 5) connected thereto. These plurality of conductive layers 110 are electrically independent for each memory block BLK, respectively.

[0032] Also, one or more conductive layers 110 located above this function as gate electrodes of the drain side selection gate line SGD and a plurality of drain side selection transistors STD (FIG. 5) connected thereto. These plurality of conductive layers 110 are smaller in width in the Y direction than the other conductive layers 110.

[0033] Below the conductive layer 110, a semiconductor layer 112 is provided. The semiconductor layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Also, an insulating layer 101 such as silicon oxide (SiO2) is provided between the semiconductor layer 112 and the conductive layer 110.

[0034] The semiconductor layer 112 functions as a source line SL (FIG. 5). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0035] The semiconductor pillars 120 are arranged in a predetermined pattern in the X direction and the Y direction as shown in FIG. 6, for example. The semiconductor pillars 120 function as channel regions of a plurality of memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS (FIG. 5). The semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially cylindrical shape as shown in FIG. 6, for example, and an insulating layer 125 such as silicon oxide is provided in the central portion. Also, the outer peripheral surfaces of the semiconductor pillars 120 are each surrounded by the conductive layer 110 and face the conductive layer 110.

[0036] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via the contacts Ch and Cb.

[0037] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are insulating films such as silicon oxide (SiO2), for example. The charge storage film is a film capable of storing charges such as silicon nitride (Si3N4), for example. The tunnel insulating film, the charge storage film, and the block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0038] Further, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities, for example.

[0039] A plurality of contacts CC are provided at the ends of the plurality of conductive layers 110 in the X direction. The plurality of conductive layers 110 are connected to the peripheral circuit PC via these plurality of contacts CC. As shown in FIG. 6, these plurality of contacts CC extend in the Z direction and are connected to the conductive layer 110 at the lower end. The contact CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0040] [Configuration of Peripheral Circuit PC] As shown in FIG. 4, for example, the peripheral circuit PC includes row decoders RD0 and RD1 respectively connected to memory cell arrays MCA0 and MCA1, and sense amplifiers SA0 and SA1. Further, the peripheral circuit PC includes a voltage generation circuit VG and a sequencer SQC. Further, the peripheral circuit PC includes an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, a status register STR, and a data output timing adjustment unit TCT. In the following description, the row decoders RD0 and RD1 may be referred to as the row decoder RD, and the sense amplifiers SA0 and SA1 may be referred to as the sense amplifier SA.

[0041] [Configuration of Row Decoder RD] As shown in FIG. 5, for example, the row decoder RD (FIG. 4) includes an address decoder 22 that decodes address data Add (FIG. 4), and a block selection circuit 23 and a voltage selection circuit 24 that transfer an operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0042] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the row address RA of the address register ADR (FIG. 4) according to a control signal from, for example, the sequencer SQC, decodes this row address RA, turns on a predetermined block selection transistor 35 and voltage selection transistor 37 corresponding to the row address RA, and turns off the other block selection transistors 35 and voltage selection transistors 37. For example, the voltages of a predetermined block selection line BLKSEL and the voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. When P-channel type transistors instead of N-channel type transistors are used, reverse voltages are applied to these wirings.

[0043] In the illustrated example, one block selection line BLKSEL is provided for each memory block BLK in the address decoder 22. However, this configuration can be changed as appropriate. For example, one block selection line BLKSEL may be provided for each of two or more memory blocks BLK.

[0044] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory block BLK. Each of these plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word line WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistor 35 is, for example, a field effect type withstand voltage transistor. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word line WL or selection gate lines (SGD, SGS, SGSb), respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24, respectively. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0045] The block selection circuit 23 further includes a plurality of transistors (not shown). These plurality of transistors are for the selection gate lines (SGD, SGS, SGSb) and the ground voltage V SSIt is a field - effect breakdown voltage transistor connected between voltage supply lines to which voltage is supplied. These multiple transistors supply a ground voltage V SS to the selection gate lines (SGD, SGS, SGSb) included in the non - selected memory block BLK. Note that the multiple word lines WL included in the non - selected memory block BLK are in a floating state.

[0046] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). These multiple voltage selection units 36 each include a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field - effect breakdown voltage transistor. The drain terminal of the voltage selection transistor 37 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23 respectively. The source terminal is electrically connected to the corresponding voltage supply line 31 respectively. The gate electrode is connected to the corresponding voltage selection line 33 respectively.

[0047] [Configuration of Sense Amplifier SA] The sense amplifiers SA0, SA1 (Fig. 4) each include a sense amplifier module SAM0, SAM1 and cache memories CM0, CM1 (data registers). The cache memories CM0, CM1 each include latch circuits XDL0, XDL1.

[0048] In the following description, the sense amplifier modules SAM0, SAM1 may be referred to as the sense amplifier module SAM, the cache memories CM0, CM1 may be referred to as the cache memory CM, and the latch circuits XDL0, XDL1 may be referred to as the latch circuit XDL.

[0049] The sense amplifier module SAM includes, for example, sense circuits respectively corresponding to a plurality of bit lines BL, and a plurality of latch circuits and the like connected to the sense circuits.

[0050] The cache memory CM includes a plurality of latch circuits XDL. The plurality of latch circuits XDL are respectively connected to the latch circuits in the sense amplifier module SAM. The latch circuit XDL holds, for example, user data Dat written to the memory cell MC or user data Dat read from the memory cell MC.

[0051] For example, as shown in FIG. 7, a column decoder COLD is connected to the cache memory CM. The column decoder COLD decodes the column address CA (FIG. 4) held in the address register ADR (FIG. 4) and selects the latch circuit XDL corresponding to the column address CA.

[0052] In addition, the user data Dat held in these plurality of latch circuits XDL is sequentially transferred to the latch circuits in the sense amplifier module SAM during the write operation. Also, the user data Dat included in the latch circuits in the sense amplifier module SAM is sequentially transferred to the latch circuits XDL during the read operation. Further, the user data Dat included in the latch circuit XDL is sequentially transferred to the input / output control circuit I / O via the column decoder COLD and the multiplexer MPX during data output described later.

[0053] [Configuration of Voltage Generation Circuit VG] The voltage generation circuit VG (FIG. 4) is connected to a plurality of voltage supply lines 31, for example, as shown in FIG. 5. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down circuit and step-up circuit are respectively connected to the power supply voltage V CC and the ground voltage V SS(FIG. 4) is connected to the voltage supply lines to which voltage is supplied. These voltage supply lines are connected to, for example, the pad electrodes P described with reference to FIGS. 2 and 3. The voltage generation circuit VG generates, for example, a plurality of operation voltages to be applied to the bit lines BL, source lines SL, word lines WL, and selection gate lines (SGD, SGS, SGSb) during a read operation, write operation, and erase operation on the memory cell array MCA according to a control signal from the sequencer SQC, and outputs them to the plurality of voltage supply lines 31 simultaneously. The operation voltage output from the voltage supply line 31 is appropriately adjusted according to a control signal from the sequencer SQC.

[0054] [Configuration of Sequencer SQC] The sequencer SQC (FIG. 4) outputs internal control signals to the row decoders RD0, RD1, the sense amplifier modules SAM0, SAM1, and the voltage generation circuit VG according to the command data Cmd held in the command register CMR. Further, the sequencer SQC appropriately outputs status data Stt indicating the state of the memory die MD to the status register STR.

[0055] Also, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY becomes the "L" state during an operation of supplying voltage to the memory cell array MCA, such as a read operation, write operation, erase operation, or during the execution of a get feature, set feature, etc. described later, and becomes the "H" state otherwise. Note that even when performing operations such as data out and status read described later, the terminal RY / / BY does not become the "L" state. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Also, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. Note that the terminal RY / / BY is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0056] In addition, the sequencer SQC includes a feature register FR. The feature register FR is a register that holds feature data Fd. The feature data Fd includes, for example, control parameters of the memory die MD, etc. The feature data Fd includes, for example, a value indicating in which of the operation modes MODEa and MODEb, which will be described later, the memory die MD is to operate. Also, the feature data Fd includes, for example, a value, which will be described later, indicating the state of the input / output control circuit I / O.

[0057] [Configuration of Address Register ADR] As shown in FIG. 4, the address register ADR is connected to the input / output control circuit I / O and holds the address data Add input from the input / output control circuit I / O. The address register ADR includes, for example, a plurality of 8-bit register columns. The register columns hold a plurality of address data Add including the address data Add corresponding to the operation being executed and the address data Add corresponding to the next operation to be executed when an internal operation such as a read operation, a write operation, or an erase operation is performed.

[0058] The address data Add includes, for example, a column address CA (FIG. 4) and a row address RA (FIG. 4). The row address RA includes, for example, a block address specifying the memory block BLK (FIG. 5), a page address specifying the string unit SU and the word line WL, a plane address specifying the memory cell array MCA (plane), and a chip address specifying the memory die MD.

[0059] Note that if an operation corresponding to another address data Add is instructed during the execution of an operation corresponding to one address data Add, the intended operation may not be properly executed. For example, in a certain memory die MD, if a data out from one plane is being executed and a data out for another plane (address data Add corresponding to a different plane) is instructed, the operation timing is adjusted so that the next data out is started after the first data out is completed.

[0060] On the other hand, for example, in a configuration where a plurality of memory dies MD are connected as shown in FIGS. 2 and 3, during the execution of data out from a certain memory die MD, when data out for another memory die MD (address data Add corresponding to a different memory die) is instructed, there may be a case where the user data Dat corresponding to the intended address cannot be suitably output.

[0061] The output of the user data Dat is instructed by switching (toggling) the input signals of the external control terminals / RE, RE. In a configuration where a plurality of memory dies MD are connected as shown in FIGS. 2 and 3, during the execution of data out from a certain memory die MD, when data out for another memory die MD (address data Add corresponding to a different memory die) is instructed, there is a possibility that both memory dies MD will execute data out corresponding to the switching (toggle) of the input signals at the external control terminals / RE, RE.

[0062] Therefore, the semiconductor memory device according to the first embodiment is configured such that the switching of the address data Add to be operated on can be executed by the input of a trigger signal. For example, in a configuration where a plurality of memory dies MD are connected as shown in FIGS. 2 and 3, during the execution of data output from a certain memory die MD, when data output for another memory die MD (address data Add corresponding to a different memory die) is instructed, the memory die MD for which data output is later instructed does not start data output even if the input signal at the external control terminals / RE, RE is switched (toggled) until a trigger signal is input. Then, after the controller die CD detects that the data output from the memory die MD that has previously executed data output has ended, it inputs a trigger signal for switching the address data Add to all the memory dies MD connected in common, and then switches (toggles) the input signal of the external control terminals / RE, RE. The memory die MD that has previously executed data output does not react even when receiving a trigger signal from the controller die CD. On the other hand, the memory die MD that has been instructed to perform data output later can execute data output in response to the switching (toggle) of the input signal at the external control terminals / RE, RE by receiving a trigger signal from the controller die CD. Therefore, it is possible to prevent the operations from colliding between the memory die MD that has previously executed data output and the memory die MD that has been instructed to perform data output later. That is, the trigger signal functions as a signal for instructing that data output can be started for the memory die MD. As a result, in a configuration where a plurality of memory dies MD are connected as shown in FIGS. 2 and 3, it becomes possible to continuously execute data output from the plurality of memory dies MD.

[0063] [Configuration of Command Register CMR] The command register CMR is connected to the input / output control circuit I / O and holds the command data Cmd input from the input / output control circuit I / O. The command register CMR includes, for example, at least one set of 8-bit register columns. When the command data Cmd is held in the command register CMR, a control signal is input to the sequencer SQC.

[0064] [Configuration of Status Register STR] The status register STR is connected to the input / output control circuit I / O and holds the status data Stt output to the input / output control circuit I / O. The status register STR includes, for example, a plurality of 8-bit register columns. The register columns hold status data Stt regarding the internal operation being executed, for example, when an internal operation such as a read operation, write operation, or erase operation is executed. Further, the register columns hold, for example, the ready / busy information of the memory cell arrays MCA0 and MCA1.

[0065] [Configuration of Data Output Timing Adjustment Unit TCT] The data output timing adjustment unit TCT is connected to the bus wiring DB between the cache memories CM0 and CM1 and the input / output control circuit I / O. The data output timing adjustment unit TCT adjusts the start timing of data output to the cache memory CM1 in order to start the data output of the cache memory CM1 without a time gap after the completion of the data output of the cache memory CM0, for example, when continuously executing data out to be described later for the cache memories CM0 and CM1.

[0066] [Configuration of Input / Output Control Circuit I / O] The input / output control circuit I / O (Fig. 4) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, and a buffer circuit. Each circuit in the input / output control circuit I / O (Fig. 4) is connected to a terminal to which the power supply voltage V CCQ and the ground voltage V SS (Fig. 4) are supplied. Note that the power supply voltage V CCQ and the ground voltage V SSThe terminal to which it is supplied is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0067] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3. The data input via the data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR according to the internal control signal from the logic circuit CTR. Also, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0068] The signal input via the data strobe signal input / output terminals DQS, / DQS (for example, the data strobe signal and its complementary signal) is used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS (switching of the input signal) and the falling edge of the voltage of the data strobe signal input / output terminal / DQS (switching of the input signal), and at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS (switching of the input signal) and the rising edge of the voltage of the data strobe signal input / output terminal / DQS (switching of the input signal).

[0069] The input / output control circuit I / O (FIG. 4) includes, for example, as shown in FIG. 8, an input circuit 201 and an output circuit 202 connected to each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS. The input circuit 201 is, for example, a receiver such as a comparator. The output circuit 202 is, for example, a driver such as an OCD (Off Chip Driver) circuit.

[0070] In addition, the input / output control circuit I / O (Fig. 4) includes a plurality of latch circuits 203 provided corresponding to each of the data signal input / output terminals DQ0 to DQ7. These plurality of latch circuits 203 are connected to the output terminals of the input circuit 201 connected to the corresponding data signal input / output terminals DQ0 to DQ7. Also, these plurality of latch circuits 203 latch "H" or "L" according to the voltage value of the output terminal of the input circuit 201 at the timing of switching the input signals of the data strobe signal input / output terminals DQS, / DQS as described above.

[0071] In addition, the input / output control circuit I / O (Fig. 4) includes a signal transfer circuit 204 provided corresponding to each of the data strobe signal input / output terminals DQS, / DQS. The signal transfer circuit 204 includes, for example, an even number of CMOS inverters connected in series. The input terminal of the signal transfer circuit 204 is connected to the output terminal of the input circuit 201. The output terminal of the signal transfer circuit 204 is connected to the latch circuit 203.

[0072] In addition, the input / output control circuit I / O (Fig. 4) includes an internal path delay detection circuit 205. As shown in Fig. 9, the internal path delay detection circuit 205 includes a signal transfer circuit 211 and a NAND circuit 212. The signal transfer circuit 211 has the same configuration as the signal transfer circuit 204 described with reference to Fig. 8. The signal transfer circuit 211 functions as a replica of the signal transfer circuit 204. One input terminal of the NAND circuit 212 is connected to the output terminal of the signal transfer circuit 211. An enable signal of the internal path delay detection circuit 205 is input to the other input terminal of the NAND circuit 212. The output terminal of the NAND circuit 212 is connected to the input terminal of the signal transfer circuit 211 and the input terminal of the counter 213.

[0073] Depending on the usage conditions of the semiconductor memory device, the operating state of the signal transfer circuit 204 described with reference to FIG. 8 may vary. In such a case, the delay amount of the signal may differ between the propagation path of the signal corresponding to the data signal input / output terminals DQ0 to DQ7 and the propagation path of the signal corresponding to the data strobe signal input / output terminals DQS, / DQS. The internal path delay detection circuit 205 is a circuit for detecting such a difference in the delay amount of the signal.

[0074] For example, when detecting the delay amount of the signal, the enable signal of the NAND circuit 212 (FIG. 9) is in the “H” state for a certain period. Along with this, the output signal of the NAND circuit 212 oscillates at a frequency corresponding to the delay amount in the signal transfer circuit 211. Therefore, by detecting the number of pulses output from the output terminal of the NAND circuit 212 during this period by the counter 213, the delay amount of the signal in the signal transfer circuits 204 and 211 can be measured. Note that the number of the above pulses is held in the feature register FR as one of the feature data Fd.

[0075] [Configuration of Logic Circuit CTR] The logic circuit CTR (FIG. 4) includes a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP and a logic circuit connected to these plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP. The logic circuit CTR receives an external control signal from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and outputs an internal control signal to the input / output control circuit I / O in response thereto.

[0076] As shown in FIG. 8, for example, the logic circuit CTR includes an input circuit 201 connected to each of the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and an output circuit 202 connected to each of the external control terminals CLE, ALE. Note that each of the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0077] The signal input via the external control terminal / CE (for example, the chip enable signal) is used when selecting the memory die MD. In the first embodiment, the memory die MD to which “L” is input to the external control terminal / CE is in a state where input / output of user data Dat, command data Cmd, and address data Add (hereinafter sometimes simply referred to as “data”) is possible. Also, in the first embodiment, the memory die MD to which “H” is input to the external control terminal / CE is in a state where input / output of data is impossible. Note that, as shown in FIG. 8, the external control terminal / CE is connected to the input circuit 201.

[0078] The signal input via the external control terminal CLE (for example, the command latch enable signal) is used when using the command register CMR or the like. The functions and the like of the external control terminal CLE will be described later.

[0079] The signal input via the external control terminal ALE (for example, the address latch enable signal) is used when using the address register ADR or the like. The functions and the like of the external control terminal ALE will be described later.

[0080] The signal input via the external control terminal / WE (for example, the write enable signal) is used when inputting data from the controller die CD to the memory die MD or the like. The functions and the like of the external control terminal / WE will be described later.

[0081] The signal input via the external control terminals / RE, RE (for example, the read enable signal and its complementary signal) is used when outputting data via the data signal input / output terminals DQ0 to DQ7. The data output from the data signal input / output terminals DQ0 to DQ7 is switched at the timing of the falling edge of the voltage of the external control terminal / RE (switching of the input signal) and the rising edge of the voltage of the external control terminal RE (switching of the input signal), and at the timing of the rising edge of the voltage of the external control terminal / RE (switching of the input signal) and the falling edge of the voltage of the external control terminal RE (switching of the input signal).

[0082] The signal (e.g., light protection signal) input via the external control terminal / WP is used for restricting the input of user data Dat from the controller die CD to the memory die MD, etc.

[0083] Also, the logic circuit CTR includes a switching circuit C20, for example, as shown in FIG. 4. When, in the memory die MD, during the execution of data out from one plane, data out for another plane (address data Add corresponding to a different plane) is instructed, the switching circuit C20 adjusts the operation timing so as to start the next data out after the first data out is completed. Also, as shown in FIGS. 2 and 3, in a configuration where a plurality of memory dies MD are connected, when data out for the memory die MD (address data Add corresponding to a different memory die) is instructed during the execution of data out from another memory die MD, the switching circuit C20 controls so as not to start data out even if the input signal at the external control terminals / RE, RE is switched (toggled) until a trigger signal is received from the controller die CD.

[0084] [Operation Modes MODEa and MODEb] The semiconductor memory device according to the present embodiment can be operated in operation modes MODEa and MODEb. Hereinafter, with reference to FIGS. 10 to 31, operation modes MODEa and MODEb will be described.

[0085] [Roles of External Terminals in Each Mode] FIG. 10 is a schematic diagram for explaining the roles of the signal input / output terminals and the external control terminals in operation mode MODEa. FIG. 11 is a schematic diagram for explaining the roles of the signal input / output terminals and the external control terminals in operation mode MODEb. In the following description, the data signal input / output terminals DQ0 to DQ7 may be denoted as data signal input / output terminals DQ<7:0>.

[0086] In operation mode MODEa, as shown in FIG. 10 for example, in addition to inputting and outputting user data Dat, the data signal input / output terminals DQ<7:0> are used for inputting and outputting data other than user data Dat, such as command data Cmd, address data Add, status data Stt, feature data Fd, etc.

[0087] On the other hand, in operation mode MODEb, as shown in FIG. 11 for example, although the data signal input / output terminals DQ<7:0> are used for inputting and outputting user data Dat, they are basically not used for inputting and outputting data other than user data Dat, such as command data Cmd, address data Add, status data Stt, feature data Fd, etc. In operation mode MODEb, the external control terminals CLE and ALE are used for inputting and outputting data other than user data Dat.

[0088] [Role of External Terminals in Operation Mode MODEa] FIG. 12 is a truth table for explaining the role of external terminals in operation mode MODEa. In FIG. 12, "Z" indicates a case where either "H" or "L" may be input. "X" indicates a case where the input signal is fixed to "H" or "L". "Input" indicates a case where data is input. "Output" indicates a case where data is output.

[0089] When inputting command data Cmd in operation mode MODEa, the controller die CD, for example, sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" according to each bit of the 8-bit command data Cmd, inputs "H" to the external control terminal CLE, inputs "L" to the external control terminal ALE, and raises the voltage of the external control terminal / WE from "L" to "H".

[0090] When "H,L" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is held in the buffer memory in the input / output control circuit I / O as command data Cmd and transferred to the command register CMR (FIG. 4).

[0091] Also, when inputting address data Add, the controller die CD, for example, sets the voltages of data signal input / output terminals DQ<7:0> to “H” or “L” according to each bit of the 8-bit data constituting the address data Add, inputs “L” to the external control terminal CLE, inputs “H” to the external control terminal ALE, and raises the voltage of the external control terminal / WE from “L” to “H”.

[0092] When “L, H” is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is held in the buffer memory in the input / output control circuit I / O as address data Add and transferred to the address register ADR (Figure 4).

[0093] Also, when inputting user data Dat, the controller die CD, for example, sets the voltages of data signal input / output terminals DQ<7:0> to “H” or “L” according to each bit of the 8-bit data constituting the user data Dat, inputs “L” to the external control terminal CLE, inputs “L” to the external control terminal ALE, and switches (toggles) the input signals of the data strobe signal input / output terminals DQS and / DQS.

[0094] When “L” is input to both of the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is held in the buffer memory in the input / output control circuit I / O as user data Dat and transferred to the cache memory CM (Figure 4) via the bus DB.

[0095] Also, when outputting user data Dat or status data Stt, the controller die CD, for example, switches (toggles) the input signals of the external control terminals / RE and RE. Along with this, 8 bits of the output user data Dat or status data Stt are output to the data signal input / output terminals DQ0 to DQ7. Also, the output signals of the data strobe signal input / output terminals DQS and / DQS are switched.

[0096] Also, when putting the memory die MD into the standby state, the controller die CD inputs “H” to the external control terminal / CE, for example.

[0097] Also, when putting the memory die MD into the bus idle state, the controller die CD inputs “H” to the external control terminal / WE, for example.

[0098] [Role of External Terminals in Operation Mode MODEb] Figs. 13 to 15 are truth tables for explaining the role of external terminals in operation mode MODEb. Note that in Figs. 13 to 15, “Z” indicates a case where either “H” or “L” may be input. “X” indicates a case where the input signal is fixed to “H” or “L”. “Input” indicates a case where data is input. “Output” indicates a case where data is output.

[0099] As described above, in operation mode MODEb, the external control terminals CLE and ALE are used for input and output of command data Cmd, address data Add, status data Stt, feature data Fd, etc. Here, as will be described later with reference to Fig. 17 and the like, in operation mode MODEb, prior to input and output of these data, a signal specifying the type of data to be input or output is input. Hereinafter, such a signal is referred to as an input / output data selection signal. In operation mode MODEb, the input / output data selection signal is called a header, and the command data Cmd, address data Add, status data Stt, feature data Fd, etc. input and output following the input / output data selection signal may be called a body. Also, a combination of one header and one body may be called a frame.

[0100] Fig. 13 shows the role of external control terminals in the first cycle of the period FSel (Fig. 17) during which the input / output data selection signal is input.

[0101] When an input / output data selection signal indicating that address data Add is to be input is input during the first cycle of period FSel, the controller die CD, for example, raises the voltage of external control terminal / WE from "L" to "H" with "L" input to external control terminal CLE and "H" input to external control terminal ALE.

[0102] When "L" is input to external control terminal CLE and "H" is input to external control terminal ALE during the first cycle of period FSel, period FSel ends in one cycle. Also, the data input to period S_In immediately after this period FSel is held in the buffer memory within the input / output control circuit I / O as address data Add and transferred to the address register ADR (Figure 4).

[0103] When an input / output data selection signal indicating that command data Cmd is to be input is input during the first cycle of period FSel, the controller die CD, for example, raises the voltage of external control terminal / WE from "L" to "H" with "H" input to external control terminal CLE and "L" input to external control terminal ALE.

[0104] When "H" is input to external control terminal CLE and "L" is input to external control terminal ALE during the first cycle of period FSel, period FSel ends in one cycle. Also, the data input to period S_In immediately after this period FSel is held in the buffer memory within the input / output control circuit I / O as command data Cmd and transferred to the command register CMR (Figure 4).

[0105] When an input / output data selection signal indicating that a trigger signal for indicating that data out has become startable is to be input is input during the first cycle of period FSel, the controller die CD, for example, raises the voltage of external control terminal / WE from "L" to "H" with "H" input to external control terminal CLE and "H" input to external control terminal ALE.

[0106] In the first cycle of the period FSel, when “H” is input to the external control terminal CLE and “H” is input to the external control terminal ALE, the period FSel ends in one cycle. Also, the address data of the operation target is switched.

[0107] In the first cycle of the period FSel, when an input / output data selection signal indicating the execution of other operations is input, the controller die CD, for example, inputs “L” to the external control terminal CLE, inputs “L” to the external control terminal ALE, and raises the voltage of the external control terminal / WE from “L” to “H”.

[0108] In the first cycle of the period FSel, when “L” is input to the external control terminal CLE and “L” is input to the external control terminal ALE, a second cycle is added to the period FSel.

[0109] Figure 14 shows the role of the external control terminals in the second cycle of the period FSel when an input / output data selection signal is input.

[0110] In the second cycle of the period FSel, when an input / output data selection signal indicating the input of data other than the user data Dat, address data Add, and command data Cmd is input, the controller die CD, for example, inputs “L” to the external control terminal CLE, inputs “H” to the external control terminal ALE, and raises the voltage of the external control terminal / WE from “L” to “H”.

[0111] Examples of data other than the user data Dat, address data Add, and command data Cmd include, for example, address data when specifying an address during the execution of a status read or get feature. Also, feature data Fd required during the execution of a set feature is included.

[0112] In the second cycle of period FSel, when “L” is input to the external control terminal CLE and “H” is input to the external control terminal ALE, the data input to period S_In immediately after this period FSel is transferred to the address register ADR (Fig. 4), the feature register FR (Fig. 4), etc. according to the command data Cmd that was input earlier.

[0113] In the second cycle of period FSel, when an input / output data selection signal indicating that data other than user data Dat is to be output is input, the controller die CD, for example, inputs “H” to the external control terminal CLE and inputs “H” to the external control terminal ALE, and then raises the voltage of the external control terminal / WE from “L” to “H”.

[0114] Examples of data other than user data Dat include status data Stt, feature data Fd output in response to the execution of getting features, etc.

[0115] In the second cycle of period FSel, when “H” is input to the external control terminal CLE and “H” is input to the external control terminal ALE, the data output to period S_In immediately after this period FSel is selected according to the command data Cmd that was input earlier and is output from the input / output control circuit I / O.

[0116] In the second cycle of period FSel, when an input / output data selection signal indicating that other operations are to be executed is input, the controller die CD, for example, inputs “L” to the external control terminal CLE and inputs “L” to the external control terminal ALE, and then raises the voltage of the external control terminal / WE from “L” to “H”.

[0117] Note that the signals input to the external control terminals CLE and ALE during period FSel are not stored in the command register CMR (Fig. 4), the address register ADR (Fig. 4), etc. Also, in the second cycle of period FSel, when “L” is input to the external control terminal CLE and “L” is input to the external control terminal ALE, a third cycle may be added to period FSel.

[0118] Figure 15 shows the role of the external control terminals during the period S_In when data other than the user data Dat is input, or during the period S_Out when data other than the user data Dat is output.

[0119] When inputting data other than the user data Dat during the period S_In, the controller die CD sets, for example, the voltages of the external control terminals CLE and ALE to “H” or “L” according to each bit of the 2-bit data constituting the data other than the user data Dat, and raises the voltage of the external control terminal / WE from “L” to “H”.

[0120] When inputting the user data Dat in the operation mode MODEb, the controller die CD sets, for example, the voltages of the data signal input / output terminals DQ<7:0> to “H” or “L” according to each bit of the 8-bit data constituting the user data Dat, and switches the input signals of the data strobe signal input / output terminals DQS and / DQS with “H, L” input to the external control terminals / RE and RE. This operation can be executed both during the period FSel and during the periods S_In and S_Out.

[0121] In the operation mode MODEb, the data input via the data signal input / output terminals DQ<7:0> is held in the buffer memory in the input / output control circuit I / O as the user data Dat, and is transferred to the cache memory CM via the bus DB.

[0122] When outputting data other than the user data Dat during the period S_Out, the controller die CD lowers, for example, the input signal of the external control terminal / WE. Along with this, 2-bit data constituting the data other than the user data Dat is output from the external control terminals CLE and ALE.

[0123] When setting the memory die MD to the standby state during the periods S_In and S_Out, the controller die CD inputs, for example, “H” to the external control terminal / CE.

[0124] When the memory die MD is set to the bus idle state during the periods S_In and S_Out, the controller die CD inputs, for example, “H” to the external control terminal / WE.

[0125] [Examples of signal input / output in each mode] FIGS. 16 and 17 are schematic waveform diagrams for explaining the operation of the memory die MD according to the first embodiment.

[0126] FIG. 16 shows waveforms when command data Cmd and address data Add are input in the operation mode MODEa. In the example of FIG. 16, at timing t101, the controller die CD inputs the command data Cmd to the memory die MD. Also, at timing t102, the controller die CD inputs the address data Add to the memory die MD. In the illustrated example, 8-bit × 5-cycle data constituting the address data Add is input at timings t102 to t103, but the number of cycles may be less than or more than 5. Also, at timing t103, the controller die CD inputs the command data Cmd to the memory die MD. Further, at timing t104, the command data Cmd is accepted in response to the rising edge of the signal input to the external control terminal / WE. Thereby, operations such as a read operation are started, and the voltage of the terminal RY / / BY falls from “H” to “L”. Note that there may be a slight delay from when the command data Cmd is accepted until the voltage of the terminal RY / / BY falls from “H” to “L”.

[0127] FIG. 17 shows waveforms when command data Cmd and address data Add are input in the operation mode MODEb. In the example of FIG. 17, “L” and “H” are input to the external control terminal / WE at a substantially constant pace. Also, when the period from when the input signal of the external control terminal / WE falls once until it falls again is defined as one cycle, FIG. 17 illustrates a one-cycle period FSel and a four-cycle period S_In.

[0128] In the example of FIG. 17, during the period FSel from timing t151 to t152, the controller die CD inputs an input / output data selection signal for designating the input of command data Cmd to the memory die MD.

[0129] Also, during the period S_In from timing t152 to t153, the controller die CD inputs the command data Cmd to the memory die MD.

[0130] Here, in the example of FIG. 17, during the period S_In, the controller die CD inputs 8-bit command data Cmd to the memory die MD in 2-bit portions over 4 cycles. For example, let the 8-bit command data Cmd be bits “7” to “0”. First, in the data input of the first cycle, with the voltages of the external control terminals CLE and ALE set to “H” or “L” according to bits “7” and “6”, the voltage of the external control terminal / WE is raised from “L” to “H”. Similarly, in the data inputs of the second to fourth cycles, with the voltages of the external control terminals CLE and ALE set to “H” or “L” according to bits “5” and “4”, bits “3” and “2”, and bits “1” and “0” respectively, the voltage of the external control terminal / WE is raised from “L” to “H”.

[0131] Also, during the period FSel from timing t153 to t154, the controller die CD inputs an input / output data selection signal for designating the input of address data Add to the memory die MD.

[0132] Also, during the period S_In from timing t154 to t155, the controller die CD inputs the address data Add to the memory die MD.

[0133] Here, in the example of FIG. 17, during the period S_In, the controller die CD inputs the 8-bit data constituting the address data Add to the memory die MD in 2-bit portions over 4 cycles.

[0134] Although not shown in the figure, similarly at timings t155 to t156, the data constituting the address data Add is input bit by bit in units of 2 bits.

[0135] Also, during the period FSel from timing t156 to t157, an input / output data selection signal for designating the input of the command data Cmd is input in the same manner as at timings t151 to t152.

[0136] Also, during the period S_In from timing t157 to t158, the controller die CD inputs the command data Cmd to the memory die MD. Further, at the timing of the rising edge of the signal input to the external control terminal / WE, which is slightly before timing t158, operations such as a read operation are started, and the voltage of the terminal RY / / BY falls from “H” to “L”.

[0137] [Operation] Next, the operation of the memory die MD will be described.

[0138] The memory die MD is configured to be capable of executing a read operation. The read operation is an operation of reading user data Dat from the memory cell array MCA by the sense amplifier module SAM (FIG. 4) and transferring the read user data Dat to the latch circuit XDL (FIG. 4). In the read operation, the user data Dat read from the memory cell array MCA is transferred to the latch circuit XDL via the bit lines BL and the sense amplifier module SAM.

[0139] Also, the memory die MD is configured to be capable of performing data out. The data out is an operation of outputting the user data Dat included in the latch circuit XDL (FIG. 4) to the controller die CD (FIG. 1). In the data out, the user data Dat included in the latch circuit XDL is output to the controller die CD via the column decoder COLD, multiplexer MPX, bus wiring DB, and input / output control circuit I / O described with reference to FIG. 7.

[0140] In addition, the memory die MD is configured to be able to execute a status read (status information output operation). The status read is an operation of outputting status data Stt included in a status register STR (Fig. 4) to a controller die CD (Fig. 1). In the status read, the status data Stt included in the status register STR is output to the controller die CD via an input / output control circuit I / O or a logic circuit CTR.

[0141] In addition, the memory die MD is configured to be able to execute a get feature (characteristic information output operation). The get feature is an operation of outputting feature data Fd included in a feature register FR (Fig. 4) to a controller die CD (Fig. 1). In the get feature, the feature data Fd included in the feature register FR is output to the controller die CD via an input / output control circuit I / O or a logic circuit CTR.

[0142] In addition, the memory die MD is configured to be able to execute a set feature. The set feature is an operation of inputting feature data Fd to a feature register FR (Fig. 4). In the set feature, the feature data Fd is input from the controller die CD to the feature register FR via an input / output control circuit I / O or a logic circuit CTR.

[0143] [Read Operation and Data Output in Operation Mode MODEa] Fig. 18 is a schematic waveform diagram showing the state when a read operation and data output are executed in operation mode MODEa. In the example of Fig. 18, the memory die MD is set to operation mode MODEa.

[0144] In the example of FIG. 18, first, command data "00h", address data Add, and command data "30h" are sequentially input via data signal input / output terminals DQ<7:0>. The command data "00h" is the command data Cmd input at the beginning of the command set instructing the read operation. The command data "30h" is the command data Cmd input at the end of the command set instructing the read operation.

[0145] With the input of the command data "00h", address data Add, and command data "30h", the read operation is started, and the voltage of terminal RY / / BY falls from "H" to "L". Also, the user data Dat is transferred to the latch circuit XDL. Also, at the timing when the read operation ends, the voltage of terminal RY / / BY rises from "L" to "H".

[0146] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via data signal input / output terminals DQ<7:0>. The command data "05h" is the command data Cmd input at the beginning of the command set instructing data out. The command data "E0h" is the command data Cmd input at the end of the command set instructing data out.

[0147] With the input of the command data "05h", address data Add, and command data "E0h", after a predetermined waiting time, the controller die CD switches (toggles) the input signals of the external control terminals / RE, RE. Thereby, data out is started, and the user data Dat is output via the data signal input / output terminals DQ.

[0148] FIG. 19 is a schematic waveform diagram showing another state when the read operation and data out are executed in the operation mode MODEa. In the example of FIG. 19, the memory die MD is set to the operation mode MODEa.

[0149] In the example of FIG. 19, first, command data "00h", address data Add, and command data "30h" are sequentially input via data signal input / output terminals DQ<7:0>. The address data Add included in this command set includes information on plane PLN0 (FIG. 4) which is the target of the read operation as the above plane address.

[0150] With the input of command data "00h", address data Add, and command data "30h", a read operation is started for plane PLN0, and user data Dat is transferred to latch circuit XDL0.

[0151] Next, command data "00h", address data Add, and command data "30h" are sequentially input via data signal input / output terminals DQ<7:0>. The address data Add included in this command set includes information on plane PLN1 (FIG. 4) which is the target of the read operation as the above plane address.

[0152] With the input of command data "00h", address data Add, and command data "30h", a read operation is started for plane PLN1, and user data Dat is transferred to latch circuit XDL1.

[0153] Next, command data "70h" is input via data signal input / output terminals DQ<7:0>. Command data "70h" is command data Cmd that instructs a status read. With the input of command data "70h", a status read is performed, and status data Stt is output via data signal input / output terminals DQ<7:0>.

[0154] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via data signal input / output terminals DQ<7:0>. The address data Add included in this command set includes information on plane PLN0 (FIG. 4) which is the target of data out as the above plane address.

[0155] With the input of command data "05h", address data Add, and command data "E0h", after a predetermined waiting time, the controller die CD switches (toggles) the input signals of the external control terminals / RE, RE. As a result, data output to plane PLN0 is started, and user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0156] After the end of data output to plane PLN0, command data "70h" is input via the data signal input / output terminals DQ<7:0>. With the input of command data "70h", a status read is performed again, and status data Stt is output via the data signal input / output terminals DQ<7:0>.

[0157] Next, in the same manner as the data output to PLN0, command data "05h", address data Add, and command data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this command set includes information on plane PLN1 (Fig. 4) which is the target of data output as the above plane address.

[0158] After a predetermined time has elapsed, the controller die CD switches (toggles) the input signals of the external control terminals / RE, RE. As a result, data output to plane PLN1 is started, and user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0159] [Read Operation and Data Output in Operation Mode MODEb] Fig. 20 is a schematic waveform diagram showing the state when performing a read operation and data output in operation mode MODEb. In the example of Fig. 20, the memory die MD is set to operation mode MODEb.

[0160] In the example of FIG. 20, first, a command set including command data "00h" is input via the external control terminals CLE and ALE. Next, a command set including command data "05h" is input via the external control terminals CLE and ALE. Note that in operation mode MODEb, data input / output via the data signal input / output terminals DQ<7:0> and data input / output via the external control terminals CLE and ALE can be executed at independent timings. For example, in the example of FIG. 20, the input of these command sets is performed during the execution of data out (during the period when the input signals of the external control terminals / RE and RE toggle).

[0161] FIG. 21 is a schematic waveform diagram showing another state when a read operation and data out are executed in operation mode MODEb. In the example of FIG. 21, the memory die MD is set to operation mode MODEb.

[0162] In the example of FIG. 21, first, command data "00h", address data Add, and command data "30h" are sequentially input via the external control terminals CLE and ALE. The address data Add included in this command set includes information on plane PLN0 (FIG. 4), which is the target of the read operation, as the above plane address.

[0163] Next, command data "00h", address data Add, and command data "30h" are sequentially input via the external control terminals CLE and ALE. The address data Add included in this command set includes information on plane PLN1 (FIG. 4), which is the target of the read operation, as the above plane address.

[0164] Next, command data "70h" is input via the external control terminals CLE and ALE. With the input of command data "70h", a status read is performed, and status data Stt is output via the external control terminals CLE and ALE.

[0165] Next, the command data "05h", the address data Add, and the command data "E0h" are sequentially input via the external control terminals CLE and ALE. This address data Add, as the above-mentioned plane address, includes information on the plane PLN0 (Fig. 4) that is the target of data output.

[0166] After a predetermined standby time, data output to the plane PLN0 is started, and the user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0167] Also, in the example of Fig. 21, while data output to the plane PLN0 is being performed, the command data "70h" is input via the external control terminals CLE and ALE. Along with the input of the command data "70h", a status read is performed. In the illustrated example, while the data output to the plane PLN0 is being executed, the status data Stt is output via the external control terminals CLE and ALE.

[0168] Also, in the example of Fig. 21, while data output to the plane PLN0 is being performed, the command data "05h", the address data Add, and the command data "E0h" are sequentially input via the external control terminals CLE and ALE. This address data Add, as the above-mentioned plane address, includes the address, etc. of the plane PLN1 (Fig. 4) that is the target of data output.

[0169] Here, in the operation mode MODEb, different from the operation mode MODEa, the data output timing adjustment unit TCT (Fig. 4) adjusts the timing of starting data output to the plane PLN1. After the data output to the plane PLN0 is completed, according to the internal signal issued by the data output timing adjustment unit TCT, data output to the plane PLN1 is started, and the user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0170] FIG. 22 is a schematic waveform diagram showing another state when a read operation and data output are executed in operation mode MODEb. In the example of FIG. 22, memory die MD is set to operation mode MODEb. Here, a case where read operations and data output are executed for a plurality of memory dies MD as shown in FIGS. 2 and 3 will be described as an example.

[0171] As described above, the memory die MD as a semiconductor memory device according to the first embodiment is configured to be able to execute data output in response to the switching (toggle) of the input signal at the external control terminals / RE, RE by receiving a trigger signal from the controller die CD after being instructed to perform data output. For example, in the example of FIG. 22, while the data output for memory die MD0 is being executed, the data output for memory die MD1 is instructed. At this point, memory die MD0 is executing data output in response to the switching (toggle) of the input signal at the external control terminals / RE, RE. On the other hand, after memory die MD1 is instructed to perform data output, it does not start data output even if the input signal at the external control terminals / RE, RE is switched (toggled) until it receives a trigger signal from controller die CD. Therefore, data output collision in memory dies MD0 and MD1 connected in common is avoided. After detecting that the data output from memory die MD0 has ended, controller die CD inputs a trigger signal to memory dies MD0 and MD1 connected in common. That is, as described with reference to FIG. 13, “H” is input to external control terminal CLE and “H” is input to external control terminal ALE. Accordingly, as shown in FIG. 22, the data output from memory die MD1 is started.

[0172] [Status Read in Operation Mode MODEa] Figure 23 shows the waveforms when performing status read in operation mode MODEa. In the example of Figure 23, at timing t201, controller die CD inputs command data 70h to memory die MD. Also, at timing t202, status data Stt is output.

[0173] [Status Read in Operation Mode MODEb] Figure 24 shows the waveforms when performing status read in operation mode MODEb.

[0174] In the example of Figure 24, during the period FSel from timing t251 to t252, controller die CD inputs an input / output data selection signal that designates the input of command data Cmd to memory die MD.

[0175] Also, during the period S_In from timing t252 to t253, controller die CD inputs command data 70h to memory die MD.

[0176] Still, in the example of Figure 24, during the period S_In, controller die CD inputs 8-bit command data 70h to memory die MD in 2-bit increments over 4 cycles.

[0177] Also, during the period FSel from timing t253 to t254, controller die CD inputs an input / output data selection signal that designates the output of data to memory die MD.

[0178] Also, during the period S_Out from timing t254 to t255, memory die MD outputs status data Stt to controller die CD.

[0179] [Other Status Reads in Operation Mode MODEa] Figure 25 shows waveforms when performing other status reads in operation mode MODEa. In the example of Figure 25, at timing t301, controller die CD is inputting command data 78h to memory die MD. The command data “78h” is command data Cmd that instructs other status reads. Also, at timing t302, controller die CD is inputting address data Add to memory die MD. In the illustrated example, after timing t302, 8-bit × 3-cycle data that constitutes address data Add is input, but the number of cycles may be less than or more than 3. Also, at timing t303, status data Stt is being output.

[0180] [Other Status Reads in Operation Mode MODEb] Figure 26 shows waveforms when performing other status reads in operation mode MODEb.

[0181] In the example of Figure 26, during the period FSel from timing t351 to t352, controller die CD is inputting an input / output data selection signal that designates the input of command data Cmd to memory die MD.

[0182] Also, during the period S_In from timing t352 to t353, controller die CD is inputting command data 78h to memory die MD.

[0183] In the example of Figure 26, during the period S_In, controller die CD is inputting 8-bit command data 78h to memory die MD in 2-bit increments over 4 cycles.

[0184] Also, during the period FSel from timing t353 to t354, controller die CD is inputting an input / output data selection signal that designates the input of address data to memory die MD.

[0185] Also, during the period S_In from timing t354 to t355, the controller die CD inputs the address data Add to the memory die MD.

[0186] Similarly, during the period FSel from timing t355 to t356 and during the period FSel from timing t357 to t358, the controller die CD inputs an input / output data selection signal that designates the input of address data to the memory die MD.

[0187] Also, during the period S_In from timing t356 to t357, the controller die CD inputs the address data Add to the memory die MD.

[0188] [Get Feature in Operation Mode MODEa] FIG. 27 shows waveforms when executing the get feature in operation mode MODEa. In the example of FIG. 27, at timing t401, the controller die CD inputs the command data EEh to the memory die MD. The command data "EEh" is the command data Cmd that instructs the get feature. Also, at timing t402, the controller die CD inputs the address data Add to the memory die MD. In the illustrated example, data of 8 bits × 3 cycles that constitutes the address data Add is input after timing t402, but the number of cycles may be less than or more than 3. Also, at timing t403, corresponding to the rising edge of the signal input to the external control terminal / WE, the get feature is started, and the voltage of the terminal RY / / BY falls from "H" to "L". Also, at timing t404, the get feature ends, and the voltage of the terminal RY / / BY rises from "L" to "H". Also, at timing t405, the feature data Fd is output.

[0189] [Status Read in Operation Mode MODEb] FIG. 28 shows waveforms when executing the status read in operation mode MODEb.

[0190] In the example of FIG. 28, during the period FSel from timing t451 to t452, the controller die CD inputs an input / output data selection signal specifying the input of command data Cmd to the memory die MD.

[0191] Also, during the period S_In from timing t452 to t453, the controller die CD inputs command data EEh to the memory die MD.

[0192] Note that in the example of FIG. 28, during the period S_In, the controller die CD inputs 8-bit command data EEh to the memory die MD in 2-bit portions over 4 cycles.

[0193] Also, during the period FSel from timing t453 to t454, the controller die CD inputs an input / output data selection signal specifying the input of address data to the memory die MD.

[0194] Also, during the period S_In from timing t454 to t455, the controller die CD inputs address data Add to the memory die MD.

[0195] Similarly, during the period FSel from timing t455 to t456 and during the period FSel from timing t457 to t458, the controller die CD inputs an input / output data selection signal specifying the input of address data to the memory die MD.

[0196] Also, during the period S_In from timing t456 to t457, the controller die CD inputs address data Add to the memory die MD.

[0197] [Set Feature in Operation Mode MODEa] Figure 29 shows the waveforms when the set feature is executed in operation mode MODEa. In the example of Figure 29, at timing t501, controller die CD inputs command data EFh to memory die MD. The command data "EFh" is command data Cmd that instructs the set feature. Also, at timing t502, controller die CD inputs address data Add to memory die MD. In the illustrated example, after timing t502, data of 8 bits × 3 cycles that constitutes address data Add is input, but the number of cycles may be less than or more than 3. Also, at timing t503, controller die CD inputs feature data Fd to memory die MD. Also, the set feature is started at timing t504, and the voltage of terminal RY / / BY has fallen from "H" to "L".

[0198] [Set Feature in Operation Mode MODEb] Figure 30 shows the waveforms when the set feature is executed in operation mode MODEb.

[0199] In the example of Figure 30, during the period FSel from timing t551 to t552, controller die CD inputs an input / output data selection signal that designates the input of command data Cmd to memory die MD.

[0200] Also, during the period S_In from timing t552 to t553, controller die CD inputs command data EFh to memory die MD.

[0201] In the example of Figure 30, during the period S_In, controller die CD inputs 8-bit command data EFh to memory die MD in 2-bit portions over 4 cycles.

[0202] Also, during the period FSel from timing t553 to t554, controller die CD inputs an input / output data selection signal that designates the input of address data to memory die MD.

[0203] Also, during period S_In from timing t554 to t555, the controller die CD inputs address data Add to the memory die MD.

[0204] Similarly, during period FSel from timing t555 to t556, the controller die CD inputs an input / output data selection signal that designates the input of address data to the memory die MD.

[0205] Also, during period S_In after timing t556 and during period S_In up to timing t557, the controller die CD inputs address data Add to the memory die MD.

[0206] Also, during period FSel from timing t557 to t558, the controller die CD inputs an input / output data selection signal that designates the input of data to the memory die MD.

[0207] Also, during period S_In from timing t558 to t559, the controller die CD inputs feature data Fd to the memory die MD.

[0208] Similarly, during period FSel from timing t559 to t560, the controller die CD inputs an input / output data selection signal that designates the input of data to the memory die MD.

[0209] Also, during period S_In after timing t560 and during period S_In up to timing t561, the controller die CD inputs feature data Fd to the memory die MD.

[0210] [Effect] As described with reference to FIG. 10 and the like, in operation mode MODEa, in addition to inputting and outputting user data Dat, the data signal input / output terminals DQ<7:0> are used for inputting and outputting data other than user data Dat, such as command data Cmd and address data Add. Therefore, for example, as described with reference to FIG. 19, when continuously performing a read operation and data output for planes PLN0 and PLN1, a command set for performing data output for plane PLN1 cannot be input until the data output for plane PLN0 is completed.

[0211] Here, the semiconductor memory device according to the present embodiment can be operated in operation mode MODEb. In operation mode MODEb, as described above, while data output via the data signal input / output terminals DQ<7:0> is being performed, command data Cmd and address data Add can be input via the external control terminals CLE and ALE. Therefore, for example, as described with reference to FIG. 21, when continuously performing a read operation and data output for planes PLN0 and PLN1, a command set for performing data output for plane PLN1 can be input even while data output for plane PLN0 is being executed. Thereby, it is possible to reduce the time required for inputting a command set to the memory die MD and realize high-speed operation of the semiconductor memory device.

[0212] Also, as described with reference to FIGS. 13 and 14 and the like, in the semiconductor memory device according to the present embodiment, when any one of “L,H”, “H,L”, “H,H” is input to the external control terminals CLE and ALE in the first cycle of period FSel, period FSel ends in one cycle. Also, when “L,L” is input to the external control terminals CLE and ALE in the first cycle of period FSel, a second cycle is added to period FSel, and other operations can be specified. Thereby, for some functions, it is possible to perform high-speed operation while suitably specifying operations.

[0213] For example, according to the semiconductor memory device according to the present embodiment, as illustrated in FIG. 31, during the execution of data output, it is also possible to execute operations such as set features and get features.

[0214] [Deserializers Applicable to Memory Die MD According to the First Embodiment] In the memory die MD according to the first embodiment, the functions of the data signal input / output terminals DQ<7:0>, the external control terminals CLE, ALE, etc. change according to whether the operation mode MODEa or MODEb is selected. Hereinafter, a circuit having such functions will be exemplified with reference to FIGS. 32 to 36. FIG. 32 is a schematic flowchart for explaining an example of such a circuit. FIGS. 33, 35, and 36 are schematic circuit diagrams for explaining other examples of such a circuit. FIG. 34 is a schematic waveform diagram for explaining the operation method of the circuit shown in FIG. 33.

[0215] The circuit corresponding to FIG. 32 may be realized by, for example, a state machine or the like. This circuit, for example, holds the signals input to the external control terminals CLE, ALE as part of the input / output data selection signal (step S101). Next, it is determined whether the external control terminals CLE, ALE are "L, L" (step S102). If the external control terminals CLE, ALE are "L, L", the process returns to step S101. If the external control terminals CLE, ALE are not "L, L", the variable cnt is set to 0 and the process proceeds to step S103. Next, the signals input to the external control terminals CLE, ALE are held as part of data other than the user data Dat (step S103). Next, it is determined whether the variable cnt is less than 4 (step S104). If the variable cnt is less than 4, 1 is added to the variable cnt and the process returns to step S103. If the variable cnt is not less than 4, the process returns to step S101.

[0216] FIG. 33 illustrates the data signal input / output terminals DQ<7:0>, the external control terminals CLE, ALE, / WE, and the circuit unit 200 connected thereto.

[0217] The circuit section 200 includes, for example, a latch circuit 210, multiplexers 220 and 230, and a deserialiser 300.

[0218] The latch circuit 210 is a latch circuit included in a command register CMR, an address register ADR, or a feature register FR. For example, a plurality of latch circuits 210 are provided corresponding to the command register CMR. The plurality of latch circuits 210 may be provided in the same number as the available command data Cmd. Also, a plurality of latch circuits 210 are provided corresponding to the address register ADR. The plurality of latch circuits 210 may be provided in the amount equal to the product of the number of address data Add that can be held and the number of bits of the address data Add. Also, a plurality of latch circuits 210 may be provided corresponding to the feature register FR. In the illustrated example, the latch circuit 210 holds 1-bit data corresponding to the input command data Cmd. The data input terminal of the latch circuit 210 is connected to the output terminals DINh<7:0>, CLEh, ALEh of the multiplexer 220 via a logic circuit, and the clock input terminal is connected to the output terminal / WEh´ of the multiplexer 230.

[0219] A selection signal SerialCA is input to each selection control terminal of the multiplexers 220 and 230. The selection signal SerialCA is in the "0" state when the operation mode MODEa is selected, and is in the "1" state when the operation mode MODEb is selected.

[0220] The multiplexer 220 has ten output terminals DINh<7:0>, CLEh, ALEh. Of these ten output terminals, eight output terminals DINh<7:0> correspond to data constituting data other than the user data Dat. Also, the remaining two output terminals CLEh, ALEh correspond to the input signals of the external control terminals CLE, ALE.

[0221] Also, the multiplexer 220 includes ten input terminals selected when the selection signal SerialCA is in the "0" state and ten input terminals selected when the selection signal SerialCA is in the "1" state. Eight of the ten input terminals corresponding to the "0" state are connected to the data signal input / output terminals DQ<7:0>. The remaining two are connected to the external control terminals CLE and ALE. The ten input terminals corresponding to the "1" state are connected to the output terminals of the deserialzier 300.

[0222] The multiplexer 230 includes one output terminal / WEh´. Also, the multiplexer 230 includes one input terminal / WEh selected when the selection signal SerialCA is in the "1" state and one input terminal selected when the selection signal SerialCA is in the "0" state. The input terminal / WEh corresponding to the "1" state is connected to the output terminal of the deserialzier 300. The input terminal corresponding to the "0" state is connected to the external control terminal / WE.

[0223] The deserialzier 300 includes ten output terminals connected to the multiplexer 220. The deserialzier 300 converts the data input bit by bit from the external control terminals CLE and ALE over four cycles into 8-bit data, adds 2-bit data indicating whether this 8-bit data is command data Cmd or address data Add, and generates 10-bit data. Also, the deserialzier 300 outputs this 10-bit data to the multiplexer 220 via the ten output terminals. This 10-bit data may be switched, for example, at the timing of the start of the period FSel.

[0224] The deserializer 300 also includes one output terminal connected to the multiplexer 230. During the period from when the data of the first cycle among the multiple cycles of data input from the external control terminal / WE is input until the data of the second cycle is input (during the first cycle of the period FSel), the deserializer 300 outputs an “L” to the input terminal / WEh of the multiplexer 230. During other periods, the deserializer 300 outputs an “H” to the input terminal / WEh of the multiplexer 230.

[0225] In the operation mode MODEa, the 8-bit data input via the data signal input / output terminal DQ<7:0> is input to the logic circuit via the output terminal DINh<7:0> of the multiplexer 220. Also, the enable signals input via the external control terminals CLE and ALE are input to the logic circuit via the output terminals CLEh and ALEh of the multiplexer 220. For example, when the 8-bit data input via the data signal input / output terminal DQ<7:0> is the command data “05h” and the input signals of the external control terminals CLE and ALE are “H, L”, the output signal of the logic circuit corresponding to the command data “05h” becomes “H”. Otherwise, the output signal of the logic circuit corresponding to the command data “05h” becomes “L”.

[0226] Also, in the operation mode MODEa, the signal input from the external control terminal / WE is output from the output terminal / WEh´ of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0227] In operation mode MODEb, 2-bit × multiple-cycle (e.g., 5 cycles or 6 cycles) data input via the external control terminals CLE and ALE is converted by the deserialzier 300 into multiple-bit (e.g., 10 bits or 12 bits) data. Also, 10-bit data among these multiple-bit data is input to the input terminals of the multiplexer 220. These data and signals are input to the logic circuit via the output terminals DINh<7:0>, CLEh, and ALEh of the multiplexer 220. For example, if “H, L” is input from the external control terminals CLE and ALE during the period FSel, and command data “05h” is input from the external control terminals CLE and ALE during the period S_In, the output signal of the logic circuit corresponding to the command data “05h” becomes “H”. Otherwise, the output signal of the logic circuit corresponding to the command data “05h” becomes “L”. Also, for example, as illustrated in FIG. 34, in operation mode MODEb, the deserialzier 300 sets / WEh to the “H” state in any one of the multiple cycles included in the period FSel or the periods S_In and S_Out, and sets / WEh to the “L” state in the other cycles.

[0228] Also, in operation mode MODEb, the signal input to the input terminal / WEh of the multiplexer 230 is output from the output terminal / WEh´ of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0229] FIGS. 35 and 36 are schematic circuit diagrams showing a partial configuration of the deserialzier 300. The deserialzier 300 includes a circuit section 310 as shown in FIG. 35 and a circuit section 320 as shown in FIG. 36.

[0230] As shown in FIG. 35, the circuit section 310 includes seven D flip-flops 311 and one D latch circuit 312.

[0231] The output terminal of the first D flip-flop 311 is connected to the data input terminals of the second and fourth D flip-flops 311 via the switch circuit 315. When the external control terminals CLE and ALE are "L, L", this switch circuit 315 transfers the output signal of the first D flip-flop 311 to the data input terminal of the second D flip-flop 311. In other cases, the output signal of the first D flip-flop 311 is transferred to the data input terminal of the fourth D flip-flop 311.

[0232] The output terminal of the second D flip-flop 311 is connected to the data input terminals of the third and fourth D flip-flops 311 via the switch circuit 315. When the external control terminals CLE and ALE are "L, L", this switch circuit 315 transfers the output signal of the second D flip-flop 311 to the data input terminal of the third D flip-flop 311. In other cases, the output signal of the second D flip-flop 311 is transferred to the data input terminal of the fourth D flip-flop 311.

[0233] The output terminal of the third D flip-flop 311 is connected to the data input terminal of the fourth D flip-flop 311. Similarly, the output terminals of the fourth to sixth D flip-flops 311 are respectively connected to the data input terminals of the fifth to seventh D flip-flops 311. The output terminal of the seventh D flip-flop 311 is connected to the data input terminal of the D latch circuit 312. The output terminal of the D latch circuit 312 is connected to the data input terminal of the first D flip-flop 311. Also, the clock input terminals of these seven D flip-flops 311 and one D latch circuit 312 are connected to the external control terminal / WE.

[0234] Further, the circuit section 310 includes seven D-latch circuits 313 and seven AND circuits 314. The data input terminals of the seven D-latch circuits 313 are respectively connected to the output terminals of the seven D flip-flops 311. Also, an inverted signal of the external control terminal / WE is input to the clock input terminals of the seven D-latch circuits 313. One input terminal of each of the seven AND circuits 314 is respectively connected to the output terminals of the seven D-latch circuits 313. The other input terminals of the seven AND circuits 314 are respectively connected to the external control terminal / WE. In the example of FIG. 35, among these seven AND circuits 314, the first to third output terminals are shown as output terminals WE1_1 to WE1_3. Also, the fourth to sixth output terminals are shown as output terminals WE2 to WE4. The remaining one output terminal is connected to the input terminal / WEh of the multiplexer 230 (FIG. 33).

[0235] Here, assume that the initial value of the data held in the seven D flip-flops 311 is 0, and the initial value of the data held in the D-latch circuit 312 is 1.

[0236] When “H” is input to the external control terminal / WE while the output signal of the D-latch circuit 312 is in the “H” state, the signal of the output terminal WE1_1 becomes the “H” state, and the signals of the output terminals WE1_2, WE1_3, WE2, WE3, WE4, and the output signal of the D-latch circuit 312 become the “L” state.

[0237] When “H” is input to the external control terminal / WE while the signal of the output terminal WE1_1 is “H” and the signals of the external control terminals CLE and ALE are “L, L”, the signal of the output terminal WE1_2 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_3, WE2, WE3, WE4, and the output signal of the D-latch circuit 312 become the “L” state.

[0238] When “H” is input to the external control terminal / WE in a state where the signal of the output terminal WE1_1 is “H” and the signals of the external control terminals CLE and ALE are “L,H”, “H,L” or “H,H”, the signal of the output terminal WE2 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE3, WE4 and the output signal of the D latch circuit 312 become the “L” state.

[0239] When “H” is input to the external control terminal / WE in a state where the signal of the output terminal WE1_2 is “H” and the signals of the external control terminals CLE and ALE are “L,L”, the signal of the output terminal WE1_3 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE2, WE3, WE4 and the output signal of the D latch circuit 312 become the “L” state.

[0240] When “H” is input to the external control terminal / WE in a state where the signal of the output terminal WE1_2 is “H” and the signals of the external control terminals CLE and ALE are “L,H”, “H,L” or “H,H”, the signal of the output terminal WE2 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE3, WE4 and the output signal of the D latch circuit 312 become the “L” state.

[0241] When “H” is input to the external control terminal / WE in a state where the signal of the output terminal WE1_3 is “H”, the signal of the output terminal WE2 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE3, WE4 and the output signal of the D latch circuit 312 become the “L” state.

[0242] When “H” is input to the external control terminal / WE in a state where the signal of the output terminal WE2 is “H”, the signal of the output terminal WE3 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE2, WE4 and the output signal of the D latch circuit 312 become the “L” state.

[0243] When “H” is input to the external control terminal / WE while the signal of the output terminal WE3 is in the “H” state, the signal of the output terminal WE4 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE2, WE3, and the output signal of the D-latch circuit 312 become the “L” state.

[0244] When “H” is input to the external control terminal / WE while the signal of the output terminal WE4 is in the “H” state, the output signal of the D-latch circuit 312 becomes the “H” state, and the signals of the output terminals WE1_1, WE1_2, WE1_3, WE2, WE3, WE4 become the “L” state.

[0245] As shown in FIG. 36, the circuit section 320 includes two D-latch circuits 321 to 326 each. The data input terminals of one of the D-latch circuits 321 to 326 are connected to the external control terminal CLE. The data input terminals of the other D-latch circuits 321 to 326 are connected to the external control terminal ALE. Also, the clock input terminals of the two D-latch circuits 321 are connected to the output terminal WE1_1 of the AND circuit 314 (FIG. 35). Similarly, the clock input terminals of the D-latch circuits 322, 323, 324, 325, 326 are connected to the output terminals WE1_2, WE1_3, WE2, WE3, WE4 of the AND circuit 314 (FIG. 35), respectively.

[0246] The data of the external control terminals CLE and ALE in the first cycle of the period FSel are held in the two D-latch circuits 321. The data of the external control terminals CLE and ALE in the second cycle of the period FSel are held in the two D-latch circuits 322. The data of the external control terminals CLE and ALE in the first cycle of the period S_In are held in the two D-latch circuits 324. The data of the external control terminals CLE and ALE in the second cycle of the period S_In are held in the two D-latch circuits 325. The data of the external control terminals CLE and ALE in the third cycle of the period S_In are held in the two D-latch circuits 326.

[0247] The output terminals of D latch circuits 321 to 323 are connected to a decode circuit 327. The decode circuit includes, for example, a plurality of output terminals corresponding to a plurality of input / output data selection signals. Such input / output data selection signals include, for example, an input / output data selection signal for inputting address data Add as described with reference to FIG. 13, an input / output data selection signal for inputting command data Cmd, and an input / output data selection signal for inputting a trigger signal for switching the address data Add. Further, such input / output data selection signals include, for example, an input / output data selection signal for inputting data and an input / output data selection signal for outputting data as described with reference to FIG. 14.

[0248] For example, when “H” is input to the external control terminal CLE and “L” is input to the external control terminal ALE in the first cycle of the period FSel, the signal of the output terminal corresponding to the output terminal CLEh becomes the “H” state, and the signals of the other output terminals become the “L” state. Further, for example, when “L” is input to the external control terminal CLE and “H” is input to the external control terminal ALE in the first cycle of the period FSel, the signal of the output terminal corresponding to the output terminal ALeh becomes the “H” state, and the signals of the other output terminals become the “L” state.

[0249] The output terminals of D latch circuits 324 to 325 are connected to the output terminal DINh<7:2> via a multiplexer 220 (FIG. 33). Note that the external control terminals CLE and ALE are connected to the output terminal DINh<1:0> via the multiplexer 220 (FIG. 33).

[0250] [Serializer Applicable to Memory Die MD According to the First Embodiment] In the memory die MD according to the first embodiment, when the operation mode MODEb is selected, 8-bit data is converted into 2-bit × 4-cycle data and output. Such a function may be realized by a circuit as shown in FIG. 37, for example. FIG. 37 is a schematic circuit diagram showing a partial configuration example of the memory die MD.

[0251] The circuit shown in FIG. 37 includes a serializer 331 and two switch circuits 332.

[0252] The serializer 331 includes eight first input terminals and one second input terminal. One bit of the 8-bit data FDATA<7:0> that constitutes the output data is input to each of the first input terminals. The external control terminal / WE is input to the second input terminal. The serializer 331 converts the 8-bit data FDATA<7:0> into 2-bit data FDATA2<1:0> in response to the input of the external control terminal / WE and sequentially outputs it over four cycles.

[0253] The two switch circuits 332 are respectively provided corresponding to the external control terminals CLE and ALE. The output terminal of the switch circuit 332 is connected to the external control terminal CLE or the external control terminal ALE. The input terminal of the switch circuit 332 is connected to the output terminal of the serializer 331. The switch circuit 332 outputs an input signal in response to the input of the gate signal S 332 . The gate signal S 332 may be in the “H” state, for example, when the external control terminal / WE is in the “L” state, it is the first cycle of the period S_Out, “L,L” is input to the external control terminals CLE and ALE in the first cycle of the period FSel, “H,L” is input to the external control terminals CLE and ALE in the second cycle of the period FSel, the operation mode MODEb is selected, and the memory die MD is selected.

[0254] [Second Embodiment] Next, with reference to FIGS. 38 and 39, the configuration of the semiconductor memory device according to the second embodiment will be described. FIG. 38 is a schematic block diagram showing the configuration of the memory die MD2 according to the second embodiment. FIG. 39 is a schematic circuit diagram showing a part of the configuration of the memory die MD2. For convenience of explanation, some configurations are omitted in FIGS. 38 and 39.

[0255] As shown in FIGS. 38 and 39, the semiconductor memory device according to this embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment can execute signal input and output via an external control terminal / CE in addition to the external control terminals CLE and ALE. As shown in FIG. 39, the external control terminal / CE according to the second embodiment is connected to an input circuit 201 and an output circuit 202. Also, as shown in FIG. 39, the external control terminal / CE according to the second embodiment includes a latch circuit 206.

[0256] Here, in the semiconductor memory device according to the first embodiment, 2-bit data was input in parallel or output in parallel by the external control terminals CLE and ALE in one cycle. For example, during the period FSel of the operation mode MODEb, 2-bit or 4-bit data was input over one cycle or two cycles. Also, during the period S_In, 8-bit data constituting data other than the user data Dat was input over four cycles. Therefore, 10-bit to 12-bit data was input over five cycles to six cycles.

[0257] Here, in the semiconductor memory device according to the second embodiment, in addition to the external control terminals CLE and ALE, signal input and output can be executed via the external control terminal / CE. Therefore, it is possible to input 3-bit data in parallel or output it in parallel in one cycle. As a result, the number of cycles required for data input can be reduced, and the operation speed can be increased.

[0258] In the semiconductor memory device according to the first embodiment, the memory die MD is in a selected state at the timing when the external control terminal / CE is in the "L" state, and the memory die MD is in a non-selected state at the timing when the external control terminal / CE is in the "H" state. The same applies when operating the semiconductor memory device according to the second embodiment in the operation mode MODEa. On the other hand, when operating the semiconductor memory device according to the second embodiment in the operation mode MODEb, the memory die MD is in a selected state at the timing when "L" is held in the latch circuit 206, and the memory die MD is in a non-selected state at the timing when "H" is held in the latch circuit 206.

[0259] Next, with reference to FIG. 40, the operation of the semiconductor memory device according to the second embodiment will be described. FIG. 40 is a schematic waveform diagram for explaining the operation of the semiconductor memory device according to the second embodiment.

[0260] In the example of FIG. 40, at timing t600, the controller die CD inputs "L" to the external control terminal / CE of the memory die MD2. Accordingly, "L" is input to the latch circuit 206 (FIG. 39), and the memory die MD2 is in a selected state.

[0261] Also, during the period FSel from timing t601 to t602, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD2. Accordingly, an input / output data selection signal indicating that command data Cmd is to be input is input.

[0262] Also, during the period S_In from timing t602 to t603, the controller die CD inputs the command data Cmd to the memory die MD2 over three cycles. Also, in the example shown, "0" is input to the external control terminal / CE in the first cycle of the period S_In.

[0263] In the illustrated example, the 1-bit data input to the external control terminal / CE in the first cycle of the period S_In is used as flag data. For example, when “0” is input to the external control terminal / CE in the first cycle of the period S_In, the cycle immediately following this period S_In is defined as the period FSel. On the other hand, when “1” is input to the external control terminal / CE in the first cycle of the period S_In, the period FSel is omitted, and the cycle immediately following this period S_In is defined as the period S_In. In this case, in the omitted period FSel, it is assumed that the data input to the external control terminals / CE, CLE, and ALE in the immediately preceding period FSel is input again to the external control terminals / CE, CLE, and ALE.

[0264] Also, during the period FSel of timings t603 to t604, the controller die CD inputs “X, L, H” to the external control terminals / CE, CLE, and ALE of the memory die MD2. Along with this, an input / output data selection signal indicating that address data Add is to be input is input.

[0265] Also, during the period S_In of timings t604 to t605, the controller die CD inputs address data Add to the memory die MD2 over three cycles. Also, in the illustrated example, “1” is input to the external control terminal / CE in the first cycle of the period S_In. Along with this, the subsequent period FSel is omitted.

[0266] Similarly, during the period S_In of timings t605 to t606, the period S_In of timings t606 to t607, and the period S_In of timings t607 to t608, the controller die CD inputs address data Add to the memory die MD2 over three cycles. Also, in the illustrated example, “1” is input to the external control terminal / CE in the first cycle of these periods S_In. Along with this, the subsequent periods FSel are omitted.

[0267] Also, during the period S_In from timing t608 to t609, the controller die CD inputs address data Add to the memory die MD2 over three cycles. Also, in the illustrated example, “0” is input to the external control terminal / CE during the first cycle of the period S_In. Therefore, the subsequent period FSel is not omitted.

[0268] Also, during the period FSel from timing t609 to t610, the controller die CD inputs “X, H, L” to the external control terminals / CE, CLE, ALE of the memory die MD2. Along with this, an input / output data selection signal indicating that command data Cmd is to be input is input.

[0269] Also, during the period S_In from timing t610 to t611, the controller die CD inputs command data Cmd to the memory die MD2 over three cycles.

[0270] [Third Embodiment] [Configuration] Next, with reference to FIG. 41, the configuration of the semiconductor memory device according to the third embodiment will be described. FIG. 41 is a schematic block diagram showing the configuration of the memory die MD3 according to the third embodiment.

[0271] As shown in FIG. 41, the semiconductor memory device according to the present embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment includes a command register CMR´ instead of the command register CMR. The command register CMR´ is basically configured in the same manner as the command register CMR.

[0272] However, the command register CMR is configured to be able to output up to 2 8 (= 256) types of control signals according to 8-bit command data Cmd.

[0273] On the one hand, the command register CMR´ is configured to be able to output 257 or more control signals. For example, the command register CMR´ may be configured to be able to output up to 512 control signals. For example, the command register CMR´ includes a command processing unit cmr1 and a command processing unit cmr2.

[0274] The command processing unit cmr1 is configured to be able to output up to 256 control signals according to 8-bit command data Cmd. The command processing unit cmr1 corresponds to, for example, the command data Cmd that can be used in the semiconductor memory device according to the first embodiment. In FIG. 41, such command data Cmd is illustrated as "Basic Command". Hereinafter, such command data Cmd may be referred to as "basic command data Cmd".

[0275] The command processing unit cmr2 is configured to be able to output up to 256 control signals according to 8-bit command data Cmd. The command processing unit cmr2 corresponds to, for example, command data Cmd other than "Basic Command". In FIG. 41, such command data Cmd is illustrated as "Extended Command". Hereinafter, such command data Cmd may be referred to as "extended command data Cmd".

[0276] Note that the command register CMR´ may further include the same configuration as the command processing units cmr1 and cmr2. In this case, the command register CMR´ may be configured to be able to output 513 or more control signals.

[0277] [Role of External Terminals in Operation Mode MODEb] FIGS. 42 and 43 are truth tables for explaining the role of external terminals in operation mode MODEb. FIG. 42 shows the role of the external control terminal in the second cycle of the period FSel during which the input / output data selection signal is input. FIG. 43 shows the role of the external control terminal in the third cycle of the period FSel during which the input / output data selection signal is input.

[0278] The semiconductor memory device according to this embodiment basically operates in the same manner as the semiconductor memory device according to the first embodiment.

[0279] However, in this embodiment, when an input / output data selection signal indicating that command data Cmd corresponding to the above "Basic Command" is to be input is input in the first cycle of the period FSel, the controller die CD, for example, inputs "H" to the external control terminal CLE, inputs "L" to the external control terminal ALE, and raises the voltage of the external control terminal / WE from "L" to "H" (see FIG. 13).

[0280] When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE in the first cycle of the period FSel, the period FSel ends in one cycle. Also, the data input to the period S_In immediately after this period FSel is held in the buffer memory in the input / output control circuit I / O as the command data Cmd corresponding to the above "Basic Command", transferred to the command register CMR' (FIG. 41), and processed by the command processing unit cmr1 (FIG. 41).

[0281] Also, in this embodiment, when an input / output data selection signal indicating that the above extended command data Cmd is to be input is input in the second cycle of the period FSel, as illustrated in FIG. 42, the controller die CD, for example, inputs "H" to the external control terminal CLE, inputs "L" to the external control terminal ALE, and raises the voltage of the external control terminal / WE from "L" to "H".

[0282] When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE in the second cycle of the period FSel, the period FSel ends in two cycles. Also, the data input to the period S_In immediately after this period FSel is held in the buffer memory in the input / output control circuit I / O as the above extended command data Cmd, transferred to the command register CMR' (FIG. 41), and processed by the command processing unit cmr2 (FIG. 41).

[0283] As described above, the command register CMR' may be configured to output 513 or more control signals.

[0284] In such a case, when an input / output data selection signal for inputting command data Cmd is input in the third cycle of the period FSel, as illustrated in FIG. 43, the controller die CD may, for example, input “H” to the external control terminal CLE and input “L” to the external control terminal ALE, and raise the voltage of the external control terminal / WE from “L” to “H”.

[0285] Also, when “H” is input to the external control terminal CLE and “L” is input to the external control terminal ALE in the third cycle of the period FSel, the period FSel may end in three cycles. Further, the data input to the period S_In immediately after this period FSel may be held in the buffer memory in the input / output control circuit I / O as command data Cmd, transferred to the command register CMR' (FIG. 41), and processed by a configuration other than the command processing units cmr1, cmr2 (FIG. 41).

[0286] [Examples of Extended Command Data Cmd] The above extended command data Cmd can be used in various applications. Hereinafter, two applications of the extended command data Cmd will be exemplified as its applications.

[0287] [Shift Read Using Extended Command Data Cmd] First, as an application of the extended command data Cmd, shift read will be exemplified.

[0288] FIG. 44(a) is a schematic histogram for explaining the threshold voltage of a memory cell MC in which 3-bit data is recorded. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. FIG. 44(b) is a table showing an example of the relationship between the threshold voltage of the memory cell MC in which 3-bit data is recorded and the recorded data.

[0289] In the example of Fig. 44(a), the threshold voltage of the memory cell MC is controlled to eight states. The threshold voltage of the memory cell MC controlled to the Er state is lower than the erase verify voltage V VFYEr . Also, for example, the threshold voltage of the memory cell MC controlled to the A state is higher than the verify voltage V VFYA and lower than the verify voltage V VFYB . Also, for example, the threshold voltage of the memory cell MC controlled to the B state is higher than the verify voltage V VFYB and lower than the verify voltage V VFYC . Similarly, the threshold voltages of the memory cells MC controlled to the C state to the F state are respectively higher than the verify voltage V VFYC to the verify voltage V VFYF and lower than the verify voltage V VFYD to the verify voltage V VFYG . Also, for example, the threshold voltage of the memory cell MC controlled to the G state is higher than the verify voltage V VFYG and lower than the read path voltage V READ .

[0290] Also, in the example of Fig. 44(a), a read voltage V CGAR is set between the threshold voltage distribution corresponding to the Er state and the threshold voltage distribution corresponding to the A state. Also, a read voltage V CGBR is set between the threshold voltage distribution corresponding to the A state and the threshold voltage distribution corresponding to the B state. Similarly, between the threshold voltage distribution corresponding to the B state and the threshold voltage distribution corresponding to the C state to between the threshold voltage distribution corresponding to the F state and the threshold voltage distribution corresponding to the G state, read voltages V CGCR to V CGGR are respectively set.

[0291] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, a memory cell MC in the erased state. For example, the data "111" is assigned to the memory cell MC in the Er state.

[0292] Also, the A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above Er state. For example, data "011" is assigned to the memory cell MC in the A state.

[0293] Also, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above A state. For example, data "001" is assigned to the memory cell MC in the B state.

[0294] Similarly, in the following, the C state to G state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B state to F state. For example, data "101", "100", "000", "010", "110" are assigned to the memory cells MC in these states.

[0295] In addition, in the case of the assignment as illustrated in Fig. 44(b), the data of the lower bit can be discriminated by one read voltage V CGDR , the data of the middle bit can be discriminated by two read voltages V CGBR , V CGFR , and the data of the upper bit can be discriminated by four read voltages V CGAR , V CGCR , V CGER , V CGGR . Such an assignment of data is sometimes called a 1-2-4 code.

[0296] In addition, the number of bits of data recorded in the memory cell MC, the number of states, the assignment of data to each state, etc. can be changed as appropriate.

[0297] Fig. 45 is a timing chart for explaining the read operation.

[0298] In addition, in the following description, the word line WL that is the target of the operation is called the selected word line WL S , and the other word lines WL are called non-selected word lines WL Umay be referred to as. Also, in the following description, among the plurality of memory cells MC included in the string unit SU (Fig. 5) that is the target of the operation, the selection word line WL S connected to (hereinafter, may be referred to as "selected memory cell MC") will be described as an example of performing a read operation on it.

[0299] Also, in the following description, as described with reference to Fig. 44(a), 3-bit data is stored in the plurality of memory cells MC, and an example in which data assignment as described with reference to Fig. 44(b) is performed on the plurality of memory cells MC will be shown. Also, in the following description, an example of discriminating the data of the middle bit of the selected memory cell MC will be shown.

[0300] At timing t701 in Fig. 45, the read operation is started, and the voltage of the terminal RY / / BY has fallen from "H" to "L".

[0301] At timing t702, the selection word line WL S and the non-selection word line WL U are supplied with the read path voltage V READ described with reference to Fig. 44(a). Also, the voltage V SG is supplied to the selection gate lines (SGD, SGS, SGSb). The voltage V SG has a magnitude such that the selection gate lines (SGD, SGS, SGSb) are in the ON state.

[0302] At timing t703, the selection word line WL S is supplied with the read voltage V CGBR . Also, during the period from timing t703 to timing t704, the current of the bit line BL is detected by the sense amplifier SA, and thereby data indicating the ON / OFF state of the memory cell MC is acquired.

[0303] At timing t704, the selection word line WL S is supplied with the read voltage V CGFRSupply. Also, during the period from timing t704 to timing t705, the current in the bit line BL is detected by the sense amplifier SA, and thereby data indicating the ON / OFF state of the memory cell MC is acquired.

[0304] At timing t705, the selected word line WL S and the non-selected word line WL U are supplied with the read path voltage V READ Supply.

[0305] At timing t706, the selected word line WL S , the non-selected word line WL U and the selected gate lines (SGD, SGS, SGSb) are supplied with the ground voltage V SS Supply.

[0306] Figure 46 is a timing chart for explaining shift read. Figure 46(a) shows the voltage of the selected word line WL S in the read operation. Figure 46(b) shows the voltage of the selected word line WL S in the shift read according to one embodiment. Figure 46(c) shows the voltage of the selected word line WL S in the shift read according to another embodiment.

[0307] Shift read is basically executed in the same manner as the read operation. However, the voltage supplied to the selected word line WL S in the shift read is different from the voltage supplied to the selected word line WL S in the read operation.

[0308] Here, when a write operation is executed on a plurality of memory cells MC, the threshold voltages of these plurality of memory cells MC are distributed as exemplified in, for example, Figure 44(a). However, after the write operation is executed and before the erase operation is executed, the threshold voltages of the plurality of memory cells MC may vary. In such a case, for example, the threshold voltages of some of the memory cells MC controlled to the A state are the read voltage V CGBRit may become larger than this and may be determined as data "0". Also, the threshold voltage of some of the memory cells MC controlled to the B state is the read voltage V CGBR it may become smaller than this and may be determined as data "1". A bit read from such a memory cell MC becomes an error bit. In such a case, the selection word line WL S is supplied with a voltage larger than the read voltage V CGAR ~V CGGR , or a voltage smaller than the read voltage V CGAR ~V CGGR so that the number of memory cells MC that become error bits can be suppressed to a minimum or a value close thereto. Therefore, in shift read, the selection word line WL S is supplied with a voltage larger than the read voltage V CGAR ~V CGGR , or a voltage smaller than the read voltage V CGAR ~V CGGR .

[0309] For example, in the example of FIG. 46(b), at timing t703, instead of supplying the read voltage V S to the selection word line WL CGBR , the read voltage V CGBR ' is supplied. The read voltage V CGBR ' is smaller than the read voltage V CGBR .

[0310] Also, for example, in the example of FIG. 46(b), at timing t704, instead of supplying the read voltage V S to the selection word line WL CGFR , the read voltage V CGFR ' is supplied. The read voltage V CGFR ' is smaller than the read voltage V CGFR .

[0311] When performing a read operation, for example, as described with reference to FIG. 20 etc., the controller die CD (FIG. 1) supplies the memory die MD with the command data "00h" as the command data Cmd. Thereafter, the controller die CD supplies the memory die MD with the address data Add and the command data "30h".

[0312] On the other hand, when performing the shift read illustrated in FIG. 46(b), instead of supplying the memory die MD with the command data "00h" as the command data Cmd (basic command data Cmd), the controller die CD (FIG. 1) may supply the extended command data Cmd such as the command data "11h", "12h", "13h",... etc. Also, when the command data "12h" is input, the read voltage V CGBR and the read voltage V CGBR ´, and the difference between the read voltage V CGFR and the read voltage V CGFR ´ (hereinafter referred to as "voltage shift amount") may be larger than the voltage shift amount when the command data "11h" is input. Similarly, the voltage shift amount when the command data "13h" is input may be larger than the voltage shift amount when the command data "12h" is input. Also, after the input of the command data "11h", "12h", "13h",... etc., the controller die CD may supply the memory die MD with the address data Add and the command data "30h". The command data "30h" may be the basic command data Cmd or the extended command data Cmd.

[0313] Also, for example, in the example of FIG. 46(c), at the timing t703, instead of supplying the read voltage V S to the selected word line WL CGBR , the read voltage V CGBR ´´ is supplied. The read voltage V CGBR ´´ is larger than the read voltage V CGBR .

[0314] Also, for example, in the example of FIG. 46(c), at the timing t704, the selected word line WL Sto the read voltage V CGFR instead of the read voltage V CGFR ´´ is supplied. The read voltage V CGFR ´´ is larger than the read voltage V CGFR .

[0315] In addition, when executing the shift read illustrated in FIG. 46(c), instead of supplying the command data “00h” as the command data Cmd (basic command data Cmd) to the memory die MD by the controller die CD (FIG. 1), the command data “21h”, “22h”, “23h”,... etc. may be supplied as the extended command data Cmd. Also, the voltage shift amount when the command data “22h” is input may be larger than the voltage shift amount when the command data “21h” is input. Similarly, the voltage shift amount when the command data “23h” is input may be larger than the voltage shift amount when the command data “22h” is input. Further, after the input of the command data “21h”, “22h”, “23h”,... etc., the controller die CD may supply the address data Add and the command data “30h” to the memory die MD. The command data “30h” may be the basic command data Cmd or the extended command data Cmd.

[0316] FIG. 47 is a schematic waveform diagram showing the state when the shift read is executed in the operation mode MODEb. In the example of FIG. 47, the memory die MD is set to the operation mode MODEb.

[0317] In the example of FIG. 47, first, a command set including the command data “11h” is input via the external control terminals CLE, ALE. Note that the command data “11h” is input as the extended command data Cmd.

[0318] Here, for example, when performing shift read in the first embodiment, the set feature is executed by a method as described with reference to FIG. 30, and thereby the voltage shift amount is input as feature data Fd to the memory die MD. Thereafter, a read operation is executed by a method as described with reference to FIG. 20.

[0319] On the other hand, when performing shift read in the third embodiment, shift read is executed by a method as described with reference to FIG. 47 without executing the set feature.

[0320] According to such a method, by omitting the execution of the set feature, it is possible to realize a speedup of the operation.

[0321] [Control of the internal path delay detection circuit 205 (FIG. 9) using the extended command data Cmd] Next, as an application of the extended command data Cmd, control of the internal path delay detection circuit 205 (FIG. 9) is exemplified.

[0322] As described with reference to FIG. 9, in the semiconductor memory device according to the first embodiment, it is possible to acquire the number of pulses output from the internal path delay detection circuit 205 as the feature data Fd. Further, based on this, it is possible to measure the delay amount of the signal in the signal transfer circuit 204 (FIG. 8).

[0323] Here, in the semiconductor memory device according to the first embodiment, the internal path delay detection circuit 205 is driven in response to the execution of the get feature. That is, the enable signal of the NAND circuit 212 (FIG. 9) in the internal path delay detection circuit 205 becomes the "H" state in response to the execution of the get feature. Therefore, in the semiconductor memory device according to the first embodiment, after the execution of the get feature and until the delay amount is measured by the internal path delay detection circuit 205, the feature data Fd cannot be acquired.

[0324] On the other hand, in the semiconductor memory device according to the third embodiment, it is possible to drive the internal path delay detection circuit 205 in response to the input of the extended command data Cmd. That is, in response to the input of the extended command data Cmd, it is possible to set the enable signal of the NAND circuit 212 (FIG. 9) in the internal path delay detection circuit 205 to the "H" state.

[0325] According to such a configuration, by driving the internal path delay detection circuit 205 in advance before the execution of the get feature, it may be possible to execute the get feature at high speed.

[0326] [Fourth Embodiment] Next, with reference to FIG. 48, the configuration of the semiconductor memory device according to the fourth embodiment will be described. FIG. 48 is a schematic block diagram showing the configuration of the memory die MD4 according to the fourth embodiment.

[0327] As shown in FIG. 48, the semiconductor memory device according to the present embodiment is basically configured in the same manner as the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to the fourth embodiment includes a command register CMR' instead of the command register CMR.

[0328] Next, with reference to FIGS. 49 and 50, the operation of the semiconductor memory device according to the fourth embodiment will be described. The semiconductor memory device according to the fourth embodiment basically operates in the same manner as the semiconductor memory device according to the second embodiment.

[0329] However, in the semiconductor memory device according to the second embodiment, the 1-bit data input to the external control terminal / CE in the first cycle of the period S_In is used as flag data. Also, in the semiconductor memory device according to the second embodiment, the period S_In is omitted according to this flag data.

[0330] On the other hand, in the semiconductor memory device according to the fourth embodiment, according to this flag data, it is determined whether the input command data Cmd is extended command data Cmd.

[0331] For example, when this flag data is "0", the command data Cmd input during this period S_In is determined not to be extended command data Cmd. In this case, this command data Cmd is processed by the command processing unit cmr1 (Fig. 48) in the command register CMR'.

[0332] On the other hand, when this flag data is "1", the command data Cmd input during this period S_In is determined to be extended command data Cmd. In this case, this command data Cmd is processed by the command processing unit cmr2 (Fig. 48) in the command register CMR'.

[0333] Fig. 49 is a schematic waveform diagram showing the state when a read operation is executed in the operation mode MODEb. In the example of Fig. 49, the memory die MD is set to the operation mode MODEb.

[0334] In the example of Fig. 49, at timing t800, the controller die CD inputs "L" to the external control terminal / CE of the memory die MD4. Accordingly, "L" is input to the latch circuit 206 (Fig. 39), and the memory die MD4 becomes the selected state.

[0335] Also, during the period FSel from timing t801 to t802, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD4. Accordingly, an input / output data selection signal indicating that command data Cmd is to be input is input.

[0336] Also, during the period S_In from timing t802 to t803, the controller die CD inputs command data "00h" to the memory die MD4 over 3 cycles. Also, in the illustrated example, "0" is input to the external control terminal / CE in the first cycle of the period S_In. Therefore, the command data "00h" is determined not to be extended command data Cmd.

[0337] Also, during the period FSel from timing t803 to t804, the controller die CD inputs "X, L, H" to the external control terminals / CE, CLE, ALE of the memory die MD4. Along with this, an input / output data selection signal indicating that address data Add is to be input is inputted.

[0338] Also, during the period S_In from timing t804 to t805, the controller die CD inputs address data Add to the memory die MD4 over 3 cycles. Also, in the example shown in the figure, in the first cycle of the period S_In, "0" or "1" may be input to the external control terminal / CE.

[0339] Also, during the periods F_Sel from timing t805 to t806, from timing t807 to t808, and from timing t809 to t810, similar to the period FSel from timing t803 to t804, the controller die CD inputs "X, L, H" to the external control terminals / CE, CLE, ALE of the memory die MD4.

[0340] Also, during the periods S_In from timing t806 to t807, after timing t808, before timing t809, and from timing t810 to t811, similar to the period S_In from timing t804 to t805, the controller die CD inputs address data Add to the memory die MD4 over 3 cycles.

[0341] Also, during the period FSel from timing t811 to t812, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD4. Along with this, an input / output data selection signal indicating that command data Cmd is to be input is inputted.

[0342] Also, during the period S_In from timing t812 to t813, the controller die CD inputs command data "30h" to the memory die MD4 over 3 cycles. Also, in the illustrated example, "0" is input to the external control terminal / CE in the first cycle of the period S_In.

[0343] Figure 50 is a schematic waveform diagram showing the state when shift read is executed in the operation mode MODEb. In the example of Figure 50, the memory die MD is set to the operation mode MODEb.

[0344] The operation shown in Figure 50 is basically executed in the same manner as the operation shown in Figure 49.

[0345] However, in the example of Figure 50, during the period S_In from timing t802 to t803, the controller die CD inputs command data "11h" to the memory die MD4 over 3 cycles. Also, in the illustrated example, "1" is input to the external control terminal / CE in the first cycle of the period S_In. Therefore, the command data "11h" is determined as the extended command data Cmd.

[0346] [Other Embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the above description is merely illustrative, and the specific configuration, operation, etc. can be adjusted as appropriate.

[0347] For example, in the semiconductor memory devices according to the first and third embodiments, in the operation mode MODEb, 2-bit data input / output was performed using the external control terminals CLE and ALE. Also, in the semiconductor memory devices according to the second and fourth embodiments, in the operation mode MODEb, 3-bit data input / output was performed using the external control terminals / CE, CLE, and ALE. However, such a method is merely an example, and the specific method can be adjusted as appropriate. For example, in the operation mode MODEb, other terminals or the like may be used to perform 3-bit or 4-bit or more data input / output. More specifically, for example, in the operation mode MODEb, instead of or in addition to the external control terminal / CE, the external control terminal / WP or the like may be used to perform 3-bit or 4-bit data input / output. Also, at least one terminal may be selected from among the terminals including the external control terminals / CE, CLE, and ALE to perform 1-bit or 2-bit data input / output.

[0348] Also, for example, in the first to fourth embodiments, the function assignments for the external control terminals / CE, CLE, ALE, etc. were exemplified. However, such an assignment is merely an example, and the specific assignment can be adjusted as appropriate.

[0349] For example, in the semiconductor memory device according to the first embodiment, a part of the functions exemplified in FIGS. 13 and 14 may be interchanged. Also, for example, functions other than those exemplified in FIGS. 13 and 14 may be added, or a part of the functions exemplified in FIGS. 13 and 14 may be omitted. Also, the third cycle of the period FSel may be added. Also, depending on the data input in the first cycle of the period FSel, the function assigned to the data input in the second cycle of the period FSel may be changed.

[0350] The command set includes command data Cmd and address data Add. In operation mode MODEb, the semiconductor memory device according to the first embodiment transmits and receives the command data Cmd and the address data Add over several cycles using an input / output data selection signal (header) and the command data Cmd or the address data Add (body), respectively. Here, the input of the command set may be aborted halfway. In that case, the command data Cmd and the address data Add may not be input up to the final cycle. In such a case, each memory die MD may be configured to be reset in response to a reset instruction signal from the controller die CD.

[0351] For example, as shown in FIG. 51, when the controller die CD aborts the input of the command set halfway, as a reset instruction signal, the voltage of the external control terminal / CE is transitioned from “L” to “H” for a certain period and then returned to “L”. Thereafter, the controller die CD inputs a new command set to the memory die MD. The new command set may be the same as or different from the command set whose input was aborted halfway. After receiving the newly input command set, the memory die MD executes an operation according to the command set.

[0352] By configuring the controller die CD to be able to transmit a reset instruction signal and configuring the memory die MD to be able to be reset in response to the reset instruction signal, a semiconductor memory device that operates stably can be realized even when it becomes necessary to abort the input of the command set halfway.

[0353] Also, for example, in the semiconductor memory devices according to the second and fourth embodiments, the 1-bit data input to the external control terminal / CE in the first cycle of the period S_In was used as flag data. Also, in the semiconductor memory device according to the second embodiment, the period S_In was omitted according to this flag data. Also, in the semiconductor memory device according to the second embodiment, it was determined whether the input command data Cmd was extended command data Cmd according to this flag data. However, such a method is merely an example, and the specific method can be adjusted as appropriate. For example, the data input to the external control terminal / CE in the first cycle of the period S_In may be used as a parity bit. In such a case, this parity bit may correspond to the 3-bit data input in the period FSel, or may correspond to the 8-bit data input in the period S_In.

[0354] Also, for example, in the semiconductor memory devices according to the second and fourth embodiments, the 1-bit data input to the external control terminal / CE in the first cycle of the period S_In was used as flag data. However, for example, the data input to a terminal other than the external control terminal / CE, or the data input after the second cycle of the period S_In, may be used as the above-mentioned flag data, parity bit, or other data.

[0355] Also, for example, in the semiconductor memory device according to the third embodiment, an example was shown in which the extended command data Cmd for executing shift read is “11h”, “12h”, “13h”... and “21h”, “22h”, “23h”.... However, the extended command data Cmd assigned to shift read is not limited to these. Any command data can be assigned within the range that can be assigned as the extended command data Cmd.

[0356] Further, for example, in the semiconductor memory devices according to the third and fourth embodiments, an example was shown in which the extended command data Cmd is 8-bit data, similar to the normal command data Cmd. However, the extended command data Cmd may be shorter than 8 bits or longer than 8 bits.

[0357] For example, when the extended command data Cmd is shorter than 8 bits, the area of the command processing unit cmr2 (FIG. 41) can be reduced. Also, for example, in the third embodiment, when the extended command data Cmd is 8 bits, the extended command data Cmd is input to the memory die MD3 over 4 cycles. On the other hand, in the third embodiment, when the extended command data Cmd is 5 bits or 6 bits, the extended command data Cmd is input to the memory die MD3 over 3 cycles. That is, when the extended command data Cmd is shorter than 8 bits, it is possible to speed up the operation.

[0358] Also, for example, when the extended command data Cmd is longer than 8 bits, it becomes possible to handle more command data Cmd.

[0359] [Others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0360] MC… Memory cell, MCA… Memory cell array, PC… Peripheral circuit, ADR… Address register, CMR… Command register.

Claims

1. A first pad capable of transmitting and receiving a first timing signal, A second pad capable of transmitting and receiving data in response to the first timing signal, A third pad capable of receiving a second timing signal, A fourth pad capable of receiving control information in response to the second timing signal, A memory cell array including a string in which a plurality of memory cell transistors are connected in series, A sense amplifier connected to the memory cell array, A first register connected to the sense amplifier and capable of storing data read from the memory cell array, A second register capable of storing first control information, A third register capable of storing second control information, A control circuit capable of executing a data out operation for outputting the data stored in the first register from the second pad and having, Based on the input to the fourth pad in response to the second timing signal for i cycles (i is an integer of 2 or more), the first control information is stored in the second register, Based on the input to the fourth pad in response to the second timing signal for j cycles (j is an integer different from i), the second control information is stored in the third register A semiconductor memory device.

2. The fourth pad is A command latch enable signal receiving pad, An address latch enable signal receiving pad and includes, j is an integer greater than i The semiconductor memory device according to Claim 1.

3. The first control information includes a command signal or an address signal, The second control information includes characteristic data information, The second register includes a command register or an address register, The third register includes a characteristic register The semiconductor memory device according to Claim 2.

4. A first receiver and a first driver connected to the second pad, A second receiver and a second driver connected to the fourth pad and further having, In the data out operation, the first driver outputs the data stored in the first register to the second pad, In the characteristic information output operation, the second driver outputs the characteristic data information stored in the characteristic register to the fourth pad The semiconductor memory device according to Claim 3.

5. Further having a fourth register for storing status information, In the status information output operation, the second driver outputs the status information stored in the fourth register to the fourth pad The semiconductor memory device according to Claim 4.

6. a fifth pad that receives a third timing signal; a receiving unit that receives a trigger signal and outputs an output start signal; further comprising: based on an input to the fourth pad corresponding to the second timing signal for k cycles, the trigger signal is transferred to the receiving unit; after receiving a command set that instructs output of data stored in the first register; after the receiving unit outputs the output start signal; the first driver outputs the data to the second pad in response to the third timing signal input to the fifth pad; after receiving the command set that instructs output of data stored in the first register; before the receiving unit outputs the output start signal; even if the third timing signal is input to the fifth pad, the first driver does not output the data to the second pad The semiconductor memory device according to claim 5.

7. a first pad capable of transmitting and receiving a first timing signal; a second pad capable of transmitting and receiving data in response to the first timing signal; a third pad capable of receiving a second timing signal; a fourth pad capable of receiving control information in response to the second timing signal; a memory cell array including a string in which a plurality of memory cell transistors are connected in series; a sense amplifier connected to the memory cell array; a first register connected to the sense amplifier and capable of storing data read from the memory cell array; a second register capable of storing first control information; a third register capable of storing second control information; a control circuit capable of executing a data out operation for outputting the data stored in the first register from the second pad; having: based on an input to the fourth pad corresponding to the second timing signal for i cycles (i is an integer of 2 or more), the received control information is stored in one of the second register or the third register; based on an input to the fourth pad corresponding to the second timing signal for j cycles (j is an integer smaller than i) following the i cycles, the received control information is stored in the one of the second register or the third register; a semiconductor memory device.

8. the first control information includes a command signal; a first command processing unit that processes a first command signal; a second command processing unit that processes a second command signal The semiconductor memory device according to any one of claims 1 to 7, further comprising

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