Antenna device having an integrated antenna array and a low-loss multilayer interposer

Abstract

The present disclosure provides an antenna device including a semiconductor wafer including a radiating layer with a plurality of antenna elements forming an antenna array, a plurality of tiles each having a beamforming circuit, and a multi-layer interposer. The multi-layer interposer may include a lower dielectric layer adjacent to a substrate, an upper dielectric layer adjacent to the radiating layer, a metal layer between the lower layer and the upper layer, the metal layer including a plurality of conductive traces, a plurality of first vias extending through both the upper layer and the lower layer and electrically coupling the beamforming circuit to the plurality of antenna elements, and a plurality of second vias extending between the beamforming circuit and the conductive traces and interconnecting the tiles.

Description

Technical Field

[0001] The present disclosure generally relates to antennas, and more specifically to a compact configuration of an antenna array integrated with a beamforming circuit.

Summary of the Invention

Problems to be Solved by the Invention

[0002] Antenna arrays are currently deployed in various applications at microwave and millimeter-wave frequencies, including aircraft, satellites, vehicles, and base stations for general terrestrial communication. Such antenna arrays typically include patch radiating elements driven using a phase shift beamforming circuit to form a phased array for directing beams. In many cases, it is desirable for the entire antenna system, including the antenna array and the beamforming circuit, to occupy a minimum space with a low profile while meeting the required performance metrics. In particular, at high millimeter-wave frequencies, due to the very small wavelengths and component dimensions / spacings, there is a problem of limiting undesirable reactance and losses.

[0003] In one aspect of the technology of the present disclosure, an antenna device includes a radiation layer including a plurality of antenna elements forming an antenna array, a semiconductor wafer including a plurality of tiles each having a beamforming circuit, and a multilayer interposer. The multilayer interposer includes a lower dielectric layer adjacent to the wafer, an upper dielectric layer adjacent to the radiation layer, a metal layer between the lower dielectric layer and the upper dielectric layer and including a plurality of conductive traces, a plurality of first vias extending through both the upper dielectric layer and the lower dielectric layer and electrically connecting the beamforming circuit to the plurality of antenna elements, and a plurality of second vias extending between the beamforming circuit and the conductive traces and interconnecting the tiles.

[0004] In another aspect, the antenna device includes a semiconductor wafer having a radiation layer with a plurality of antenna elements forming an antenna array, and a plurality of RF beamforming circuits each having a transistor region internally formed in the semiconductor wafer, wherein each beamforming circuit has at least one phase shifter and a transmit path amplifier and / or a receive path amplifier, a multilayer interposer, and a substrate. The multilayer interposer includes a lower dielectric layer adjacent to the substrate, an upper dielectric layer adjacent to the radiation layer, and a metal layer between the lower layer and the upper layer, the metal layer including a plurality of conductive traces forming a combiner / distributor network for combining and / or distributing signals between the plurality of RF beamforming circuits and input / output connection points of the interposer, a plurality of first vias extending through both the upper layer and the lower layer and electrically connecting the plurality of RF beamforming circuits to the plurality of antenna elements, and a plurality of second vias extending between the RF beamforming circuits and the conductive traces, some of which interconnect the antenna elements with the combiner / distributor network through the RF beamforming circuits. The wafer further includes at least one intermediate amplifier that amplifies a transmitted or received signal routed from another one of the second vias from / to an intermediate point of the combiner / distributor network and outputs the amplified transmitted or received signal back to the combiner / distributor network through a further one of the second vias.

[0005] In another aspect, a method of manufacturing an antenna device includes sequentially applying the same reticle image to each of a plurality of regions of a semiconductor wafer, thereby forming respective tiles within each region, each tile including a transistor region ion implanted within the wafer and an RF beamforming circuit having a metal wiring pattern on the surface of the wafer, and attaching an interposer to the wafer. The interposer includes a lower dielectric layer adjacent to the wafer, an upper dielectric layer, a metal layer between the lower dielectric layer and the upper dielectric layer, the metal layer including a plurality of conductive traces, a plurality of first vias extending through both the upper layer and the lower layer, and a plurality of second vias extending between the lower surface of the interposer and the metal layer and interconnecting the plurality of tiles. A radiation layer including a plurality of antenna elements is mounted or formed on the upper surface of the interposer, such that the antenna elements are electrically connected to the RF beamforming circuit through the plurality of first vias.

Brief Description of the Drawings

[0006] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description in conjunction with the accompanying drawings in which like reference numerals indicate like elements or features. Various elements of the same or similar type may be distinguished by adding a dash and a second label that differentiates between the same / similar elements to the reference label (e.g., -1, -2), or by directly adding a second label to the reference label. However, if a given description uses only the first reference label, it is applicable to any one of the same / similar elements having the same first reference label regardless of the second label. Elements and features may not be drawn to scale in the drawings.

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[0019] The following description is provided to assist in a comprehensive understanding of specific exemplary embodiments of the technology disclosed herein for illustrative purposes with reference to the accompanying drawings. This specification includes various specific details to assist those skilled in the art in understanding the technology, but these details should be regarded as merely illustrative. For the sake of brevity and clarity, descriptions of well-known functions and structures may be omitted if they may obscure the understanding of the technology by those skilled in the art.

[0020] In this specification, a substrate may be said to "include" a circuit, or "include a circuit formed therein," etc., even if the circuit is only partially formed within the substrate (e.g., as a doped region of a transistor or an embedded conductor). A substrate said to include a circuit may also have conductive elements partially formed on the surface of the substrate.

[0021] In this specification, a "beamforming circuit" can be any circuit that contributes to the formation of an antenna beam. A beamforming circuit can be composed of one or more active components and / or one or more passive components. Examples of active components include amplifiers, phase shifters, and switches, and examples of passive components include filters and portions of transmission lines. A plurality of interconnected beamforming circuits can together form an RF front end connected to an antenna array.

[0022] As used herein, the term "via transition" means a set of two or more connections that includes at least one via, where a set of connections collectively effect a transition from one transmission line or mechanism to another. A via transition can be a set of three vias of a ground-signal-ground (GSG) connection between a coplanar waveguide (CPW), microstrip, or strip to a probe feed connected to an antenna element. A via transition can also be a GSG connection between a CPW or microstrip to a strip line, in which case the GSG connection includes two vias and a ground-ground connection. In yet other examples, a via transition that connects a microstrip or CPW in one layer to a microstrip in another layer can have one via and one direct connection.

[0023] FIG. 1 is an exploded perspective view of an antenna device 10 according to one embodiment. The antenna device 10 includes a radiating layer 20, a wafer 40, and a multilayer interposer 30 disposed between the radiating layer 20 and the wafer 40. The antenna element 22 of the radiating layer 20 is connected through the interposer 30 to a beamforming circuit within the wafer 40. The wafer 40 is composed of a semiconductor material such as silicon, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The interposer 30 can be composed of a material having a lower loss tangent than the wafer 40, such as quartz or fused silica. The interposer 30 provides low-loss routing and distribution / combination of RF signals between connection points within the wafer 40, or between the wafer 40 and the antenna element 22. In one example, the antenna device 10 is configured for operation over a millimeter (mm) wave frequency band generally defined as a band within the range of 30 GHz to 300 GHz. In other examples, the antenna device 10 operates within the microwave range of approximately 1 GHz to 30 GHz, or within the sub-microwave range below 1 GHz. As used herein, a radio frequency (RF) signal means a signal having any frequency below 1 GHz to 300 GHz.

[0024] The radiating layer 20 may include "n" antenna elements 22-1 to 22-n that define an antenna array 23 formed on the upper surface of the dielectric 25. The number n of the antenna elements 22, their types, sizes, shapes, element-to-element spacing, and the manner in which they are supplied from the beamforming circuit can be changed by design to achieve the target performance metrics. Examples of such performance metrics include beam width, pointing direction, polarization, side lobes, power loss, beam shape, etc. over the required frequency band. The antenna elements 22 can be microstrip patch antenna elements as illustrated in FIG. 1, or other radiator types such as printed dipoles or slotted elements. Depending on the application, the antenna elements 22 can be connected to beamforming components for transmitting and / or receiving RF signals. The connections of the antenna elements 22-1 to 22-n to the beamforming circuit may each be through probe feeds 27-1 to 27-n formed within the dielectric 25 and connected to other vias within the interposer 30. The dielectric 25 can be a low-loss material such as an air / honeycomb material that can be grown atomically layer by layer over the interposer 30. As an additional example, other materials such as liquid crystal polymer or quartz may be used.

[0025] The interposer 30 may include a low-loss dielectric material such as quartz or fused silica. In one embodiment, the interposer 30 has a stripline structure, in which case the interposer 30 is formed on the upper surface of the upper dielectric layer 33 and functions as both a stripline for the antenna element 22 and an upper ground plane with respect to the ground plane, an upper metal layer 36, a lower metal layer (lower ground plane) 39 formed on the bottom surface of the lower dielectric layer 31, and a metal (conductive) layer 37 between the upper dielectric layer 33 and the lower dielectric layer 31 for forming the center conductor of the stripline structure. Each of the metal layers 39, 37, and 36 may be a thin-film metal layer. The upper metal layer 36 has an opening therein through which the probe feed 27 is connected to the upper end of the via 72s and is separated from the ground plane. The lower metal layer 39 also has an opening through which the lower ends of the vias 72s and 82s penetrate. The vias 72s connect the probe feed 27 to the connection points on the wafer 40. The vias 72s are each part of each of the respective GSG via transitions 72 discussed below. The vias 82s are blind vias that connect the points of the center conductor of the layer 37 to other connection points on the wafer 40. The vias 82s are each part of each of the respective via transitions 82 also described below. The metal layer 37 is patterned to form a synthesizer / distributor network 35 having a plurality of interconnected conductive traces each routing an RF signal. The synthesizer / distributor network 35 synthesizes and / or distributes RF signals propagating between the input / output (I / O) connection point p4 and the connection points on the wafer 40 for further routing to / from the antenna element 22. For example, in the transmit direction, the synthesizer / distributor network 35 functions as a distributor for distributing the input transmit signal at the I / O point p4 between a plurality of distributed signal paths, such that the corresponding plurality of distributed transmit signals are provided to network endpoints 35e such as 35e1 and 35e2. In the receive direction, the synthesizer / distributor network 35 functions as a synthesizer for synthesizing the received signals received at the endpoints 35e into a composite receive signal output at the I / O point p4.

[0026] In other embodiments, the interposer 30 has a microstrip structure, in which case the lower ground plane 39 can be replaced with a patterned metal layer forming the conductor of the microstrip transmission line. In this case, the central metal layer 37 can be omitted, and the upper ground plane 36 can function as both the microstrip ground plane and the ground plane for the antenna element 22. In yet other embodiments, a coplanar waveguide (CPW) transmission line is used within the interposer 30, in which case the lower ground plane 39 is replaced with the CPW conductor, the central metal layer 37 may be omitted, and the upper ground plane 36 remains. In yet another embodiment, the central metal layer 37 is patterned to form the conductor of the microstrip transmission line of the interposer 30, and the lower ground plane 39 is the ground of the microstrip transmission line. In this case, the vias 82s connect the microstrip conductor to the signal line in the wafer 40, and a direct ground-ground connection can be made between the ground plane 39 and the ground of the wafer 40. In another example, the central metal layer 37 is a CPW, and three vias are used for the GSG connection between the CPWs or for the microstrip in the wafer 40.

[0027] Wafer 40 is an example of a semiconductor substrate that includes all of the active beamforming circuitry between a single RF input / output port (e.g., p4) and the antenna array 23. This approach is different from the conventional configuration where individual chips with beamforming circuitry are attached to the substrate. In one embodiment, wafer 40 is said to be an “array size” substrate by having a form factor that is approximately equal to that of the antenna array 23. For example, the antenna array 23 can be composed of dozens, hundreds, or thousands or more antenna elements 22, and all are connected to the beamforming circuitry of a single wafer 40 through the interposer 30. Wafer 40 can include a number “k” of “tiles” 42-1 through 42-k formed internally, and each tile 42 includes one or more sub-circuits 48 (interchangeably “beamforming circuits”), such as “w” sub-circuits 48-1 through 48-w included within tile 42-1. As used herein, a tile means a circuit formed within a wafer using a reticle-based image applied to a single area (hereinafter, “tile area”). (An example of tile formation using a reticle is described below in connection with FIG. 5.) In one embodiment, all tiles 42 are of the same overall circuit configuration, number of sub-circuits 48, and are of the same design with a physical layout. In other embodiments, some of the tiles 42 are different from each other. A “source street” 55 exists between adjacent tiles 42, and this is a separation area on the wafer 40 where there is no metal wiring. Interconnections can be provided within the interposer 30 to connect adjacent tiles 42 across the source street 55. For example, conductive traces of the synthesizer / distributor 35 can function as interconnections such that, in combination with via transitions 82, they effectively interconnect sub-circuits 48 of different tiles of the wafer 40. In connection with such interposer interconnections for interconnecting tiles 42 across the source street 55, many beamforming circuits 48 are integrally formed within a single wafer 40 without individual chip dicing and reattachment, thereby facilitating the manufacturing process. Further, the actual state of the wafer that is separately allocated to the synthesizer / distributor network can be used for other circuits or purposes.

[0028] Here, in another example of a large-scale antenna array, note that a plurality of wafers 40 are arranged side by side to form a multi-wafer sub-assembly, and a single interposer 30 is bonded to the plurality of wafers 40 to interconnect a number of antenna elements to a beamforming circuit dispersed on the multi-wafer sub-assembly.

[0029] Any sub-circuit 48 may include a beamforming circuit having an ion-implanted transistor region formed internally within the wafer 40. The beamforming circuit includes front-end beamforming components such as a transmit path amplifier, a transmit path phase shifter, a bandpass filter, a receive path low-noise amplifier (LNA), a receive path phase shifter, a transmit / receive (T / R) switch, and / or a synthesizer / distributor "on the wafer", or portions thereof. Any sub-circuit 48 may be referred to as a "chip unit" having a beamforming circuit that can be conventionally incorporated into individual chips diced from the wafer and reattached to a substrate. In the present technology, the manufacturing process for forming the antenna device 10 is rationalized by forming a number of sub-circuits 48 within a single wafer 40 without dicing the chips from the wafer and reattaching them to a substrate. Further, interconnections such as wire bonding for connecting individual chips to a substrate are avoided, thereby reducing inductance and improving reliability.

[0030] Any sub - circuit 48 can be electrically connected to one or more antenna elements 22 through respective one or more vias 72s. For example, the sub - circuit 48 - 1 of tile 42 - 1 can have a connection point p1 that is connected through vias 72s (part of via transition 72) to the connection point p2 of the probe feed 27 - 1 for the antenna element 22 - 1. In one embodiment, some or all of the endpoints 35e of the synthesizer / distributor 35 are connected through respective vias 82s to a synthesizer / distributor 49 “on - wafer” that, in a similar manner, routes signals to / from two or more sub - circuits 48. For example, the endpoint 35e1 is connected through a first via 82s to the connection point p3 of the synthesizer / distributor 49, while the endpoint 35e2 is connected from a second via 82s to another synthesizer / distributor 49 (not shown). To distribute a transmitted signal, such an on - wafer synthesizer / distributor 49 receives the transmitted signal on an input path and distributes the signal to a plurality of output paths, each of which is connected to a respective sub - circuit 48. A reciprocal synthesizing operation can be performed for received path signals. In other embodiments, the synthesizer / distributor 49 is omitted and all endpoints 35e are directly connected to respective sub - circuits 48 through vias 82s.

[0031] In one embodiment, some or all of the tiles 42 include at least one sub - circuit 65 that functions as an intermediate amplifier. The sub - circuit 65 amplifies a transmitted or received signal routed through vias 82s from / to an intermediate point (other than the endpoint 35e) of the synthesizer / distributor 35 and then outputs / reroutes the amplified signal back to the synthesizer / distributor 35 at another intermediate point through another via 82s.

[0032] FIG. 2 illustrates an exemplary configuration of a portion of the assembled antenna device 10 shown in cross-section. (Note that a detailed example of the interconnections and the flow of operating signals within the antenna device 10 will be described below in connection with FIGS. 6-9.) In this example, the wafer 40 is electrically and mechanically connected to the interposer 30 through a number of solder balls (or copper pillars) 59 connected between the lower metal layer 39 of the interposer 30 and the upper surface 41 of the wafer 40. For example, in the case of a large antenna array 23, the number of solder balls 59 can be in the thousands. The interposer 30 further includes a thin film metal layer 36 that can be formed by electroplating on the upper surface of the upper layer 33. The radiation layer 20 can be bonded to the metal layer 36 by atomically growing a plurality of layers of an air / honeycomb dielectric material of the dielectric 25 on the metal layer 36. Alternatively, a pre-cut slab of the dielectric 25 is fused to the metal layer 36 through a direct bond interconnect (DBI) bond, a thermocompression bond, or other suitable process. If a fusion method is used, the metal layer 36 can alternatively be formed first on the lower surface of the dielectric 25 instead of the upper surface of the interposer 30.

[0033] The example of FIG. 2 illustrates two sub - circuits 48 - 1 and 48 - 2 that are part of the same tile 42, and a sub - circuit 65 that can be part of the same tile or a different tile 42. The radiation layer 20 is connected to probe feeds 27 - 1, 27 - 2, each including antenna elements 22 - 1, 22 - 2 that are similarly connected to vias 72s. This example illustrates a via transition 72 implemented as a set of three vias that form part of a GSG connection: a "signal via" 72s, a first "ground via" 72g1, and a second ground via 72g2. The signal via 72s is connected to the probe feed 27 - 1 at one end and to the "signal contact" 51s of the sub - circuit 48 - 1 through a solder ball 59 at the opposite end. The signal contact 51s forms a set of GSG contacts 51 together with a first ground contact 51g1 and a second ground contact 51g2 on the opposite side thereof. The first and second ground vias 72g1, 72g2 are connected to the first and second ground contacts 51g1, 51g2 at one end through their respective solder balls 59 and to the ground plane 36 at the opposite end. In a stripline configuration, the via transition 82 can function as a stripline to CPW, a stripline to microstrip, or a stripline to stripline transition depending on the type of transmission - line interface within the wafer 40. In any case, each via transition 82 can include a signal via 82s (blind via) connected between the central conductor in layer 37 and the signal contact 51s, a ground via 82g1 connected between the ground plane 36 and the ground contact 51g1, and an adjacent connection (through the solder ball 59) between the ground contact 51g2 and the lower ground plane 39. In this way, signal energy can flow freely between the stripline of the interposer 30 and the CPW, microstrip, or stripline interface of the wafer 40. In this specification, the signal via 72s is an example of a "first via" and the signal via 82s is an example of a "second via".

[0034] Each sub - circuit 48 includes one or more beam - forming components such as amplifier 52 and phase shifter 54. The sub - circuits 48 of different tiles 42 are effectively interconnected by vias 82s connected to the combiner / splitter 35. Any sub - circuit 48 may receive a control signal or bias signal CNT on the control line 47 to control one or more internal active components. The control line 47 may be connected to an external component through an input terminal on the bottom surface 44 of the wafer 40. The beam - forming components of the sub - circuit 48 may convert (e.g., amplify, phase - shift, and / or filter) the transmission signal received from the combiner / splitter 35 through the combiner / splitter 49 on the wafer and output the converted transmission signal to the respective antenna elements 22. The round - trip operation can be performed in the receive - path direction using a T / R switch (not shown) and / or circuitry to implement a full - duplex or other transmit - receive separation scheme. When the combiner / splitter 49 is implemented as a CPW, the conductor of the CPW or the microstrip conductor may be formed on the surface 41 of the wafer 40 as illustrated. Since the solder ball 59 has a diameter sufficient to create a gap 77 between the surfaces on both sides of the wafer 40 and the interposer 30, the gap 77 may be sufficient to prevent the ground plane 39 from short - circuiting or adversely affecting the signal carried by the CPW or the microstrip conductor.

[0035] In some examples, the sub - circuit 48 may further include a distributor (not shown) that distributes the converted transmission signal (e.g., output by the amplifier 52) and feeds two or more antenna elements 22. Such a distributor may perform a round - trip combining operation in the receive direction.

[0036] In the example of FIG. 2, the synthesizer / distributor 35 is divided at the level of the metal layer 37 and has an input signal path 35a that is routed through the via transition 82 to the transmit amplifier 62 of the subcircuit 65. The amplified transmit signal output by the amplifier 62 is then routed back to the synthesizer / distributor 35 through another via transition 82. For example, if the input signal path 35 is relatively long and has high losses, the amplifier 62 can restore the magnitude of the transmit signal to a desired level. In the receive direction, a receive path amplifier (not shown) can be similarly disposed within the subcircuit 65. In this case, a T / R switch or other isolation circuit can be included within the subcircuit 65 to separate the transmit and receive signals. The I / O point p4 can receive an input transmit signal and / or output a receive signal through a connector (not shown) attached to the side surface of the interposer 30. In another example, an I / O connector (not shown) is attached to the bottom surface 44 of the wafer 40. In this case, the I / O point p4 can be connected to the I / O connector through another via transition 82. The latter via transition 82 can be connected to the wafer 40 at the upper end of a via within the wafer 40 or at a connection point corresponding to a coaxial feedthrough within the wafer 40. The lower end of the via or feedthrough within the wafer 40 can be connected to the I / O connector at the bottom surface 44.

[0037] Generally, subcircuits 48 of the same tile or different tiles can be connected to each other for RF signals and / or control signals routed through the interconnect paths of the interposer 30. The interconnect paths between the subcircuits 48 can be formed in the metal layer 37 by using blind vias such as 82s and / or another metal layer at different levels (not shown) within the interposer 30. If the subcircuits 48-1 and 48-2 of FIG. 2 are alternatively subcircuits of different tiles 42, a source strip region 55 exists between the tiles 42. Since no metal wiring is applied to the upper surface 41 of the wafer 40 within the source strip region 55, the "between tiles" between the subcircuits 48 can be connected through the interposer 30 through such a layer 37.

[0038] FIG. 3 illustrates another exemplary configuration of the assembled antenna device 10. This configuration differs from the configuration of FIG. 2 in that the solder balls 59 are omitted and instead, a direct bonding is formed between the interposer 30 and the wafer 40, for example, by a DBI bonding method. As a result, the via transitions 72, 82 of the interposer 30 are directly bonded to the metal contacts 51 of the wafer 40. In a large antenna array, this approach eliminates thousands of solder balls 59, thereby improving the reliability of the antenna device 10. To avoid a short circuit between the ground plane 39 and the conductive elements on the surface 41 (e.g., the CPW or microstrip inner conductor on the surface 41), a separation layer can be deposited on any conductor on or near the wafer surface 41.

[0039] FIG. 4 illustrates an exemplary tile arrangement on a wafer and an exemplary tile configuration of the antenna device 10. As mentioned, a tile means a circuit formed within a wafer using a reticle-based image applied to a specific physical surface, which is referred to herein as a "tile region". As illustrated, the disk-shaped wafer 40 can have tiles 42 formed in rows and columns, with source streets 55 between adjacent tiles 42. However, unlike conventional designs, the tiles 42 are not cut from the wafer along the source streets 55. Tiles such as 42-1 can include a grid layout of subcircuits 48-1 to 48-w (one or more of which can be the subcircuit 65 discussed earlier). In some examples, only completely rectangular or square tiles 42 are formed as part of the wafer 40, and some peripheral surface area of the wafer 40 remains unused. In other examples, additional subcircuits can be formed at the circular outer periphery of the wafer.

[0040] FIG. 5 schematically illustrates how tiles of wafer 40 can be formed using a reticle. The reticle 90 is a tool that patterns a film or mask (already deposited on the wafer) to expose areas for processing and ultimately generates a photolithography image 91 that forms a complete circuit after many process steps. The image 91 typically has a span "d" that is limited to only a portion of the diameter of the wafer 40. Typically, the span d is less than half of the diameter of the wafer 40 to generate a circuit image on the surface of the wafer 40 at the target resolution. In some cases, by stepping the reticle 90 laterally and repeating the exposure with the same image 91, the same image can be generated in the tile regions across the wafer 40. (In other examples, different images can be used in different respective regions of the wafer 40 as part of the same processing phase.) Therefore, in FIG. 5, as part of the first exposure step, the reticle 90 first produces the first image 91 to generate the first exposure for tile 42-i. The reticle 90 is then translated laterally as illustrated by path 93 and produces a second image 91 that is typically the same as the first image to generate the first exposure for the second tile 42-(i + 1). The process can be repeated for all tile regions of the wafer 40. Next, a first processing step such as ion implantation for doping transistor regions or electroplating to deposit a first metal wiring layer can be performed simultaneously on the wafer 40 for all tile regions. Next, another mask or film can be deposited on the surface of the wafer 40, and the reticle 90 can be controlled again to start a second round of tile region exposure corresponding to the second processing step and continue until all processing steps are completed. In the overall process, a source strip 55 is formed between adjacent tiles, which is a metal-free separation region that has conventionally been used for die-style or individual chips from the wafer. In this embodiment, dicing between the tiles 42 is not performed, thereby manufacturing the wafer 40 as a continuous substrate with many tiles 42 formed internally.

[0041] FIG. 6 illustrates an exemplary layout of contiguous tiles on wafer 40 of antenna device 10 according to an example. Tiles 42-i, 42-(i + 1), and 42-(i + 2) are arranged in a given row of wafer 40 having source streets 55 between adjacent tiles. Each tile 42 may have a plurality of interconnected subcircuits 48-1 to 48-w, which may be diced from the wafer along region 66 (and along source street 55) to form individual chips that can be reattached to a substrate to form conventional devices. In this embodiment, the chips are not diced, and each tile such as 42-i may have synthesizers / distributors on a plurality of wafers such as 49-1 and 49-2.

[0042] FIG. 7A schematically illustrates an exemplary connection and signal flow between subcircuits 48 within the same tile such as 42-i of FIG. 6 interconnected using interposer 30. FIG. 7B is a functional block diagram of this example. In the transmission direction, an RF signal output from subcircuit 48-j is distributed between paths 35c and 35d of synthesizer / distributor 35 within interposer 30. The distributed signals are re-routed to return to wafer 40 through respective paths 722, 724 (e.g., via transition vias 82), which connect to distributors 49-1, 49-2 on the wafer at points p6 and p7, respectively. Distributors 49-1, 49-2 on the wafer redistribute the signal between a plurality of paths, and these redistributed signals are provided to adjacent subcircuit pairs (48-(j - 2), 48-(j - 1)) and (48-(j + 1), 48-(j + 2)), respectively. Each subcircuit 48 may convert an input signal and output the signal converted through interposer 30 to antenna element 22, as illustrated by path 713. A reciprocating signal flow may occur in the reception direction.

[0043] FIG. 8 schematically illustrates an exemplary connection configuration between sub - circuits of different tiles and signal routing across the tiles in the antenna device 10 according to one embodiment. In the transmission direction, an RF signal originating from the sub - circuit 48 - P of tile 42-(i + 1) is output through the interposer 30 and is split between paths 35f and 35g of the combiner / splitter 35. Path 35f traverses across the source strip 55 and is connected through via transition 82 to the splitter 49 - u on the wafer of the adjacent tile 42 - i. Path 35g traverses across tile 42-(i + 1) and is connected through another via transition 82 to the splitter 49 - v on the wafer. The splitters 49 - u, 49 - v on the wafer re - split the signal between adjacent sub - circuits 48 for conversion and output it to the antenna array 23. The round - trip signal can flow in the reception direction.

[0044] FIG. 9 illustrates an exemplary tile layout along with an example signal routing for one embodiment of the antenna device 10. In this example, the wafer 40 includes a grid layout of 60 tiles 42-1 through 42-60, with one tile omitted from each corner of the square profile. Each tile, such as 42-j (where j is any number from 1 to 60), has the same design and may include sub-circuits 48-1 through 48-16 having an RF front-end circuit and another sub-circuit 65 (hereinafter simply “amplifier 65”) for providing intermediate amplification. Each sub-circuit 48 may include a set of contacts 51 as described above for connection to respective antenna elements 22 through via transitions 72. The thick lines in FIG. 9 represent the paths of an exemplary synthesizer / distributor 35 within the interposer 30. The RF I / O connection point p4 located within the interposer 30 near the concentrated edge of the wafer 40 is connected to the input path 35a. The input path 35a extends to the concentration point p8 of the interposer 30 where it is distributed for supply to the left and right tiles 42. In an example of the transmit path, the transmit signal is re-routed from the synthesizer / distributor 35 to the amplifier 65-1 of the tile 42 on each side by a via transition 82. There, it is amplified and routed to the synthesizer / distributor 35 by another via transition 82 for further distribution at point p9 towards the tiles in the upper and lower quadrants. Downstream, further distribution by the synthesizer / distributor 35 and amplification by an amplifier such as 65-2 may occur as necessary or desired to restore the distributed transmit signal to an appropriate level.

[0045] As can be seen in the enlarged view of tile 42-j, the transmission signal corresponding to tile 42-j can be routed from the interposer 30 through via transition 82 to the intermediate amplifier 65 and amplified. The amplified output can be routed up to the combiner / splitter 35 and distributed to two paths, one of which can terminate at the endpoint 35ej. There, another via transition 82 can route the signal back to the combiner / splitter 49-j on the wafer. In this example, the combiner / splitter 49-j is a 1:16 power divider / combiner having 16 endpoints connected to their respective subcircuits 48-1 to 48-16 for transmission through the antenna element 22. The round-trip operation can occur on the receiving path from the antenna element 22. One or more of the same amplifiers 65 can be provided within each tile 42, but it should be noted that some of the amplifiers 65 can be actively used while others are unused (disconnected and / or off). The selection of which amplifiers 65 to use and the method of energizing them for variable amplification can depend on the overall layout of the tile 42 and the target electric field (antenna current) distribution across the aperture of the antenna array 23. For example, instead of designing a uniform electric field distribution, an external antenna element can supply less RF power to achieve a target antenna pattern with lower side lobes.

[0046] Figure 10 is a flowchart of an exemplary method of forming an antenna device 10 having an interposer with a stripline structure. The order of the various process steps of the method can be changed as desired. The wafer 40 is formed of a plurality of tiles using a reticle as described above with respect to FIG. 5 (S102). An interposer 30 with a stripline structure is formed (S104), and the interposer includes upper and lower ground planes and vias (e.g., blind vias 82s and "complete vias" 82g1, 72s, 72g1, 72g2 that extend completely between the lower and upper surfaces of the interposer).

[0047] The wafer is attached to the lower ground plane of the interposer (S106) using either the solder ball connection scheme (Figure 2) or the direct attachment method (Figure 3) described previously. The dielectric layer of the radiation layer 20 can be grown on the upper ground plane (S108). The material of the dielectric layer can be an air / honeycomb material grown atomically layer by layer. Once the dielectric layer is complete, antenna elements can be formed on the dielectric layer, and probe feed vias can be formed through the dielectric layer (S110), thereby completing the manufacture of the antenna device 10. The probe feed vias connect to the metal wiring of the antenna elements at one end and to the upper metal wiring of the interposer signal vias 72s at the opposite end.

[0048] Figure 11 is a flow diagram of an exemplary process step for forming the interposer of the method of Figure 10 and represents one embodiment of process S104. The order of the various process steps of this method can be changed as desired. The lower dielectric layer of the interposer is provided (S112). The upper surface of the lower dielectric layer is patterned and metal-wired to form the synthesizer / distributor 35 (S114), and the bottom surface of the lower dielectric layer is patterned and metal-wired to form the lower ground plane 39 having openings for the signal vias 72s and 82s. The openings prevent short circuits of the signal vias to the lower ground plane. Therefore, in the region of each signal via 72s and 82s, the metal wiring pattern can be formed as a square for a central metal disk or via pad surrounded by a separation ring from which the metal has been removed and similarly surrounded by the ground plane metal.

[0049] Blind vias 82s of via transition 82 connected to the points of the synthesizer / dispatcher 35 may be formed (S116). Next, the upper dielectric layer of the stripline may be formed or attached on the metal-wired upper surface of the lower substrate (S118). The upper surface of the dielectric layer may be metal-wired in a pattern for forming an upper ground plane having similar openings to enable a separated connection between the probe feed via and the signal vias 72s. Next, it may be drilled for the complete vias 82g1 of via transition 72 and via transition 82, and the holes are filled with metal to complete the formation of the vias (S120), thereby completing the manufacture of the interposer 30.

[0050] Embodiments of the antenna device as described above may be formed with a low profile and achieve excellent performance (e.g., lower loss and higher frequency operation) compared to conventional designs. Further, the structure is suitable for an accelerated manufacturing process. By providing an interposer with vias to interconnect reticle image-based tiles across the source strip separation region, multiple beamforming circuits may be internally formed within a single wafer. Thereby, a wafer of array size with beamforming circuits may be manufactured without the need for dicing and reattaching individual chips to a substrate. Further, the area within the wafer separately allocated for the synthesizer / dispatcher network may be freed for other purposes.

[0051] Although the techniques described herein have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the subject matter defined by the following claims and their equivalents.

Claims

1. A radiation layer (20) comprising a plurality of antenna elements (22) forming an antenna array; A semiconductor wafer (40) comprising a plurality of tiles (42) each having a beamforming circuit (48); A multilayer interposer (30), A lower dielectric layer (31) adjacent to the wafer; An upper dielectric layer (33) adjacent to the radiation layer; A metal layer (37) between the lower dielectric layer and the upper dielectric layer, the metal layer (37) comprising a plurality of conductive traces (35); A plurality of first vias (72) extending through both the upper dielectric layer and the lower dielectric layer and electrically connecting the beamforming circuit to the plurality of antenna elements; A plurality of second vias (82) extending between the beamforming circuit and the conductive trace and interconnecting the plurality of tiles, the multilayer interposer comprising the antenna device (10); Each of the plurality of tiles has the same overall circuit configuration, the same number of subcircuits (48), and the same design with the same physical layout, the antenna device (10).

2. The wafer further comprises a source strip (55) separating the plurality of tiles from each other, the antenna device (10) according to claim 1.

3. Each of the first vias is a signal via (72s) of a ground-signal-ground (GSG) via transition, and has a first ground via (72g1) on one side of the signal via and a second ground via on the other side of the signal via. The antenna device (10) according to claim 1, further comprising (72g2).

4. The multilayer interposer (30) has a stripline structure comprising the upper dielectric layer, the lower dielectric layer, a lower ground plane (39) between the wafer and the lower dielectric layer, and an upper ground plane (36) between the upper dielectric layer and the radiation layer, and the upper ground plane functions as a ground plane for the antenna elements. The first and second ground vias are respectively connected to respective first and second ground contacts (51g1, 51g2) on the wafer at one end and to the upper ground plane at the opposite end, the antenna device (10) according to claim 3.

5. Each of the second vias (82s) is a signal via for via transition, and further includes a ground via (82g1) connecting a third ground contact of the wafer to the upper ground plane, and a ground-ground connection connecting a fourth ground contact of the wafer to the lower ground plane. The antenna device (10) according to claim 4.

6. The conductive trace of the metal layer is part of a synthesizer / distributor network (35), and the synthesizer / distributor network distributes a radio frequency (RF) transmission signal received at an input / output (I / O) connection point (P4) of the interposer to each of one or more of the beamforming circuits using one of each of the second vias at respective endpoints (35e) of the synthesizer / distributor network. The antenna device (10) according to claim 1.

7. The RF transmission signal is received at the I / O connection point from a connection point on the wafer using additional vias (82) within the interposer. The antenna device (10) according to claim 6.

8. Each of the distributed transmission signals is routed to each of the plurality of tiles at respective endpoints of the synthesizer / distributor network. Each of the respective tiles further includes a synthesizer / distributor on the wafer, and the synthesizer / distributor on the wafer is electrically connected to the respective endpoints and further distributes the distributed signal into at least two further distributed signals, routing each further distributed signal to one of the beamforming circuits of the respective tile. The antenna device (10) according to claim 6.

9. The plurality of conductive traces form a synthesizer / distributor network (35), and at least one of the plurality of tiles includes an intermediate amplifier. The intermediate amplifier amplifies a transmission signal or a reception signal routed by the synthesizer / distributor network from / to an intermediate point of the synthesizer / distributor network through another via within the interposer, and outputs the amplified transmission or reception signal back to the synthesizer / distributor network (35) through a further via (82). The antenna device (10) according to claim 1.

10. The plurality of conductive traces form a synthesizer / distributor network (35), each of the plurality of tiles includes an intermediate amplifier (65), the intermediate amplifier is connectable to respective intermediate points of the synthesizer / distributor network (35) through another via (82) in the interposer on the input side, and is connectable to another respective intermediate point of the synthesizer / distributor network (35) through a further via on the output side, and each intermediate amplifier is configured to selectively amplify a transmitted signal or a received signal routed by the synthesizer / distributor network. The antenna device (10) according to claim 1.

11. The plurality of conductive traces form a synthesizer / distributor network (35), and the synthesizer / distributor network synthesizes a plurality of radio frequency (RF) received signals received by the antenna element and adjusted by the beamforming circuit into a synthesized RF received signal output using a further via in the interposer leading to a connection point on the wafer. The antenna device (10) according to claim 1.

12. The antenna device (10) according to claim 1, further comprising a plurality of solder bumps (59) each electrically connecting one of the first via or the second via to the wafer.

13. The wafer is directly bonded to the multilayer interposer. The antenna device (10) according to claim 1.

14. The radiation layer grows on the interposer and includes an air / honeycomb material that supports the antenna element. The antenna device (10) according to claim 1.

15. The antenna element is a patch antenna element each driven by a probe feed (27) electrically connected to one of the first vias. The antenna device according to claim 1.

16. A radiation layer (20) comprising a plurality of antenna elements (22) forming an antenna array, A semiconductor wafer (40) comprising a plurality of radio frequency (RF) beamforming circuits (48), each of the plurality of radio frequency (RF) beamforming circuits having a transistor region formed internally in the semiconductor wafer, and each beamforming circuit including at least one phase shifter (54) and at least one of a transmit path amplifier (52) and a receive path amplifier (52). The semiconductor wafer (40). A multi-layer interposer (30), a lower dielectric layer (31) adjacent to the substrate, an upper dielectric layer (33) adjacent to the radiation layer, a metal layer (37) between the lower dielectric layer and the upper dielectric layer, the metal layer (37) including a plurality of conductive traces forming a combiner / distributor network (35) for combining and / or distributing signals between the plurality of RF beamforming circuits and the input / output connection points (P4) of the interposer, a plurality of first vias (72) extending through both the upper dielectric layer and the lower dielectric layer and electrically connecting the plurality of RF beamforming circuits to the plurality of antenna elements, a plurality of second vias (82) extending between the RF beamforming circuits and the conductive traces, some of the second vias interconnecting the antenna elements through the RF beamforming circuits with the combiner / distributor network, a multi-layer interposer (30), comprising an antenna device (10), the wafer includes at least one intermediate amplifier (62), the intermediate amplifier amplifying a transmitted or received signal routed from / to an intermediate point of the combiner / distributor network through another one of the second vias and outputting the amplified transmitted or received signal back to the combiner / distributor network through a further one of the second vias, an antenna device (10).

17. The multi-layer interposer has a stripline structure, the stripline structure comprising the upper dielectric layer, the lower dielectric layer, a lower ground plane (39) between the wafer and the lower dielectric layer, and an upper ground plane (36) between the upper dielectric layer and the radiation layer, the upper ground plane functioning as a ground plane for the antenna elements, the antenna device (10) according to claim 16.

18. The combiner / distributor network distributes a transmitted signal into a plurality of distributed transmitted signals at respective endpoints of the combiner / distributor network, each of the distributed transmitted signals being routed to the wafer at a respective one of the endpoints, The wafer further includes a plurality of combiners / dividers (49) on the wafer, each of the plurality of combiners / dividers being electrically connected to one of the endpoints respectively, further dividing the distributed transmission signal into at least two further distribution signals, and routing each further distribution signal to one of the RF beamforming circuits, the antenna device (10) according to claim 16.

19. Each of the transmission path amplifier and the reception path amplifier is a millimeter wave amplifier, the antenna device (10) according to claim 16.

20. The multilayer interposer is composed of quartz or fused silica, the antenna device (10) according to claim 16.

21. A method of manufacturing an antenna device (10), comprising: forming each tile (42) in each region by sequentially applying the same reticle image (91) to a plurality of regions of a semiconductor wafer (40), each tile comprising a transistor region ion-implanted in the wafer and a radio frequency (RF) beamforming circuit (48) having a metal wiring pattern on the surface of the wafer, step (S102); attaching an interposer (30) to the wafer (steps S104, S106), the interposer including a lower dielectric layer adjacent to the wafer, an upper dielectric layer, and a metal layer between the lower dielectric layer and the upper dielectric layer, a plurality of conductive traces, a plurality of first vias extending through both the upper dielectric layer and the lower dielectric layer, and a plurality of second vias extending between the lower surface of the interposer and the metal layer to interconnect the plurality of tiles, steps (S104, S106); attaching a radiation layer including a plurality of antenna elements to the upper surface of the interposer, such that the antenna elements are electrically connected to the RF beamforming circuit through the plurality of first vias (S108, S110), a method including the step.

22. The step of attaching the radiation layer to the upper surface of the interposer includes: growing an air / honeycomb material on the interposer (S108); forming a probe feed via (27) in the air / honeycomb material electrically connected at a first end to each of the first vias (S110). forming the antenna element electrically connected to an end portion opposite to the probe feed via on or within the air / honeycomb material (S110), the method according to claim 21, comprising.

23. The step of attaching the interposer to the wafer includes attaching a plurality of solder bumps (59) to the lower surface of the interposer and / or the wafer, and soldering electrical contacts (51) of each of the wafer and the interposer to the opposite side of the plurality of solder bumps, the method according to claim 21.

24. The method according to claim 21, wherein the step of attaching the interposer (30) to the wafer includes directly attaching the lower surface of the interposer to the main surface (41) of the wafer using a direct bonding interface bonding method.

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