Indicating device, electronic device

Abstract

To provide a liquid crystal display device which can reduce the power consumption, or a liquid crystal display device which can achieve reduction in the variation of the transmittance.SOLUTION: A liquid crystal display device comprises: a first substrate including a transistor including an oxide semiconductor film in a channel formation region, a pixel electrode electrically connected to the transistor, an insulating layer in contact with the pixel electrode, and a first common electrode in contact with the insulating layer; a second substrate which is arranged so as to face the first substrate and includes a second common electrode; and a liquid crystal layer which is sandwiched between the first substrate and the second substrate. The liquid crystal layer uses a negative liquid crystal material. The specific resistivity of the liquid crystal material is greater than or equal to 1.0×1013 Ω cm and less than or equal to 1.0×1016 Ω cm.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, their driving methods, or their manufacturing methods. In particular, the present invention relates to, for example, active matrix liquid crystal display devices. devices.

Background Art

[0002] In recent years, with the rapid spread of portable information terminals such as smartphones, the performance of the terminals themselves has been rapidly improved. The screen size has been increasing and the resolution has been improving, and at the same time, power consumption of the display device has been emphasized. As a display device, for example, a liquid crystal display device using a liquid crystal element is typical. devices.

[0003] As display modes of liquid crystal display devices, for example, a vertical alignment (VA) mode in which liquid crystal molecules having negative dielectric anisotropy are vertically aligned with respect to the substrate surface, or an in-plane switching (IPS) mode and a fringe field switching (FFS) mode in which liquid crystal molecules having positive or negative dielectric anisotropy are horizontally aligned with respect to the substrate surface and an in-plane electric field is applied to the liquid crystal layer can be mentioned. mode, etc. can be mentioned.

[0004] For example, as a liquid crystal display device having the above-described FFS driving method, a first substrate having a first common electrode layer, liquid crystal sandwiched between the first substrate and a second substrate, and a first common electrode layer on the first substrate and a pixel electrode and a second common electrode layer on the second substrate are provided to generate an electric field between both of them. A display device having high-speed responsiveness and a wide viewing angle is disclosed (see Patent Document 1). (see Patent Document 1)

[0005] Also, as a liquid crystal display device using the FFS driving method, a liquid crystal display device capable of driving liquid crystal using two pairs of electrodes and achieving high-speed response is disclosed (see Patent Document 2).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the liquid crystal driving device disclosed in Patent Document 1, in order to achieve wide viewing angle conversion and high-speed response, three electrodes are used to control liquid crystal molecules. However, even if high-speed response is achieved, since it is necessary to drive the three electrodes separately, the power consumption of the display device increases.

[0008] Also, in the liquid crystal driving device disclosed in Patent Document 2, since it is necessary to drive liquid crystal by two pairs of electrodes, in other words, four electrodes, at least four power supply lines are required,

[0009] Under the technical background as described above, one aspect of the present invention is to provide a liquid crystal display device capable of reducing power consumption. Or, one aspect of the present invention is One of the problems is to provide a liquid crystal display device capable of reducing fluctuations in transmittance. Alternatively, one aspect of the present invention has, as one of its problems, to provide a liquid crystal display device capable of reducing fluctuations in display luminance. Alternatively, one aspect of the present invention has, as one of its problems, to provide a liquid crystal display device capable of reducing display flicker. Alternatively, one aspect of the present invention has, as one of its problems, to provide a liquid crystal display device capable of reducing eye strain. Alternatively, one aspect of the present invention has, as one of its problems, to provide a liquid crystal display device capable of realizing an eye-friendly display. Alternatively, one aspect of the present invention has, as one of its problems, to provide a liquid crystal display device capable of reducing the impact on eye fatigue. Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

[0010]

Means for Solving the Problems

[0011] In a liquid crystal display device according to one aspect of the present invention, after writing of an image signal to a pixel portion has stopped, an insulated gate field effect transistor (hereinafter simply referred to as a transistor) having an extremely small off-current is provided in the pixel in order to maintain the display of the image in the pixel portion. By using the transistor as an element for controlling the supply of voltage to a liquid crystal element included in the pixel, it is possible to ensure a long period during which the supply of voltage to the liquid crystal element is maintained. Therefore, as in the case of a still image, the same image information is present in the pixel portion over several consecutive frame periods. When image signals are repeatedly written, the writing of image signals to the pixel section is temporarily stopped. By stopping the drive frequency, the drive frequency is lowered. In other words, the image signal Even if the number of times writing is reduced, the image display can be maintained.

[0012] Furthermore, in the liquid crystal display device according to one aspect of the present invention, the liquid crystal element includes a pixel electrode, a first common electrode, and a second common electrode. The liquid crystal layer has an electric field applied thereto by three electrodes, a first common electrode, and a second common electrode. The liquid crystal layer uses a negative liquid crystal material, and the specific resistivity of the liquid crystal material is 1.0 × 10 13 Ω·c m or more 1.0×10 16 Ω·cm or less. By using this configuration, Even if the number of times the image signal is written within a period is reduced, the fluctuation in transmittance is small, and the LCD For the viewer of the display device, the liquid crystal display device can be one in which image flicker is suppressed. . [Effects of the Invention]

[0013] According to one embodiment of the present invention, a liquid crystal display device capable of reducing power consumption is provided. Furthermore, according to one embodiment of the present invention, it is possible to reduce fluctuations in transmittance. It is possible to provide a liquid crystal display device that can [Brief description of the drawings]

[0014]

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Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0016] In addition, in this specification, the liquid crystal display device means a module in a state where a panel in which liquid crystal elements are formed in each pixel and an IC including a drive circuit or a controller is mounted on the panel is included in its scope. Further, the liquid crystal display device according to one aspect of the present invention includes a device substrate corresponding to a form before the liquid crystal element is completed in the process of manufacturing the liquid crystal display device in its scope. Further, the liquid crystal display device according to one aspect of the present invention may include a touch panel which is a position input device capable of detecting a position pointed by a finger or a stylus and generating a signal including the position information.

[0017]

[0018]

[0019] (Embodiment 1) In this embodiment, a configuration example of a pixel of a liquid crystal display device according to one aspect of the present invention will be described with reference to FIG. 1.

[0019] 〈Configuration Example of Pixel〉 FIG. 1(A) shows a configuration example of a pixel of a liquid crystal display device according to one aspect of the present invention. The pixel 100 shown in FIG. 1(A ) includes a liquid crystal element 111 and controls the supply of an image signal to the liquid crystal element 111 It has a transistor 112 and a capacitive element 113.

[0020] The liquid crystal element 111 includes a pixel electrode, a first common electrode, a second common electrode, and a liquid crystal layer containing a liquid crystal material between which a voltage is applied between the pixel electrode, the first common electrode, and the second common electrode. It has the liquid crystal layer containing the liquid crystal material between which a voltage is applied between the pixel electrode, the first common electrode, and the second common electrode. It has it.

[0021] Also, in FIG. 1(A), the region where a voltage is applied between the pixel electrode and the first common electrode of the liquid crystal element 111 is defined as the liquid crystal element 111a, the region where a voltage is applied between the pixel electrode and the second common electrode is defined as the liquid crystal element 111b, and the region where a voltage is applied between the first common electrode and the second common electrode is defined as the liquid crystal element 111c, and they are each illustrated. Also, in FIG. 1(A), the region where a voltage is applied between the pixel electrode and the first common electrode of the liquid crystal element 111 is defined as the liquid crystal element 111a, the region where a voltage is applied between the pixel electrode and the second common electrode is defined as the liquid crystal element 111b, and the region where a voltage is applied between the first common electrode and the second common electrode is defined as the liquid crystal element 111c, and they are each illustrated. Also, in FIG. 1(A), the region where a voltage is applied between the pixel electrode and the first common electrode of the liquid crystal element 111 is defined as the liquid crystal element 111a, the region where a voltage is applied between the pixel electrode and the second common electrode is defined as the liquid crystal element 111b, and the region where a voltage is applied between the first common electrode and the second common electrode is defined as the liquid crystal element 111c, and they are each illustrated. Also, in FIG. 1(A), the region where a voltage is applied between the pixel electrode and the first common electrode of the liquid crystal element 111 is defined as the liquid crystal element 111a, the region where a voltage is applied between the pixel electrode and the second common electrode is defined as the liquid crystal element 111b, and the region where a voltage is applied between the first common electrode and the second common electrode is defined as the liquid crystal element 111c, and they are each illustrated.

[0022] Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113. Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113. Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113. Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113. LC Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113. Also, in FIG. 1(A), the case where the liquid crystal element 111 is in the FFS (Fringe Field Switching) mode is exemplified, and the region where the pixel electrode and the first common electrode overlap with an insulating film therebetween is provided. This region has a function as a capacitance for holding the voltage V applied between the pixel electrode and the first common electrode. In FIG. 1(A), the capacitance of this region is illustrated as the capacitive element 113.

[0023] The transistor 112 controls whether to supply the potential of the image signal input to the wiring SL to the pixel electrode of the liquid crystal element 111. A predetermined reference potential V is applied to the first common electrode of the liquid crystal element 111. The transistor 112 controls whether to supply the potential of the image signal input to the wiring SL to the pixel electrode of the liquid crystal element 111. A predetermined reference potential V is applied to the first common electrode of the liquid crystal element 111. The transistor 112 controls whether to supply the potential of the image signal input to the wiring SL to the pixel electrode of the liquid crystal element 111. A predetermined reference potential V is applied to the first common electrode of the liquid crystal element 111. COM1 is applied.

[0024] Hereinafter, the specific connection relationship between the liquid crystal element 111, the transistor 112, and the capacitive element 113 will be described. Hereinafter, the specific connection relationship between the liquid crystal element 111, the transistor 112, and the capacitive element 113 will be described.

[0025] In this specification, "connection" means electrical connection, corresponding to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily refer to the state of being directly connected. Even a state where current, voltage, or potential is indirectly connected through circuit elements such as wiring, resistors, diodes, and transistors so that they can be supplied or transmitted is also included in this category.

[0026] Also, even when components that are independent on a circuit diagram are connected, in reality, for example, when a part of the wiring functions as an electrode, there may be a case where one conductive film has the functions of multiple components. In this specification, "connection" includes such a case where one conductive film has the functions of multiple components within its category.

[0027] Also, the source and drain of a transistor change their names depending on the channel type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, for the sake of convenience, when explaining the connection relationship of a transistor, it is assumed that the source and drain are fixed, but in reality, the names of the source and drain are interchanged according to the above potential relationship.

[0028] Also, the source of a transistor is a part of the semiconductor film that functions as an active layer, the source means a source electrode connected to the above semiconductor film. Similarly, for a transistor the drain means a drain region that is part of the above semiconductor film, or a drain electrode connected to the above semiconductor film is meant. Also, the gate means a gate electrode.

[0029] In the pixel 100 shown in FIG. 1(A), the gate of the transistor 112 is electrically connected to the wiring GL. One of the source and drain of the transistor 112 is connected to the wiring SL and the other of the source and drain of the transistor 112 is connected to the pixel electrode of the liquid crystal element 111 is continued. And the capacitor element 113 has a pair of electrodes, one electrode is electrically connected to the pixel electrode of the liquid crystal element 111, and a predetermined potential V COM1 is applied to the other electrode. Also, in the pixel 100 shown in FIG. 1(A), the second common electrode of the liquid crystal element 111 is connected to the wiring CL, and V COM2 is applied to the wiring CL.

[0030] In FIG. 1(A), in the pixel 100, the case where one transistor 112 is used as a switch for controlling the input of the image signal to the pixel 100 is illustrated. However, in the pixel 10 0, a plurality of transistors may function as one switch.

[0031] And in one aspect of the present invention, the off-current of the transistor 112 is made extremely small. With the above configuration, it is possible to ensure a long period during which the voltage applied to the liquid crystal element 111 is held. Therefore, in the case where an image signal having the same image information is written to the pixel 100 over several consecutive frame periods, such as a still image, the driving frequency is lowered ​​That is to say, the number of times an image signal is written to pixel 100 within a certain period is reduced even so, the gradation display can be maintained. For example, by using transistor 112 including a highly purified oxide semiconductor in the channel formation region, the interval between writes of the image signal can be 10 seconds or more, preferably 30 seconds or more, more preferably 1 minute or more. Then the longer the interval between writes of the image signal, the more the power consumption can be reduced.

[0032] By using a semiconductor such as an oxide semiconductor having a larger bandgap and a lower intrinsic carrier density than silicon or germanium in transistor 112, the breakdown voltage of transistor 112 can be increased and the off-current can be made extremely small. Therefore, compared with the case of using a transistor formed of a semiconductor such as ordinary silicon or germanium, the deterioration of transistor 112 can be prevented and the voltage held in liquid crystal element 111 can be maintained. Even if the amount of charge leaking through transistor 112 is small, due to several factors, after the writing of the image signal is completed, the electric field applied to the liquid crystal layer may change.

[0033] For example, as one factor causing a change in the electric field applied to the liquid crystal layer, adsorption of ionic impurities to the alignment film can be cited. Although the liquid crystal material contains ionic impurities, when the impurities are adsorbed to the alignment film, an electric field called residual DC may be generated. When residual DC caused by adsorption of impurities is generated, the electric field applied to the liquid crystal layer changes, so the transmittance of liquid crystal element 111 also changes. And the longer the time a DC voltage is applied to the liquid crystal element, the more residual DC

[0034] occurs. ​​​​​​​​Since it becomes stronger, in the driving method where the writing interval of the image signal is long as in one aspect of the present invention, in the case of a normal driving method with a frame frequency of about 60 Hz, the change in transmittance is large and it is likely to occur.

[0035] Another factor that changes the electric field applied to the liquid crystal layer is the leakage current flowing through the liquid crystal element 111. When a voltage is applied to the liquid crystal element 111, through the liquid crystal layer between the pixel electrode and the first common electrode, or through the liquid crystal layer between the pixel electrode and the second common electrode, a slight leakage current flows, so that the absolute value of the voltage applied to the liquid crystal element 111 decreases with the passage of time. Therefore, in the case of a driving method where the writing interval of the image signal is long as in one aspect of the present invention, for example, compared with a normal driving method with a frame frequency of about 60 Hz, the change in transmittance is likely to be large. However, in the liquid crystal display device of one aspect of the present invention, the liquid crystal layer used for the liquid crystal element 111 uses a negative liquid crystal material, and the intrinsic resistivity of the liquid crystal material is 1.0×10 Ω·cm or more and 1.

[0036] However, in the liquid crystal display device of one aspect of the present invention, the liquid crystal layer used for the liquid crystal element 111 uses a negative liquid crystal material, and the intrinsic resistivity of the liquid crystal material is 1.0×10 Ω·cm or more and 1. 13 Ω·cm or less. More preferably, the intrinsic resistivity of the liquid crystal material is 1.0 ×10 16 Ω·cm or more and 1.0×10 ×10 14 Ω·cm or more and 1.0×10 16 Ω·cm or less. Note that the value of the intrinsic resistivity of the liquid crystal material in this specification etc. is the value measured at 20°C. By using a negative liquid crystal material for the liquid crystal layer used in the liquid crystal element 111, the variation in the transmittance of the liquid crystal element 1

[0037] 11 can be suppressed. Also, by setting the intrinsic resistivity of the liquid crystal material within the above range, the leakage current flowing through the liquid crystal element 111 can be reduced. ​

[0038] The liquid crystal element 111 has a difference in transmittance depending on the polarity (positive (+) polarity or negative (-) polarity) applied to the liquid crystal layer. For example, when a positive-type liquid crystal material and a negative-type liquid crystal material are used as the material of the liquid crystal layer included in the liquid crystal element 111, a difference in transmittance due to the polarity can occur. Here, the transmittance due to the polarity when a positive-type liquid crystal material and a negative-type liquid crystal material are used will be described with reference to FIG. 2. Note that the positive-type liquid crystal material is a liquid crystal material having positive dielectric anisotropy, and the negative-type liquid crystal material is a liquid crystal material having negative dielectric anisotropy. Here, the transmittance due to the polarity when a positive-type liquid crystal material and a negative-type liquid crystal material are used will be described with reference to FIG. 2. Note that the positive-type liquid crystal material is a liquid crystal material having positive dielectric anisotropy, and the negative-type liquid crystal material is a liquid crystal material having negative dielectric anisotropy. Here, the transmittance due to the polarity when a positive-type liquid crystal material and a negative-type liquid crystal material are used will be described with reference to FIG. 2. Note that the positive-type liquid crystal material is a liquid crystal material having positive dielectric anisotropy, and the negative-type liquid crystal material is a liquid crystal material having negative dielectric anisotropy. Here, the transmittance due to the polarity when a positive-type liquid crystal material and a negative-type liquid crystal material are used will be described with reference to FIG. 2. Note that the positive-type liquid crystal material is a liquid crystal material having positive dielectric anisotropy, and the negative-type liquid crystal material is a liquid crystal material having negative dielectric anisotropy.

[0039] FIG. 2(A) shows the voltage-transmittance characteristics when a positive-type liquid crystal material (manufactured by Merck KGaA: MLC-7030) is used, and FIG. 2(B) shows the voltage-transmittance characteristics when a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006) is used. FIG. 2(A) shows the voltage-transmittance characteristics when a positive-type liquid crystal material (manufactured by Merck KGaA: MLC-7030) is used, and FIG. 2(B) shows the voltage-transmittance characteristics when a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006) is used. FIG. 2(A) shows the voltage-transmittance characteristics when a positive-type liquid crystal material (manufactured by Merck KGaA: MLC-7030) is used, and FIG. 2(B) shows the voltage-transmittance characteristics when a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006) is used. The physical property values of the positive-type liquid crystal material shown in FIG. 2(A) are such that the anisotropy of the dielectric constant Δε is 3.8, and the resistivity ρ is 4.9×10 Ω·cm. Also, the physical property values of the negative-type liquid crystal material shown in FIG. 2(B) 14 are such that the anisotropy of the dielectric constant Δε is -3.0, and the resistivity ρ is 1.8×10 Ω·cm. In the voltage-transmittance characteristics shown in FIGS. 2(A) and 2(B), the horizontal axis 13 represents the voltage (V), and the vertical axis represents the transmittance (%). Also, in the voltage-transmittance characteristics shown in FIGS. 2(A) and 2(B), the solid line represents the transmittance when a positive (+) polarity is applied, and the dashed line represents the transmittance when a negative (-) polarity is applied. and the dashed line represents the transmittance when a negative (-) polarity is applied. and the dashed line represents the transmittance when a negative (-) polarity is applied.

[0040] From FIGS. 2(A) and 2(B), when using a negative-type liquid crystal material, It can be seen that the difference in transmittance due to polarity is small. This is considered to be caused by the flexoelectric effect. The flexoelectric effect is a phenomenon in which polarization occurs mainly due to the molecular shape and the orientation strain.

[0041] For example, spontaneous polarization occurs by applying splay or bend orientation strain to nematic liquid crystals. Originally, there is no distinction in the polarity of the applied voltage for the liquid crystal molecules themselves, but the spontaneous polarization tends to show opposite behavior depending on the polarity of the electric field. Therefore, it is considered that fluctuations in transmittance due to polarity occur. The flexoelectric polarization P generated by the flexoelectric effect is expressed by the following mathematical formula (1).

[0042]

Equation

[0043] Here, e is the flexoelectric coefficient mainly due to the molecular shape, n is the director of the liquid crystal, and the polarization is expressed as the product of the flexoelectric coefficient and the orientation strain.

[0044] Therefore, in order to suppress the generation of polarization and reduce the flicker, it is preferable to reduce the flexoelectric coefficient or the orientation strain.

[0045] From FIGS. 2(A) and (B), by using a negative-type liquid crystal material, the orientation strain caused by the above-described flexoelectric effect can be reduced.

[0046] In addition, a liquid crystal display device according to an aspect of the present invention controls the driving of the liquid crystal element 111 using a pixel electrode, a first common electrode, and a second common electrode. As a driving method of the liquid crystal element 111, the following description will be made with reference to FIG. 1(B). ​​​​​​​

[0047] FIG. 1(B) corresponds to a cross-sectional view showing an example of the liquid crystal element 111 of the liquid crystal display device according to one embodiment of the present invention. Corresponding.

[0048] The liquid crystal element 111 includes a first common electrode 122 on a substrate 120, an insulating layer 124 on the first common electrode 122, a pixel electrode 126 on the insulating layer 124, a liquid crystal layer 134 on the insulating layer 124 and the pixel electrode 126, a second common electrode 132 on the liquid crystal layer 134, and a substrate 130 on the second common electrode 132. Further, as shown in FIG. 1(B), the pixel electrode 126 is in contact with the insulating layer 124, and the insulating layer 124 is in contact with the first common electrode 122. Note that the first common electrode 122, the insulating layer 124, and the pixel electrode 126 are formed on the substrate 120, and the second common electrode 132 is formed below the substrate 130. That is, the liquid crystal layer 134 is sandwiched between the substrate 120 and the substrate 130. Further, since an opening (slit) is formed in the pixel electrode 126 on the insulating layer 124, a plurality of pixel electrodes 126 are shown in FIG. 1(B).

[0049] Further, in the cross-sectional view shown in FIG. 1(B), the liquid crystal element 111a is formed by the first common electrode 122, the pixel electrode 126, and the liquid crystal layer 134. By applying a voltage between the first common electrode 122 and the pixel electrode 126, the alignment state of the liquid crystal layer 134 can be controlled. Also, the liquid crystal element 111b is formed by the second common electrode 132, the pixel electrode 126, and the liquid crystal layer 134. By applying a voltage between the second common electrode 132 and the pixel electrode 126, the alignment state of the liquid crystal layer 134 can be controlled. Further, a voltage is applied between the first common electrode 122 and the second common electrode 132 in the liquid crystal element 111c. ​​​​​​​​​​​​​​​ By this, the alignment state of the liquid crystal layer 134 can be controlled. Also, as shown in FIG. 1(A) The capacitive element 113 is formed by a first common electrode 122, an insulating layer 124, and a pixel electrode 126 The insulating layer 124 has a function as a dielectric layer of the capacitive element 113 .

[0050] Also, in the cross-sectional view shown in FIG. 1(B), the voltage applied to the liquid crystal layer 134 is schematically represented by an arrow .

[0051] For example, by applying 5.5 V to the pixel electrode 126, 0 V to the first common electrode 122, and 0.8 V to the second common electrode 132, respectively, the liquid crystal element 11 1 shown in FIG. 1(B) can be driven. In this case, since the potential difference between the first common electrode 122 and the second common electrode 132 is 0.8 V, the influence of the electric field of the liquid crystal element 111c shown in FIG. 1(B) is small. On the other hand, there is a potential difference of 5.5 V between the first common electrode 122 and the pixel electrode 126 , and there is a potential difference of 4.7 V between the pixel electrode 126 and the second common electrode 132. Therefore, mainly, the alignment direction of the liquid crystal in the liquid crystal layer 134 is controlled by the potential difference between the first common electrode 122 and the pixel electrode 126, and further, by the potential applied to the second common electrode 132, the alignment control of the liquid crystal element 111 by the first common electrode 122 and the pixel electrode 126 can be assisted . Therefore, it is preferable that the first common electrode 122 and the second common electrode 132 are connected to independent power supply lines and can be controlled at independent potentials . . By making the potential difference between the first common electrode 122 and the second common electrode 132 smaller than the potential difference between the first common electrode 122 and the pixel electrode 126 in this way, the transmittance of the liquid crystal layer 134 . .

[0052] Thus, by making the potential difference between the first common electrode 122 and the second common electrode 132 smaller than the potential difference between the first common electrode 122 and the pixel electrode 126, the transmittance of the liquid crystal layer 134 can be adjusted The change can be suppressed to a small level.

[0053] Also, in the liquid crystal layer 134 of the liquid crystal element 111, a negative-type liquid crystal material is used, and the resistance rate is preferably 1.0×10 13 Ω·cm or more and 1.0×10 16 Ω·cm or less.

[0054] In this way, the liquid crystal layer 134 is controlled by the three electrodes of the first common electrode 122, the pixel electrode 126, and the second common electrode 132, and by using a negative-type liquid crystal, the change in the transmittance of the liquid crystal layer 134 can be suppressed to a small level, and flickering can be prevented from being visually recognized. This is an excellent effect that can only be achieved in one aspect of the present invention.

[0055] Also, in the liquid crystal display device according to one aspect of the present invention, the voltage V of the liquid crystal element 111 LC1 is held by the capacitance element 113, so the area of the capacitance element 113 can be suppressed to be small. That is, while suppressing the area of the capacitance element 113, flickering can be suppressed from being visually recognized. Therefore, high definition of the pixel can be achieved, and moreover, the interval at which the image signal is written to the pixel can be lengthened, so that eye fatigue can be reduced and a liquid crystal display device that is gentle on the eyes can be realized.

[0056] <Example of Panel Configuration> Next, an example of the panel configuration corresponding to one form of the liquid crystal display device will be described.

[0057] In the panel 230 shown in FIG. 3, in the pixel portion 231, there are a plurality of pixels 100, and wirings GL1 to GLy (y is a natural number) represented by the wirings GL for selecting the pixels 100 for each row, and Wiring SL1 to wiring SLx (x is a natural number) are provided for supplying an image signal to the selected pixel 100. The input of the signal to the wiring GL is controlled by the drive circuit 232. The input of the image signal to the wiring SL is controlled by the drive circuit 233. A plurality of pixels 100 are respectively connected to at least one of the wirings GL and at least one of the wirings SL.

[0058] Note that the type and number of the wirings provided in the pixel portion 231 can be determined by the configuration, number, and arrangement of the pixels 100. Specifically, in the case of the pixel portion 231 shown in FIG. 3, the pixels 100 of x columns × y rows are arranged in a matrix, and the case where the wirings SL1 to SLx and the wirings GL 1 to GLy are arranged in the pixel portion 231 is exemplified.

[0059] In one aspect of the present invention, by intermittently setting the drive circuits 232 and 233 to an operating state, while maintaining the display of the image, the number of times of writing the image signal to the pixel portion 231 can be significantly reduced. For example, when using the transistor 112 including a highly purified oxide semiconductor in the channel formation region, the length of the frame period can be 10 seconds or more, preferably 30 seconds or more , more preferably 1 minute or more. Therefore, the drive frequencies of the drive circuits 232 and 233 can be significantly reduced, and the power consumption of the liquid crystal display device can be reduced.

[0060] Note that in one aspect of the present invention, sequential driving may be used in which the image signal is sequentially input from the drive circuit 233 to the wirings SL1 to SLx, or from the drive circuit 233 to the wirings SL1 to Sequential line driving for inputting image signals to wiring SLx may be used. Alternatively, in one aspect of the present invention the liquid crystal display device according to one aspect may use a driving method for sequentially inputting image signals for each of a plurality of wirings SL.

[0061] Also, the selection of the wiring GL may use a progressive method or an interlace method.

[0062] Note that the response time from when a voltage is applied until the transmittance of the liquid crystal converges is generally on the order of ten-odd msec. Therefore, the slowness of the response of the liquid crystal is likely to be visually recognized as blurring of the moving image. Thus, in one aspect of the present invention, overdrive driving may be used to temporarily increase the voltage applied to the liquid crystal element 111 to rapidly change the alignment of the liquid crystal. By using overdrive driving, the response speed of the liquid crystal can be increased, blurring of the moving image can be prevented, and the quality of the moving image can be improved.

[0063] Also, if the transmittance of the liquid crystal element 111 continues to change without converging even after the transistor 112 becomes non-conductive, the relative permittivity of the liquid crystal changes, so the voltage held by the liquid crystal element 111 is likely to change. In particular, when the capacitance value of the capacitance element 113 connected to the liquid crystal element 111 is small as in one aspect of the present invention, the change in the voltage held by the liquid crystal element 111 described above is likely to occur significantly. However, by using the above overdrive driving, the response time can be shortened, so the change in the transmittance of the liquid crystal element 111 after the transistor 112 becomes non-conductive can be reduced. Therefore, even when the capacitance value of the capacitance element 113 connected in parallel to the liquid crystal element 111 is small, the transistor 112 is in a non-conductive state. ​​​​​​​​​​​​​​After that, it is possible to prevent the voltage held by the liquid crystal element 111 from changing.

[0064] Furthermore, the liquid crystal material used for the liquid crystal element 111 is a negative-type liquid crystal material and has a resistivity of 1.0×1 0 13 Ω·cm or more and 1.0×10 16 Ω·cm or less. Therefore, after the transistor 112 becomes non-conductive, it is possible to prevent the voltage held by the liquid crystal element 111 from changing. .

[0065] <Example configuration of the liquid crystal display device> Next, an example configuration of the liquid crystal display device according to one aspect of the present invention will be described.

[0066] In FIG. 4, the configuration of the liquid crystal display device according to one aspect of the present invention is shown as a block diagram as an example. The liquid crystal display device 240 shown in FIG. 4 includes a panel 230 having a plurality of pixels 100 in a pixel portion 231, a controller 241, and a power supply circuit 247. Further, the liquid crystal display device 240 shown in FIG. 4 includes an input device 242, a CPU 243, an image processing circuit 244, and an image memory 2 45. Also, the liquid crystal display device 240 shown in FIG. 4 includes a driving circuit 2 32 and a driving circuit 233 in the panel 230.

[0067] Note that the controller 241 has a function of supplying various driving signals for controlling the operations of the driving circuit 232, the driving circuit 233, etc. to the panel 230. The driving signals include a start pulse signal for the driving circuit 233 that controls the operation of the driving circuit 233, a clock signal for the driving circuit 233, a start pulse signal for the driving circuit 232 that controls the operation of the driving circuit 232, a clock signal for the driving circuit 232, and the like.

[0068] The input device 242 has the function of giving information and instructions to the CPU 243 of the liquid crystal display device 240. For example, an instruction for changing the panel 230 from the operating state to the stopped state, or an instruction for changing the pixel section 231 from the stopped state to the operating state can be given to the CPU 243. As the input device 242, a keyboard, a mouse, a touch panel, or the like can be used.

[0069] The CPU 243 has the function of executing an instruction by decoding the instruction input from the input device 242 and comprehensively controlling the operations of various circuits of the liquid crystal display device 240.

[0070] For example, when an instruction for changing the pixel section 231 from the operating state to the stopped state is sent from the input device 242, the CPU 243 stops the supply of the power supply voltage Vp from the power supply circuit 247 to the pixel section 231, and in addition, issues an instruction to the controller 241 to stop the supply of the drive signal to the panel 230.

[0071] Or, when an instruction for changing the pixel section 231 from the stopped state to the operating state is sent from the input device 242, the CPU 243 resumes the supply of the power supply voltage Vp from the power supply circuit 247 to the pixel section 231, and in addition, issues an instruction to the controller 241 to resume the supply of the drive signal to the panel 230.

[0072] The image memory 245 has the function of storing the data 246 having the image information input to the liquid crystal display device 240. In FIG. 4, the case where only one image memory 245 is provided in the liquid crystal display device 240 is illustrated, but a plurality of image memories 245 are provided in the liquid crystal display device 240. ​ It may be provided. For example, three data respectively corresponding to hues such as red, blue, and green 246. When a full-color image is displayed on the pixel unit 231, image memories 24 corresponding to the data 24

[0073] The image memory 245 may use, for example, a storage circuit such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). Or, VRAM (Video RAM) may be used for the image memory 245.

[0074] The image processing circuit 244 has a function of generating an image signal from the data 246 by writing the data 246 into the image memory 245 of the data 246 and reading the data 246 from the image memory 245 according to an instruction from the controller 241.

[0075] In addition to the function of supplying the power supply voltage Vp to the panel 230, the power supply circuit 247 has a function of supplying the potential V COM 1 and the potential V COM 2 to the pixel 100.

[0076] <Top view of pixel> Next, an example of the top view of the pixel 100 shown in Fig. 1(A) is shown in Fig. 5. In Fig. 5, In order to clarify the top view of the pixel 100, some components such as the gate insulating film are omitted from the illustration. Also, cross-sectional views corresponding to the cross-sections between the dashed-dotted lines A1 - A2 and between the dashed-dotted lines A3 - A4 shown in Fig. 5 are shown in Fig. 6.

[0077] The pixel 100 shown in Figs. 5 and 6 has a transistor 1 on a substrate 302 having an insulating surface. ​​​​A conductive film 304 having a function as 12 gates and a function as a wiring GL is provided. Also, on the substrate 302, a first common electrode 318 having a function as an electrode of the capacitor element 113 and a function as a first common electrode is provided. That is, a potential V is supplied to the first common electrode 318. COM1

[0078] Further, an insulating film 306 is provided on the substrate 302 so as to cover the conductive film 304. Then, an oxide semiconductor film 308 that functions as a channel formation region of the transistor 112 is provided at a position overlapping the conductive film 304 with the insulating film 306 interposed therebetween. The oxide semiconductor film 308 has conductive films 310 and 312 provided thereon. Also, a conductive film 313 formed in the same process as the conductive films 310 and 312 is provided on the insulating film 306. The conductive film 310 has a function as a wiring SL and a function as a source or drain of the transistor 112. The conductive film 312 has a function as a source or drain of the transistor 112. The conductive film 313 has a function as a capacitor line. The conductive film 312 has a function as a source or drain of the transistor 112. The conductive film 313 has a function as a capacitor line.

[0079] Further, an insulating film 314 is provided on the insulating film 306, the oxide semiconductor film 308, and the conductive films 310, 312, and 313. An insulating film 316 having a function as a planarization film is provided on the insulating film 314. Also, openings 360 reaching the conductive film 3 12 are provided in the insulating films 314 and 316. Also, openings 362 reaching the conductive film 3 13 are provided in the insulating films 314 and 316.

[0080] The first common electrode 318 is provided on the insulating film 316. The first common electrode 318 ​​is connected to the conductive film 313 through the opening 362. Also, an insulating film 320 is provided on the common electrode 318 of the first and a pixel electrode 322 is provided at a position overlapping the common electrode 318 of the first on the insulating film 320. The insulating film 320 has an opening 364 at a position overlapping the opening 360, and the conductive film 312 and the pixel electrode 322 are connected through the openings 360 and 364. Note that the pixel electrode 322 has an opening (slit) as shown in the top view of FIG. 5. Also, an alignment film 324 is provided on the insulating film 320 and the pixel electrode 322.

[0081] Also, a substrate 330 is provided so as to face the substrate 302. Below the substrate 330 are provided a light-shielding film 332 having a function of blocking visible light, a colored film 334 transmitting visible light in a specific wavelength range, an insulating film 336 in contact with the light-shielding film 332 and the colored film 334, a second common electrode 338 in contact with the insulating film 336, and an alignment film 340 in contact with the second common electrode 338. The insulating film 336 has a function of suppressing the surface shape of the light-shielding film 332 and the colored film 334 from impairing the flatness of the second common electrode 338 or the alignment film 340. Note that the insulating film 336 may not be provided.

[0082] Then, a liquid crystal layer 350 containing a liquid crystal material is provided between the substrate 302 and the substrate 330 so as to be sandwiched between the alignment film 324 and the alignment film 340. The liquid crystal element 111 has at least the first common electrode 318, the insulating film 320, the pixel electrode 322, the second common electrode 338, and the liquid crystal layer 350. Note that the liquid crystal layer 350 uses a negative liquid crystal material, and the resistivity of the liquid crystal material is 1.0×10 Ω·cm or more and 1.0×10 13 Ω·cm or less.​​​​​​​​​16 It is below Ω·cm.

[0083] 〈Fabrication method〉 Next, an example of the fabrication method of the pixel shown in FIG. 6 will be described with reference to FIGS. 7 and 8. .

[0084] As shown in FIG. 7(A), after forming a conductive film on the substrate 302, the conductive film is etched or the like to process the shape, thereby forming the conductive film 304. Next, an insulating film 306 is formed on the conductive film 304. Next, after forming an oxide semiconductor film on the insulating film 306, the oxide semiconductor film is etched or the like to process the shape, and an island-shaped separated oxide semiconductor film 308 is formed at a position overlapping the conductive film 304.

[0085] As the substrate 302, a substrate having heat resistance sufficient to withstand subsequent fabrication processes is desirable. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like is used. .

[0086] As the conductive film 304, a film made of a conductive material containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, indium, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten may be used by laminating one layer or two or more layers. For example, , as the conductive film 304, a conductive film in which a copper film is laminated on a tungsten nitride film or a single-layer tungsten sten film can be used.

[0087] As the insulating film 306, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and acid yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and acid An insulating film containing one or more kinds of tantalum oxide may be used as a single layer or as a laminate.

[0088] For example, when the insulating film 306 has a two-layer structure, the first layer may be a silicon nitride film and the second layer may be a multi-layer film with a silicon oxide film. The second silicon oxide film may be a silicon oxynitride film. Further, the first silicon nitride film can be a silicon oxynitride film.

[0089] It is preferable to use a silicon oxide film with a low defect density as the silicon oxide film. Specifically, a silicon oxide film is used in which the spin density of spins derived from a signal with a g value of 2.001 in electron spin resonance (ESR) is 3 × 10 17 spins / cm 3 or less, preferably 5 × 10 16 spins / cm 3 or less. It is preferable to use a silicon oxide film having an excessive amount of oxygen as the silicon oxide film. For the silicon nitride film, a silicon nitride film with a small amount of hydrogen and ammonia released is used. The release amounts of hydrogen and ammonia may be measured by TDS (Thermal Desorption Spectroscopy: temperature-programmed desorption gas spectroscopy) analysis.

[0090] The materials that can be used for the oxide semiconductor film 308 are described in detail in Embodiment 2. Further, if a large amount of hydrogen is contained in the oxide semiconductor film used as the oxide semiconductor film 308, when hydrogen binds to the oxide semiconductor, a part of hydrogen becomes a donor and generates electrons that are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. ​​​It will shift to Therefore, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film so that it contains as few impurities as possible.

[0091] Note that due to the dehydration treatment (dehydrogenation treatment) on the oxide semiconductor film, oxygen may decrease from the oxide semiconductor film. Therefore, in order to compensate for the oxygen vacancies increased by the dehydration treatment (dehydrogenation treatment) on the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide semiconductor film.

[0092] In this way, the oxide semiconductor film can be made into an oxide semiconductor film that is i-type (intrinsic) or substantially i-type (intrinsic) approaching i-type infinitely by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and compensating for oxygen vacancies by oxygen addition treatment.

[0093] Next, as shown in FIG. 7(B), after forming a conductive film on the insulating film 306 and the oxide semiconductor film 308, the shape of the conductive film is processed by etching or the like to form conductive films 310 and 312 in contact with the oxide semiconductor film 308. Also, a conductive film 313 is formed on the insulating film 306 in the same process as the process of forming the conductive films 310 and 312.

[0094] As the conductive films 310, 312, and 313, for example, a single metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component can be used as a single-layer structure or a laminated structure. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, tung sten ​​​​​​​​​A two-layer structure in which a titanium film is laminated on a stainless steel film, on a copper-magnesium-aluminum alloy film A two-layer structure in which a copper film is laminated, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. There is also a case where a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used. Further, the conductive film can be formed, for example, by a sputtering method. and further a molybdenum film or a molybdenum nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film and further a molybdenum film or a molybdenum nitride film is formed thereon, etc. There is also a case where a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used. Further, the conductive film can be formed, for example, by a sputtering method. Next, as shown in FIG. 7(C), an insulating film 306, an oxide semiconductor film 308, and an insulating film 314 are formed on the conductive films 310, 312, and 313. As the insulating film 314, for example, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is held at 180° C. or higher and 400° C. or lower, more preferably 200° C. or higher and 370° C. or lower,

[0095] and a raw material gas is introduced into the processing chamber to set the pressure in the processing chamber to 30 Pa or higher and 250 Pa or lower, more preferably 40 Pa or higher and 200 Pa or lower, and a high-frequency power is supplied to an electrode provided in the processing chamber to form a silicon oxide film or a silicon oxynitride film.

[0096] As the raw material gas for the insulating film 314, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, oxygen, ozone, nitrous oxide, As the raw material gas for the insulating film 314, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, oxygen, ozone, nitrous oxide, and a raw material gas is introduced into the processing chamber to set the pressure in the processing chamber to 30 Pa or higher and 250 Pa or lower, more preferably 40 Pa or higher and 200 Pa or lower, and a high-frequency power is supplied to an electrode provided in the processing chamber to form a silicon oxide film or a silicon oxynitride film. and a high-frequency power is supplied to an electrode provided in the processing chamber to form a silicon oxide film or a silicon oxynitride film.

[0097] As the raw material gas for the insulating film 314, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, oxygen, ozone, nitrous oxide, As the raw material gas for the insulating film 314, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, oxygen, ozone, nitrous oxide, As the raw material gas for the insulating film 314, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, oxygen, ozone, nitrous oxide, There is nitrogen oxide, etc.

[0098] In this embodiment, the insulating film 314 has a laminated structure of a first insulating film and a second insulating film. For example, as the first insulating film, silane with a flow rate of 20 sccm and nitrous oxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 40 Pa, the substrate temperature is 220 °C, and 2 100 W of high-frequency power is supplied to the parallel plate electrode using a high-frequency power source of 7.12 MHz. By plasma CVD, a silicon oxynitride film with a thickness of 50 nm is formed. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 and, when the supplied power is converted to power per unit area (power density), it is 1.6×10 W / cm -2 m 2 Under these conditions, a silicon oxynitride film that permeates oxygen can be formed.

[0099] The second insulating film is formed by maintaining the substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 1 80 °C or higher and 260 °C or lower, more preferably 180 °C or higher and 230 °C or lower, introducing source gases into the processing chamber to make the pressure in the processing chamber 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower, and supplying high-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W 2 / cm or lower to form a silicon oxide film or a silicon oxynitride film.

[0100] As the film formation conditions for the second insulating film, in the processing chamber at the above pressure, high-frequency power with the above power density

[0100] ​ By supplying power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. , since the oxidation of the source gas proceeds, the oxygen content in the second insulating film becomes more than the stoichiometric composition. However, when the substrate temperature is the above temperature, the bonding force between silicon and oxygen is weak, so part of the oxygen desorbs due to heating. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and from which part of the oxygen desorbs due to heating can be formed. possible.

[0101] In the present embodiment, as the second insulating film, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 400 0 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 22 0 °C, and a 400-nm-thick silicon oxynitride film is formed by plasma CVD using a high-frequency power source of 27.12 MHz and supplying 1500 W of high-frequency power to the parallel-plate electrode. . The plasma CVD apparatus is a parallel-plate type plasma CVD 2 apparatus with an electrode area of 6000 cm and when the supplied power is converted to power per unit area (power density), it is 2.5 ×10 -1 W / cm 2 .

[0102] Next, after forming at least the insulating film 314, a heat treatment is performed to move the oxygen contained in the insulating film 314 to the oxide semiconductor film 308 to compensate for the oxygen deficiency in the oxide semiconductor film 308. This is preferable.

[0103] Next, as shown in FIG. 7(D), a desired region of the insulating film 314 is processed to form an opening 360 reaching the conductive film 312 and an opening 362 reaching the conductive film 313.

[0104] ​​​​As a method for forming the openings 360 and 362, for example, a dry etching method or a wet etching method is used. Also, the openings 360 and 362 may be formed by combining the dry etching method and the wet etching method.

[0105] Next, as shown in FIG. 8(A), an insulating film 316 having an opening is formed. The insulating film 316 has openings at positions corresponding to the openings 360 and 362. The insulating film 316 is a film that serves as a base for the first common electrode 318 and has a function of preventing the formation of irregularities on the first common electrode 318 by transistors, conductive films, etc. That is, it has a function as a planarizing film. For the insulating film 316, an acrylic resin, a polyimide resin, etc. can be used.

[0106] Next, as shown in FIG. 8(B), the first common electrode 318 is formed on the insulating film 316. Then, an insulating film 320 is formed so as to cover the insulating film 316 and the first

[0107] common electrode 318. The first common electrode 318 is connected to the conductive film 313 through the opening 362. As the first common electrode 318, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium

[0108] tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc., can be used. Also, the first common electrode 318 can be A silicon oxide film or the like can be used. In particular, the insulating film 320 is a dielectric of the capacitor element. The insulating film is made of nitride. A silicon nitride film or a silicon oxynitride film is preferred.

[0109] The insulating film 320 may be, for example, a silicon nitride film having a thickness of 50 nm or more and 400 nm or less. Alternatively, a silicon nitride oxide film or the like can be used. A silicon nitride film with a thickness of 100 nm is used as the film thickness 0.

[0110] In addition, the silicon nitride film is preferably formed at a high temperature in order to enhance blocking properties. Preferably, the substrate temperature is 100°C or higher and lower than the distortion point of the substrate, more preferably 300°C or higher and 400°C or lower. It is preferable to form the film by heating at a temperature of 00°C or less. However, when forming the film at a high temperature, Oxygen may be released from the oxide semiconductor film 308, causing a phenomenon in which the carrier concentration increases. Therefore, the temperature should be set at a level at which such a phenomenon does not occur.

[0111] Next, as shown in FIG. 8C, an opening 364 is formed in the insulating film 320. 4 is formed in a region located at an opening 360 formed in the insulating film 316. The opening 364 is formed so as to expose the conductive film 312. The openings 360, 362 can be formed by employing the methods described above.

[0112] Next, as shown in FIG. 8(D), a pixel electrode 322 is formed on the insulating film 320. The pixel electrode 322 is connected to the conductive film 312 through the openings 360 and 364 .

[0113] The pixel electrode 322 is formed by forming a transparent conductive film on the insulating film 320 and processing the shape of the transparent conductive film by etching or the like.

[0114] As the pixel electrode 322, a conductive film containing indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0115] Next, an alignment film 324 is formed on the insulating film 320 and the pixel electrode 322 (not shown). The alignment film 324 can be formed using a rubbing method, an optical alignment method, or the like.

[0116] The structure formed on the substrate 302 in the above steps can be formed.

[0117] Next, a method for manufacturing a structure formed below the substrate 330 provided to face the substrate 302 will be described below.

[0118] First, the substrate 330 is prepared. As the substrate 330, the materials shown in the substrate 302 can be used. Next, a light-shielding film 332 and a colored film 334 in contact with the substrate 330 are formed. The light-shielding film 332 and the colored film 334 are formed at desired positions using various materials by a printing method, an inkjet method, an etching method using photolithography technology, etc.

[0119] Next, an insulating film 336 in contact with the light-shielding film 332 and the colored film 334 is formed. As the insulating film 336, for example, an organic insulating film such as an acrylic resin can be used. ​​​​​​​​​By forming, for example, impurities contained in the colored film 334 can be prevented from diffusing toward the liquid crystal layer 350 side. This can suppress diffusion.

[0120] Next, a second common electrode 338 in contact with the insulating film 336 is formed. As the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method. For the conductive film that can be used for the second common electrode 338, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmissive conductive materials can be used. Also, as the conductive layer that can be used for the second common electrode 338, for example, it can be formed using a sputtering method.

[0121] Next, an alignment film 340 in contact with the second common electrode 338 is formed. The formation method of the alignment film 340 can be formed by applying the formation method of the alignment film 324. Next, an alignment film 340 in contact with the second common electrode 338 is formed. The formation method of the alignment film 340 can be formed by applying the formation method of the alignment film 324.

[0122] The structure formed below the substrate 330 can be formed in the above steps.

[0123] Thereafter, a liquid crystal layer 350 is formed between the substrate 302 and the substrate 330. As the formation method of the liquid crystal layer 350, a dispenser method (dropping method) or an injection method in which the substrates 302 and 330 are bonded together and then liquid crystal is injected using capillary action can be used. Thereafter, a liquid crystal layer 350 is formed between the substrate 302 and the substrate 330. As the formation method of the liquid crystal layer 350, a dispenser method (dropping method) or an injection method in which the substrates 302 and 330 are bonded together and then liquid crystal is injected using capillary action can be used. Thereafter, a liquid crystal layer 350 is formed between the substrate 302 and the substrate 330. As the formation method of the liquid crystal layer 350, a dispenser method (dropping method) or an injection method in which the substrates 302 and 330 are bonded together and then liquid crystal is injected using capillary action can be used.

[0124] In the above steps, the pixel shown in FIG. 6 can be manufactured.

[0125] As described above, the configuration, method, etc. shown in this embodiment are the same as those shown in other embodiments. They can be used in appropriate combinations.

[0126] (Embodiment 2) In this embodiment, an oxide semiconductor that can be used in a liquid crystal display device according to one aspect of the present invention will be described.

[0127] An oxide semiconductor (purified OS) that has reduced impurities such as moisture or hydrogen serving as an electron donor (donor) and has also been purified by reducing oxygen vacancies is of type i (intrinsic semiconductor) or extremely close to type i. Therefore, a transistor having a channel formation region in the purified oxide semiconductor film has an extremely small off-current and high reliability. Specifically, the fact that the off-current of a transistor having a channel formation region in the purified oxide semiconductor film is small can be proven by various experiments. For example, even in an element with a channel width of 1 ×

[0128] 10 μm and a channel length of 10 μm, the off-current is below the measurement limit of a semiconductor parameter analyzer 10 6 even when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, that is, a characteristic of 1 × 10 A or less can be obtained. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less -13 . Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or flowing out of the capacitor element is controlled by the transistor to measure the off-current. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is determined from the change in the charge amount per unit time of the capacitor element. The off-current of the transistor is measured using a circuit in which a capacitor element and a transistor are connected and the charge flowing into or flowing out of the capacitor element is controlled by the transistor. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is determined from the change in the charge amount per unit time of the capacitor element. In this measurement, the purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is determined from the change in the charge amount per unit time of the capacitor element. The leakage current was measured. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor was 3 V a smaller leakage current of several tens yA / μm was obtained. Therefore, a transistor using a highly purified oxide semiconductor film in the channel formation region has a significantly smaller leakage current than a transistor using crystalline silicon.

[0129] Note that, unless otherwise specified, in this specification, the leakage current means, in an n-channel transistor, the current flowing between the source and the drain when the potential of the gate is 0 or less with the potential of the source as a reference in a state where the drain is at a higher potential than the source and the gate. Alternatively, in this specification, the leakage current means, in a p-channel transistor, the current flowing between the source and the drain when the potential of the gate is 0 or more with the potential of the source as a reference in a state where the drain is at a lower potential than the source and the gate.

[0130] Note that as the oxide semiconductor, it is preferable to contain at least indium (In) or zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. Also, it is preferable to have tin (Sn) as a stabilizer. Also, it is preferable to have hafnium (Hf) as a stabilizer. Also, it is preferable to have aluminum (Al) as a stabilizer. Also, it is preferable to contain zirconium (Zr) as a stabilizer.

[0131] Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, etc. Unlike silicon carbide, gallium nitride, or gallium oxide, transistors with excellent electrical characteristics can be fabricated by sputtering or wet methods, and they have advantages such as excellent mass productivity. Also, different from silicon carbide, gallium nitride, or gallium oxide, the above In-Ga-Zn-based oxide can fabricate transistors with excellent electrical characteristics on a glass substrate. Also, it can accommodate the enlargement of the substrate size.

[0132] Also, as other stabilizers, it may contain any one or more of lanthanoids, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).

[0133] For example, as oxide semiconductors, indium oxide, gallium oxide, tin oxide, zinc oxide, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based acid oxide (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide , Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr-Zn-based oxide, I n-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In -Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In- Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Y b-Zn-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In -Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Z n-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used.

[0134] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, it may contain metal elements other than In, Ga, and Zn. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field, can sufficiently reduce the off-current, and also has a high mobility.

[0135] For example, In-Ga-Zn-based oxides with atomic ratios such as In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:1.2 (5:5 :6), In:Ga:Zn = 2:2:1, In:Ga:Zn = 3:1:2, etc., or oxides in the vicinity of their compositions can be used. Alternatively, In-Sn-Zn-based oxides with atomic ratios such as In:Sn:Zn = 1:1:1, In:Sn:Zn = 2:1:3, or In:Sn: Zn = 2:1:5, or oxides in the vicinity of their compositions are preferably used.

[0136] For example, a relatively high mobility can be obtained relatively easily in In-Sn-Zn-based oxides. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

[0137] ​​​​​​Oxide semiconductor films are roughly classified into non-single-crystalline oxide semiconductor films and single-crystalline oxide semiconductor films. The non-single-crystalline oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. Here, the CAAC-OS film will be described.

[0138] Here, the CAAC-OS film will be described.

[0139] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC- OS film also include cases where the size fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. Included are cases where the size fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm.

[0140] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Elec tron Microscope), it is not possible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, it can be said that the CAAC- OS film is less likely to have a decrease in electron mobility due to grain boundaries.

[0141] When the CAAC-OS film is observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal parts. Metal atoms in each layer have a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film. in each layer have a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film. in each layer have a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0142] On the one hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0143] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, " perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0144] From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0145] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, a peak may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0146] On the other hand, in the analysis by the in-plane method in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear at around 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. The single crystal acid of InGaZnO4 ​​​​​ In the case of a compound semiconductor film, when 2θ is fixed near 56° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), six peaks attributable to crystal planes equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, even when φ scan is performed with 2θ fixed near 56°, no distinct peak appears. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film.

[0147] Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially. It can be seen that although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. Therefore, as confirmed by the above cross-sectional TEM observation, each layer of the metal atoms arranged in a layered manner is a plane parallel to the ab plane of the crystal. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film.

[0148] Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Note that the crystal parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film.

[0149] Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Furthermore, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0150] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the (311) plane of the ZnGa2O4 crystal. Therefore, it is believed that the Z The CAAC-OS film shows that it contains nGa2O4 crystals. It is preferable that the peak is shown around 36° in 2θ and that the peak is not shown around 36° in 2θ.

[0151] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0152] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0153] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or is substantially called high-purity genuineness. An oxide semiconductor that is high-purity genuine or substantially high-purity genuine film has few carrier generation sources, so the carrier density can be lowered. Therefore, the transistor using the oxide semiconductor film rarely has electrical characteristics (also called normally-off.) in which the threshold voltage becomes negative. In addition, an oxide semiconductor film that is high-purity genuine or substantially high-purity genuine has few carrier traps. Therefore, the transistor using the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor . Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics . and a long time is required. Sometimes it behaves like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics .

[0154] In addition, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light .

[0155] The CAAC-OS film is formed, for example, by sputtering using a polycrystalline metal oxide target. When ions collide with the target, the crystal regions contained in the target may split from the a-b plane and peel off as plate-like or pellet-like sputtering particles having a plane parallel to the a-b plane. In this case, the CAAC-OS film can be formed by the plate-like or pellet-like sputtering particles reaching the substrate while maintaining the crystal state .

[0156] In addition, in order to form a CAAC-OS film, it is preferable to apply the following conditions ​​​

[0157] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the processing chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas having a temperature of −80° C. or lower, preferably −100° C. or lower is used.

[0158] In addition, by increasing the substrate heating temperature during film formation, the microstructure of sputtered particles is improved after they reach the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When plate-shaped or pellet-shaped sputtering particles reach the substrate, they migrate on the substrate. Sputtering occurs and the flat surface of the sputtered particle adheres to the substrate.

[0159] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0160] The oxide semiconductor layer may have a stacked structure.

[0161] Here, the oxide semiconductor film 308 used in the transistor 112 shown in FIG. An example of a stacked structure of a dielectric film 307 and an oxide semiconductor film 309 will be described with reference to FIG. Do the following.

[0162] 9A shows an oxide semiconductor film used in the transistor 112. 307 and an oxide semiconductor film 309. The structure is the same as that of transistor 112 shown in FIG. 6, and the previous description can be referred to. It is possible.

[0163] It is preferable to use a metal oxide in which the oxide semiconductor film 307 and the oxide semiconductor film 309 have at least one same constituent element. Or, the constituent elements of the oxide semiconductor film 307 and the oxide semiconductor film 309 may be the same, and the compositions of both may be different. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M.

[0164] The oxide semiconductor film 307 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, an oxide semiconductor having a wide energy gap When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively. When the oxide semiconductor film 307 is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 5:5:6 (1:1:1.2), In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 307 to be formed includes fluctuations of plus or minus 20% of the atomic ratio of the metal elements contained in the sputtering target as an error, respectively.

[0165] When the oxide semiconductor film 307 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M. When the oxide semiconductor film 307 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M. When the oxide semiconductor film 307 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M. When the oxide semiconductor film 307 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M.

[0166] The oxide semiconductor film 307 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As described above, an oxide semiconductor having a wide energy gap By using a conductor, the off-state current of the transistor 112 can be reduced.

[0167] The thickness of the oxide semiconductor film 307 is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0168] The oxide semiconductor film 309 is typically an In—Ga oxide, an In—Zn oxide, or an In— M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) The energy of the bottom of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 307. Specifically, the energy of the bottom of the conduction band of the oxide semiconductor film 309 is The difference in energy from the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, or 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or That is, the electron affinity of the oxide semiconductor film 309 and the electron affinity of the oxide semiconductor film 309 are 0.4 eV or less. The difference between the electron affinity of 07 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 e V or less.

[0169] When the oxide semiconductor film 309 contains the element M at a higher atomic ratio than In, the following (1) The energy gap of the oxide semiconductor film 309 can be increased. (2) The electron affinity of the oxide semiconductor film 309 is reduced. (3) External impurities are removed. (4) The insulating property is higher than that of the oxide semiconductor film 307. Since M is a metal element with a strong bond to oxygen, by having a higher atomic ratio than In, Oxygen deficiency is less likely to occur.

[0170] When the oxide semiconductor film 309 is an In-M-Zn oxide, I excluding Zn and O The atomic ratio of n to M is preferably such that In is less than 50 atomic% and M is 50 atom ic% or more, more preferably, In is less than 25 atomic% and M is 75 atomic % or more.

[0171] Also, when the oxide semiconductor film 307 and the oxide semiconductor film 309 are In-M-Zn oxides (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), compared with the oxide semiconductor film 307, the atomic ratio of M contained in the oxide semiconductor film 309 is larger, typically is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher atomic ratio compared with the above atoms contained in the oxide semiconductor film 307.

[0172] Also, when the oxide semiconductor film 309 is In:M:Zn = x1:y1:z1 [atomic ratio] and the oxide semiconductor film 307 is In:M:Zn = x2:y2:z2 [atomic ratio], y1 / x 1 is larger than y2 / x2, preferably, y1 / x1 is 1.5 times or more than y2 / x2 is. More preferably, y1 / x1 is more than 2 times larger than y2 / x2, even more preferably is, y1 / x1 is more than 3 times larger than y2 / x2. At this time, in the oxide semiconductor film if y2 is x2 or more, it is preferable because stable electrical characteristics can be imparted to the transistor 102 using the oxide semiconductor film. However, if y2 becomes 3 times or more of x2, the field effect mobility of the transistor 102 using the oxide semiconductor film decreases, so y2 is preferably less than 3 times of x2. is preferably less than 3 times of x2. is preferably less than 3 times of x2.

[0173] When the oxide semiconductor film 309 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide is preferably such that M > In, and further, Zn ≧ M. As such atomic ratios of the metal elements of the sputtering target, In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:3, In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:5, In:Ga:Zn = 1:3:6, In:Ga:Zn = 1:3:7, In:Ga:Zn = 1:3:8, In:Ga:Zn = 1:3:9, In:Ga:Zn = 1:3:10, In:Ga:Zn = 1:6:4, In:Ga:Zn = 1:6:5, In:Ga:Zn = 1:6:6, In:Ga:Zn = 1:6:7, In:Ga:Zn = 1:6:8, In:Ga:Zn = 1:6:9, In:Ga:Zn = 1:6:10 are preferable. Note that the atomic ratios of the metal elements contained in the oxide semiconductor film 307 and the oxide semiconductor film 309 formed using the above sputtering target each include a plus or minus 20% variation from the atomic ratios of the metal elements contained in the above sputtering target as an error. In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:3, In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:5, In:Ga:Zn = 1:3:6, In:Ga:Zn = 1:3:7, In:Ga:Zn = 1:3:8, In:Ga:Zn = 1:3:9, In:Ga:Zn = 1:3:10, In:Ga:Zn = 1:6:4, In:Ga:Zn = 1:6:5, In:Ga:Zn = 1:6:6, In:Ga:Zn = 1:6:7, In:Ga:Zn = 1:6:8, In:Ga:Zn = 1:6:9, In:Ga:Zn = 1:6:10 are preferable. In addition, not limited to these, those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor film 307 appropriate. The oxide semiconductor film 309 is the oxide semiconductor film when forming the insulating film 314 formed later. In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:3, In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:5, In:Ga:Zn = 1:3:6, In:Ga:Zn = 1:3:7, In:Ga:Zn = 1:3:8, In:Ga:Zn = 1:3:9, In:Ga:Zn = 1:3:10, In:Ga:Zn = 1:6:4, In:Ga:Zn = 1:6:5, In:Ga:Zn = 1:6:6, In:Ga:Zn = 1:6:7, In:Ga:Zn = 1:6:8, In:Ga:Zn = 1:6:9, In:Ga:Zn = 1:6:10 Note that the atomic ratios of the metal elements contained in the oxide semiconductor film 307 and the oxide semiconductor film 309 formed using the above sputtering target each include a plus or minus 20% variation from the atomic ratios of the metal elements contained in the above sputtering target as an error. In addition, not limited to these, those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor film 307 appropriate. Note that the atomic ratios of the metal elements contained in the oxide semiconductor film 307 and the oxide semiconductor film 309 formed using the above sputtering target each include a plus or minus 20% variation from the atomic ratios of the metal elements contained in the above sputtering target as an error.

[0174] Note that it is not limited to these, and those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor film 307 appropriate. The oxide semiconductor film 309 is the oxide semiconductor film when forming the insulating film 314 formed later. In addition, not limited to these, those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor film 307 appropriate.

[0175] The oxide semiconductor film 309 is the oxide semiconductor film when forming the insulating film 314 formed later. It also functions as a damage mitigation film for 307. The thickness of the oxide semiconductor film 309 is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less.

[0176] In the oxide semiconductor film 307 included in the transistor 112, if silicon or carbon, which is one of the Group 14 elements, is included, oxygen deficiency increases in the oxide semiconductor film 307, and it becomes n- type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 307, and also the concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 309 and the oxide semiconductor film 307 (concentration obtained by secondary ion mass spectrometry) is 2×10 atoms / cm 18 atoms / cm 3 or less , preferably 2×10 17 atoms / cm 3 or less.

[0177] Also, in the oxide semiconductor film 307, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals may generate carriers when combined with the oxide semiconductor, and the off-current of the transistor may increase significantly. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film 307.

[0178] Also, if nitrogen is included in the oxide semiconductor film 307, carriers, i.e., electrons, are generated, the carrier density increases, and it tends to become n-type. As a result, when using an oxide semiconductor containing nitrogen ​​The transistor formed is likely to have normally-on characteristics. Therefore, in the oxide semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5×10 18 atoms / cm 3 or less. .

[0179] In the transistor 112 shown in FIG. 9(A), an oxide semiconductor film 309 is provided between the oxide semiconductor film 307, which serves as the main carrier movement path, and the insulating film 314, on the side of the conductive film 304 that functions as a gate. As a result, even if trap levels are formed due to impurities and defects between the oxide semiconductor film 309 and the insulating film 314, there is a gap between the trap levels and the oxide semiconductor film 307. As a result, electrons flowing through the oxide semiconductor film 307 are less likely to be trapped by the trap levels, the on-current of the transistor 112 can be increased, and the field-effect mobility can be enhanced. Further, when electrons are trapped in the trap levels, the electrons become negative fixed charges. As a result, the threshold voltage of the transistor 112 fluctuates. However, since there is a gap between the oxide semiconductor film 307 and the trap levels, it is possible to reduce the trapping of electrons in the trap levels and reduce the fluctuation of the threshold voltage. In addition, the oxide semiconductor film 307 and the oxide semiconductor film 309 are fabricated such that a continuous junction (here, in particular, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the layers. That is, trap centers and recombination centers are not formed at the interfaces of the films. As a result, the threshold voltage of the transistor 112 fluctuates. However, since there is a gap between the oxide semiconductor film 307 and the trap levels, it is possible to reduce the trapping of electrons in the trap levels and reduce the fluctuation of the threshold voltage.

[0180] Note that the oxide semiconductor film 307 and the oxide semiconductor film 309 are fabricated so that a continuous junction (in particular, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the layers. That is, they are fabricated so that a continuous junction (here, in particular, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the layers. Specifically, at the interface of each film, trap centers and recombination centers ​The layered structure is formed so that there are no impurities that would create such defect levels. Impurities are present between the stacked oxide semiconductor films 307 and 309. When this happens, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. They combine and disappear.

[0181] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without being exposed to the atmosphere. Each chamber in the sputtering device is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gases, especially gases containing carbon or hydrogen, from flowing back into the .

[0182] Here, the band structure of the stacked layer structure included in the transistor 112 is shown in FIG. This will be used to explain.

[0183] FIG. 9B schematically illustrates a part of the band structure included in the transistor 112. Here, the case where silicon oxide layers are provided as the insulating films 306 and 314 will be described. 9B is a silicon oxide layer used as the insulating film 306. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 307. EcS2 denotes the energy of the bottom of the conduction band of the oxide semiconductor film 309, and Ec I2 represents the energy at the lower end of the conduction band of the silicon oxide layer used as the insulating film 314.

[0184] As shown in FIG. 9(B), in the oxide semiconductor film 307 and the oxide semiconductor film 309, the energy at the lower end of the conduction band changes smoothly without a barrier. In other words, it can be said that it changes continuously. This is because the oxide semiconductor film 307 and the oxide semiconductor film 309 contain common elements, and oxygen moves mutually between the oxide semiconductor film 307 and the oxide semiconductor film 309, forming a mixed layer. Thus, it can be said that a mixed layer is formed.

[0185] From FIG. 9(B), it can be seen that in the oxide semiconductor film 308, the oxide semiconductor film 307 becomes a well, and in the transistor using the oxide semiconductor film 308, the channel formation region is formed in the oxide semiconductor film 307. Note that since the energy at the lower end of the conduction band of the oxide semiconductor film 308 changes continuously, it can also be said that the oxide semiconductor film 307 and the oxide semiconductor film 309 are continuously joined.

[0186] As shown in FIG. 9(B), near the interface between the oxide semiconductor film 309 and the insulating film 314, trap levels may be formed due to impurities or defects such as silicon or carbon, which are constituent elements of the insulating film 314. However, by providing the oxide semiconductor film 309, the oxide semiconductor film 307 and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor film 307 may reach the trap levels across the energy difference. When electrons are trapped at the trap levels, negative fixed charges are generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction.​​​​​​​​​​ It will end up. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably or 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable.

[0187] By using the oxide semiconductor described above in the transistor of the liquid crystal display device in one aspect of the present invention, even after the writing of the image signal to the pixel portion is stopped, the display of the image in the pixel portion can be maintained. Further, by using the transistor as an element for controlling the supply of voltage to the liquid crystal element included in the pixel, it is possible to ensure a long period during which the supply of voltage to the liquid crystal element is maintained.

[0188] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0189] (Embodiment 3) In the present embodiment, an example different from the top view and cross-sectional view of the pixel 100 shown in FIGS. 5 and 6 of Embodiment 1 will be described with respect to the configuration example of the pixel of the liquid crystal display device according to one aspect of the present invention. Using FIGS. 10 and 11.

[0190] An example of the top view of the pixel 100 shown in FIG. 1(A) is shown in FIG. 10. In FIG. 10, in order to clarify the top view of the pixel 100, some of the components such as the gate insulating film are omitted and shown. Further, cross-sectional views corresponding to the cut surfaces between the dashed-dotted lines A1 - A2 and between the dashed-dotted lines A3 - A4 shown in FIG. 10 are shown in FIG. 11.

[0191] The pixel 100 shown in FIGS. 10 and 11 includes a transistor on a substrate 302 having an insulating surface. ​​​​A conductive film 304 having a function as a gate of the Ta 112 and a function as a wiring GL is provided. Also, on the substrate 302, an electrode 354 having a function as an electrode of the capacitor element 113 and a function as a first common electrode is provided.

[0192] Further, an insulating film 306 is provided on the substrate 302 so as to cover the conductive film 304. Then, an oxide semiconductor film 308 that functions as a channel formation region of the transistor 112 is provided at a position overlapping the conductive film 304 with the insulating film 306 interposed therebetween. The oxide semiconductor film 308 has conductive films 310 and 312 provided thereon. Also, a conductive film 313 formed in the same process as the conductive films 310 and 312 is provided on the electrode 354 and the insulating film 306. . The conductive film 310 has a function as a wiring SL and a function as a source or drain of the transistor 112. The conductive film 312 has a function as a source or drain of the transistor 112. The conductive film 313 has a function as a capacitor line.

[0193] Note that the electrode 354 is formed in the same process as the oxide semiconductor film 308. Also, the electrode 35 4 is a conductive oxide semiconductor having a higher conductivity than the oxide semiconductor film 308. The electrode 3 54 is provided in contact with the insulating film 321, and hydrogen contained in the insulating film 321 diffuses into the electrode 3 54, thereby increasing the conductivity. Also, since the region of the electrode 354 in contact with the conductive film 313 is not in contact with the insulating film 314, oxygen vacancies in the oxide semiconductor are not compensated for, so the conductivity increases. Therefore, the electrode 354 has a function as an electrode even if it is an oxide semiconductor film formed in the same process as the oxide semiconductor film 308.

[0194] ​​​​ An insulating film 314 is provided so as to cover the oxide semiconductor film 308 and the conductive films 310 and 312. The insulating film 314 is provided so as to cover one end of the electrode 354 and one end of the conductive film 313. The insulating film 314 has an opening 364 through which a part of the electrode 354 and a part of the conductive film 313 are exposed.

[0195] An insulating film 321 is provided on the insulating film 314, the electrode 354, and the conductive film 313. The insulating films 314 and 321 are provided with an opening 366 reaching the conductive film 312. A pixel electrode 322 is provided on the insulating film 321. The pixel electrode 322 is connected to the conductive film 312 through the opening 366. The pixel electrode 322 is provided at a position overlapping the electrode 354 that functions as the first common electrode, and has an opening (slit) as shown in the top view of FIG. 10. An alignment film 324 is provided on the insulating film 321 and the pixel electrode 322.

[0196] A substrate 330 is provided so as to face the substrate 302. Below the substrate 330, there are provided a light-shielding film 332 having a function of blocking visible light, a colored film 334 transmitting visible light in a specific wavelength range, an insulating film 336 in contact with the light-shielding film 332 and the colored film 334, a second common electrode 338 in contact with the insulating film 336, and an alignment film 340 in contact with the second common electrode 338.

[0197] A liquid crystal layer 350 containing a liquid crystal material is provided between the substrate 302 and the substrate 330 so as to be sandwiched between the alignment film 324 and the alignment film 340. The electrode 354 that functions as an electrode, the insulating film 321, the pixel electrode 322, and the second common electrode 3 38 constitute the liquid crystal element 111. The liquid crystal layer 350 uses a negative-type liquid crystal material, and the resistivity of the liquid crystal material is 1.0×10 13 Ω·cm or more and 1.0×10 16 Ω ·cm or less.

[0198] In the configuration of the pixel 100 shown in this embodiment, there is no insulating film that functions as a planarization film, the electrode 354 that functions as the first common electrode is formed in the same process as the oxide semiconductor film 308, and the conductive film 313 that functions as a capacitance line is provided in contact with the electrode 354, which is significantly different from the configuration shown in FIGS. 5 and 6 of the previous embodiment 1.

[0199] Thus, by not using a planarization film, it is possible to suppress impurities (such as water, etc.) contained in the planarization film from entering the oxide semiconductor film 308. Therefore, the reliability of the transistor 112 using the oxide semiconductor film 308 is improved, and a liquid crystal display device with high display quality can be obtained.

[0200] Next, an example of the method for manufacturing the pixel shown in FIG. 11 will be described with reference to FIGS. 12 and 13.

[0201] As shown in FIG. 12(A), after forming a conductive film on the substrate 302, the conductive film is processed into a desired shape by etching or the like to form the conductive film 304. Next, an insulating film 306 is formed on the conductive film 304. Next, after forming an oxide semiconductor film on the insulating film 306, the oxide semiconductor film is processed into a desired shape by etching or the like and separated into islands at positions overlapping the conductive film 304. ​​​​The formed oxide semiconductor film 308 and the oxide semiconductor film 352 separated from the oxide semiconductor film 308 are formed.

[0202] As the substrate 302, the conductive film 304, the insulating film 306, and the oxide semiconductor film 308, the materials and manufacturing methods that can be used for the substrate 302, the conductive film 304, the insulating film 306, and the oxide semiconductor film 308 described in Embodiment 1 are incorporated and formed. Also, the oxide semiconductor film 352 can be formed by using the same materials and manufacturing methods as those of the oxide semiconductor film 308.

[0203] Next, as shown in FIG. 12(B), after forming a conductive film on the insulating film 306 and the oxide semiconductor films 308 and 352, the shape of the conductive film is processed by etching or the like, thereby forming conductive films 310 and 312 in contact with the oxide semiconductor film 308 and a conductive film 313 in contact with the oxide semiconductor film 352.

[0204] As the conductive films 310, 312, and 313, the materials and manufacturing methods that can be used for the conductive films 310, 312, and 313 described in Embodiment 1 are incorporated and formed.

[0205] Next, as shown in FIG. 12(C), an insulating film 314 is formed on the insulating film 306, the oxide semiconductor films 308 and 352, and the conductive films 310, 312, and 313.

[0206] As the insulating film 314, the materials and manufacturing methods that can be used for the insulating film 314 described in Embodiment 1 are incorporated and formed.

[0207] Next, as shown in FIG. 12(D), the shape of the insulating film 314 is processed by etching or the like, An opening 364 is formed so that a part of the oxide semiconductor film 352 and a part of the conductive film 313 are exposed. Note that it is sufficient if at least the oxide semiconductor film 352 is exposed, and it is not necessary to expose the surface of the conductive film 313. As a method for forming the opening 364, for example, a dry etching method or a wet etching method is used. Also, the opening 364 may be formed by combining the dry etching method and the wet etching method.

[0208]

[0209] Next, as shown in FIG. 13(A), an insulating film 314 and an insulating film 321 that covers the opening 364 are formed.

[0210] The insulating film 321 is a film formed of a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor, and further contains hydrogen. For this reason, when the hydrogen in the insulating film 321 diffuses into the oxide semiconductor film 352, in the oxide semiconductor film 352, hydrogen combines with oxygen, or hydrogen combines with oxygen vacancies and electrons that are carriers are generated. As a result, the oxide semiconductor film 352 becomes more conductive than the oxide semiconductor film 308 and becomes an electrode �54 that functions as the first common electrode.

[0211] As the insulating film 321, for example, a silicon nitride film having a thickness of 50 nm or more and 400 nm or less, or a silicon oxynitride film can be used. In the present embodiment, a silicon nitride film having a thickness of 100 nm is used as the insulating film 321.

[0212] Also, the silicon nitride film is preferably formed at a high temperature in order to enhance the blocking property. Preferably, for example, the film is formed by heating at a temperature of 100 °C or higher and below the distortion point of the substrate, more preferably 300 °C or higher and 4 00 °C or lower. However, when forming the film at a high temperature, oxygen may desorb from the oxide semiconductor film 308, and a phenomenon of an increase in carrier concentration may occur . Therefore, the temperature should be set such that such a phenomenon does not occur .

[0213] Also, in FIGS. 11 and 13, although not shown, after forming the insulating film 321, an additional insulating film may be formed. As the insulating film, for example, a silicon oxide film formed by the PE-CVD method using an organic silane gas can be used. The silicon oxide film can be provided with a thickness of 300 nm or more and 600 nm or less. As the organic silane gas, silicic acid ethyl (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethyl cyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxy silane (SiH(OC2H5)3), tris(dimethylamino)silane (SiH( N(CH3)2)3), and other silicon-containing compounds can be used. Further, the above-mentioned silicon oxide film can be formed, for example, by the PE-CVD method using an organic silane gas and oxygen, with the substrate temperature being 200 °C or higher and 550 °C or lower, preferably 220 °C or higher and 500 °C or lower, more preferably 300 °C or higher and 450 °C or lower . . .

[0214] By forming the above-mentioned insulating film further on the insulating film 321, it becomes possible to planarize the unevenness caused by transistors and the like. Also, the above-mentioned insulating film is formed of an inorganic material . Therefore, compared with planarization resin films using organic materials, the oxide semiconductor film is affected more. Fewer impurities.

[0215] Next, after forming at least the insulating film 314, a heat treatment is performed to remove the oxide film contained in the insulating film 314. The oxygen vacancies in the oxide semiconductor film 308 are filled by transferring the oxygen thereto. It is preferable.

[0216] Next, as shown in FIG. 13(B), desired regions of the insulating films 314 and 321 are removed. Then, an opening 366 reaching the conductive film 312 is formed.

[0217] The opening 366 can be formed by, for example, dry etching or wet etching. In addition, the opening is made by combining dry etching and wet etching. A portion 366 may be formed.

[0218] Next, as shown in Fig. 13(C), a pixel electrode 322 is formed on the insulating film 321. The pixel electrode 322 is connected to the conductive film 312 through the opening 366 .

[0219] The pixel electrode 322 is formed by forming a transparent conductive film on the insulating film 321 and then etching the transparent conductive film. It is formed by processing the shape of the transparent conductive film.

[0220] As the pixel electrode 322, a material that can be used for the pixel electrode 322 described in Embodiment 1 is It can be formed by using materials and manufacturing methods.

[0221] Next, an alignment film 324 (not shown) is formed on the insulating film 321 and the pixel electrodes 322. The alignment film 324 can be formed by using a rubbing method, a photoalignment method, or the like.

[0222] The structure formed on the substrate 302 in the above process can be formed.

[0223] The substrate 330 provided facing the substrate 302, the liquid crystal element 111, etc. can be formed by referring to the description of Embodiment 1.

[0224] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0225] (Embodiment 4) In the present embodiment, an example of an electronic device using a liquid crystal display device according to an aspect of the present invention will be described with reference to FIG. 14.

[0226] The liquid crystal display device according to an aspect of the present invention can be used for a display device, a personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, examples of electronic devices that can use the liquid crystal display device according to an aspect of the present invention include mobile phones, game machines including portable types, portable information terminals, electronic books, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 14. FIG. 14(A) shows a portable game machine, including a housing 5001, a housing 5002, and a display unit 5003. 4.

[0227] ​ , a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, etc. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 5003 or the display unit 5004. Note that the portable game machine shown in Fig. 14(A) has two display units, the display unit 5003 and the display unit 5004, but the number of display units of the portable game machine is not limited to this.

[0228] Fig. 14(B) is a display device, which has a housing 5201, a display unit 5202, a support base 5203, etc. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 5202. Note that display devices include all information display devices for personal computers, TV broadcast reception, advertisement display, etc.

[0229] Fig. 14(C) is a notebook personal computer, which has a housing 5401, a display unit 540 2, a keyboard 5403, a pointing device 5404, etc. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 5402.

[0230] Fig. 14(D) is a portable information terminal, which has a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection part 5605, operation keys 5606, etc. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5 602. The first housing 5601 and the second housing 5602 are connected by the connection part 5 605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection part 5605. The video on the first display unit 5603 is transmitted through the connection part Switch according to the angle between the first housing 5601 and the second housing 5602 in 5605. This may be the configuration. The liquid crystal display device according to one aspect of the present invention can be used for the first display unit 5603 or the second display unit 5604. Note that a liquid crystal display device with a function as a position input device added to at least one of the first display unit 5603 and the second display unit 5604 can be used. Note that the function as a position input device can be added by providing a touch panel to the liquid crystal display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, to the pixel portion of the liquid crystal display device.

[0231] FIG. 14(E) is a video camera, which includes a first housing 5801, a second housing 5802, a display unit 5803, operation keys 5804, a lens 5805, a connection portion 5806, etc. The operation keys 5804 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by the connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. The switching of the video on the display unit 5803 may be performed according to the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806. The liquid crystal display device according to one aspect of the present invention can be used for the display unit 5803.

[0232] FIG. 14(F) is a mobile phone, and the housing 5901 is provided with a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection portion 5906, and operation buttons 5905. is provided. A liquid crystal display device according to an aspect of the present invention is used in a circuit of a mobile phone. This can be done. Further, when a liquid crystal display device according to an aspect of the present invention is formed on a flexible substrate, as shown in FIG. 14(F), the liquid crystal display device can be applied to a display unit 5902 having a curved surface.

[0233] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

Example

[0234] In this example, the transmittance of a liquid crystal display device, which is an aspect of the present invention, was measured. The liquid crystal display device used in this example will be described below with reference to FIG. 15.

[0235] The liquid crystal display device 720 shown in FIG. 15(A) is an example of a liquid crystal display device according to an aspect of the present invention.

[0236] The liquid crystal display device 720 shown in FIG. 15(A) includes a substrate 602, a conductive film 604 that functions as a gate of a transistor on the substrate 602, an insulating film 606 on the substrate 602 and the conductive film 604, an insulating film 606, an oxide semiconductor film 608 formed at a position overlapping the conductive film 604 on the insulating film 606, conductive films 610 and 612 connected to the oxide semiconductor film 608, an insulating film 614 formed on the insulating film 606, the oxide semiconductor film 608, and the conductive films 610 and 612, an insulating film 616 on the insulating film 614, a first common electrode 618 on the insulating film 616, an insulating film 620 on the insulating film 614 and the first common electrode 618, a pixel electrode 622 on the insulating film 620, an alignment film 624 on the insulating film 620 and the pixel electrode 622, and a liquid crystal layer 6 on the alignment film 624. ​​​​​50, an alignment film 640 on the liquid crystal layer 650, and a second common electrode 638 on the alignment film 640, an insulating film 636 on the second common electrode 638, a light-shielding film 632 and a colored film 6 34, and a substrate 630 on the light-shielding film 632 and the colored film 634.

[0237] Note that a transistor 712 is constituted by a conductive film 604, an insulating film 606, an oxide semiconductor film 608, and conductive films 610, 6 12. Further, the conductive film 612 of the transistor 712 is connected to the pixel electrode 6 22 through openings provided in the insulating film 616 and the insulating film 620.

[0238] Next, a description will be given of a comparative liquid crystal display device 730 shown in FIG. 15(B).

[0239] The liquid crystal display device 730 shown in FIG. 15(B) includes a substrate 602, a conductive film 604 that functions as a gate of a transistor on the substrate 602, an insulating film 60 6 on the substrate 602 and the conductive film 604, an insulating film 606, an oxide semiconductor film 608 formed at a position overlapping the conductive film 604 on the insulating film 606, conductive films 610, 612 connected to the oxide semiconductor film 608, and an insulating film 614 formed on the insulating film 606, the oxide semiconductor film 608, and the conductive films 610, 612, an insulating film 616 on the insulating film 614, a first common electrode 618 on the insulating film 616, an insulating film 620 on the insulating film 614 and the first common electrode 618, a pixel electrode 62 2 on the insulating film 620, an alignment film 624 on the insulating film 620 and the pixel electrode 622, a liquid crystal layer 6 50 on the alignment film 624, an alignment film 640 on the liquid crystal layer 650, an insulating film 636 on the alignment film 640, a light-shielding film 632 and a colored film 6 on the insulating film 6 36, and a substrate 63 on the light-shielding film 632 and the colored film 634. 22, an alignment film 640 on the insulating film 620 and the pixel electrode 622, a liquid crystal layer 6 50 on the alignment film 624, an alignment film 640 on the liquid crystal layer 650, an insulating film 636 on the alignment film 640, an insulating film 6 36, a light-shielding film 632 and a colored film 634 on the insulating film 636, and a substrate 63 ​​0 and an electrode 642 on the substrate 630.

[0240] Note that the conductive film 604, the insulating film 606, the oxide semiconductor film 608, the conductive films 610, and The transistor 712 is configured by the transistor 12. The conductive film 612 is connected to the pixel electrode 6 through openings provided in the insulating films 616 and 620. It is connected to 22.

[0241] 15A and 15B are diagrams illustrating a liquid crystal display device 720 according to one embodiment of the present invention. The difference between the comparative liquid crystal display device 730 and the comparative liquid crystal display device 730 is the second common electrode 638 and the electrode 642. More specifically, the liquid crystal display device 720 has a second common electrode 630 below the substrate 630. 638 is provided, and the liquid crystal display device 730 has an electrode 642 provided above the substrate 630. It is being used.

[0242] In the configuration shown in FIG. 15(A), the alignment film 640 is formed by the second common electrode 638. On the other hand, in the configuration shown in FIG. In this case, the electrode 642 is provided above the substrate 630, and therefore, Therefore, it is difficult to apply a voltage to the liquid crystal layer 650.

[0243] The manufacturing method of the liquid crystal display devices 720 and 730 shown in FIGS. 15(A) and 15(B) will be described below. In the liquid crystal display device 720 and the liquid crystal display device 730, the second common electrode 63 The structures are the same except for the electrode 642 and the electrode 8. First, the manufacturing method of the common structure will be described. The following is an explanation.

[0244] A glass substrate was used as the substrate 602. Then, a conductive film 604 was formed on the substrate 602. It was formed. As the conductive film 604, a tungsten film with a thickness of 200 nm was formed by sputtering method. After that, an insulating film 606 was formed on the substrate 602 and the conductive film 604. As the insulating film 60 6, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm were stacked and formed.

[0245] Note that the silicon nitride film had a three-layer stacked structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film.

[0246] As the first silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm and ammonia gas with a flow rate of 100 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus The pressure in the processing chamber was controlled to 100 Pa, and 2000 W of power was supplied using a high-frequency power source of 27.12 MHz to form a film with a thickness of 50 nm. As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus The pressure in the processing chamber was controlled to 100 Pa, and 2000 W of power was supplied using a 27.12 MHz high-frequency power source to form a film with a thickness of 300 nm. As the third silicon nitride film, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus, and the pressure in the processing chamber was controlled to 100 Pa and 2000 W of power was supplied using a 27.12 MHz high-frequency power source to form a film with a thickness of 50 nm. Note that the substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film was 350 °C.

[0247] As the silicon oxynitride film, silane with a flow rate of 20 sccm and nitrous oxide with a flow rate of 3000 sccm were supplied as raw material gases to the processing chamber of a plasma CVD apparatus, and the pressure in the processing chamber was controlled to 4 0 Pa, and 100 W of power was supplied using a 27.12 MHz high-frequency power supply to form a silicon oxynitride film. The substrate temperature during the formation of the silicon oxynitride film was 350 °C.

[0248] Next, an oxide semiconductor film 608 was formed at a position overlapping the conductive film 604 via the insulating film 606. Here, an oxide semiconductor film with a thickness of 35 nm was formed on the insulating film 614 by sputtering.

[0249] The oxide semiconductor film used a sputtering target with an In:Ga:Zn = 1:1:1 (atomic ratio), and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm were supplied as sputtering gases to the processing chamber of the sputtering apparatus. The pressure in the processing chamber was controlled to 0 .6 Pa, and 5 kW of DC power was supplied to form it. The substrate temperature during the formation of the oxide semiconductor film was 170 °C.

[0250] Next, conductive films 610 and 612 in contact with the oxide semiconductor film 608 were formed.

[0251] As the conductive films 610 and 612, an aluminum film with a thickness of 400 nm was formed on a tungsten film with a thickness of 50 nm, and a titanium film with a thickness of 100 nm was formed on the aluminum film.

[0252] Next, the substrate was moved to a depressurized processing chamber, heated at 350 °C, and then 150 W of high-frequency power was supplied to the upper electrode provided in the processing chamber using a 27.12 MHz high-frequency power supply. ​​​​​​​​​​The oxide semiconductor film 608 was exposed to oxygen plasma generated in a nitrogen dioxide atmosphere.

[0253] Next, an insulating film 614 was formed on the oxide semiconductor film 608 and the conductive films 610 and 612. Here, as the insulating film 614, a three-layer laminated structure of a first oxide insulating film, a second oxide insulating film, and a nitride insulating film was formed.

[0254] First, after the above oxygen plasma treatment, without exposing to the atmosphere, the first oxide insulating film and the second oxide insulating film were continuously formed. As the first oxide insulating film, a silicon oxynitride film with a thickness of 50 nm was formed, and as the second oxide insulating film, a silicon oxynitride film with a thickness of 400 nm was formed.

[0255] The first oxide insulating film was formed by plasma CVD using silane with a flow rate of 20 sccm and nitrous oxide with a flow rate of 3000 sccm as source gases, with the pressure in the processing chamber being 200 Pa, the substrate temperature being 350 °C, and 100 W of high-frequency power being supplied to the parallel plate electrodes.

[0256] The second oxide insulating film was formed by plasma CVD using silane with a flow rate of 160 sccm and nitrous oxide with a flow rate of 4000 sccm as source gases, with the pressure in the processing chamber being 200 Pa, the substrate temperature being 220 °C, and 150 0 W of high-frequency power being supplied to the parallel plate electrodes. Under these conditions it is possible to form a silicon oxynitride film that contains more oxygen than the stoichiometric composition and from which a part of the oxygen is desorbed by heating.

[0257] Next, a heat treatment was performed to desorb water, nitrogen, hydrogen, etc. from the first oxide insulating film and the second oxide insulating film, and at the same time, a part of the oxygen contained in the second oxide insulating film was transferred to the oxide semiconductor film 6 It was supplied to 08. Here, heat treatment was performed at 350 °C for 1 hour in a nitrogen and oxygen atmosphere. It was.

[0258] Next, a nitride insulating film with a thickness of 100 nm was formed on the second oxide insulating film. The nitride insulating film used silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 scc m as the source gas, the pressure in the processing chamber was 100 Pa, the substrate temperature was 350 °C, and 1000 W of high-frequency power was supplied to the parallel plate electrode and formed by plasma CVD method. It was.

[0259] Next, an opening reaching the conductive film 612 was formed in the insulating film 614. The opening was formed by dry etching method.

[0260] Next, an insulating film 616 having an opening was formed on the insulating film 614. As the insulating film 616, an acrylic resin which is an organic resin material was used. The film thickness of the acrylic resin was 2 μm. It was.

[0261] Next, a first common electrode 618 was formed on the insulating film 616. As the first common electrode 618, a conductive film of indium oxide-tin oxide compound (ITO-SiO2) with a thickness of 100 nm was formed by sputtering method. The composition of the target used for the conductive film was In 2O3:SnO2:SiO2 = 85:10:5 [wt%]. It was.

[0262] Next, an insulating film 620 was formed on the insulating film 616 and the first common electrode 618. As the insulating film 6 20, a nitride insulating film with a thickness of 300 nm was formed. The nitride insulating film had a flow rate of 50 s ccm of silane, a flow rate of 5000 sccm of nitrogen, and a flow rate of 100 sccm of ammonia gas S was used as the source gas, the pressure in the processing chamber was 200 Pa, the substrate temperature was 220 °C, and 1000 W of high-frequency power was supplied to the parallel plate electrode to form by plasma CVD method.

[0263] Next, the pixel electrode 622 was formed on the insulating film 620. As the pixel electrode 622, sputtering was used to form a conductive film of indium oxide-tin oxide compound (ITO-SiO2) with a thickness of 80 nm. The composition of the target used for the conductive film was the same as that of the first common electrode 61 8. After that, heat treatment was performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0264] Next, the alignment film 624 was formed on the insulating film 620 and the pixel electrode 622. As the alignment film 624 a polyimide film with a thickness of 60 nm was used. The resistivity of the polyimide film used as the alignment film 624 was 4.0×10 Ω·cm. 15

[0265] The structure formed on the substrate 602 was fabricated through the above steps.

[0266] Next, the manufacturing method of the structure formed on the substrate 630 provided facing the substrate 602 will be described. The structure formed on the substrate 630 is different between the liquid crystal display device 720 shown in FIG. 15(A) and the liquid crystal display device 730 shown in FIG. 15(B). Therefore, in the following description, the manufacturing methods will be separately described for the liquid crystal display device 720 and the liquid crystal display device 730. Also, the liquid crystal display device 720 will be regarded as sample 1, and the liquid crystal display device 730 will be regarded as sample 2 and explanations will be given respectively.

[0267] <Manufacturing method of the structure formed on the substrate 630 shown in FIG. 15(A)> ​As the substrate 630, a glass substrate was used. Next, a light-shielding film 632 was formed in a desired region in contact with the substrate 630. As the light-shielding film 632, an organic resin film containing a black pigment with a thickness of 600 nm was used by the spin coating method.

[0268] Next, a colored film 634 was formed in contact with the substrate 630. As the colored film 634, an organic resin film with a thickness of 1.4 μm containing a pigment was used by the spin coating method.

[0269] Next, an insulating film 636 was formed in contact with the light-shielding film 632 and the colored film 634. As the insulating film 636, an acrylic resin with a thickness of 1.5 μm was used.

[0270] Next, a second common electrode 638 was formed in contact with the insulating film 636. The second common electrode 638 was formed by a sputtering method to form a conductive film of indium oxide-tin oxide compound (ITO-SiO2) with a thickness of 100 nm. The composition of the target used for the conductive film was the same as that of the first common electrode 618.

[0271] Next, an alignment film 640 was formed in contact with the second common electrode 638. As the alignment film 640, the same material as the alignment film 624 was used.

[0272] Next, the fabricated substrate 630 and the substrate 602 described above were bonded together, and a liquid crystal material that functions as a liquid crystal layer 650 was injected using the drop-sealing method.

[0273] As the liquid crystal layer 650, the cell gap (the distance between the alignment film 624 and the alignment film 640) was adjusted to be 3.5 μm, and a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006) was used.

[0274] In the above process, Sample 1, which is a liquid crystal display device according to one aspect of the present invention shown in FIG. 15(A), was fabricated. This was done.

[0275] <Method for fabricating the structure formed on the substrate 630 shown in FIG. 15(B)> As the substrate 630, a glass substrate was used. Next, a light-shielding film 632 was formed in a desired region in contact with the substrate 630. As the light-shielding film 632, an organic resin film containing a black pigment with a thickness of 600 nm was used by the spin coating method. This was done.

[0276] Next, a colored film 634 was formed in contact with the substrate 630. As the colored film 634, an organic resin film with a thickness of 1.4 μm containing a pigment was used by the spin coating method. This was done.

[0277] Next, an insulating film 636 was formed in contact with the light-shielding film 632 and the colored film 634. As the insulating film 636, an acrylic resin with a thickness of 1.5 μm was used. This was done.

[0278] Next, an electrode 642 was formed in contact with the substrate 630 on the surface where the insulating film 636 was not formed. As the electrode 642, a conductive film of indium oxide - tin oxide compound (ITO - SiO2) with a thickness of 100 nm was formed by the sputtering method. Note that the composition of the target used for the conductive film was the same as that of the first common electrode 618. This was done. This was done. This was done.

[0279] Next, an alignment film 640 was formed in contact with the insulating film 636. As the alignment film 640, the same material as the alignment film 624 was used. This was done.

[0280] Next, the fabricated substrate 630 was bonded to the substrate 602 described above, and a liquid crystal material that functions as the liquid crystal layer 650 was injected using the droplet sealing method. This was done.

[0281] As the liquid crystal layer 650, the cell gap (distance between the alignment films 624 and 640) was adjusted to be 3. 5 μm, and a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006) was used.

[0282] In the above process, Sample 2, which is a comparative liquid crystal display device shown in FIG. 15(B), was fabricated.

[0283] Next, the transmittance of the fabricated Sample 1 and Sample 2 was measured. When measuring the transmittance of Sample 1 0 V was applied to the first common electrode 618, 5.5 V was applied to the pixel electrode 622, and 0.8 V was applied to the second common electrode 638, respectively. Also, the voltages applied to the pixel electrode 622, the second common electrode 63 8, and the second common electrode 638 were applied intermittently, and data rewriting was performed every time a voltage was applied . Also, when measuring the transmittance of Sample 2, 0 V was applied to the first common electrode 618, 5.5 V was applied to the pixel electrode 622, and 0.8 V was applied to the electrode 642, respectively . Also, the voltages applied to the pixel electrode 622, the second common electrode 638, and the electrode 642 were applied intermittently, and data rewriting was performed every time a voltage was applied. Note that the control of data rewriting for Sample 1 and Sample 2 is performed by the transistor 712 formed in the liquid crystal display device .

[0284] The results of the time-transmittance characteristics of Sample 1 and Sample 2 are shown in FIGS. 16 to 20. In FIGS. 16 to 20, the horizontal axis represents time (s), and the vertical axis represents transmittance (%). Also , in FIGS. 16 to 20, the results are those of the time-transmittance characteristics when set to the maximum gradation (when the transmittance becomes 100%). Also, FIG. 21 shows the results of the time-trans mittance characteristics of Sample 1. In FIG. 21, the horizontal axis represents time (s), and the vertical axis represents transmittance (%. ). ) are each represented. Also, in FIG. 21, the result of the time-transmittance characteristic when it is set to an intermediate gradation (when the transmittance is set to 50%) is shown. Note that when it is set to an intermediate gradation , the result of the time-transmittance characteristic may be different from that when it is set to the maximum gradation.

[0285] Note that the time-transmittance characteristics shown in FIGS. 16(A), 17(A), 18(A), 19(A), and 20(A) are the results of sample 1 which is one aspect of the present invention, and FIGS. 16(B), 17(B), 18(B), 19(B), and 20(B) are the results of comparative sample 2.

[0286] Also, in the time-transmittance characteristics shown in FIGS. 16(A) and (B), data rewriting is performed once every 1 sec, and in the time-transmittance characteristics shown in FIGS. 17(A) and (B), data rewriting is performed once every 5 sec. In the time-transmittance characteristics shown in FIGS. 18(A) and (B), data rewriting is performed once every 15 sec. In the time-transmittance characteristics shown in FIGS. 19(A ) and (B), data rewriting is performed once every 30 sec. In the time-transmittance characteristics shown in FIGS. 20(A) and (B), data rewriting is performed once every 60 sec. Note that in graphs with the same data rewriting interval, the timing of data rewriting is performed at different times. Therefore, in the time-transmittance characteristics shown in FIGS. 16 to 2 0, the timing of rewriting is not the same time.

[0287] Also, in the time-transmittance characteristics shown in FIG. 21(A), data rewriting is performed once every 1 sec, and in the time-transmittance characteristics shown in FIG. 21(B), data rewriting is performed once every 5 sec. has rewritten the data, and in the time-transmittance characteristics shown in Fig. 21(C), 6 rewrites the data once every 0 sec.

[0288] From the results of Figs. 16 to 20, it can be seen that Sample 1, which is one aspect of the present invention, has little variation in transmittance over time. On the other hand, for the comparative Sample 2, the transmittance varies greatly over time. In particular, when the data rewrite interval is long, for example, in the case of rewriting the data once every 60 sec as shown in Fig. 20(B), a variation in transmittance of 3% or more is confirmed. This suggests that Sample 1, which is one aspect of the present invention, can suppress the variation in the transmittance of the liquid crystal layer 650 by applying a voltage to the second common electrode 638. On the other hand, for the comparative Sample 2, the second common electrode 638 is not provided, and an electrode 642 located above the substrate 630 is given the same potential as the second common electrode 638. Therefore, no potential is applied from the electrode 642 to the liquid crystal layer 650, and the variation in the liquid crystal layer 650 cannot be suppressed. Moreover, from the results shown in Fig. 21, Sample 1, which is one aspect of the present invention, has a transmittance variation of about 2% with data rewriting once every 5 sec. This suggests that, depending on the display image, it may be recognized as flickering, so it is better to rewrite the data in less than 5 sec.

Example

[0289]

[0290]

[0291] ​​​​​​​​​​​The liquid crystal display device used in the calculation shown in FIG. 22(A) includes a substrate 802 and electrodes on the substrate 802 804a, 804b, 854a, 854b, an insulating film 814 that covers the electrodes 804a, 804b and covers the ends of the electrodes 854a, 854b, an insulating film 821 on the insulating film 814 and the electrodes 854a, 85 4b, an insulating film 856 on the insulating film 821, and a pixel electrode 822a provided at a position overlapping with the electrode 854a through the insulating films 821, 856 and a pixel electrode 822b provided at a position overlapping with the electrode 854b through the insulating films 821, 85 6, a liquid crystal layer 850 on the insulating film 856 and the pixel electrodes 822a, 822b, an electrode 838 on the liquid crystal layer 850, and a substrate 830 on the electrode 838. It has such a configuration.

[0292] Note that the configuration of the liquid crystal display device used in the calculation shown in FIG. 22(A) simplifies the pixels of the liquid crystal display device according to one aspect of the present invention shown in FIGS. 10 and 11 and is used to simplify the calculation. Specifically, the substrate 802 corresponds to the substrate 302 shown in FIG. 11, the electrodes 804a , 804b correspond to the conductive films 304 shown in FIG. 11, the electrodes 854a, 854b correspond to the electrodes 354 shown in FIG. 11, the insulating film 814 corresponds to the insulating film 314 shown in FIG. 11, and the insulating film 82 1 corresponds to the insulating film 321 shown in FIG. 11, the pixel electrodes 822a, 822b correspond to the pixel electrodes 322 shown in FIG. 11, the liquid crystal layer 850 corresponds to the liquid crystal layer 350 shown in FIG. 11, the electrode 838 corresponds to the second common electrode 338 shown in FIG. 11, and the substrate 830 corresponds to the substrate 330 shown in FIG. 11. Note that the insulating film 856 shown in FIG. 22(A) is not shown in FIG. 11.

[0293] Also, the liquid crystal display device used in the calculation shown in FIG. 22(B) is used in the calculation shown in FIG. 22(A). ​​​​The structure of the liquid crystal display device is such that the electrode 838 on the liquid crystal layer 850 is not provided, and the structure other than that is the same as that shown in Fig. 22(A). The structure outside is the same as that in Fig. 22(A).

[0294] In the structure of the liquid crystal display device used in the calculations shown in Figs. 22(A) and (B), the cross-sectional structure of two pixels is shown. The left side in the figure, more specifically, the side including the electrode 804a, the electrode 854a, and the pixel electrode 822a is represented as one pixel, and the right side in the figure, more specifically, the side including the electrode 804b, the electrode 854b, and the pixel electrode 822b is represented as the other pixel. Also, in Figs. 22(A) and (B), the pixel electrodes 822a and 822b are each represented as one electrode by combining three separated electrodes. In addition, in Figs. 22(A) and (B), the pixel electrodes 822a and 822b are each separated and three electrodes are represented as one electrode.

[0295] Also, the structure of the liquid crystal display device used in the calculation shown in Fig. 22(A) was taken as Sample 3, and the structure of the liquid crystal display device used in the calculation shown in Fig. 22(B ) was taken as Sample 4. Note that Sample 3 is the structure of a liquid crystal display device according to one aspect of the present invention, and Sample 4 is the structure of a liquid crystal display device according to one aspect for comparison.

[0296] Also, the electrodes 804a and 804b shown in Figs. 22(A) and (B) were set to have a thickness of 200 nm and a width of 2 μm, the electrodes 854a and 854b were set to have a thickness of 200 nm and a width of 20 μm, the insulating film 814 was set to have a thickness of 500 nm, the insulating film 821 was set to have a thickness of 100 nm, the insulating film 856 was set to have a thickness of 400 nm, the pixel electrodes 822a and 822b were set to have a thickness of 100 nm and a width of 2 μm, the liquid crystal layer 850 was set to have a thickness of 4 μm and a negative-type liquid crystal material (manufactured by Merck KGaA: MLC-3006), and the electrode 838 shown in Fig. 22(A) was set to have a thickness of 100 nm.

[0297] Also, with respect to the configuration of the liquid crystal display device used in the calculation shown in Fig. 22(A), to the electrode 804a 0V, to the electrode 804b 6V, to the electrodes 854a, 854b 0V, to the pixel electrode 822a 0V, to the pixel electrode 822b 6V, and to the electrode 838 0V were respectively applied, and the transmittance of the liquid crystal layer 8 50 was calculated.

[0298] Also, with respect to the configuration of the liquid crystal display device used in the calculation shown in Fig. 22(B), to the electrode 804a 0V, to the electrode 804b 6V, to the electrodes 854a, 854b 0V, to the pixel electrode 822a 0V, to the pixel electrode 822b 6V were respectively applied, and the transmittance of the liquid crystal layer 850 was calculated [[ID=1 / / 5]] was performed. Note that the settings for each of the above electrodes, in both Figs. 22(A) and (B), assumed that the left pixel in the figure was black display and the right pixel in the figure was white display, and the applied voltage is as such.

[0299] Fig. 23 shows the calculation results of the transmittance. Note that for the calculation of the transmittance, LCD Master (manufactured by Shintech) was used as the calculation software.

[0300] In Fig. 23, the horizontal axis represents the position (μm) and the vertical axis represents the transmittance (%). Also, in Fig. 23, the solid line represents Sample 3 and the dashed line represents Sample 4. Also , in Fig. 23, to represent the positions of the electrodes 804a, 804b, 854a, 8 54b shown in Figs. 22(A) and (B), the shapes of the electrodes 804a, 804b, 854a, 854b are schematically represented by a gray solid line .

[0301] From the calculation results shown in Fig. 23, it can be seen that Sample 3, which is a configuration of one aspect of the present invention, has a low transmittance in the vicinity of positions 20 to 30 μ m. On the other hand, Sample 4 of one aspect for comparison has positions 20 to 30 It can be seen that the transmittance is high near μ. This is because Sample 3 has the electrode 838 above the liquid crystal layer 850 as compared with Sample 4 , suggesting that the voltage applied to the electrode 838 (0 V in this embodiment ) suppresses the increase in transmittance near the position of 20 to 30 μm. Also , it can be confirmed that the transmittance of Sample 3 is higher than that of Sample 4 near the position of 40 to 50 μm . In FIG. 23, in the left pixels represented by the positions of 0 to 25 μm, since the voltage of each electrode is set to 0 V, it is desirable to have a black display, that is, a low transmittance. Also, in the right pixels represented by the positions of 26 μ to 55 μm , since 6 V is applied to the electrode 804b and the electrode 854b respectively , it is desirable to have a white display, that is, a high transmittance. Therefore, Sample 3 having the configuration of one aspect of the present invention has a configuration having the electrode 838 above the liquid crystal layer 850 as compared with Sample 4 having a configuration of one aspect for comparison , and it could be confirmed by calculation that it has excellent transmittance characteristics .

[0302] As described above, the liquid crystal display device having the configuration of one aspect of the present invention suggests that it can be a liquid crystal display device with excellent contrast between white display and black display in adjacent pixels . .

[0303] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments or the configuration shown in other examples .

Explanation of reference numerals

[0304] 100 Pixel 102 Transistor 111 Liquid crystal element 111a Liquid crystal element 111b Liquid crystal element 111c Liquid crystal element 112 Transistor 113 Capacitive element 120 Substrate 122 Common electrode 124 Insulating layer 126 Pixel electrode 130 Substrate 132 Common electrode 134 Liquid crystal layer 230 Panel 231 Pixel section 232 Driving circuit 233 Driving circuit 240 Liquid crystal display device 241 Controller 242 Input device 243 CPU 244 Image processing circuit 245 Image memory 246 Data 247 Power supply circuit 302 Substrate 304 Conductive film 306 Insulating film 307 Oxide semiconductor film 308 Oxide semiconductor film 309 Oxide semiconductor film 310 Conductive film 312 Conductive film 313 Conductive film 314 Insulating film 316 Insulating film 318 Common electrode 320 Insulating film 321 Insulating film 322 Pixel electrode 324 Alignment film 330 Substrate 332 Light-shielding film 334 Colored film 336 Insulating film 338 Common electrode 340 Alignment film 350 Liquid crystal layer 352 Oxide semiconductor film 354 Electrode 360 Opening 362 Opening 364 Opening 366 Opening 602 Substrate 604 Conductive Film 606 Insulating Film 608 Oxide Semiconductor Film 610 Conductive Film 612 Conductive Film 614 Insulating Film 616 Insulating Film 618 Common Electrode 620 Insulating Film 622 Pixel Electrode 624 Alignment Film 630 Substrate 632 Light-Shielding Film 634 Colored Film 636 Insulating Film 638 Common Electrode 640 Alignment Film 642 Electrode 650 Liquid Crystal Layer 712 Transistor 720 Liquid Crystal Display Device 730 Liquid Crystal Display Device 802 Substrate 804a Electrode 804b Electrode 814 Insulating Film 821 Insulating Film 822a Pixel Electrode 822b Pixel Electrode 830 Substrate 838 Electrode 850 Liquid Crystal Layer 854a Electrode 854b Electrode 856 Insulating Film 5001 Housing 5002 Housing 5003 Display Unit 5004 Display Unit 5005 Microphone 5006 Speaker 5007 Operation Key 5008 Stylus 5201 Housing 5202 Display Unit 5203 Support Stand 5401 Housing 5402 Display Unit 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display Unit 5604 Display Unit 5605 Connection Port 5606 Operation Key 5801 Housing 5802 Housing 5803 Display Unit 5804 Operation Key 5805 Lens 5806 Connection Port 5901 Housing 5902 Display Unit 5903 Camera 5904 Speaker 5905 Button 5906 External Connection Port 5907 Microphone

Claims

1. A display device having a pixel including a transistor and a capacitive element, having a first conductive film having a region that functions as a gate electrode of the transistor, having a first insulating film located on the first conductive film and having a region that functions as a gate insulating film of the transistor, having a first oxide semiconductor film located on the first insulating film and having a channel formation region of the transistor, having a second conductive film having a region in contact with the upper surface of the first oxide semiconductor film and having a region that functions as one of a source electrode or a drain electrode of the transistor, having a third conductive film having a region in contact with the upper surface of the first oxide semiconductor film and having a region that functions as the other of the source electrode or the drain electrode of the transistor, having a silicon oxide film having a region in contact with the upper surface of the first oxide semiconductor film and a region overlapping with the channel formation region, having a second insulating film having a region in contact with the upper surface of the silicon oxide film, having a fourth conductive film having a region in contact with the upper surface of the second insulating film, a region in contact with the upper surface of the second conductive film, and functioning as a pixel electrode, having a second oxide semiconductor film having a region that functions as a first electrode of the capacitive element, having the second insulating film having a first region in contact with the upper surface of the second oxide semiconductor film, wherein the second oxide semiconductor film does not overlap with the silicon oxide film in the first region, having the fourth conductive film having a region overlapping with the second oxide semiconductor film via the second insulating film and having a region that functions as a second electrode of the capacitive element, having a fifth conductive film having a region in contact with the upper surface of the second oxide semiconductor film, wherein the second conductive film has a region in contact with the upper surface of the first insulating film, wherein the third conductive film has a region in contact with the upper surface of the first insulating film, in plan view, the second oxide semiconductor film has a larger area than the first oxide semiconductor film, the first oxide semiconductor film and the second oxide semiconductor film have a region in contact with the upper surface of the first insulating film, the silicon oxide film has a region in contact with the upper surface of the first insulating film, the first conductive film contains at least one of copper, titanium, and molybdenum, the second conductive film and the third conductive film contain at least one of copper, titanium, and molybdenum, The display device having the first oxide semiconductor film and the second oxide semiconductor film has In, Ga, and Zn.

2. A display device having pixels each including a transistor and a capacitor element, having a first conductive film having a region that functions as a gate electrode of the transistor, having a first insulating film that is located on the first conductive film and has a region that functions as a gate insulating film of the transistor, having a first oxide semiconductor film that is located on the first insulating film and has a channel formation region of the transistor, having a second conductive film that has a region in contact with the upper surface of the first oxide semiconductor film and has a region that functions as one of a source electrode or a drain electrode of the transistor, having a third conductive film that has a region in contact with the upper surface of the first oxide semiconductor film and has a region that functions as the other of the source electrode or the drain electrode of the transistor, having a silicon oxide film having a region in contact with the upper surface of the first oxide semiconductor film and a region overlapping with the channel formation region, having a second insulating film having a region in contact with the upper surface of the silicon oxide film, having a fourth conductive film that has a region in contact with the upper surface of the second insulating film, a region in contact with the upper surface of the second conductive film, and functions as a pixel electrode, having a second oxide semiconductor film having a region that functions as a first electrode of the capacitor element, having the second insulating film having a first region in contact with the upper surface of the second oxide semiconductor film, wherein the second oxide semiconductor film does not overlap with the silicon oxide film in the first region, having a fourth conductive film that has a region overlapping with the second oxide semiconductor film via the second insulating film and has a region that functions as a second electrode of the capacitor element, having a fifth conductive film having a region in contact with the upper surface of the second oxide semiconductor film, wherein the second conductive film has a region in contact with the upper surface of the first insulating film, wherein the third conductive film has a region in contact with the upper surface of the first insulating film, in plan view, the area of the second oxide semiconductor film is larger than that of the first oxide semiconductor film, wherein the first oxide semiconductor film and the second oxide semiconductor film have a region in contact with the upper surface of the first insulating film, wherein the silicon oxide film has a region in contact with the upper surface of the first insulating film, wherein the first conductive film contains at least one of copper, titanium, and molybdenum, The second conductive film and the third conductive film have at least one of copper, titanium, and molybdenum. The display device in which the first oxide semiconductor film and the second oxide semiconductor film have indium oxide.

3. An electronic device including the display device according to claim 1 or 2.

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