Semiconductor device

Abstract

To propose a storage device capable of enhancing storage capacity per unit area while ensuring a data retention period.SOLUTION: A storage device includes: a storage element; a transistor including an oxide semiconductor in an active layer for controlling accumulation, retention, and release of charges in the storage element; and a capacitive element connected to the storage element. At least one of a pair of electrodes of the capacitive element has light-blocking properties. In addition, the storage device has a conduction film or an insulation film having light-blocking properties. The active layer is located between the electrode having light-blocking properties and the conduction film or the insulation film having light-blocking properties.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory device and a semiconductor device using the memory device.

Background Art

[0002] In recent years, as a new semiconductor material having both high mobility obtained by polysilicon or microcrystalline silicon and uniform device characteristics obtained by amorphous silicon, metal oxides exhibiting semiconductor characteristics, called oxide semiconductors, have attracted attention. Metal oxides are used in various applications. For example, indium oxide, which is a well-known metal oxide, is used as a transparent electrode material in liquid crystal display devices and the like. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Insulated gate field effect transistors (hereinafter simply referred to as transistors) using such metal oxides exhibiting semiconductor characteristics in a channel formation region are already known.

[0003] 00000560000057000005800000590000060000006100000620000063000006400000650000066

Prior Art Documents

Patent Documents

[0004] Patent Document 1 Japanese Patent Application Laid-Open No. 2010-021520 Patent Document 2 Japanese Patent Application Laid-Open No. 2009-277701 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] In the case of a semiconductor memory device (hereinafter simply referred to as a memory device) using a transistor including the above oxide semiconductor in a channel formation region, the threshold voltage of the transistor shifts, or the off-current increases, so that the charge to be held in the memory element is easily released, and the period during which data can be held tends to be shortened. Therefore, in order to ensure a longer period during which accurate data is held in the memory device, it is important to prevent deterioration of the characteristics of the transistor due to light irradiation.

[0006] In addition, the smaller the area occupied by each memory cell in the memory device, the higher the storage capacity per unit area can be increased. However, when the area occupied by the memory cell is reduced, the exclusive area of the capacitive element provided in each memory cell for holding the charge of the memory element also has to be reduced. Therefore, it becomes difficult for the capacitive element to secure a capacitance value large enough to hold data in the memory device for a long period.

[0007] In view of the above problems, an object of the present invention is to propose a memory device capable of increasing the storage capacity per unit area while ensuring a period for holding data. Alternatively, an object of the present invention is to propose a semiconductor device using the above memory device. MEANS FOR SOLVING THE PROBLEMS

[0008] ​​​​​​​​ A memory device according to one aspect of the present invention includes a transistor that functions as a memory element, and a transistor including an oxide semiconductor in an active layer for controlling the accumulation, retention, and release of charges in the memory element. And a capacitor element connected to the memory element. Alternatively, a memory device according to one aspect of the present invention includes a capacitor element that functions as a memory element, and a transistor including an oxide semiconductor in a channel formation region for controlling the accumulation, retention, and release of charges in the memory element. And has. And at least one of a pair of electrodes included in the capacitor element has a light-shielding property. Further, a memory device according to one aspect of the present invention has a light-shielding layer such as a light-shielding conductive film or insulating film, and is characterized in that it is located between an electrode having a light-shielding property and the light-shielding layer and the active layer.

[0009] The active layer of the transistor that functions as a memory element may also contain an oxide semiconductor.

[0010]

[0011] The oxide semiconductor has a band gap approximately three times that of silicon and a lower intrinsic carrier density than silicon. By including a semiconductor material having the above-described characteristics in the channel formation region, a transistor with an extremely low off-current can be realized. By using the transistor having the above configuration as a switching element for holding the charges accumulated in the memory element, leakage of charges from the memory element can be prevented.

[0012] The oxide semiconductor has a mobility as high as that obtained by microcrystalline silicon or polycrystalline silicon and uniform device characteristics obtained by amorphous silicon. Semiconductor. It is a metal oxide that exhibits conductive properties. And water or hydrogen acts as an electron donor. The oxide semiconductor (purified oxide) is highly purified by reducing impurities such as The oxide semiconductor (i-type) is an i-type (intrinsic semiconductor) or is very close to i-type. A transistor using a compound semiconductor has a characteristic of having a significantly low off-state current. The oxide semiconductor with high purity and reduced oxygen vacancies was analyzed by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry The degree measurement is 5 x 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 More information below: Preferably 5 x 10 17 / cm 3 or less, more preferably 1 × 10 16 / cm 3 The following The carrier density of the oxide semiconductor film, which can be measured by Hall effect measurement, is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 1 1 / cm 3 The band gap of the oxide semiconductor is preferably 2 eV or more. is 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film in which oxygen vacancies are reduced, the oxide semiconductor film is highly purified by sufficiently reducing the amount of oxygen. As a result, the off-state current and leakage current of the transistor can be reduced.

[0013] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The measurement of the hydrogen concentration in the conductive film is performed by SIMS. In principle, SIMS has difficulty accurately obtaining data in the vicinity of the sample surface and in the vicinity of the laminated interface with films of different materials. Therefore, when analyzing the thickness-direction distribution of the hydrogen concentration in the film by SIMS, in the range where the film to be measured exists, the average value in the region where there are no extreme fluctuations in the value and a substantially constant value can be obtained is adopted as the hydrogen concentration. Also, when the thickness of the film to be measured is small, it may be impossible to find a region where a substantially constant value can be obtained due to the influence of the hydrogen concentration in the adjacent film. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is adopted as the hydrogen concentration in the film. Furthermore, when there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value in the region where the film exists, the value of the inflection point is adopted as the hydrogen concentration. Specifically, it can be proven by various experiments that the off-current of a transistor using an oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer is low. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current (the drain current when the voltage between the gate electrode and the source electrode is 0 V or less) is below the measurement limit of the semiconductor parameter analyzer, that is, it can obtain a characteristic of 1×10 A or less. In this case, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, a capacitive element and a transistor (gate insulator

[0014] Specifically, the fact that the off-current of a transistor using an oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer is low can be proven by various experiments. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current (the drain current when the voltage between the gate electrode and the source electrode is 0 V or less) is below the measurement limit of the semiconductor parameter analyzer, that is, μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current (the drain current when the voltage between the gate electrode and the source electrode is 0 V or less) is below the measurement limit of the semiconductor parameter analyzer, that is, 6 μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current (the drain current when the voltage between the gate electrode and the source electrode is 0 V or less) is below the measurement limit of the semiconductor parameter analyzer, that is, electrode voltage) is from 1 V to 10 V, the off-current (the drain current when the voltage between the gate electrode and the source electrode is 0 V or less) is below the measurement limit of the semiconductor parameter analyzer, that is, and the drain current) is below the measurement limit of the semiconductor parameter analyzer, that is, A or less. -13 A or less. In this case, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, a capacitive element and a transistor (gate insulator The thickness of the insulating film is 100 nm), and the circuit that controls the charge flowing into or out of the capacitive element by the transistor is used. In the experiment, when an oxide semiconductor film with high purity and reduced oxygen deficiency is used in the channel formation region as the transistor, the off-current density of the transistor is measured from the transition of the charge amount per unit time of the capacitive element. When the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is found that an even lower off-current density of 10 zA / μm to 100 zA / μm can be obtained. In the experiment using a circuit that controls the charge flowing into or out of the capacitive element by the transistor, when an oxide semiconductor film with high purity and reduced oxygen deficiency is used in the channel formation region as the transistor, the off-current density of the transistor is measured from the transition of the charge amount per unit time of the capacitive element. When the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is found that an even lower off-current density of 10 zA / μm to 100 zA / μm can be obtained. When the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is found that an even lower off-current density of 10 zA / μm to 100 zA / μm can be obtained. Therefore, in the semiconductor device according to one aspect of the present invention, the off-current density of the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer can be 10 zA / μm or less, preferably 1 zA / μm or less, more preferably 1 yA / μm or less, depending on the voltage between the source electrode and the drain electrode. Therefore, the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer has an off-current that is significantly lower than that of the transistor using crystalline silicon. more preferably 1 yA / μm or less, depending on the voltage between the source electrode and the drain electrode. Therefore, the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer has an off-current that is significantly lower than that of the transistor using crystalline silicon. more preferably 1 yA / μm or less, depending on the voltage between the source electrode and the drain electrode. Therefore, the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer has an off-current that is significantly lower than that of the transistor using crystalline silicon. more preferably 1 yA / μm or less, depending on the voltage between the source electrode and the drain electrode. Therefore, the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer has an off-current that is significantly lower than that of the transistor using crystalline silicon. more preferably 1 yA / μm or less, depending on the voltage between the source electrode and the drain electrode. Therefore, the transistor using the oxide semiconductor film with high purity and reduced oxygen deficiency as the active layer has an off-current that is significantly lower than that of the transistor using crystalline silicon.

[0015] The oxide semiconductor is a quaternary metal oxide such as In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide such as In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn-O-based oxide semiconductor, a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg- O-based oxide semiconductor, or a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg- O-based oxide semiconductor, or a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg- O-based oxide semiconductor, or a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg- O-based oxide semiconductor, or a binary metal oxide such as In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg- -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, and , In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. can be used. In this specification, for example, an In-Sn-Ga-Zn-O-based oxide semiconductor means a metal oxide containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn), and its stoichiometric composition ratio is not particularly limited. Also, the above oxide semiconductor may contain silicon.

[0016] Alternatively, the oxide semiconductor can be represented by the chemical formula InMO3(ZnO) m (m > 0, m is a natural number and is not limited). Here, M represents one or more metal elements selected from Zn, Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc.

Advantages of the Invention

[0017] In one aspect of the present invention, a transistor including an oxide semiconductor in the active layer is used as a switching element for controlling the charge retention in a memory element, thereby preventing the leakage of charges from the memory element. Also, by sandwiching the above active layer with an electrode, a conductive film, and an insulating film having light-shielding properties, it is possible to prevent the characteristics of the above transistor from deteriorating due to light. Specifically, it is possible to suppress the shift of the threshold voltage and prevent the increase of the off-current. Furthermore, in one aspect of the present invention, the above electrode having light-shielding properties is used as an electrode of a capacitive element. Thus, since the capacitive element and the transistor are arranged in the memory cell so as to overlap, the capacitive element While securing the exclusive area or the capacity value, it is possible to reduce the area occupied by the memory cell. It can be done.

[0018] Therefore, the memory device according to one aspect of the present invention can increase the storage capacity per unit area while securing the period for holding data. Alternatively, the present invention can improve the reliability and enhance the functionality of the semiconductor device by using the memory device in the semiconductor device. That is, by using the above memory device in a semiconductor device, the reliability of the semiconductor device can be improved and its functionality can be enhanced.

Brief Description of the Drawings

[0019]

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Mode for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0021] Note that all kinds of semiconductor devices that can use a storage device, such as integrated circuits such as a microprocessor and an image processing circuit, an RF tag, a storage medium, and a semiconductor display device, are included in the scope of the present invention. Further, semiconductor display devices include liquid crystal display devices, light-emitting devices having a light-emitting element such as an organic light-emitting element (OLED) provided in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc., and semiconductor display devices having a circuit element using a semiconductor film in a pixel portion or a driving circuit are included in the scope thereof.

[0022] (Embodiment 1) In FIG. 1(A), the configuration of a memory cell of a storage device according to an aspect of the present invention is shown as a circuit diagram by way of example. In the circuit diagram shown in FIG. 1(A), a memory cell 101 includes a transistor 102 that functions as a memory element, a transistor 103 that functions as a switching element, and a capacitive element ​​ It has 104. The transistor 102 that functions as a memory element stores data by accumulating charges in the gate capacitance formed between the gate electrode and the active layer.

[0023] The memory cell 101 may further have other circuit elements such as transistors, diodes, resistive elements, capacitive elements, inductance, etc., as necessary.

[0024] Note that the source electrode and the drain electrode of the transistor change their names depending on the polarity of the transistor and the potential difference applied to each electrode. Generally, in an n-channel type transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the drain electrode. Also, in a p-channel type transistor, the electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. Hereinafter, either one of the source electrode and the drain electrode is referred to as the first terminal, and the other is referred to as the second terminal, and the connection relationship of the transistor 102, the transistor 103, and the capacitive element 104 included in the memory cell 101 will be described.

[0025] In the memory cell 101 shown in FIG. 1(A), the potential of a signal including data is applied to the node connected to the first terminal of the transistor 103. Also, the second terminal of the transistor 103 is connected to the gate electrode of the transistor 102. One pair of electrodes of the capacitive element 104 is connected to the gate electrode of the transistor 102, and the other is connected to the node to which a predetermined potential is applied.

[0026] Also, FIG. 1(B) shows, as an example, the configuration of a memory cell different from that in FIG. 1(A) in a circuit diagram.​​​​​​​​​​​​​ In the circuit diagram shown in FIG. 1(B), the memory cell 101 includes a capacitor element 105 that functions as a storage element and a transistor 103 that functions as a switching element. Data is stored by accumulating charge in the capacitor element 105 that functions as a storage element. In the memory cell 101 shown in FIG. 1(B), the potential of a signal containing data is applied to a node connected to the first terminal of the transistor 103. One of the pair of electrodes of the capacitor element 105 is connected to the second terminal of the transistor 103, and the other is connected to a node to which a predetermined potential is applied.

[0027]

[0028] In this specification, "connection" means electrical connection, which corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily mean a directly continuous state, but also includes an indirectly connected state via circuit elements such as wiring, resistors, diodes, and transistors so that current, voltage, or potential can be supplied or transmitted.

[0029] Also, even if components that are independent on the circuit diagram are connected, actually, for example, when a part of the wiring functions as an electrode, there may be a case where a single conductive film has the functions of a plurality of components. In this specification, "connection" includes such a case where a single conductive film has the functions of a plurality of components.

[0030] In one aspect of the present invention, as the switching element shown in FIG. 1(A) or FIG. 1(B), ​​​​​​​​​​​​In the channel formation region of the functioning transistor 103, it includes an oxide semiconductor having a wider bandgap and a lower intrinsic carrier density than a silicon semiconductor, which is characterized by that. By including an oxide semiconductor having the characteristics as described above in the channel formation region, a transistor 103 with an extremely low off-current can be realized. By using the transistor 103 having the above configuration as a switching element for holding the charge stored in the transistor 102 or the capacitor element 105 that functions as a memory element, the leakage of the above charge can be prevented. Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, when the drain electrode is at a higher potential than the source electrode and the gate electrode, and the potential of the gate electrode is 0 or less when referenced to the potential of the source electrode, the current flowing between the source electrode and the drain electrode. Alternatively, in this specification, the off-current means, in a p-channel type transistor,

[0031] when the drain electrode is at a lower potential than the source electrode and the gate electrode, and the potential of the gate electrode is 0 or more when referenced to the potential of the source electrode, the current flowing between the source electrode and the drain electrode. When the potential of the gate electrode is 0 or less when referenced to the potential of the source electrode, it means the current flowing between the source electrode and the drain electrode. Or, in this specification, the off-current means, in a p-channel type transistor, when the drain electrode is at a lower potential than the source electrode and the gate electrode, and the potential of the gate electrode is 0 or more when referenced to the potential of the source electrode, it means the current flowing between the source electrode and the drain electrode. When the potential of the gate electrode is 0 or more when referenced to the potential of the source electrode, it means the current flowing between the source electrode and the drain electrode. As an example of a semiconductor material having a wider bandgap and a lower intrinsic carrier density than a silicon semiconductor, in addition to an oxide semiconductor,

[0032] compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) can be mentioned. It is essential that compound semiconductors such as silicon carbide and gallium nitride are single crystals. To obtain a single crystal material, compared with an oxide semiconductor, compound semiconductors such as silicon carbide and gallium nitride can be cited. Compound semiconductors such as silicon carbide and gallium nitride must be single crystals. To obtain a single crystal material, compared with an oxide semiconductor, Crystal growth at a temperature significantly higher than the process temperature, epitaxial growth on a special substrate, etc. require strict manufacturing conditions, and it is difficult to form a film on a silicon wafer that is easily available or a glass substrate with a low heat resistance temperature. However, oxide semiconductors can be manufactured by sputtering or wet methods (such as printing methods), and have the advantage of excellent mass productivity. In addition, since oxide semiconductors can be formed at room temperature, it is possible to form a film on a glass substrate or on an integrated circuit using a semiconductor element, and it is also possible to cope with an increase in the size of the substrate. Therefore, among the wide-gap semiconductors described above, oxide semiconductors in particular have the merit of high mass productivity. Also, when trying to obtain a crystalline oxide semiconductor to improve the performance of a transistor (for example, field-effect mobility), a crystalline oxide semiconductor can be obtained by heat treatment at 200°C to 800°C. Note that in Fig. 1(A), the transistor 102 that functions as a memory element may have an oxide semiconductor film in its active layer. Alternatively, in the active layer of the transistor 102, a semiconductor such as amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium other than the oxide semiconductor may be used. By using an oxide semiconductor film in the active layer of all the transistors in the memory cell 101, the process can be simplified. In addition, by using a semiconductor material with a higher mobility than the oxide semiconductor, such as polycrystalline or single-crystalline silicon, in the active layer of the transistor 102 that functions as a memory element, data can be read from the memory cell 101 at high speed.

[0033]

[0034] ​​​​​​​​​​​​​Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIG. 1(A) or FIG. 1(B), the case where the transistor 103 has a gate electrode only on one side of the active layer is shown. When the transistor 103 has a pair of gate electrodes sandwiching the active layer, a signal for controlling switching is applied to one of the gate electrodes, and the other gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied from elsewhere. In the latter case, the same height of potential may be applied to the pair of electrodes, or a fixed potential such as ground may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor 103 can be controlled.

[0035] In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. In FIG. 1(B), the configuration in which the memory cell 101 has only one transistor 103 that functions as a switching element is shown, but the present invention is not limited to this configuration. In one aspect of the present invention, it is sufficient that at least one transistor that functions as a switching element is provided in each memory cell, and the number of the above transistors may be plural. When the memory cell 101 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel.

[0036] Note that in this specification, the state where transistors are connected in series means, for example, a state where only one of the first terminal and the second terminal of the first transistor is connected to only one of the first terminal and the second terminal of the second transistor. Also, Note that in this specification, the state where transistors are connected in series means, for example, a state where only one of the first terminal and the second terminal of the first transistor is connected to only one of the first terminal and the second terminal of the second transistor. Also, Note that in this specification, the state where transistors are connected in series means, for example, a state where only one of the first terminal and the second terminal of the first transistor is connected to only one of the first terminal and the second terminal of the second transistor. Also, The state in which the transistors are connected in parallel means that the first terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the first transistor is connected to the second terminal of the second transistor. The state in which the first terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the first transistor is connected to the second terminal of the second transistor. means.

[0037] Next, FIG. 1(C) shows an example of a cross-sectional view of the transistor 103 and the capacitive element 104 included in FIG. 1(A). Note that, although FIG. 1(C) shows the cross-sectional structure of the memory cell 101 shown in FIG. 1(A), the transistor 103 and the capacitive element 105 included in FIG. 1(B) can also adopt the same configuration as FIG. 1(C). In the cross-sectional view shown in FIG. 1(C), the capacitive element 104 and the transistor 103 are formed on a substrate 110 having an insulating surface, and the capacitive element 104 and the transistor 103 overlap with each other with an insulating film 111 interposed therebetween. In the cross-sectional view shown in FIG. 1(C), the capacitive element 104 and the transistor 103 are formed on a substrate 110 having an insulating surface, and the capacitive element 104 and the transistor 103 overlap with each other with an insulating film 111 interposed therebetween. C) can adopt the same configuration.

[0038] In the cross-sectional view shown in FIG. 1(C), the capacitive element 104 and the transistor 103 are formed on a substrate 110 having an insulating surface, and the capacitive element 104 and the transistor 103 overlap with each other with an insulating film 111 interposed therebetween. In the cross-sectional view shown in FIG. 1(C), the capacitive element 104 and the transistor 103 are formed on a substrate 110 having an insulating surface, and the capacitive element 104 and the transistor 103 overlap with each other with an insulating film 111 interposed therebetween. 1 is interposed and overlaps.

[0039] Specifically, the capacitive element 104 includes an electrode 112 formed on a substrate 110 having an insulating surface, an insulating film 113 on the electrode 112, and an electrode 114 that overlaps the electrode 112 with the insulating film 113 interposed therebetween. The overlapping portion of the electrode 112, the insulating film 113, and the electrode 114 functions as the capacitive element 104. Specifically, the capacitive element 104 includes an electrode 112 formed on a substrate 110 having an insulating surface, an insulating film 113 on the electrode 112, and an electrode 114 that overlaps the electrode 112 with the insulating film 113 interposed therebetween. The overlapping portion of the electrode 112, the insulating film 113, and the electrode 114 functions as the capacitive element 104. 14. The overlapping portion of the electrode 112, the insulating film 113, and the electrode 114 functions as the capacitive element 104. functions as the capacitive element 104.

[0040] Also, the transistor 103 includes a gate electrode 115 on an insulating film 111 covering the electrode 114, an insulating film 116 on the gate electrode 115, an active layer 117 including an oxide semiconductor that overlaps the gate electrode 115 with the insulating film 116 interposed therebetween, a source electrode 118 on the active layer 117, and a drain electrode 119. Further, the transistor 103 includes the active layer 117, Also, the transistor 103 includes a gate electrode 115 on an insulating film 111 covering the electrode 114, an insulating film 116 on the gate electrode 115, an active layer 117 including an oxide semiconductor that overlaps the gate electrode 115 with the insulating film 116 interposed therebetween, a source electrode 118 on the active layer 117, and a drain electrode 119. Further, the transistor 103 includes the active layer 117, 15, an insulating film 116 on the gate electrode 115, an active layer 117 including an oxide semiconductor that overlaps the gate electrode 115 with the insulating film 116 interposed therebetween, a source electrode 118 on the active layer 117, and a drain electrode 119. Further, the transistor 103 includes the active layer 117, 8, a drain electrode 119. Further, the transistor 103 includes the active layer 117, It may include a component of an insulating film 120 covering the source electrode 118 and the drain electrode 119. The transistor 103 has a bottom gate structure, and a part of the active layer 117 is etched between the source electrode 11 8 and the drain electrode 119 to form a channel etch structure.

[0041] In addition, in FIG. 1(C), the case where the transistor 103 has a single gate structure is illustrated, but the transistor 103 may have a multi-gate structure having a plurality of electrically connected gate electrodes and having a plurality of channel formation regions.

[0042] In one aspect of the present invention, as shown in FIG. 1(C), an insulating film 1 21 having light-shielding properties is formed so as to cover the transistor 103. Specifically, an insulating film 121 functioning as a light-shielding layer is formed so as to overlap with the active layer 117 of the transistor 1 03.

[0043] The light-shielding layer such as the insulating film, wiring or electrode having light-shielding properties has a low transmittance for light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer, or in a wavelength region shorter than this. Specifically, assuming that the absorption edge wavelength is λ0, the light-shielding layer has a transmittance of 50% or less, more preferably 30% or less, for light having a wavelength of 100 nm or more and λ0 + 100 nm or less. For example, when the absorption edge wavelength of the active layer 117 formed using an In-Ga-Zn-O-based oxide semiconductor is 393 nm, the light-shielding layer has a transmittance of 50% or less, more preferably 30% or less, for light having a wavelength of 100 nm or more and 493 nm or less. Note that it is not necessary for all the light included in the above wavelength range to satisfy the above transmittance, and at least one wavelength included in the above wavelength range needs to satisfy the above transmittance. It is only necessary that the light satisfies the above transmittance range. Further, it is desirable in terms of preventing light deterioration of the oxide semiconductor that the transmittance of light on the longer wavelength side than the above wavelength range also satisfies the above range. For example, the insulating film 121 can be formed using a resin in which black pigments such as carbon black and titanium suboxide having a smaller oxidation number than titanium dioxide, and ultraviolet absorbers such as titanium dioxide and zinc oxide are dispersed. For the resin, for example, organic resins such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin, and siloxane-based resins can be used.

[0044] The siloxane-based resin is a material in which a lattice structure is formed by bonds between silicon (Si) and oxygen (O). As substituents, in addition to hydrogen, at least one of fluorine, fluoro group, and organic groups (for example, alkyl group, aromatic hydrocarbon) may be included. When a resin is used for the insulating film 121, in order to prevent impurities such as hydrogen and water contained in the resin from entering the active layer 117, the insulating film 116, or the interface between the active layer 117 and other insulating films and the vicinity thereof, it is desirable to form an insulating film 122 using a material with high barrier properties between the insulating film 121 and the active layer 117. Examples of the insulating film 122 with high barrier properties include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. In addition, since the characteristics of the transistor 103 may deteriorate when the active layer 117 and the insulating film 122 with a high nitrogen content ratio are in direct contact, as shown in FIG. 1(C), an insulating film 120 such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio is formed between the active layer 117 and the insulating film 122. It is desirable. As substituents, in addition to hydrogen, at least one of fluorine, fluoro group, and organic groups (for example, alkyl group, aromatic hydrocarbon) may be included. When a resin is used for the insulating film 121, in order to prevent impurities such as hydrogen and water contained in the resin from entering the active layer 117, the insulating film 116, or the interface between the active layer 117 and other insulating films and the vicinity thereof, it is desirable to form an insulating film 122 using a material with high barrier properties between the insulating film 121 and the active layer 117.

[0045] Examples of the insulating film 122 with high barrier properties include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. In addition, since the characteristics of the transistor 103 may deteriorate when the active layer 117 and the insulating film 122 with a high nitrogen content ratio are in direct contact, as shown in FIG. 1(C), an insulating film 120 such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio is formed between the active layer 117 and the insulating film 122. It is desirable. Examples of the insulating film 122 with high barrier properties include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. In addition, since the characteristics of the transistor 103 may deteriorate when the active layer 117 and the insulating film 122 with a high nitrogen content ratio are in direct contact, as shown in FIG. 1(C), an insulating film 120 such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio is formed between the active layer 117 and the insulating film 122. It is desirable. In addition, since the characteristics of the transistor 103 may deteriorate when the active layer 117 and the insulating film 122 with a high nitrogen content ratio are in direct contact, as shown in FIG. 1(C), an insulating film 120 such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio is formed between the active layer 117 and the insulating film 122. It is desirable. It is desirable to form an insulating film 120 such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio between the active layer 117 and the insulating film 122.

[0046] In addition, by using an inorganic material containing oxygen for the insulating film 120 in contact with the active layer 117, water Oxygen vacancies have occurred in the active layer 117 due to the heat treatment for reducing the amount of oxygen or hydrogen. Even if this happens, oxygen is supplied to the active layer 117 from the insulating film 120, and oxygen vacancies that become donors are reduced. Therefore, the active layer 117 can be reduced to satisfy the stoichiometric composition ratio. The transistor 103 can be made closer to an i-type structure, and variations in the electrical characteristics of the transistor 103 due to oxygen vacancies can be reduced. This can reduce the electrical resistance and improve the electrical characteristics.

[0047] In addition, by subjecting the active layer 117 to a heat treatment in an oxygen atmosphere, oxygen is added to the oxide semiconductor. In addition, oxygen vacancies that become donors in the active layer 117 may be reduced. The heating is carried out at a temperature of, for example, 100°C or higher and lower than 350°C, preferably 150°C or higher and lower than 250°C. The oxygen gas used in the heat treatment in the oxygen atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heat treatment device is preferably 6N (99.9999%) or less. ) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration in oxygen is 1p pm or less, preferably 0.1 ppm or less).

[0048] Alternatively, oxygen may be added to the active layer 117 by using an ion implantation method or an ion doping method. For example, the 2.45 GHz master Oxygen plasma generated by microwaves may be added to the active layer 117 .

[0049] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. It is a nitride oxide, and in terms of its composition, it has a higher nitrogen content than oxygen content. It means a substance. For example, silicon oxynitride has oxygen in the range of 50 atomic % or more and 70 atomic % or less, nitrogen in the range of 0.5 atomic % or more and 15 atomic % or less, silicon in the range of 25 atomic % or more and 35 atomic % or less, and hydrogen in the range of 0.1 atomic % or more and 10 atomic % or less. Also, silicon oxynitride can be a substance containing oxygen in the range of 5 atomic % or more and 30 atomic % or less, nitrogen in the range of 20 atomic % or more and 55 atomic % or less, silicon in the range of 25 atomic % or more and 35 atomic % or less, and hydrogen in the range of 10 atomic % or more and 30 atomic % or less. However, the above composition ranges are those when measured using the Rutherford backscattering spectrometry ( RBS) or the hydrogen forward scattering method (HFS). Also, the content ratios of the constituent elements take values such that their total does not exceed 100 atomic %. RBS: Rutherford Backscattering Spectromet ry) or the hydrogen forward scattering method (HFS: Hydrogen Forward Scatte ring). Also, the content ratios of the constituent elements take values such that their total does not exceed 100 atomic %.

[0050] Furthermore, in one aspect of the present invention, as shown in Fig. 1(C), at least one of the electrodes 112 or 114 of the capacitive element 104 has light-shielding properties. And the electrode 112 or 114 having light-shielding properties is formed at a position overlapping with the active layer 117 of the transistor 103. And the electrode 112 or 114 having light-shielding properties is formed at a position overlapping with the active layer 117 of the transistor 103. And the electrode 112 or 114 having light-shielding properties is formed at a position overlapping with the active layer 117 of the transistor 103. formed.

[0051] With the above configuration, since the active layer 117 is sandwiched between the electrode 112 or 114 having light-shielding properties and the insulating film 121 having light-shielding properties, light near the absorption edge wavelength of the oxide semiconductor or light in a wavelength region shorter than this can be prevented from entering the active layer 117. With the above configuration, since the active layer 117 is sandwiched between the electrode 112 or 114 having light-shielding properties and the insulating film 121 having light-shielding properties, light near the absorption edge wavelength of the oxide semiconductor or light in a wavelength region shorter than this can be prevented from entering the active layer 117. can be prevented from entering the active layer 117.

[0052] Next, FIG. 1(D) shows an example of a cross-sectional view of the transistor 103 and the capacitor element 104 included in FIG. 1(A). Note that in FIG. 1(D), the cross-sectional structure of the memory cell 101 shown in FIG. 1(A) is shown, but the transistor 103 and the capacitor element 105 included in FIG. 1(B) can also adopt the same configuration as FIG. 1(D). In the cross-sectional view shown in FIG. 1(D), similar to FIG. 1(C), the capacitor element 104 and the transistor 103 are formed on the substrate 110 having an insulating surface, and the capacitor element 104 and the transistor 103 overlap with each other with the insulating film 111 interposed therebetween. The specific configurations of the capacitor element 104 and the transistor 103 are the same as those in FIG. 1(C). Thus, in FIG. 1(D), the wiring 123 is formed of a conductive film having light-shielding properties, and the transistor 103 is covered with the wiring 123. Specifically, the light-shielding wiring 123 is formed so as to overlap with the active layer 117 of the transistor 103. The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner.

[0053] In the cross-sectional view shown in FIG. 1(D), similar to FIG. 1(C), the capacitor element 104 and the transistor 103 are formed on the substrate 110 having an insulating surface, and the capacitor element 104 and the transistor 103 overlap with each other with the insulating film 111 interposed therebetween. The specific configurations of the capacitor element 104 and the transistor 103 are the same as those in FIG. 1(C). Thus, in FIG. 1(D), the wiring 123 is formed of a conductive film having light-shielding properties, and the transistor 103 is covered with the wiring 123. Specifically, the light-shielding wiring 123 is formed so as to overlap with the active layer 117 of the transistor 103. The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner.

[0054] The specific configurations of the capacitor element 104 and the transistor 103 are the same as those in FIG. 1(C). Thus, in FIG. 1(D), the wiring 123 is formed of a conductive film having light-shielding properties, and the transistor 103 is covered with the wiring 123. Specifically, the light-shielding wiring 123 is formed so as to overlap with the active layer 117 of the transistor 103. The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. The specific configurations of the capacitor element 104 and the transistor 103 are the same as those in FIG. 1(C). Thus, in FIG. 1(D), the wiring 123 is formed of a conductive film having light-shielding properties, and the transistor 103 is covered with the wiring 123. Specifically, the light-shielding wiring 123 is formed so as to overlap with the active layer 117 of the transistor 103. The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner.

[0055] The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. The characteristics required for the light-shielding wiring 123 are, as described above, that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used for the active layer or in a wavelength region shorter than this is low. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. Therefore, a metal having both conductivity and light-shielding properties is used for the wiring 123. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. For example, for the wiring 123, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked manner. .

[0056] Furthermore, in FIG. 1(D), similar to FIG. 1(C), at least one of the electrodes 112 or the electrode 114 of the capacitive element 104 has light-shielding properties. And the light-shielding electrode 112 or the electrode 114 is formed at a position overlapping with the active layer 117 of the

[0057] transistor 103. With the above configuration, in FIG. 1(D), since the active layer 117 is sandwiched between the light-shielding electrode 112 or electrode 114 and the light-shielding wiring 123, light in the vicinity of the absorption edge wavelength of the oxide semiconductor or light in a shorter wavelength region

[0058] can be prevented from entering the active layer 117. Note that in FIGS. 1(C) and 1(D), the transistor 103 may have a back gate electrode at a position overlapping with the channel formation region of the active layer 117 on the insulating film 120. When forming the back gate electrode, an insulating film is formed so as to cover the back gate electrode. The back gate electrode may be in a floating state that is electrically insulated, or may be in a state where a potential is applied. In the latter case, the back gate electrode may be applied with the same potential as the gate electrode 115, or a fixed potential such as ground may be applied. By controlling the height of the potential applied to the back

[0059] gate electrode, the threshold voltage of the transistor 103 can be controlled. Note that in FIGS. 1(C) and 1(D), the case where the transistor 103 is a bottom gate type and has a channel etch structure is shown, but the structure of the transistor used in one

[0060] aspect of the present invention is not limited to this configuration.In one aspect of the present invention, a transistor 103 including an oxide semiconductor in the active layer 117 is used as a switching element for controlling the charge retention in the transistor 102 or the capacitor element 105 that functions as a memory element, thereby preventing the leakage of the charge. Also, by sandwiching the active layer 117 with layers such as an electrode having light-shielding properties, a conductive film, and an insulating film, it is possible to prevent the characteristics of the transistor 103 from deteriorating due to light. Specifically, it is possible to suppress the shift of the threshold voltage and prevent the off-current from increasing. Further, in one aspect of the present invention, the electrode having light-shielding properties is used as the electrode 112 or the electrode 114 of the capacitor element 104 or the capacitor element 105. Therefore, since the capacitor element 104 or the capacitor element 105 and the transistor 103 are arranged in the memory cell 101 so as to overlap, it is possible to reduce the occupied area of the memory cell 101 while securing the exclusive area or the capacitance value of the capacitor element 104 or the capacitor element 105. Thus, the memory device according to one aspect of the present invention can increase the memory capacity per unit area while securing the period for holding data. Alternatively, the present invention can improve the reliability and enhance the functionality of the semiconductor device by using the memory device in the semiconductor device. Next, FIG. 2 shows an example of a more specific connection configuration of various wirings in the memory cell 101. The memory cell 101 shown in FIG. 2(A) has a transistor 103 that functions as a switching element and a capacitor element 105 that functions as a memory element. The gate of the transistor 103

[0061]

[0062]

[0063] The word electrode is connected to the word line WL. Also, the first terminal of the transistor 103 is connected to the data line DL, and the second terminal is connected to one electrode of the capacitor element 105. The other electrode of the capacitor element 105 is connected to a node to which a fixed potential such as ground is applied. Continued.

[0064] In the memory cell 101 shown in Fig. 2(A), when writing data, the transistor 103 turns on, and the potential of the signal including data from the data line DL is applied to one electrode of the capacitor element 105 through the transistor 103. Then, according to the potential of the above signal, the amount of charge stored in the capacitor element 105 is controlled, and data is written into the capacitor element 105. The potential of the signal including data from the data line DL is applied to one electrode of the capacitor element 105 through the transistor 103. Then, according to the potential of the above signal, the amount of charge stored in the capacitor element 105 is controlled, and data is written into the capacitor element 105. And the potential of the signal including data from the data line DL is applied to one electrode of the capacitor element 105 through the transistor 103. Then, according to the potential of the above signal, the amount of charge stored in the capacitor element 105 is controlled, and data is written into the capacitor element 105. 05 is controlled, and data is written into the capacitor element 105. Is performed.

[0065] Next, when holding data, the transistor 103 turns off, and the charge is held in the capacitor element 105. As described above, the transistor 103 has the characteristic that the off-current is extremely low. Therefore, the charge stored in the capacitor element 105 is less likely to leak, and data can be held for a longer period than when light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103. Next, when holding data, the transistor 103 turns off, and the charge is held in the capacitor element 105. As described above, the transistor 103 has the characteristic that the off-current is extremely low. Therefore, the charge stored in the capacitor element 105 is less likely to leak, and data can be held for a longer period than when light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103. Next, when holding data, the transistor 103 turns off, and the charge is held in the capacitor element 105. As described above, the transistor 103 has the characteristic that the off-current is extremely low. Therefore, the charge stored in the capacitor element 105 is less likely to leak, and data can be held for a longer period than when light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103. Next, when holding data, the transistor 103 turns off, and the charge is held in the capacitor element 105. As described above, the transistor 103 has the characteristic that the off-current is extremely low. Therefore, the charge stored in the capacitor element 105 is less likely to leak, and data can be held for a longer period than when light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103. Next, when holding data, the transistor 103 turns off, and the charge is held in the capacitor element 105. As described above, the transistor 103 has the characteristic that the off-current is extremely low. Therefore, the charge stored in the capacitor element 105 is less likely to leak, and data can be held for a longer period than when light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103.

[0066] When reading data, the transistor 103 turns on, and the charge stored in the capacitor element 105 is taken out through the data line DL. Then, by reading the difference in the amount of the above charge, the data can be read. When reading data, the transistor 103 turns on, and the charge stored in the capacitor element 105 is taken out through the data line DL. Then, by reading the difference in the amount of the above charge, the data can be read. When reading data, the transistor 103 turns on, and the charge stored in the capacitor element 105 is taken out through the data line DL. Then, by reading the difference in the amount of the above charge, the data can be read.

[0067] The memory cell 101 shown in Fig. 2(B) has a transistor 103 that functions as a switching element, a transistor 102 that functions as a storage element, and a capacitor element 104. The memory cell 101 shown in Fig. 2(B) has a transistor 103 that functions as a switching element, a transistor 102 that functions as a storage element, and a capacitor element 104. The The gate electrode of transistor 103 is connected to the first word line WLa. Also, the first terminal of transistor 103 is connected to the first data line DLa, and the second terminal is connected to the gate electrode of transistor 102. The first terminal of transistor 102 is connected to the second data line DLb, and the second terminal is connected to a node to which a fixed potential such as ground is applied. One of the pair of electrodes of the capacitive element 104 is connected to the gate electrode of transistor 102, and the other

[0068] is connected to the second word line WLb. In the memory cell 101 shown in FIG. 2(B), when writing data, transistor 103 is turned on, and the potential of the signal including data from the first data line DLa is applied to the gate electrode of transistor 102 through transistor 103. Then, according to the potential of the above signal, the gate capacitance of transistor 102 and the amount of charge stored in capacitive element 104 are controlled,

[0069] thereby writing data to transistor 102 and capacitive element 104. Next, when holding data, transistor 103 is turned off, and the gate capacitance of transistor 102 and the charge stored in capacitive element 104 are held. As described above, transistor 103 has the characteristic that its off-current is extremely low. Therefore, the above charge is less likely to leak, and data can be held for a longer period compared to the case where no light shielding is performed or when a semiconductor

[0070] material such as silicon is used for transistor 103. Since the potential difference between the pair of electrodes is maintained by the charge conservation law, the second word line WL The change in the potential of b is applied to the gate electrode of the transistor 102. Transistor 102 has a threshold voltage that changes depending on the amount of charge stored in its gate capacitance. Therefore, by reading the difference in the amount of charge stored from the magnitude of the drain current of the transistor 102 obtained by changing the potential of the gate electrode of the transistor 102, data can be read.

[0071] The memory cell 101 shown in FIG. 2(C) is different from the memory cell 10 1 shown in FIG. 2(B) in that one data line DL has the functions of the first data line DLa and the second data line DLb combined. Specifically, the memory cell 101 shown in FIG. 2(C) includes a switching element transistor 103 that functions as, a transistor 102 that functions as a storage element, and a capacitive element 104. The gate electrode of the transistor 103 is connected to the first word line WLa Further, the first terminal of the transistor 103 is connected to the data line DL, and the second terminal is connected to the gate electrode of the transistor 102. The first terminal of the transistor 102 is connected to the data line DL, and the second terminal is connected to a node to which a fixed potential such as ground is applied One pair of electrodes of the capacitive element 104 has one connected to the gate electrode of the tra nsistor 102 and the other connected to the second word line WLb.

[0072] The memory cell 101 shown in FIG. 2(C) can perform operations such as data writing, holding, and reading in the same manner as the memory cell 101 shown in FIG. 2(B).

[0073] The memory cell 101 shown in FIG. 2(D) includes a transistor 103 that functions as a switching element, a transistor 102 that functions as a memory element, a capacitor element 104, and a transistor 106 that functions as a switching element for controlling data readout. The gate electrode of the transistor 103 is connected to the first word line WLa. Also, the first terminal of the transistor 103 is connected to the first data line DLa, and the second terminal is connected to the gate electrode of the transistor 102. The first terminal of the transistor 102 is connected to the second terminal of the transistor 106, and the second terminal is connected to a node to which a fixed potential such as ground is applied. The first terminal of the transistor 106 is connected to the second data line DLb. The gate electrode of the transistor 106 is connected to the second word line WLb. One pair of electrodes of the capacitor element 104 is connected to the gate electrode of the transistor 102, and the other is connected to a node to which a fixed potential is applied. 03, a transistor 102 that functions as a memory element, a capacitor element 104, and a transistor 106 that functions as a switching element for controlling data readout. The gate electrode of the transistor 103 is connected to the first word line WLa. Also, the first terminal of the transistor 103 is connected to the first data line DLa, and the second terminal is connected to the gate electrode of the transistor 102. The first terminal of the transistor 102 is connected to the second terminal of the transistor 106, and the second terminal is connected to a node to which a fixed potential such as ground is applied. The first terminal of the transistor 106 is connected to the second data line D Lb. The gate electrode of the transistor 106 is connected to the second word line WLb. One pair of electrodes of the capacitor element 104 is connected to the gate electrode of the transistor 102, and the other is connected to a node to which a fixed potential is applied. In the memory cell 101 shown in FIG. 2(D), when writing data, the transistor 103 turns on, and the potential of the signal including data from the first data line DLa is applied to the gate electrode of the transistor 102 through the transistor

[0074] 103. Then, according to the potential of the above signal, the gate capacitance of the transistor 102 and the amount of charge stored in the capacitor element 104 are controlled, and data is written to the transistor 102 and the capacitor element 104. Next, when holding data, the transistor 103 turns off, and the gate capacitance of the transistor 102 and the charge stored in the capacitor element 104 are held. As described above, the transistor 102 and the capacitor element 104 are written with data.

[0075] 102 and the charge stored in the capacitor element 104 are held. As described above, the gate capacitance of the transistor 102 and the charge stored in the capacitor element 104 are held. The standby 103 has the characteristic that its off-current is extremely low. Therefore, the accumulated charge is less likely to leak, and when light shielding is not performed, or when a semiconductor material such as silicon is used it can hold data for a longer period compared to the case.

[0076] When reading data, the transistor 10 6 turns on due to the change in the potential of the second word line WLb. When the transistor 106 turns on, a drain current of a height corresponding to the amount of charge accumulated in its gate capacitance flows through the transistor 102. Therefore, the difference in the amount of accumulated charge can be read from the magnitude of the drain current of the transistor 102, and data can be read accordingly.

[0077] (Embodiment 2) In this embodiment, an example of the specific configuration of a memory cell included in a memory device according to an aspect of the present invention will be described. In this embodiment, a memory cell having the circuit configuration shown in FIG. 2(C) will be taken as an example, and its structure will be described.

[0078] FIG. 3 shows an example of a top view of a memory cell. In FIG. 3, for the sake of clearly showing the configuration of the memory cell, all insulating films other than the insulating film having light-shielding properties are omitted. Also, the cross-sectional view along the dashed line A1 - A2 in FIG. 3 is shown in FIG. 4.

[0079] The memory cell shown in FIGS. 3 and 4 has a transistor 102, a transistor 103, and a capacitor element 104 on a substrate 110 having an insulating surface. And the capacitor element 104 formed on the substrate 110 is covered with an insulating film 111, and on the insulating film 111 is a transistor 1 02 and the transistor 103 are formed. And the capacitor element 104 and the transistor 102 and the transistor 103 overlap with the insulating film 111 interposed therebetween.

[0080] Specifically, the capacitor element 104 includes an electrode 112 formed on a substrate 110 having an insulating surface, an insulating film 113 on the electrode 112, and an electrode 1 14 that overlaps the electrode 112 with the insulating film 113 interposed therebetween. The overlapping portion of the electrode 112, the insulating film 113, and the electrode 114 functions as the capacitor element 104.

[0081] Also, the transistor 103 includes a conductive film 130 and a conductive film 131 that function as a source electrode or a drain electrode on the insulating film 111, an active layer 132 containing an oxide semiconductor that is in contact with the conductive film 130 and the conductive film 131, an insulating film 133 that covers the conductive film 130, the conductive film 131, and the active layer 132, and a gate electrode 13 4 that overlaps the active layer 132 with the insulating film 133 interposed therebetween.

[0082] The transistor 103 shown in FIGS. 3 and 4 is a top-gate type, and the conductive film 130 and the conductive film 131 that function as a source electrode or a drain electrode are in contact with the lower side of the active layer 132, which is a bottom-contact structure.

[0083] Also, the transistor 102 includes a conductive film 131 and a conductive film 135 that function as a source electrode or a drain electrode on the insulating film 111, an active layer 136 containing an oxide semiconductor that is in contact with the conductive film 131 and the conductive film 135, an insulating film 133 that covers the conductive film 131, the conductive film 135, and the active layer 136, and a gate electrode 13 7 that overlaps the active layer 136 with the insulating film 133 interposed therebetween. ​​​​​​​

[0084] The transistor 102 shown in FIGS. 3 and 4 is a top-gate type like the transistor 103, and has a bottom contact structure in which the conductive films 131 and 135 that function as a source electrode or a drain electrode are in contact with the lower side of the active layer 136.

[0085] Also, FIGS. 3 and 4 illustrate the case where the transistors 102 and 103 have a single gate structure, but the transistors 102 and 103 may have a multi-gate structure having a plurality of channel formation regions by having a plurality of electrically connected gate electrodes.

[0086] And the conductive film 130 is in contact with the electrode 114 through the contact hole 138 formed in the insulating film 111.

[0087] Also, an insulating film 139 is formed so as to cover the transistors 102 and 103. And on the insulating film 139, a light-shielding conductive film 141 connected to the gate electrode 137 of the transistor 102 through the contact hole 140 formed in the insulating film 139 is formed. Also, the conductive film 141 is connected to the conductive film 130 through the contact hole 142 formed in the insulating film 139 and the insulating film 133. Also, on the insulating film 139, a light-shielding conductive film 144 connected to the gate electrode 134 of the transistor 103 through the contact hole 143 formed in the insulating film 139 is formed.

[0088] The light-shielding conductive film 141 covers at least a part of the active layer 136 of the transistor 102, It is formed at an overlapping position. In order to further prevent light from entering the active layer 136, it is desirable to completely cover the entire active layer 136 with the conductive film 141.

[0089] In addition, the conductive film 144 having light-shielding properties is formed at a position overlapping at least a part of the active layer 132 of the transistor 103. In order to further prevent light from entering the active layer 132, it is desirable to completely cover the entire active layer 132 with the conductive film 144.

[0090] Furthermore, in one aspect of the present invention, at least one of the electrodes 112 or 114 of the capacitor element 104 has light-shielding properties. And the light-shielding electrode 112 or 114 is formed at a position overlapping the active layer 132 of the transistor 103 and the active layer 136 of the transistor 102. The active layer 132 and the active layer 136 only need to overlap at least a part of them with the electrode 112 or the electrode 114. However, in order to further prevent light from entering the active layer 132 or the active layer 136, it is desirable that the entire active layer 132 or the entire active layer 136 completely overlaps with the electrode 112 or the electrode 114.

[0091] The properties required for the light-shielding electrodes 112, 114, the conductive film 141, and the conductive film 144 are, as described above, such that the transmittance of light in the vicinity of the absorption edge wavelength of the oxide semiconductor used in the active layer, or in a wavelength region shorter than this, is low. Therefore, for the electrodes 112, 114, the conductive film 141, and the conductive film 144, a metal having both conductivity and light-shielding properties is used. For example, for the electrodes 112, 114, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, and alloy materials mainly composed of these metal materials are used. ​​​​​​​​​​​​​​The conductive film, or nitrides of these metals, can be used either singly or in a laminated structure. Also , in addition to the materials described above, aluminum or copper can also be used for the conductive films 141 and 144. When aluminum or copper is used for the conductive films 141 and 144, it is advisable to use them in combination with a high melting point metal material to avoid problems with heat resistance and corrosiveness. As the high melting point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used.

[0092] For example, when the electrodes 112, 114, conductive films 141, and 144 have a two-layer laminated structure, a two-layer laminated structure in which a molybdenum film is laminated on an aluminum film, a two-layer structure in which a molybdenum film is laminated on a copper film, a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film, or a two-layer structure in which a titanium nitride film and a molybdenum film are laminated is preferable. When the electrodes 112, 114, conductive films 141, and 144 have a three-layer laminated structure, it is preferable to have a structure in which an aluminum film, an aluminum-silicon alloy film, an aluminum-titanium alloy film, or an aluminum-neodymium alloy film is used as the intermediate layer, and a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film is laminated as the upper and lower layers.

[0093] And the film thicknesses of the electrodes 112, 114, conductive films 141, and 144 are, for example, 10 nm to 400 nm, preferably 100 nm to 200 nm.

[0094] In one aspect of the present invention, with the above configuration, since the active layer 136 is sandwiched between the light-shielding electrode 112 or electrode 114 and the light-shielding conductive film 141, the absorption edge of the oxide semiconductor Light near the wavelength or light in a wavelength region shorter than this can be prevented from entering the active layer 136. This can be achieved. Also, since the active layer 132 is sandwiched between the light-shielding electrode 112 or electrode 114 and the light-shielding conductive film 144, light near the absorption edge wavelength of the oxide semiconductor or light in a wavelength region shorter than this can be prevented from entering the active layer 132. .

[0095] Note that in FIGS. 3 and 4, a configuration in which the active layer 132 or the active layer 136 is shielded from light using the conductive films 141 and 144 that function as wirings is given as an example. However, similar to the configuration shown in FIG. 1(C), an insulating film having light-shielding properties may be used to shield the active layer 132 or the active layer 136 from light.

[0096] Also, in FIGS. 3 and 4, a case where the transistor 102 that functions as a memory element contains an oxide semiconductor in its active layer 136 is illustrated. However, the transistor 102 does not necessarily have to contain an oxide semiconductor in its active layer. For example, when forming the active layer of the transistor 102 using a semiconductor material such as silicon or germanium, the active layer and the capacitor element 104 can be formed together on a single insulating surface. And further, the electrode 112 of the capacitor element 104 can also be formed using a semiconductor material such as silicon or germanium in the same manner as the above active layer.

[0097] And the electrode 112 also functions as the second word line WLb. Also, the conductive film 144 also functions as the first word line WLa. Also, the conductive film 131 also functions as the data line DL. The conductive film 135 functions as a wiring to which a fixed potential such as ground is applied.

[0098] Although there are no major restrictions on the materials that can be used as the substrate 110, at least, it is necessary to have heat resistance to withstand the heat treatment in the manufacturing process. For example for the substrate 110, a glass substrate, a quartz substrate, a ceramic substrate, etc. produced by the fusion method or the float method can be used. As the glass substrate, when the temperature of the subsequent heat treatment is high it is advisable to use one with a strain point of 730 °C or higher. Substrates made of flexible synthetic resins such as plastics generally tend to have a lower heat resistance temperature compared to the above substrates, but they can be used if they can withstand the processing temperature in the manufacturing process.

[0099] Also, the insulating film 133 can be formed by using the plasma CVD method, the sputtering method, etc., as a single layer or by laminating a silicon oxide film , a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film , an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film or a tantalum oxide film. The insulating film 133 that functions as a gate insulating film desirably contains as few impurities as possible such as moisture, hydrogen, and oxygen. When forming a silicon oxide film by the sputtering method, a silicon target or a quartz target is used as the target, and oxygen or a mixed gas of oxygen and argon is used as the sputtering gas . .

[0100] By removing impurities, an i-type or substantially i-type oxide semiconductor (a highly purified oxide semiconductor) is extremely sensitive to interface levels and interface charges. Therefore, the interface between the highly purified oxide semiconductor and the gate insulating film is important. Therefore, the highly purified oxide semiconductor The gate insulating film (GI) in contact with the conductor is required to be of high quality.

[0101] For example, high-density plasma CVD using microwaves (frequency 2.45 GHz) can form a high-quality insulating film that is dense and has high insulation resistance, so it is suitable as a method for forming the insulating film 133. This is because when a highly purified oxide semiconductor is in close contact with a high-quality gate insulating film, the interface level can be reduced to improve the interface characteristics. Of course, as long as a high-quality insulating film 133 can be formed as the gate insulating film, other film formation methods such as sputtering and plasma CVD can be applied. Also, an insulating film whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment after film formation may be used. In any case, it is necessary not only that the film quality as the gate insulating film is good, but also that it can reduce the interface level density between the gate insulating film and the oxide semiconductor and form a good interface.

[0102] Moreover, by using an inorganic material containing oxygen for the insulating film 133, even if oxygen deficiency occurs in the active layer 132 and the active layer 136 due to heat treatment for reducing moisture or hydrogen, oxygen can be supplied from the insulating film 133 to the active layer 132 and the active layer 136, reducing the oxygen deficiency serving as a donor and making the composition ratio stoichiometric. Therefore, the active layer 13 2 and the active layer 136 can be made closer to the i-type, reducing the variation in the electrical characteristics of the transistor due to oxygen deficiency and realizing an improvement in the electrical characteristics. In addition, the oxide semiconductor film used as the active layer 132 or the active layer 136 has a film thickness of 2 nm or more. In any case, it is necessary not only that the film quality as the gate insulating film is good, but also that it can reduce the interface level density between the gate insulating film and the oxide semiconductor and form a good interface. Moreover, by using an inorganic material containing oxygen for the insulating film 133, even if oxygen deficiency occurs in the active layer 132 and the active layer 136 due to heat treatment for reducing moisture or hydrogen, oxygen can be supplied from the insulating film 133 to the active layer 132 and the active layer 136, reducing the oxygen deficiency serving as a donor and making the composition ratio stoichiometric. Therefore, the active layer 13 .

[0103] Also, by using an inorganic material containing oxygen for the insulating film 133, even if oxygen deficiency has occurred in the active layer 132 and the active layer 136 due to heat treatment for reducing moisture or hydrogen, oxygen can be supplied from the insulating film 133 to the active layer 132 and the active layer 136, reducing the oxygen deficiency serving as a donor and making the composition ratio stoichiometric. Thus, the active layer 132 and the active layer 136 can be made closer to the i-type, reducing the variation in the electrical characteristics of the transistor due to oxygen deficiency and realizing an improvement in the electrical characteristics. Moreover, the oxide semiconductor film used as the active layer 132 or the active layer 136 has a film thickness of 2 nm or more. Therefore, the active layer 13 2 and the active layer 136 can be made closer to the i-type, reducing the variation in the electrical characteristics of the transistor due to oxygen deficiency and realizing an improvement in the electrical characteristics. That is, the variation in the electrical characteristics of the transistor due to oxygen deficiency can be reduced, and an improvement in the electrical characteristics can be achieved.

[0104] In addition, the oxide semiconductor film used as the active layer 132 or the active layer 136 has a film thickness of 2 nm or more. Less than 200 nm, preferably a film thickness of 3 nm or more and 50 nm or less, more preferably a film thickness of 3 nm or more and 20 nm or less. The oxide semiconductor film is formed using an oxide semiconductor as a target by sputtering method. Further, the oxide semiconductor film can be formed by sputtering in a rare gas (e.g., argon) atmosphere , an oxygen atmosphere, or a mixed atmosphere of a rare gas (e.g., argon) and oxygen. It can be formed by the method.

[0105] As described above, the oxide semiconductor film includes a quaternary metal oxide In-Sn-Ga-Zn -O-based oxide semiconductor, a ternary metal oxide In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-G a-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn -O-based oxide semiconductor, a binary metal oxide In-Zn-O-based oxide semiconductor, Sn- Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor , Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn-O-based oxide semiconductor, etc. can be used.

[0106] For example, when using a thin film of an In-Ga-Zn-O-based oxide semiconductor obtained by sputtering as an oxide semiconductor film, as a target, for example, a target having a composition ratio of In2O3:Ga2O3:Z nO = 1:1:1 [mole ratio] is used. Also, a target having a composition ratio of In2O 3:Ga2O3:ZnO = 1:1:2 [mole ratio], and also a target having In2O3:Ga2O3:ZnO = 1:1:4 [mole ratio] is used It is possible. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more 100% or less, preferably 95% or more and less than 100%. Using a target with a high filling rate results in a dense oxide semiconductor film being formed.

[0107] When using an In-Zn-O-based material as the oxide semiconductor, the composition ratio of the target used is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (when converted to molar ratio, In2O3 :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (when converted to molar ratio In2O3:ZnO = 10:1 to 2:1), more preferably In:Zn = 1 .5:1 to 15:1 (when converted to molar ratio, In2O3:ZnO = 3:4 to 15:2). For example, for the target used to form an In-Zn-O-based oxide semiconductor, when the atomic ratio is In:Zn:O = X:Y:Z, then Z > 1.5X + Y. By keeping the ratio of Zn within the above range it is possible to achieve an improvement in mobility.

[0108] Note that in the oxide semiconductor film formed by sputtering or the like, there may be a large amount of moisture or hydrogen as impurities. Since moisture or hydrogen easily forms donor levels, it is an impurity for the oxide semiconductor. Therefore, in one aspect of the present invention, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film, the oxide semiconductor film is heat-treated in an atmosphere of nitrogen, oxygen, ultra-dry air, or a noble gas (argon, helium, etc.). The above gas desirably has a water content of 20 ppm or less, preferably 1 ppm or less, preferably 1 0 ppb or less.

[0109] ​​​​By subjecting the oxide semiconductor film to heat treatment, moisture or hydrogen in the oxide semiconductor film can be desorbed. Specifically, heat treatment may be performed at 300°C or higher and 700°C or lower, preferably 300°C or higher and 50 0°C or lower. For example, it may be performed at about 500°C for 3 minutes or more and 6 minutes or less. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate.

[0110] The heat treatment apparatus may be, in addition to an electric furnace, an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid T hermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used.

[0111] By the above-described heat treatment, the concentration of hydrogen in the oxide semiconductor film can be reduced and purified. Thereby, the characteristics of the oxide semiconductor film can be stabilized. Also, by heat treatment below the glass transition temperature, an oxide semiconductor film with a small carrier density due to hydrogen and a wide bandgap can be formed. Therefore, using a large-area substrate, a transistor​​​ 102. The transistor 103 can be manufactured, and mass productivity can be enhanced.

[0112] When heating the oxide semiconductor film, depending on the material and heating conditions of the oxide semiconductor film, plate-like crystals may be formed on its surface. The plate-like crystals are preferably single crystals with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Also, even if they are not single crystals, it is preferable that each crystal is a polycrystal with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Moreover, in addition to the c-axis orientation, it is preferable that the ab planes of each crystal coincide, or the a-axis or the b-axis coincides. When there are irregularities on the underlying surface of the oxide semiconductor film, the plate-like crystals become polycrystals. Therefore, it is desired that the underlying surface is as flat as possible. In one aspect of the present invention, the transistor 103 including an oxide semiconductor in the active layer 132 is used as a switching element for controlling the charge retention in the transistor 102 or the capacitor element 104 used as a memory element, thereby preventing the leakage of the above charge. Also, by sandwiching the active layer 132 with a light-shielding layer such as an electrode having light-shielding properties, a conductive film, or an insulating film, the deterioration of the characteristics of the transistor 103 due to light can be prevented. Specifically, the shift of the threshold voltage can be suppressed, and the increase in the off-current can be prevented. Furthermore, in one aspect of the present invention, the electrode having light-shielding properties is used as the electrode 112 or the electrode 114 of the capacitor element 104. Therefore, since the capacitor element 104 and the transistor 103 are arranged in the memory cell 101 so as to overlap, the exclusive area or the capacitance value of the capacitor element 104 can be ensured.

[0113] ​​​​​​​​​​​​​At the same time, the area occupied by the memory cells 101 can be reduced.

[0114] Therefore, a storage device according to one embodiment of the present invention can secure a data retention period while simply Alternatively, the present invention provides a method for manufacturing a semiconductor memory device, the method comprising: By using the semiconductor device, the reliability and functionality of the semiconductor device can be improved.

[0115] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0116] (Embodiment 3) In this embodiment, the transistor 103 functioning as a switching element is An example of a different configuration will be described.

[0117] FIG. 5A illustrates an example of a cross-sectional view of the transistor 103 and the capacitor 104. 5(A) shows the cross-sectional structure of the memory cell 101 shown in FIG. 1(A), but FIG. The transistor 103 and the capacitor 105 included in the semiconductor device 100 also have the same structure as that shown in FIG. It is possible.

[0118] In the cross-sectional view shown in FIG. 5A, similarly to FIG. 1D, A capacitor 104 and a transistor 103 are formed. 103 overlaps with an insulating film 111 sandwiched therebetween.

[0119] The specific configuration of the capacitor 104 is the same as that shown in FIG. 1(D) in that the gate 103 has a channel protection structure.

[0120] The transistor 103 shown in Fig. 5(A) includes a gate electrode 150 on an insulating film 111, a n insulating film 151 on the gate electrode 150, an active layer 152 containing an oxide semiconductor that overlaps the gate electrode 150 on the insulating film 151, a channel protection film 153 formed on the active layer 152 at a position overlapping the gate electrode 150, a source electrode 154 and a drain electrode 155 formed on the active layer 152. Further, the transistor 103 may include an insulating film 156 formed on the source electrode 154, the drain electrode 155, and the channel protection film 153 and the active layer 152 in its

[0121] components. By providing the channel protection film 153, it is possible to prevent damage such as film loss due to plasma or an etchant during etching in a later process to the portion that becomes the channel formation region of the active layer 152. Therefore, the reliability of the transistor can be improved.

[0122] By using an inorganic material containing oxygen for the channel protection film 153, even if oxygen deficiency occurs in the active layer 152 due to a heat treatment for reducing moisture or hydrogen, oxygen can be supplied from the channel protection film 153 to the active layer 152 to reduce oxygen deficiency serving as a donor and achieve a stoichiometric composition ratio. Thus, the active layer 152 can be made closer to the i-type, variations in the electrical characteristics of the transistor due to oxygen deficiency can

[0123] be reduced, and improvements in electrical characteristics such as high breakdown voltage This is also acceptable. The back gate electrode is formed so as to overlap with the channel formation region of the active layer 152. The back gate electrode may be in a floating state that is electrically insulated, or it may be in a state where a potential is applied. In the latter case, the back gate electrode may be given the same potential as the gate electrode 150, or a fixed potential such as ground may be applied. By controlling the height of the potential applied to the back gate electrode, the threshold voltage of the transistor 103 can be controlled. 103 can be controlled.

[0124] And in Fig. 5(A), a wiring 123 is formed of a conductive film having light-shielding properties, and in that it covers the transistor 103 with the wiring 123, it is the same as Fig. 1(D). Specifically, a light-shielding wiring 123 is formed so as to overlap with the active layer 152 of the transistor 103. a light-shielding wiring 123 is formed so as to overlap with the active layer 152 of the transistor 103. is formed.

[0125] Furthermore, in Fig. 5(A), similar to Fig. 1(D), at least one of the electrodes 112 or the electrode 114 included in the capacitor element 104 has light-shielding properties. And the light-shielding electrode 112 or the electrode 114 is formed at a position overlapping with the active layer 152 of the transistor 103.

[0126] With the above configuration, in Fig. 5(A), since the active layer 152 is sandwiched between the light-shielding electrode 112 or the electrode 114 and the light-shielding wiring 123, light in the vicinity of the absorption edge wavelength of the oxide semiconductor, or light in a wavelength region shorter than this, can be prevented from entering the active layer 152. wiring 123, light in the vicinity of the absorption edge wavelength of the oxide semiconductor, or light in a wavelength region shorter than this, can be prevented from entering the active layer 152. can be prevented.

[0127] Also, another example of a configuration different from Fig. 1(D) of the transistor 103 that functions as a switching element will be described. Another example of a configuration different from Fig. 1(D) of the transistor 103 that functions as a switching element will be described.

[0128] FIG. 5(B) shows an example of a cross-sectional view of the transistor 103 and the capacitor element 104. Note that in FIG. 5(B), the cross-sectional structure of the memory cell 101 shown in FIG. 1(A) is shown, but the transistor 103 and the capacitor element 105 included in FIG. 1(B) can also adopt the same configuration as that in FIG. 5(B). This can be done.

[0129] In the cross-sectional view shown in FIG. 5(B), similar to FIG. 1(D), on a substrate 110 having an insulating surface, the capacitor element 104 and the transistor 103 are formed, and the capacitor element 104 and the transistor 103 overlap with the insulating film 111 interposed therebetween.

[0130] The specific configuration of the capacitor element 104 is the same as that in FIG. 1(D). In FIG. 5(B), the transistor 103 is of the bottom gate type, and in addition, the source electrode or the drain electrode is in contact with the active layer at the lower side, which is different from FIG. 1(D) in that it is a bottom contact structure.

[0131] The transistor 103 shown in FIG. 5(B) has a gate electrode 160 on the insulating film 111, an insulating film 161 on the gate electrode 160, a source electrode 164 and a drain electrode 165 formed on the insulating film 161, and an active layer 162 including an oxide semiconductor formed at a position overlapping the gate electrode 160 on the insulating film 161 and in contact with the source electrode 164 and the drain electrode 165. Further, the transistor 103 may include an insulating film 166 formed on the source electrode 164, the drain electrode 165, and the active layer 162 in its components. Moreover, by using an inorganic material containing oxygen for the insulating film 166 in contact with the active layer 162, water

[0132] can be prevented. Oxygen vacancies have occurred in the active layer 162 due to the heat treatment for reducing the amount of oxygen or hydrogen. Even if this happens, oxygen is supplied to the active layer 162 from the insulating film 166, and oxygen vacancies that become donors are reduced. Therefore, the active layer 162 can be formed by reducing the amount of the stoichiometric composition. The transistor 103 can be made closer to an i-type structure, and variations in the electrical characteristics of the transistor 103 due to oxygen vacancies can be reduced. This can reduce the electrical resistance and improve the electrical characteristics.

[0133] The transistor 103 further includes a back gate electrode on the insulating film 166. The back gate electrode is formed so as to overlap the channel forming region of the active layer 162. The back gate electrode may be in an electrically insulating floating state, In the latter case, the back gate electrode may be in a state where a potential is applied. The same potential as 160 may be given, or a fixed potential such as ground may be given. By controlling the potential applied to the back gate electrode, the transistor The threshold voltage of 103 can be controlled.

[0134] In FIG. 5B, a wiring 123 is formed using a conductive film having a light-shielding property. 1(D) in that the transistor 103 is covered by the insulating film 104. Specifically, A light-shielding wiring 123 is formed so as to overlap with the active layer 162 of the transistor 103. do.

[0135] 5B, similarly to FIG. 1D, the electrode 112 or At least one of the electrodes 112 and 114 has a light-shielding property. Alternatively, an electrode 114 is formed at a position overlapping with an active layer 162 of the transistor 103 .

[0136] With the above configuration, in FIG. 5(B), the active layer 162 is sandwiched between the light-shielding electrode 112 or electrode 114 and the light-shielding wiring 123, so that light in the vicinity of the absorption edge wavelength of the oxide semiconductor or light in a wavelength region shorter than this can be prevented from entering the active layer 162. This is possible.

[0137] In FIGS. 5(A) and 5(B), the configuration in which the active layer 152 or the active layer 1 62 is shielded from light using the wiring 123 is taken as an example. However, similar to the configuration shown in FIG. 1(C), an insulating film having light-shielding properties may be used to shield the active layer 152 or the active layer 162 from light.

[0138] Also, in FIGS. 5(A) and 5(B), the case where the transistor 103 has a single gate structure is illustrated. However, the transistor 103 may have a multi-gate structure having a plurality of channel formation regions by having a plurality of electrically connected gate electrodes.

[0139] This embodiment can be implemented in appropriate combination with the above embodiment.

[0140] (Embodiment 4) In this embodiment, a specific configuration of the memory unit and its operation will be described.

[0141] FIG. 6 is an example of a circuit diagram of a memory unit 200 having a plurality of memory cells 101 shown in FIG. 2(A). Regarding the configuration of the memory cell 101, the content described in Embodiment 1 can be referred to. This can be considered.

[0142] In the memory unit 200 shown in FIG. 6, various wirings such as a plurality of word lines WL and a plurality of data lines DL ​​​​​is provided, and a signal or a fixed potential from the drive circuit is supplied to each memory via these wirings. The number of the wirings can be determined according to the number and arrangement of the memory cells 101.

[0143] Specifically, in the case of the storage unit 200 shown in FIG. 6, memory cells in a 3-row × 4-column matrix are connected, and word lines WL1 to WL3 and data lines DL1 to DL4 are arranged in the storage unit 200 as an example.

[0144] Next, the operation of the storage unit 200 shown in FIG. 6 will be described.

[0145] First, the operation of the storage unit 200 during data writing will be described. When a signal having a pulse is input to the word line WL1 during writing, the potential of the pulse, specifically, the high-level potential, is applied to the gate electrode of the transistor 103 connected to the word line WL1. Therefore, all the transistors 103 having their gate electrodes connected to the word line WL1 are turned on.

[0146] Next, signals including data as information are input to the data lines DL1 to DL4. The potential levels of the signals input to the data lines DL1 to DL4 naturally differ depending on the content of the data. The potential input to the data lines DL1 to DL4 is applied to one electrode of the capacitive element 105 through the on transistors 103. Then, by controlling the amount of charge stored in the capacitive element 105 according to the potential of the signal, data is written into the capacitive element 105.

[0147] When the input of the signal having a pulse to the word line WL1 ends, the gate of the transistor connected to the word line WL1​​​​​​​​​​​​ All the transistors 103 to which electrodes are connected are turned off. Then, a signal having a pulse is sequentially input to the word line WL2 , the word line WL3, and the above-described operation is repeated in the memory cell 101 having the word line WL2 , the memory cell 101 having the word line WL3. is repeated in the same manner.

[0148] Next, the operation of the storage unit 200 during data retention will be described. During retention , a potential at a level at which the transistor 103 is turned off, specifically, a low-level potential, is applied to all the word lines WL1 to WL3. Since the off-state current of the transistor 103 is extremely low as described above, the charge stored in the capacitive element 105 is less likely to leak, and compared with the case where light shielding is not performed or when a semiconductor material such as silicon is used for the transistor 103 , data can be retained for a long period of time.

[0149] Next, the operation of the storage unit 200 during data readout will be described. At the time of data readout , similar to the writing time, a signal having a pulse is sequentially input to the word lines WL1 to WL3. When the potential of the pulse, specifically, a high-level potential, is applied to the gate electrode of the transistor 103 connected to the word line WL1, all the transistors 103 become turned on.

[0150] When the transistor 103 is turned on, the charge stored in the capacitive element 105 is taken out via the data line DL. Then, by reading the difference in the amount of the charge, data can be read out

[0151] Note that a readout circuit is connected to the end of each data line DL, and the output signal of the readout circuit includes the data actually read from the memory unit.

[0152] In this embodiment, the operations of writing, holding, and reading are sequentially performed on a plurality of memory cells 101 and the driving method therefor has been described. However, the present invention is not limited to this configuration. The above operations may be performed only on the memory cell 101 of the designated address.

[0153] Also, in the case of the memory unit 200 shown in FIG. 6, the case where three wirings, i.e., a data line DL, a word line WL, and a wiring for supplying a fixed potential to the electrode of the capacitor element 105, are connected to each memory cell 101 is exemplified. However, in one aspect of the present invention, the number of wirings each memory cell has is not limited to this. A signal for controlling the switching of the transistor 103, a signal for controlling the charge amount of the capacitor element 105, and a fixed potential can be supplied to the memory cell 101, and furthermore, the potential including the charge amount accumulated in the capacitor element 105 as information can be sent to the drive circuit. The number of wirings and the connection structure may be appropriately determined so that this can be achieved.

[0154] This embodiment can be implemented in appropriate combination with the above embodiment.

[0155] (Embodiment 5) In this embodiment, a specific configuration of the memory unit and its operation will be described.

[0156] FIG. 7 is an example of a circuit diagram of a memory unit 201 having a plurality of memory cells 101 shown in FIG. 2(C). Regarding the configuration of the memory cell 101, reference can be made to the content described in Embodiment 1.

[0157] ​​​​In the memory unit 201 shown in FIG. 7, a plurality of first word lines WLa, a plurality of second word lines WLb, and various wirings such as a plurality of data lines DL are provided, and signals or fixed potentials from the drive circuit are supplied to each memory cell 101 via these wirings. The number of the above wirings can be determined according to the number and arrangement of the memory cells 101.

[0158] Specifically, in the case of the memory unit 201 shown in FIG. 7, memory cells in a 3-row × 3-column matrix are connected, and the first word lines WLa1 to WLa3, the second word lines WLb1 to WLb3, and the data lines DL1 to DL3 are arranged in the memory unit 201 as an example.

[0159] Next, the operation of the memory unit 201 shown in FIG. 7 will be described. FIG. 8 is a timing chart showing the time change of the potential of the signals input to the plurality of first word lines WLa1 to WLa3, the plurality of second word lines WLb1 to WLb3, and the plurality of data lines DL1 to DL3. The timing chart shown in FIG. 8 illustrates the case where both the transistor 102 and the transistor 103 are of n-channel type and handle binary data.

[0160] Note that the potential of the signal in the timing chart is shown such that the rise or fall is vertical. However, since the actual potential of the signal is affected by factors such as the load of the wiring and noise, it is easily understood by those skilled in the art that the waveform of the signal will be smoothed.

[0161] First, the operation of the memory unit 201 during data writing will be described. When writing, when a signal having a pulse is input to the first word line WLa1, the potential of the pulse , specifically, a high-level potential is applied to the gate electrodes of the transistors 103 connected to the first word line WLa1. Therefore, all the transistors 103 whose gate electrodes are connected to the first word line WLa1 are turned on. On the other hand, a low-level potential is applied to the second word lines WLb1 to WLb 3.

[0162] Next, signals containing data as information are input to the data lines DL1 to DL3. The level of the potential of the signals input to the data lines DL1 to DL3 naturally varies depending on the content of the data . The potential applied to the data lines DL1 to DL3 is applied to the gate electrode of the transistor 102 and one electrode of the capacitor element 104 through the turned-on transistor 103. Then, according to the potential of the above signal, by controlling the gate capacitance of the transistor 102 and the amount of charge stored in the capacitor element 104, data is written into the memory cell 101. is performed.

[0163] When the input of the signal having a pulse to the first word line WLa1 ends, all the transistors 103 whose gate electrodes are connected to the first word line WL a1 are turned off. Then, signals having pulses are sequentially input to the first word line WLa2 and the first word line WLa3, and in the memory cell 101 having the first word line WLa2 and the memory cell 101 having the first word line WLa3, the above-described operations are repeated in the same manner.

[0164] Next, the operation of the storage unit 201 during data retention will be described. During retention, , at all the first word lines WLa1 to WLa3, the transistors 103 are at a level where they are turned off. A potential, specifically a low-level potential, is applied. Since the transistor 103 has an extremely low off-current as described above, the gate capacitance of the transistor 102 and the charge stored in the capacitive element 104 are less likely to leak, and data can be retained for a longer period compared to the case where no light shielding is performed or when a semiconductor material such as silicon is used for the transistor 103. As the off-current is extremely low as described above, the gate capacitance of the transistor 102 and the charge stored in the capacitive element 104 are less likely to leak, and data can be retained for a longer period compared to the case where no light shielding is performed or when a semiconductor material such as silicon is used for the transistor 103. On the other hand, a low-level potential is continuously applied to the second word lines WLb1 to WLb3. Next, the operation of the memory unit 201 during data reading will be described. At the time of data reading, a low-level potential is input to all of the first word lines WLa1 to WLa3, so that a low-level potential is applied to the gate electrode of the transistor 103. Therefore, the transistors 103 whose gate electrodes are connected to the first word lines WLa1 to WLa3 all remain off. On the other hand, a signal having a pulse is input to the second word line WLb1, and the potential of the pulse, specifically a high-level potential, is applied to the other electrode of the capacitive element 104. Since the potential difference between the pair of electrodes of the capacitive element 104 is maintained by the charge conservation law, the change in the potential of the second word line WLb1 is applied to the gate electrode of the transistor 102. And since the threshold voltage of the transistor 102 changes according to the amount of charge stored in its gate capacitance, a drain current of a magnitude corresponding to the amount of charge stored in its gate capacitance flows through the transistor 102. Therefore, the magnitude of the drain current of the transistor 102

[0165] A low-level potential is continuously applied to the second word lines WLb1 to WLb3. .

[0166] Next, the operation of the memory unit 201 during data reading will be described. At the time of data reading, a low-level potential is input to all of the first word lines WLa1 to WLa3, so that a low-level potential is applied to the gate electrode of the transistor 103. Therefore, the transistors 103 whose gate electrodes are connected to the first word lines WLa1 to WLa3 all remain off.

[0167] On the other hand, a signal having a pulse is input to the second word line WLb1, and the potential of the pulse, specifically a high-level potential, is applied to the other electrode of the capacitive element 104. Since the potential difference between the pair of electrodes of the capacitive element 104 is maintained by the charge conservation law, the change in the potential of the second word line WLb1 is applied to the gate electrode of the transistor 102. And, since the threshold voltage of the transistor 102 changes according to the amount of charge stored in its gate capacitance, a drain current of a magnitude corresponding to the amount of charge stored in its gate capacitance flows through the transistor 102. Therefore, the magnitude of the drain current of the transistor 102 From this, by reading the difference in the amount of stored charge, data can be read out from the data line DL. can be read out.

[0168] When the input of a signal having a pulse to the second word line WLb1 ends, all the transistors 102 of the memory cell 101 having the second word line WL b1 turn off. Then, a signal having a pulse is sequentially input to the second word line WLb2 and the second word line WLb3, and the memory cell 101 having the second word line WLb2 and the memory cell 1 01 having the second word line WLb3, the above-described operation is repeated in the same manner. 01 having the second word line WLb3, the above-described operation is repeated in the same manner. 01, the above-described operation is repeated in the same manner.

[0169] Note that a read circuit is connected to the ends of the data lines DL1 to DL3, and the output signal of the read circuit includes the data actually read from the storage unit 201.

[0170] In the present embodiment, the driving method of sequentially performing the writing, holding, and reading operations on a plurality of memory cells 101 has been described, but the present invention is not limited to this configuration. The above operations may be performed only on the memory cell 101 of the specified address. In the present embodiment, the driving method of sequentially performing the writing, holding, and reading operations on a plurality of memory cells 101 has been described, but the present invention is not limited to this configuration. The above operations may be performed only on the memory cell 101 of the specified address. In the present embodiment, the driving method of sequentially performing the writing, holding, and reading operations on a plurality of memory cells 101 has been described, but the present invention is not limited to this configuration. The above operations may be performed only on the memory cell 101 of the specified address.

[0171] Further, in the case of the storage unit 201 shown in FIG. 7, the case where four wirings, i.e., the first word line WLa, , the second word line WLb, the data line DL, and the wiring for supplying a fixed potential to the transistor 102, are connected to each memory cell 101 is exemplified. However, in one aspect of the present invention the number of wirings included in each memory cell is not limited to this. A signal for controlling the switching of the transistor 103, a signal for controlling the amount of charge accumulated in the gate capacitance of the transistor 102, and a fixed potential can be supplied to the memory cell 101, and the number of wirings included in each memory cell is not limited to this. A signal for controlling the switching of the transistor 103, a signal for controlling the amount of charge accumulated in the gate capacitance of the transistor 102, and a fixed potential can be supplied to the memory cell 101, and the number of wirings included in each memory cell is not limited to this. A signal for controlling the switching of the transistor 103, a signal for controlling the amount of charge accumulated in the gate capacitance of the transistor 102, and a fixed potential can be supplied to the memory cell 101, and the number of wirings included in each memory cell is not limited to this. A signal for controlling the switching of the transistor 103, a signal for controlling the amount of charge accumulated in the gate capacitance of the transistor 102, and a fixed potential can be supplied to the memory cell 101, and The potential including the amount of charge accumulated in the gate capacitance as information is sent to the drive circuit. The number of wirings and the connection structure may be appropriately determined so that this can be achieved.

[0172] This embodiment can be implemented in appropriate combination with the above-described embodiment.

[0173] (Embodiment 6) FIG. 9 shows, as an example, a block diagram of the configuration of a memory device according to an aspect of the present invention. In FIG. 9 The memory device 300 shown includes a storage unit 301 provided with a plurality of memory cells, and a drive circuit 302 that controls the operation of the storage unit 301.

[0174] The drive circuit 302 can control various operations such as writing data to the storage unit 301, reading data from the storage unit 301, and holding data in the storage unit 301, according to signals from the control circuit.

[0175] In FIG. 9, it is assumed that the control circuit that supplies signals to the drive circuit 302 is provided outside the memory device 300 and not included in the memory device 300, but the control circuit may be included in the components of the memory device.

[0176] Next, an example of a specific configuration of the drive circuit of a memory device according to an aspect of the present invention will be described.

[0177] FIG. 10 shows, as an example, a block diagram of a specific configuration of a memory device according to an aspect of the present invention. Note that, in the block diagram shown in FIG. 10, the circuits in the memory device are classified by function and shown as independent blocks, but in actuality, it is difficult to completely separate the circuits by function, and one circuit may be related to multiple functions.

[0178] The memory device 300 shown in FIG. 10 has a memory unit 301 and a drive circuit 302. The drive circuit 302 includes a read circuit 303 that generates a signal containing data read from the memory unit 301 as information, a word line drive circuit 304 that selects the memory cells of the memory unit 301 row by row, and a data line drive circuit 305 that controls writing of data in the selected memory cells in the memory unit 301. And the drive circuit 302 has a control circuit 306 that controls the operations of the read circuit 303, the word line drive circuit 304, and the data line drive circuit 305.

[0179] Also, in the memory device 300 shown in FIG. 10, the word line drive circuit 304 has a decoder 307, a level shifter 308, and a buffer 309. The data line drive circuit 305 has a decoder 310, a level shifter 311, and a selector 312.

[0180] Note that the memory device 300 according to one aspect of the present invention only needs to include at least the memory unit 301 in its configuration. Further, the memory device 300 according to one aspect of the present invention includes, in its scope, a memory module in a state where a part or all of the drive circuit 302 is connected to the memory unit 301. The memory module may be in a so-called packaged state provided with connection terminals that can be mounted on a printed wiring board or the like and further protected with resin or the like.

[0181] Also, the memory unit 301, the read circuit 303, the word line drive circuit 304, the data line drive circuit 305, and the control circuit 306 may all be formed using a single substrate, or any one or all of them may be formed using mutually different substrates.

[0182] When using different substrates, electrical connection can be ensured via an FPC (Flexible Printed Circuit) or the like. In this case, a part of the drive circuit 302 may be connected to the FPC using the COF (Chip On Film) method. it) etc. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. or, using the COG (Chip On Glass) method, electrical connection can be ensured. This can be done.

[0183] When a signal AD including the addresses (Ax, Ay) of the storage unit 301 as information is input to the storage device 300, the control circuit 306 sends the column - direction address Ax to the data - line drive circuit 305 and the row - direction address Ay to the word - line drive circuit 304. Also, the control circuit 306 sends a signal DATA including the data input to the storage device 300 as information to the data - line drive circuit 305. In addition, the control circuit 306 sends the column - direction address Ax to the data - line drive circuit 305 and the row - direction address Ay to the word - line drive circuit 304. Also, the control circuit 306 sends a signal DATA including the data input to the storage device 300 as information to the data - line drive circuit 305. 305.

[0184] The selection of the data writing operation and reading operation in the storage unit 301 is selected by signals RE (Read enable), WE (Write enable ) etc. supplied to the control circuit 306. Further, when there are a plurality of storage units 301, a signal CE (Chip enable) for selecting the storage unit 301 may be input to the control circuit 306. In this case, the operation selected by the signals RE and WE is executed in the storage unit 301 selected by the signal CE. ) etc. to the control circuit 306. In this case, the operation selected by the signals RE and WE is executed in the storage unit 301 selected by the signal CE. In this case, the operation selected by the signals RE and WE is executed in the storage unit 301 selected by the signal CE.

[0185] In the storage unit 301, when the writing operation is selected by the signal WE, according to the instruction from the control circuit 306, in the decoder 307 of the word - line drive circuit 304, the address A follows. A signal for selecting the memory cell corresponding to y is generated. This signal is sent to the level shifter 308, where its amplitude is adjusted. Then, the waveform is processed in the buffer 309 and input into the storage unit 3 01. On the other hand, in the data line driving circuit 305, according to the instruction from the control circuit 306 , a signal for selecting the memory cell corresponding to the address Ax among the memory cells selected in the decoder 310 is generated. This signal is sent to the level shifter 311 where its amplitude is adjusted, and then input into the selector 312. In the selector 312, the signal DATA is sampled according to the input signal, and the sampled signal is input into the memory cell corresponding to the address (Ax, Ay).

[0186] Also, in the storage unit 301, when the read operation is selected by the signal RE, according to the instruction from the control circuit 30 6, a signal for selecting the memory cell corresponding to the address Ay is generated in the decoder 307 of the word line driving circuit 304. This signal is sent to the level shifter 308 where its amplitude is adjusted, then the waveform is processed in the buffer 309 and input into the storage unit 301. On the other hand, in the read circuit 303, according to the instruction from the control circuit 306 , the memory cell corresponding to the address Ax among the memory cells selected by the decoder 307 is selected. Then, the data stored in the memory cell corresponding to the address (Ax, Ay) is read out, and a signal containing this data as information is generated.

[0187] This embodiment can be implemented in appropriate combination with the above embodiments.

[0188] (Embodiment 7) In this embodiment, an example of the specific configuration of the read circuit will be described.​​​​​​​

[0189] The potential read from the memory section is determined according to the data written in the memory cell. Therefore, ideally, the same digital value data is stored in multiple memory cells. If so, the potentials read from multiple memory cells should all be at the same level. However, in reality, the transistors that function as memory elements or the transistors that are used for reading data are The characteristics of the transistors that function as switching elements in the memory cells vary. In this case, even if all the data to be read is the same digital value, However, since the potential actually read out varies, the distribution has a certain range. Even if there is some variation in the potential read from the memory, accurate data is stored as information. and a readout circuit that produces a signal whose amplitude and waveform have been processed to meet desired specifications. Preferably, a path is provided in the drive circuit.

[0190] An example of a readout circuit is shown in the circuit diagram of FIG. 11. The readout circuit shown in FIG. A switching circuit for controlling the input of the potential Vdata read out from the A transistor 260 that functions as an element and a transistor 261 that functions as a resistor are provided. 11 also includes an operational amplifier 262.

[0191] Specifically, the transistor 261 has its gate electrode and drain electrode (or drain region) is connected, and a high level is applied to the gate electrode and the drain electrode. The source electrode of the transistor 261 is connected to the power supply potential Vdd. It is connected to the non-inverting input terminal (+) of the amplifier 262. Therefore, the transistor 261 , between the node to which the power supply potential Vdd is applied and the non-inverting input terminal (+) of the operational amplifier 262 functions as a resistor. In FIG. 11, a transistor with its gate electrode and drain electrode connected is used as a resistor, but the present invention is not limited to this, and any element that functions as a resistor can be substituted.

[0192] Also, the transistor 260 that functions as a switching element has its gate electrode connected to the bit lines BL1 to BL3 respectively. And, according to the potentials of the bit lines BL1 to BL3, the supply of the potential Vdata to the source electrode of the transistor 260 is controlled.

[0193] For example, when the transistor 260 connected to the bit line BL1 is turned on, the potential obtained by resistively dividing the potential Vdata and the power supply potential Vdd by the transistors 260 and 261 is applied to the non-inverting input terminal (+) of the operational amplifier 262. And, since the level of the power supply potential Vdd is fixed, the level of the potential obtained by resistive division reflects the level of the potential Vdata, that is, the digital value of the read data.

[0194] On the other hand, a reference potential Vref is applied to the inverting input terminal (-) of the operational amplifier 262. And, depending on whether the potential applied to the non-inverting input terminal (+) is higher or lower than the reference potential Vref, the level of the potential Vout at the output terminal can be made different, whereby a signal indirectly containing data as information can be obtained.

[0195] Even for memory cells storing data of the same value, due to variations in characteristics among the memory cells, variations also occur in the level of the read potential Vdata, and its distribution may have a width. Therefore, the level of the reference potential Vref is determined in consideration of the variations in the potential Vdata of the node in order to accurately read the value of the data. Also, in FIG. 11, since it is an example of a read circuit for handling binary digital values, one operational amplifier is used for each node to which the potential Vdata is applied, but the number of operational amplifiers is not limited to this. When handling n-valued (n is a natural number of 2 or more) data, the number of operational amplifiers for each node to which the potential Vdata is applied is set to n - 1. This embodiment can be implemented in appropriate combination with the above embodiment.

[0196] In (Embodiment 8), an example of calculating the off-current of a transistor will be described.

[0197]

[0198] First, the configuration of the characteristic evaluation circuit used for calculating the off-current will be described with reference to FIG. 12. In this embodiment, the characteristic evaluation circuit includes a plurality of measurement systems 801 connected in parallel to each other. Specifically, FIG. 12 illustrates a characteristic evaluation circuit in which eight measurement systems 801 are connected in parallel.

[0199]

[0200]

[0201] The measurement system 801 includes a transistor 811, a transistor 812, a capacitive element 813, a transistor 814, and a transistor 815.

[0201] ​​​​​​​​Transistor 811 is a transistor for charge injection. And transistor 811 has its first terminal connected to the node supplied with potential V1, and its second terminal is connected to the first terminal of transistor 812. The gate electrode of transistor 811 is connected to the node supplied with potential Vext_a.

[0202] Transistor 812 is a transistor for leakage current evaluation. Note that in this embodiment the leakage current includes the off-current of the transistor. And transistor 81 2 has its first terminal connected to the second terminal of transistor 811, and its second terminal is connected to the node supplied with potential V2. The gate electrode of transistor 812 is connected to the node supplied with potential Vext_b.

[0203] The first electrode of capacitor element 813 is connected to the second terminal of transistor 811 and the first terminal of transistor 812 The second electrode of capacitor element 813 is connected to the node supplied with potential V2.

[0204] Transistor 814 has its first terminal connected to the node supplied with potential V3 and its second terminal connected to the first terminal of transistor 815. The gate electrode of transistor 814 is connected to the second terminal of transistor 811, the first terminal of transistor 812 and the first electrode of capacitor element 813. Note that the location where the gate electrode of this transistor 814 is connected is defined as node A.

[0205] Transistor 815 has its first terminal connected to the second terminal of transistor 814 Further, the second terminal is connected to a node to which a potential V4 is applied. The transistor The gate electrode of 815 is connected to a node to which a potential Vext_c is applied.

[0206] Then, the measurement system 801 outputs, as the potential Vout of the output signal, the potential of the second terminal of the transistor 814 and the node to which the first terminal of the transistor 815 is connected.

[0207] In this embodiment, as the transistor 811, a transistor including an oxide semiconductor in the active layer is used, and the size of the channel formation region included in the active layer is such that the channel length L = 10 μm and the channel width W = 10 μm.

[0208] Note that the channel formation region corresponds to a region of the semiconductor film that overlaps with the gate electrode with a gate insulating film interposed therebetween, between the source electrode and the drain electrode.

[0209] Also, as the transistors 814 and 815, transistors including an oxide semiconductor in the active layer are used, and the size of the channel formation region included in the active layer is such that the channel length L = 3 μm and the channel width W = 100 μm.

[0210] Also, as the transistor 812, a bottom gate structure transistor including an oxide semiconductor in the active layer, having source electrodes and drain electrodes in contact with the upper part of the active layer, and having no overlap region where the source electrodes and drain electrodes overlap with the gate electrode, and having an offset region with a width of 1 μm is used. By providing the offset region, the parasitic capacitance can be reduced. Furthermore, as the transistor 812, the channel formation region included in the active layer is as follows: ​​Transistors having different sizes are used as shown in Conditions 1 to 6 of Table 1.

[0211]

Table 1

[0212] When the charge injection transistor 811 is not provided in the measurement system 801, when injecting charge into the capacitor element 81 3, it is necessary to turn on the leakage current evaluation transistor 812 once. In this case, if the leakage current evaluation transistor 812 is an element that requires time to reach the steady state from on to off, the measurement takes time. As shown in FIG. 12, by providing the charge injection transistor 811 and the leakage current evaluation transistor 812 separately in the measurement system 80 1, the leakage current evaluation transistor 812 can always be kept off during charge injection. Therefore, the time required for measurement can be shortened. In addition, by providing the charge injection transistor 811 and the leakage current evaluation transistor 812 separately in the measurement system 801, each transistor can be made an appropriate size. Also, by making the channel width W of the leakage current evaluation transistor 812 larger than the channel width W of the charge injection transistor 8 11, the leakage current component in the characteristic evaluation circuit other than the leakage current of the leakage current evaluation transistor 812 can be made relatively small. As a result, the leakage current of the leakage current evaluation transistor 812 can be measured with high precision. At the same time, since it is not necessary to turn on the leakage current evaluation transistor 8

[0213] 12 once during charge injection, a part of the charge in the channel formation region does not flow to the node A Also, by providing the charge injection transistor 811 and the leakage current evaluation transistor 812 separately in the measurement system 801, each transistor can be made an appropriate size. Also, by making the channel width W of the leakage current evaluation transistor 812 larger than the channel width W of the charge injection transistor 8 11, the leakage current component in the characteristic evaluation circuit other than the leakage current of the leakage current evaluation transistor 812 can be made relatively small. As a result, the leakage current of the leakage current evaluation transistor 812 can be measured with high precision. At the same time, since it is not necessary to turn on the leakage current evaluation transistor 8 12 once during charge injection, a part of the charge in the channel formation region does not flow to the node A Thereby, the leakage current component in the characteristic evaluation circuit other than the leakage current of the leakage current evaluation transistor 812 can be relatively reduced. As a result, the leakage current of the leakage current evaluation transistor 812 can be measured with high precision. At the same time, since it is not necessary to turn on the leakage current evaluation transistor 8 12 once during charge injection, a part of the charge in the channel formation region does not flow to the node A 12 once, a part of the charge in the channel formation region does not flow to the node A There is no influence on the potential fluctuation of node A due to the inclusion.

[0214] On the other hand, by making the channel width W of the charge injection transistor 811 smaller than the channel width W of the leakage current evaluation transistor 812, the leakage current of the charge injection transistor 811 can be relatively reduced. Also, during charge injection, the influence on the potential fluctuation of node A due to a part of the charge in the channel formation region flowing into node A is small. The influence on the potential fluctuation of node A due to a part of the charge in the channel formation region flowing into node A is also small.

[0215] Also, as shown in FIG. 12, by adopting a structure in which a plurality of measurement systems 801 are connected in parallel, the leakage current of the characteristic evaluation circuit can be calculated more accurately.

[0216] Next, a specific method for calculating the off-current of a transistor using the characteristic evaluation circuit shown in FIG. 12 will be described.

[0217] First, the leakage current measurement method of the characteristic evaluation circuit shown in FIG. 12 will be described with reference to FIG. 13. FIG. 13 is a timing chart for explaining the leakage current measurement method using the characteristic evaluation circuit shown in FIG. 12. It is a timing chart.

[0218] The leakage current measurement method using the characteristic evaluation circuit shown in FIG. 12 can be divided into a writing period and a holding period. The operations in each period will be described below. Note that in both the writing period and the holding period, the potential V2 and the potential V4 are set to 0 V, the potential V3 is set to 5 V, and the potential Vext_c is set to 0.5 V. Vext_c is set to 0.5 V.

[0219] First, in the writing period, the potential Vext_b is set to a high potential VL (-3 V) at which the transistor 812 is turned off. Also, the potential V1 is set to the writing potential Vw. First, in the writing period, the potential Vext_b is set to a high potential VL (-3 V) at which the transistor 812 is turned off. Also, the potential V1 is set to the writing potential Vw. After that, the potential Vext_a is set to a potential with a height such that the transistor 811 is on for a certain period of time. It is set to VH (5V). With the above configuration, charge is accumulated at node A, and the potential of node A becomes a value equivalent to the write potential Vw. Next, the potential Vext_a is set to a potential VL with a height such that the transistor 8 11 is off. After that, the potential V1 is set to the potential VSS (0 V).

[0220] Next, during the holding period, the change in the potential of node A caused by the change in the amount of charge held by node A is measured. From the change in potential, the current value flowing between the first terminal and the second terminal of the transistor 812 can be calculated. Thus, the charge accumulation at node A and the measurement of the change in the potential of node A can be performed. The measurement of the change in the potential of node A due to the change in the amount of charge held by node A (also referred to as the accumulation and measurement operation) is repeated. First, the first accumulation and measurement operation is repeated 15 times. In the first accumulation and measurement operation, a potential of 5V is input as the write potential Vw during the write period, and a hold of 1 hour is performed during the hold period. Next, the second accumulation and measurement operation is repeated 2 times. In the second accumulation and measurement operation, the write potential Vw is set to 3.5V during the write period, and a hold of 50 hours is performed during the hold period. Next, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . By repeating the accumulation and measurement operations, it can be confirmed that the measured current value is the value in the steady state. In other words, among the current I flowing through node A

[0221] Charge accumulation at node A and measurement of the change in the potential of node A (also referred to as the accumulation and measurement operation) is repeated. First, the first accumulation and measurement operation is repeated 15 times. In the first accumulation and measurement operation, a potential of 5V is input as the write potential Vw during the write period, and a hold of 1 hour is performed during the hold period. Next, the second accumulation and measurement operation is repeated 2 times. In the second accumulation and measurement operation, the write potential Vw is set to 3.5V during the write period, and a hold of 50 hours is performed during the hold period. Next, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . By repeating the accumulation and measurement operations, it can be confirmed that the measured current value is the value in the steady state. In other words, among the current I flowing through node A . Next, the second accumulation and measurement operation is repeated 2 times. In the second accumulation and measurement operation, the write potential Vw is set to 3.5V during the write period, and a hold of 50 hours is performed during the hold period. Next, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . In the second accumulation and measurement operation, the write potential Vw is set to 3.5V during the write period, and a hold of 50 hours is performed during the hold period. Next, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . Next, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . In the third accumulation and measurement operation, the write potential Vw is set to 4.5V during the write period, and a hold of 10 hours is performed . By repeating the accumulation and measurement operations, it can be confirmed that the measured current value is the value in the steady state. In other words, among the current I flowing through node A . That is, among the current I flowing through node A A . Among them, The transient current (the current component that decreases with the passage of time after the start of measurement) can be removed. As a result, the leakage current can be measured with higher accuracy.

[0222] Generally, the potential V of node A A can be expressed as follows as a function of the potential Vout of the output signal. It can be done.

[0223]

Equation

[0224] Also, the charge Q of node A A is the potential V of node A A , the capacitance C connected to node A A , a constant using (const), is expressed as follows. The capacitance C connected to node A A is the sum of the capacitance value of the capacitance element 813 and the capacitance value of the capacitances other than the capacitance element 813.

[0225]

Equation

[0226] The current I of node A A is the time derivative of the charge flowing into node A (or the charge flowing out of node A), so the current I of node A A is expressed as follows.

[0227]

Equation

[0228] For example, let Δt be about 54000 sec. From the capacitance C connected to node A A and the potential Vout of the output signal , the current I of node A ASince it can be obtained, the leakage current of the characteristic evaluation circuit can be obtained.

[0229] Next, the measurement result of the potential Vout of the output signal by the measurement method using the characteristic evaluation circuit and the value of the leakage current of the characteristic evaluation circuit calculated from the measurement result are shown.

[0230] In FIG. 14, as an example, the relationship between the elapsed time Time related to the above measurement (first accumulation and measurement operation) under conditions 1, 2, and 3 and the potential Vout of the output signal is shown. In FIG. 15 the relationship between the elapsed time Time related to the above measurement and the leakage current calculated by the measurement is shown. It can be seen that the potential Vout of the output signal has been fluctuating since the start of the measurement, and it takes 10 hours or more to reach the steady state.

[0231] Also, in FIG. 16, the relationship between the potential of node A and the leakage current under conditions 1 to 6 estimated by the above measurement is shown. In FIG. 16, for example, under condition 4, when the potential of node A is 3. 0V, the leakage current is 28 yA / μm. Since the leakage current also includes the off-current of transistor 812, the off-current of transistor 812 can also be regarded as 28 yA / μm or less.

[0232] As described above, in the characteristic evaluation circuit using a transistor including a highly purified oxide semiconductor layer having a function as a channel formation layer, since the leakage current is sufficiently low, it can be seen that the off-current of the transistor is sufficiently small.

[0233] (Embodiment 9) In this embodiment, an example of the configuration of an RF tag, which is one of the semiconductor devices of the present invention, will be described.

[0234] FIG. 17 is a block diagram showing one form of the RF tag of the present invention. In FIG. 17, the RF tag 5 50 has an antenna circuit 551 and an integrated circuit 552. The integrated circuit 552 includes a power supply circuit 553, a demodulation circuit 554, a modulation circuit 555, a regulator 556, an arithmetic circuit 557 , a storage device 558, and a booster circuit 559.

[0235] Next, an example of the operation of the RF tag 550 will be described. When a radio wave is sent from an interrogator , the radio wave is converted into an AC voltage in the antenna circuit 551. In the power supply circuit 553, the AC voltage from the antenna circuit 551 is rectified to generate a voltage for power supply. The voltage for power supply generated in the power supply circuit 553 is supplied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes or adjusts the height of the voltage for power supply from the power supply circuit 553, and then supplies it to various circuits such as the demodulation circuit 554, the modulation circuit 555, the arithmetic circuit 557, the storage device 558, or the booster circuit 559 in the integrated circuit 552.

[0236] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the subsequent arithmetic circuit 557. The arithmetic circuit 557 performs arithmetic processing according to the signal input from the demodulation circuit 554 and generates a separate signal. When performing the above arithmetic processing, the storage device 558 can be used as a primary cache memory or a secondary cache memory. Also, the arithmetic circuit 557 analyzes the signal input from the demodulation circuit 554 and, according to the content of the command sent from the interrogator , outputs information in the storage device 558 or executes the content of the command in the storage device 558. The signal output from the arithmetic circuit 557 is encoded and sent to the modulation circuit 555 ​ It operates. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 according to the signal. The radio wave modulated in the antenna circuit 551 is received by the interrogator.

[0237] In this way, the communication between the RF tag 550 and the interrogator is performed by modulating the radio wave used as the carrier (carrier wave). The carrier varies depending on standards such as 125 kHz, 13.56 MHz, and 950 MHz. Also, there are various modulation methods such as amplitude modulation, frequency modulation, and phase modulation depending on the standard. However, any modulation method can be used as long as it conforms to the standard.

[0238] The signal transmission method can be classified into various types such as electromagnetic coupling method, electromagnetic induction method, and microwave method depending on the wavelength of the carrier.

[0239] The boost circuit 559 boosts the voltage output from the regulator 556 and supplies it to the storage device 558.

[0240] In one aspect of the present invention, the storage device 558 has the configuration shown in the above embodiment, and it is characterized in that the storage capacity per unit area can be increased while securing the period for holding data. Therefore, the RF tag 550 according to one aspect of the present invention can enhance the reliability of data by using the above storage device 558. Also, by using the above storage device 558, the RF tag 550 can be miniaturized or enhanced in functionality.

[0241] In this embodiment, the configuration of the RF tag 550 having the antenna circuit 551 has been described. However, the RF tag according to one aspect of the present invention does not necessarily include an antenna circuit as its component. There is no need. Also, an oscillation circuit or a secondary battery may be provided in the RF tag shown in FIG. 17. .

[0242] This embodiment can be implemented in appropriate combination with the above embodiment.

[0243] (Embodiment 10) In this embodiment, an example of a belt-shaped storage medium, which is one of the semiconductor devices using the storage device according to one aspect of the present invention, will be described.

[0244] FIG. 18(A) shows, as an example, the configuration of the storage medium according to one aspect of the present invention. FIG. 18( A) shows a storage medium including a storage device 701 according to one aspect of the present invention, a connector 702 that electrically connects the driving device and the storage medium, and various signals input and output via the connector 702 , an interface 703 that performs signal processing according to specifications, a light-emitting diode 704 that lights up according to the operating state of the storage medium, etc., and a controller 705 that controls the operations of various circuits and semiconductor elements in the storage medium, such as the storage device 701, the interface 703, and the light-emitting diode 704, are mounted on a printed wiring board 706. In addition, a crystal oscillator used to generate a clock signal for controlling the operation of the controller 705, a regulator for controlling the height of the power supply potential in the storage medium, etc. may be provided.

[0245] As shown in FIG. 18(B), the printed wiring board 706 shown in FIG. 18(A) may be covered with a cover material 707 made of resin or the like so that the connector 702 and the light-emitting diode 704 are partially exposed for protection.

[0246] The memory device 701 according to one aspect of the present invention is characterized in that it can increase the memory capacity per unit area while securing a period for holding data. Therefore, by using the above-described memory device 701, the reliability of data can be enhanced for the memory medium according to one aspect of the present invention. Also, by using the above-described memory device 701, the memory medium can be miniaturized. This embodiment can be implemented in appropriate combination with the above-described embodiment.

Example

[0247] By using the semiconductor device according to one aspect of the present invention, it is possible to provide an electronic device with high reliability and an electronic device having high functionality. The semiconductor device according to one aspect of the present invention can be used in a display device, a notebook personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as electronic devices in which the semiconductor device according to one aspect of the present invention can be used, there are a mobile phone, a portable game machine, a portable information terminal, an electronic book, a video camera, a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 19.

[0248]

[0249]

[0250] ​​​​​​​​​​​​​FIG. 19(A) is a portable game machine, which includes a housing 7031, a housing 7032, a display unit 7033, a display unit 7034, a microphone 7035, a speaker 7036, operation keys 7037, a start button 7038, etc. The semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of a portable game machine. By using the semiconductor device according to one aspect of the present invention for the integrated circuit for controlling the driving of a portable game machine, a highly reliable portable game machine and a portable game machine having high functions can be provided. Note that the portable game machine shown in FIG. 19(A) has two display units 7033 and 7034, but the number of display units included in the portable game machine is not limited to this.

[0251] FIG. 19(B) is a mobile phone, which includes a housing 7041, a display unit 7042, an audio input unit 7043, an audio output unit 7044, operation keys 7045, a light receiving unit 7046, etc. By converting the light received by the light receiving unit 7046 into an electrical signal, an external image can be captured. The semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of a mobile phone. By using the semiconductor device according to one aspect of the present invention for the integrated circuit for controlling the driving of a mobile phone, a highly reliable mobile phone and a mobile phone having high functions can be provided.

[0252] FIG. 19(C) is a portable information terminal, which includes a housing 7051, a display unit 7052, operation keys 7053 etc. In the portable information terminal shown in FIG. 19(C), a modem may be built in the housing 7051. The semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of a portable information terminal. For the integrated circuit for controlling the driving of a portable information terminal, the semiconductor device of the present invention ​​​​​​​​​​ By using the semiconductor device according to one aspect, a highly reliable portable information terminal or a portable information terminal having high functionality can be provided.

[0253] This example can be implemented in appropriate combination with the above-described embodiment.

Description of Reference Numerals

[0254] 101 Memory cell 102 Transistor 103 Transistor 104 Capacitor element 105 Capacitor element 106 Transistor 110 Substrate 111 Insulating film 112 Electrode 113 Insulating film 114 Electrode 115 Gate electrode 116 Insulating film 117 Active layer 118 Source electrode 119 Drain electrode 120 Insulating film 121 Insulating film 122 Insulating film 123 Wiring 130 Conductive film 131 Conductive film 132 Active layer 133 Insulating film 134 Gate electrode 135 Conductive film 136 Active layer 137 Gate electrode 138 Contact hole 139 Insulating film 140 Contact hole 141 Conductive film 142 Contact hole 143 Contact hole 144 Conductive film 150 Gate electrode 151 Insulating film​ 152 Active layer 153 Channel protection film 154 Source electrode 155 Drain electrode 156 Insulating film 160 Gate electrode 161 Insulating film 162 Active layer 164 Source electrode 165 Drain electrode 166 Insulating film 200 Memory section 201 Memory section 260 Transistor 261 Transistor 262 Operational amplifier 300 Memory device 301 Memory section 302 Drive circuit 303 Readout circuit 304 Word line drive circuit 305 Data line drive circuit 306 Control circuit 307 Decoder 308 Level shifter 309 Buffer 310 Decoder 311 Level shifter 312 Selector 550 RF tag 551 Antenna circuit 552 Integrated circuit 553 Power supply circuit 554 Demodulation circuit 555 Modulation circuit 556 Regulator 557 Arithmetic circuit 558 Memory device 559 Boost circuit 701 Memory device 702 Connector 703 Interface 704 Light emitting diode 705 Controller 706 Printed wiring board 707 Cover Material 801 Measurement System 811 Transistor 812 Transistor 813 Capacitive Element 814 Transistor 815 Transistor 7031 Housing 7032 Housing 7033 Display Unit 7034 Display Unit 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display Unit 7043 Voice Input Section 7044 Voice Output Section 7045 Operation Key 7046 Light Receiving Section 7051 Housing 7052 Display Unit 7053 Operation Key

Claims

1. A semiconductor device having a capacitive element, a first transistor, and a second transistor, wherein one of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, the other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, one of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, the capacitive element having a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, the second electrode of the capacitive element having a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor, wherein the channel formation region of the first transistor is above the capacitive element and has a region overlapping the capacitive element, and is a semiconductor device having an oxide semiconductor layer, the oxide semiconductor layer having the channel formation region of the first transistor, and in a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer has a bending point.

2. A semiconductor device having a capacitive element, a first transistor, and a second transistor, wherein one of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, the other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, one of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, the capacitive element having a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, the second electrode of the capacitive element having a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor, wherein the channel formation region of the first transistor is above the capacitive element and has a region overlapping the capacitive element, and is a semiconductor device having an oxide semiconductor layer and a first insulating layer, the oxide semiconductor layer having the channel formation region of the first transistor, the first insulating layer having a region in contact with the oxide semiconductor layer, the first insulating layer having silicon and oxygen, and in a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer has a bending point.

3. It has a capacitive element, a first transistor, and a second transistor, One of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, The other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, One of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, The capacitive element has a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, The second electrode of the capacitive element has a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor, A semiconductor device in which a channel formation region of the first transistor is above the capacitive element and has a region overlapping the capacitive element, It has an oxide semiconductor layer, a first insulating layer, and a second insulating layer, The oxide semiconductor layer has a channel formation region of the first transistor, The first insulating layer has a region between the oxide semiconductor layer and the second insulating layer, The first insulating layer has silicon and oxygen, The second insulating layer has silicon and nitrogen, In a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer is a semiconductor device having a bending point.

4. In any one of Claims 1 to 3, The oxide semiconductor layer is a semiconductor device having In, Ga, and Zn.

5. In any one of Claims 1 to 3, The oxide semiconductor layer is a semiconductor device that is In—Zn—O.

6. It has a capacitive element, a first transistor, and a second transistor, One of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, The other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, One of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, The capacitive element has a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, The second electrode of the capacitive element has a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor, The semiconductor device in which the channel formation region of the first transistor has a region above and overlapping with the capacitor element, has an oxide semiconductor layer, the oxide semiconductor layer has the channel formation region of the first transistor, the oxide semiconductor layer is In - O, in a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer has a bending point.

7. having a capacitor element, a first transistor, and a second transistor, one of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, the other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, one of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, the capacitor element has a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, the second electrode of the capacitor element has a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor, The semiconductor device in which the channel formation region of the first transistor has a region above and overlapping with the capacitor element, has an oxide semiconductor layer and a first insulating layer, the oxide semiconductor layer has the channel formation region of the first transistor, the first insulating layer has a region in contact with the oxide semiconductor layer, the oxide semiconductor layer is In - O, the first insulating layer has silicon and oxygen, in a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer has a bending point.

8. having a capacitor element, a first transistor, and a second transistor, one of the source electrode or the drain electrode of the first transistor is always in conduction with the gate electrode of the second transistor, the other of the source electrode or the drain electrode of the first transistor is always in conduction with a first wiring, one of the source electrode or the drain electrode of the second transistor is always in conduction with the first wiring, the capacitor element has a first electrode, an insulating film having a region on the first electrode, and a second electrode having a region on the insulating film, The second electrode of the capacitive element has a region in contact with a first conductive film that functions as one of the source electrode or the drain electrode of the first transistor. The channel formation region of the first transistor is a semiconductor device having a region above the capacitive element and overlapping the capacitive element. It has an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The oxide semiconductor layer has a channel formation region of the first transistor. The first insulating layer has a region between the oxide semiconductor layer and the second insulating layer. The oxide semiconductor layer is In—O. The first insulating layer contains silicon and oxygen. The second insulating layer contains silicon and nitrogen. In a cross-sectional view in the channel length direction of the first transistor, the oxide semiconductor layer has a bending point.

9. In any one of Claims 1 to 8, A semiconductor device in which an off-current density of the first transistor is 100 zA / μm or less.

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